diff options
author | Mike Frysinger <vapier.adi@gmail.com> | 2008-08-06 05:05:20 -0400 |
---|---|---|
committer | Bryan Wu <cooloney@kernel.org> | 2008-08-06 05:05:20 -0400 |
commit | 778307d372555f979cf6cef112a6d7fbff056cd9 (patch) | |
tree | 6ab304d2f1ef333f48b56eb2913268fe9dfc9714 | |
parent | d6a29891369827317659b7833170d2f5f0c7b97f (diff) |
Blackfin arch: remove support for Anomaly 05000125 as it doesnt exist on any supported processor/silicon
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
-rw-r--r-- | arch/blackfin/mach-bf527/head.S | 19 | ||||
-rw-r--r-- | arch/blackfin/mach-bf533/head.S | 18 | ||||
-rw-r--r-- | arch/blackfin/mach-bf537/head.S | 39 | ||||
-rw-r--r-- | arch/blackfin/mach-bf561/head.S | 17 | ||||
-rw-r--r-- | arch/blackfin/mach-common/Makefile | 2 | ||||
-rw-r--r-- | arch/blackfin/mach-common/cacheinit.S | 77 | ||||
-rw-r--r-- | include/asm-blackfin/mach-common/cdef_LPBlackfin.h | 8 |
7 files changed, 2 insertions, 178 deletions
diff --git a/arch/blackfin/mach-bf527/head.S b/arch/blackfin/mach-bf527/head.S index fe05cc1ef174..a16a26575280 100644 --- a/arch/blackfin/mach-bf527/head.S +++ b/arch/blackfin/mach-bf527/head.S | |||
@@ -105,17 +105,8 @@ ENTRY(__start) | |||
105 | R1 = [p0]; | 105 | R1 = [p0]; |
106 | R0 = ~ENICPLB; | 106 | R0 = ~ENICPLB; |
107 | R0 = R0 & R1; | 107 | R0 = R0 & R1; |
108 | |||
109 | /* Anomaly 05000125 */ | ||
110 | #if ANOMALY_05000125 | ||
111 | CLI R2; | ||
112 | SSYNC; | ||
113 | #endif | ||
114 | [p0] = R0; | 108 | [p0] = R0; |
115 | SSYNC; | 109 | SSYNC; |
116 | #if ANOMALY_05000125 | ||
117 | STI R2; | ||
118 | #endif | ||
119 | 110 | ||
120 | /* Turn off the dcache */ | 111 | /* Turn off the dcache */ |
121 | p0.l = LO(DMEM_CONTROL); | 112 | p0.l = LO(DMEM_CONTROL); |
@@ -123,18 +114,8 @@ ENTRY(__start) | |||
123 | R1 = [p0]; | 114 | R1 = [p0]; |
124 | R0 = ~ENDCPLB; | 115 | R0 = ~ENDCPLB; |
125 | R0 = R0 & R1; | 116 | R0 = R0 & R1; |
126 | |||
127 | /* Anomaly 05000125 */ | ||
128 | #if ANOMALY_05000125 | ||
129 | CLI R2; | ||
130 | SSYNC; | ||
131 | #endif | ||
132 | [p0] = R0; | 117 | [p0] = R0; |
133 | SSYNC; | 118 | SSYNC; |
134 | #if ANOMALY_05000125 | ||
135 | STI R2; | ||
136 | #endif | ||
137 | |||
138 | 119 | ||
139 | #if defined(CONFIG_BF527) | 120 | #if defined(CONFIG_BF527) |
140 | p0.h = hi(EMAC_SYSTAT); | 121 | p0.h = hi(EMAC_SYSTAT); |
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S index c671e8549b17..fb49169c0e7b 100644 --- a/arch/blackfin/mach-bf533/head.S +++ b/arch/blackfin/mach-bf533/head.S | |||
@@ -116,17 +116,8 @@ ENTRY(__start) | |||
116 | R1 = [p0]; | 116 | R1 = [p0]; |
117 | R0 = ~ENICPLB; | 117 | R0 = ~ENICPLB; |
118 | R0 = R0 & R1; | 118 | R0 = R0 & R1; |
119 | |||
120 | /* Anomaly 05000125 */ | ||
121 | #if ANOMALY_05000125 | ||
122 | CLI R2; | ||
123 | SSYNC; | ||
124 | #endif | ||
125 | [p0] = R0; | 119 | [p0] = R0; |
126 | SSYNC; | 120 | SSYNC; |
127 | #if ANOMALY_05000125 | ||
128 | STI R2; | ||
129 | #endif | ||
130 | 121 | ||
131 | /* Turn off the dcache */ | 122 | /* Turn off the dcache */ |
132 | p0.l = LO(DMEM_CONTROL); | 123 | p0.l = LO(DMEM_CONTROL); |
@@ -134,17 +125,8 @@ ENTRY(__start) | |||
134 | R1 = [p0]; | 125 | R1 = [p0]; |
135 | R0 = ~ENDCPLB; | 126 | R0 = ~ENDCPLB; |
136 | R0 = R0 & R1; | 127 | R0 = R0 & R1; |
137 | |||
138 | /* Anomaly 05000125 */ | ||
139 | #if ANOMALY_05000125 | ||
140 | CLI R2; | ||
141 | SSYNC; | ||
142 | #endif | ||
143 | [p0] = R0; | 128 | [p0] = R0; |
144 | SSYNC; | 129 | SSYNC; |
145 | #if ANOMALY_05000125 | ||
146 | STI R2; | ||
147 | #endif | ||
148 | 130 | ||
149 | /* Initialise UART - when booting from u-boot, the UART is not disabled | 131 | /* Initialise UART - when booting from u-boot, the UART is not disabled |
150 | * so if we dont initalize here, our serial console gets hosed */ | 132 | * so if we dont initalize here, our serial console gets hosed */ |
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S index 6b019eaee0b6..5bc89bbb89d0 100644 --- a/arch/blackfin/mach-bf537/head.S +++ b/arch/blackfin/mach-bf537/head.S | |||
@@ -105,17 +105,8 @@ ENTRY(__start) | |||
105 | R1 = [p0]; | 105 | R1 = [p0]; |
106 | R0 = ~ENICPLB; | 106 | R0 = ~ENICPLB; |
107 | R0 = R0 & R1; | 107 | R0 = R0 & R1; |
108 | |||
109 | /* Anomaly 05000125 */ | ||
110 | #if ANOMALY_05000125 | ||
111 | CLI R2; | ||
112 | SSYNC; | ||
113 | #endif | ||
114 | [p0] = R0; | 108 | [p0] = R0; |
115 | SSYNC; | 109 | SSYNC; |
116 | #if ANOMALY_05000125 | ||
117 | STI R2; | ||
118 | #endif | ||
119 | 110 | ||
120 | /* Turn off the dcache */ | 111 | /* Turn off the dcache */ |
121 | p0.l = LO(DMEM_CONTROL); | 112 | p0.l = LO(DMEM_CONTROL); |
@@ -123,48 +114,20 @@ ENTRY(__start) | |||
123 | R1 = [p0]; | 114 | R1 = [p0]; |
124 | R0 = ~ENDCPLB; | 115 | R0 = ~ENDCPLB; |
125 | R0 = R0 & R1; | 116 | R0 = R0 & R1; |
126 | |||
127 | /* Anomaly 05000125 */ | ||
128 | #if ANOMALY_05000125 | ||
129 | CLI R2; | ||
130 | SSYNC; | ||
131 | #endif | ||
132 | [p0] = R0; | 117 | [p0] = R0; |
133 | SSYNC; | 118 | SSYNC; |
134 | #if ANOMALY_05000125 | ||
135 | STI R2; | ||
136 | #endif | ||
137 | 119 | ||
138 | /* Initialise General-Purpose I/O Modules on BF537 */ | 120 | /* Initialise General-Purpose I/O Modules on BF537 */ |
139 | /* Rev 0.0 Anomaly 05000212 - PORTx_FER, | ||
140 | * PORT_MUX Registers Do Not accept "writes" correctly: | ||
141 | */ | ||
142 | p0.h = hi(BFIN_PORT_MUX); | 121 | p0.h = hi(BFIN_PORT_MUX); |
143 | p0.l = lo(BFIN_PORT_MUX); | 122 | p0.l = lo(BFIN_PORT_MUX); |
144 | #if ANOMALY_05000212 | ||
145 | R0.L = W[P0]; /* Read */ | ||
146 | SSYNC; | ||
147 | #endif | ||
148 | R0 = (PGDE_UART | PFTE_UART)(Z); | 123 | R0 = (PGDE_UART | PFTE_UART)(Z); |
149 | #if ANOMALY_05000212 | ||
150 | W[P0] = R0.L; /* Write */ | ||
151 | SSYNC; | ||
152 | #endif | ||
153 | W[P0] = R0.L; /* Enable both UARTS */ | 124 | W[P0] = R0.L; /* Enable both UARTS */ |
154 | SSYNC; | 125 | SSYNC; |
155 | 126 | ||
127 | /* Enable peripheral function of PORTF for UART0 and UART1 */ | ||
156 | p0.h = hi(PORTF_FER); | 128 | p0.h = hi(PORTF_FER); |
157 | p0.l = lo(PORTF_FER); | 129 | p0.l = lo(PORTF_FER); |
158 | #if ANOMALY_05000212 | ||
159 | R0.L = W[P0]; /* Read */ | ||
160 | SSYNC; | ||
161 | #endif | ||
162 | R0 = 0x000F(Z); | 130 | R0 = 0x000F(Z); |
163 | #if ANOMALY_05000212 | ||
164 | W[P0] = R0.L; /* Write */ | ||
165 | SSYNC; | ||
166 | #endif | ||
167 | /* Enable peripheral function of PORTF for UART0 and UART1 */ | ||
168 | W[P0] = R0.L; | 131 | W[P0] = R0.L; |
169 | SSYNC; | 132 | SSYNC; |
170 | 133 | ||
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S index cf1a2dff01e7..0a1443b6b462 100644 --- a/arch/blackfin/mach-bf561/head.S +++ b/arch/blackfin/mach-bf561/head.S | |||
@@ -105,16 +105,8 @@ ENTRY(__start) | |||
105 | R1 = [p0]; | 105 | R1 = [p0]; |
106 | R0 = ~ENICPLB; | 106 | R0 = ~ENICPLB; |
107 | R0 = R0 & R1; | 107 | R0 = R0 & R1; |
108 | |||
109 | #if ANOMALY_05000125 | ||
110 | CLI R2; | ||
111 | SSYNC; | ||
112 | #endif | ||
113 | [p0] = R0; | 108 | [p0] = R0; |
114 | SSYNC; | 109 | SSYNC; |
115 | #if ANOMALY_05000125 | ||
116 | STI R2; | ||
117 | #endif | ||
118 | 110 | ||
119 | /* Turn off the dcache */ | 111 | /* Turn off the dcache */ |
120 | p0.l = LO(DMEM_CONTROL); | 112 | p0.l = LO(DMEM_CONTROL); |
@@ -122,17 +114,8 @@ ENTRY(__start) | |||
122 | R1 = [p0]; | 114 | R1 = [p0]; |
123 | R0 = ~ENDCPLB; | 115 | R0 = ~ENDCPLB; |
124 | R0 = R0 & R1; | 116 | R0 = R0 & R1; |
125 | |||
126 | /* Anomaly 05000125 */ | ||
127 | #if ANOMALY_05000125 | ||
128 | CLI R2; | ||
129 | SSYNC; | ||
130 | #endif | ||
131 | [p0] = R0; | 117 | [p0] = R0; |
132 | SSYNC; | 118 | SSYNC; |
133 | #if ANOMALY_05000125 | ||
134 | STI R2; | ||
135 | #endif | ||
136 | 119 | ||
137 | /* Initialise UART - when booting from u-boot, the UART is not disabled | 120 | /* Initialise UART - when booting from u-boot, the UART is not disabled |
138 | * so if we dont initalize here, our serial console gets hosed */ | 121 | * so if we dont initalize here, our serial console gets hosed */ |
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile index 422bfee34adc..5e6b20e423d6 100644 --- a/arch/blackfin/mach-common/Makefile +++ b/arch/blackfin/mach-common/Makefile | |||
@@ -3,7 +3,7 @@ | |||
3 | # | 3 | # |
4 | 4 | ||
5 | obj-y := \ | 5 | obj-y := \ |
6 | cache.o cacheinit.o entry.o \ | 6 | cache.o entry.o \ |
7 | interrupt.o lock.o irqpanic.o arch_checks.o ints-priority.o | 7 | interrupt.o lock.o irqpanic.o arch_checks.o ints-priority.o |
8 | 8 | ||
9 | obj-$(CONFIG_PM) += pm.o dpmc_modes.o | 9 | obj-$(CONFIG_PM) += pm.o dpmc_modes.o |
diff --git a/arch/blackfin/mach-common/cacheinit.S b/arch/blackfin/mach-common/cacheinit.S deleted file mode 100644 index 22fada0c1cb3..000000000000 --- a/arch/blackfin/mach-common/cacheinit.S +++ /dev/null | |||
@@ -1,77 +0,0 @@ | |||
1 | /* | ||
2 | * File: arch/blackfin/mach-common/cacheinit.S | ||
3 | * Based on: | ||
4 | * Author: LG Soft India | ||
5 | * | ||
6 | * Created: ? | ||
7 | * Description: cache initialization | ||
8 | * | ||
9 | * Modified: | ||
10 | * Copyright 2004-2006 Analog Devices Inc. | ||
11 | * | ||
12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or modify | ||
15 | * it under the terms of the GNU General Public License as published by | ||
16 | * the Free Software Foundation; either version 2 of the License, or | ||
17 | * (at your option) any later version. | ||
18 | * | ||
19 | * This program is distributed in the hope that it will be useful, | ||
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
22 | * GNU General Public License for more details. | ||
23 | * | ||
24 | * You should have received a copy of the GNU General Public License | ||
25 | * along with this program; if not, see the file COPYING, or write | ||
26 | * to the Free Software Foundation, Inc., | ||
27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
28 | */ | ||
29 | |||
30 | /* This function sets up the data and instruction cache. The | ||
31 | * tables like icplb table, dcplb table and Page Descriptor table | ||
32 | * are defined in cplbtab.h. You can configure those tables for | ||
33 | * your suitable requirements | ||
34 | */ | ||
35 | |||
36 | #include <linux/linkage.h> | ||
37 | #include <asm/blackfin.h> | ||
38 | |||
39 | .text | ||
40 | |||
41 | #if ANOMALY_05000125 | ||
42 | #if defined(CONFIG_BFIN_ICACHE) | ||
43 | ENTRY(_bfin_write_IMEM_CONTROL) | ||
44 | |||
45 | /* Enable Instruction Cache */ | ||
46 | P0.l = LO(IMEM_CONTROL); | ||
47 | P0.h = HI(IMEM_CONTROL); | ||
48 | |||
49 | /* Anomaly 05000125 */ | ||
50 | CLI R1; | ||
51 | SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ | ||
52 | .align 8; | ||
53 | [P0] = R0; | ||
54 | SSYNC; | ||
55 | STI R1; | ||
56 | RTS; | ||
57 | |||
58 | ENDPROC(_bfin_write_IMEM_CONTROL) | ||
59 | #endif | ||
60 | |||
61 | #if defined(CONFIG_BFIN_DCACHE) | ||
62 | ENTRY(_bfin_write_DMEM_CONTROL) | ||
63 | P0.l = LO(DMEM_CONTROL); | ||
64 | P0.h = HI(DMEM_CONTROL); | ||
65 | |||
66 | CLI R1; | ||
67 | SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ | ||
68 | .align 8; | ||
69 | [P0] = R0; | ||
70 | SSYNC; | ||
71 | STI R1; | ||
72 | RTS; | ||
73 | |||
74 | ENDPROC(_bfin_write_DMEM_CONTROL) | ||
75 | #endif | ||
76 | |||
77 | #endif | ||
diff --git a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h index ede210eca4ec..d39c396f850d 100644 --- a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h +++ b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h | |||
@@ -39,11 +39,7 @@ | |||
39 | #define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS) | 39 | #define bfin_read_SRAM_BASE_ADDRESS() bfin_read32(SRAM_BASE_ADDRESS) |
40 | #define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val) | 40 | #define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val) |
41 | #define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) | 41 | #define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) |
42 | #if ANOMALY_05000125 | ||
43 | extern void bfin_write_DMEM_CONTROL(unsigned int val); | ||
44 | #else | ||
45 | #define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val) | 42 | #define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val) |
46 | #endif | ||
47 | #define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) | 43 | #define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) |
48 | #define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val) | 44 | #define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS,val) |
49 | #define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR) | 45 | #define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR) |
@@ -129,11 +125,7 @@ extern void bfin_write_DMEM_CONTROL(unsigned int val); | |||
129 | #define DTEST_DATA3 0xFFE0040C | 125 | #define DTEST_DATA3 0xFFE0040C |
130 | */ | 126 | */ |
131 | #define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) | 127 | #define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) |
132 | #if ANOMALY_05000125 | ||
133 | extern void bfin_write_IMEM_CONTROL(unsigned int val); | ||
134 | #else | ||
135 | #define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val) | 128 | #define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val) |
136 | #endif | ||
137 | #define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) | 129 | #define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) |
138 | #define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val) | 130 | #define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS,val) |
139 | #define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR) | 131 | #define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR) |