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authorMark Brown <broonie@opensource.wolfsonmicro.com>2010-12-23 07:03:07 -0500
committerMark Brown <broonie@opensource.wolfsonmicro.com>2010-12-24 06:32:45 -0500
commit617eecdb3d51624afca3be546b72fe80d8708370 (patch)
tree02cd1eb961c2afcbdbda9500b00b56aada42862f
parent524d7692bcdbec9027bfdc001a8aeb6eb6837117 (diff)
ASoC: Remove WM8995 write sequencer bitfield definitions
They're very verbose and extremely repetitive so bulk up the kernel more than is ideal. If required we can readd with WRITE_SEQUENCER_n type definitions that cover the entire register bank in a few defines. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
-rw-r--r--sound/soc/codecs/wm8995.h4480
1 files changed, 0 insertions, 4480 deletions
diff --git a/sound/soc/codecs/wm8995.h b/sound/soc/codecs/wm8995.h
index 6409e5a6b574..5642121c4977 100644
--- a/sound/soc/codecs/wm8995.h
+++ b/sound/soc/codecs/wm8995.h
@@ -4236,4486 +4236,6 @@
4236#define WM8995_SPK2_MUTE_SEQ1_SHIFT 0 /* SPK2_MUTE_SEQ1 - [7:0] */ 4236#define WM8995_SPK2_MUTE_SEQ1_SHIFT 0 /* SPK2_MUTE_SEQ1 - [7:0] */
4237#define WM8995_SPK2_MUTE_SEQ1_WIDTH 8 /* SPK2_MUTE_SEQ1 - [7:0] */ 4237#define WM8995_SPK2_MUTE_SEQ1_WIDTH 8 /* SPK2_MUTE_SEQ1 - [7:0] */
4238 4238
4239/*
4240 * R12288 (0x3000) - Write Sequencer 0
4241 */
4242#define WM8995_WSEQ_ADDR0_MASK 0x3FFF /* WSEQ_ADDR0 - [13:0] */
4243#define WM8995_WSEQ_ADDR0_SHIFT 0 /* WSEQ_ADDR0 - [13:0] */
4244#define WM8995_WSEQ_ADDR0_WIDTH 14 /* WSEQ_ADDR0 - [13:0] */
4245
4246/*
4247 * R12289 (0x3001) - Write Sequencer 1
4248 */
4249#define WM8995_WSEQ_DATA0_MASK 0x00FF /* WSEQ_DATA0 - [7:0] */
4250#define WM8995_WSEQ_DATA0_SHIFT 0 /* WSEQ_DATA0 - [7:0] */
4251#define WM8995_WSEQ_DATA0_WIDTH 8 /* WSEQ_DATA0 - [7:0] */
4252
4253/*
4254 * R12290 (0x3002) - Write Sequencer 2
4255 */
4256#define WM8995_WSEQ_DATA_WIDTH0_MASK 0x0700 /* WSEQ_DATA_WIDTH0 - [10:8] */
4257#define WM8995_WSEQ_DATA_WIDTH0_SHIFT 8 /* WSEQ_DATA_WIDTH0 - [10:8] */
4258#define WM8995_WSEQ_DATA_WIDTH0_WIDTH 3 /* WSEQ_DATA_WIDTH0 - [10:8] */
4259#define WM8995_WSEQ_DATA_START0_MASK 0x000F /* WSEQ_DATA_START0 - [3:0] */
4260#define WM8995_WSEQ_DATA_START0_SHIFT 0 /* WSEQ_DATA_START0 - [3:0] */
4261#define WM8995_WSEQ_DATA_START0_WIDTH 4 /* WSEQ_DATA_START0 - [3:0] */
4262
4263/*
4264 * R12291 (0x3003) - Write Sequencer 3
4265 */
4266#define WM8995_WSEQ_EOS0 0x0100 /* WSEQ_EOS0 */
4267#define WM8995_WSEQ_EOS0_MASK 0x0100 /* WSEQ_EOS0 */
4268#define WM8995_WSEQ_EOS0_SHIFT 8 /* WSEQ_EOS0 */
4269#define WM8995_WSEQ_EOS0_WIDTH 1 /* WSEQ_EOS0 */
4270#define WM8995_WSEQ_DELAY0_MASK 0x000F /* WSEQ_DELAY0 - [3:0] */
4271#define WM8995_WSEQ_DELAY0_SHIFT 0 /* WSEQ_DELAY0 - [3:0] */
4272#define WM8995_WSEQ_DELAY0_WIDTH 4 /* WSEQ_DELAY0 - [3:0] */
4273
4274/*
4275 * R12292 (0x3004) - Write Sequencer 4
4276 */
4277#define WM8995_WSEQ_ADDR1_MASK 0x3FFF /* WSEQ_ADDR1 - [13:0] */
4278#define WM8995_WSEQ_ADDR1_SHIFT 0 /* WSEQ_ADDR1 - [13:0] */
4279#define WM8995_WSEQ_ADDR1_WIDTH 14 /* WSEQ_ADDR1 - [13:0] */
4280
4281/*
4282 * R12293 (0x3005) - Write Sequencer 5
4283 */
4284#define WM8995_WSEQ_DATA1_MASK 0x00FF /* WSEQ_DATA1 - [7:0] */
4285#define WM8995_WSEQ_DATA1_SHIFT 0 /* WSEQ_DATA1 - [7:0] */
4286#define WM8995_WSEQ_DATA1_WIDTH 8 /* WSEQ_DATA1 - [7:0] */
4287
4288/*
4289 * R12294 (0x3006) - Write Sequencer 6
4290 */
4291#define WM8995_WSEQ_DATA_WIDTH1_MASK 0x0700 /* WSEQ_DATA_WIDTH1 - [10:8] */
4292#define WM8995_WSEQ_DATA_WIDTH1_SHIFT 8 /* WSEQ_DATA_WIDTH1 - [10:8] */
4293#define WM8995_WSEQ_DATA_WIDTH1_WIDTH 3 /* WSEQ_DATA_WIDTH1 - [10:8] */
4294#define WM8995_WSEQ_DATA_START1_MASK 0x000F /* WSEQ_DATA_START1 - [3:0] */
4295#define WM8995_WSEQ_DATA_START1_SHIFT 0 /* WSEQ_DATA_START1 - [3:0] */
4296#define WM8995_WSEQ_DATA_START1_WIDTH 4 /* WSEQ_DATA_START1 - [3:0] */
4297
4298/*
4299 * R12295 (0x3007) - Write Sequencer 7
4300 */
4301#define WM8995_WSEQ_EOS1 0x0100 /* WSEQ_EOS1 */
4302#define WM8995_WSEQ_EOS1_MASK 0x0100 /* WSEQ_EOS1 */
4303#define WM8995_WSEQ_EOS1_SHIFT 8 /* WSEQ_EOS1 */
4304#define WM8995_WSEQ_EOS1_WIDTH 1 /* WSEQ_EOS1 */
4305#define WM8995_WSEQ_DELAY1_MASK 0x000F /* WSEQ_DELAY1 - [3:0] */
4306#define WM8995_WSEQ_DELAY1_SHIFT 0 /* WSEQ_DELAY1 - [3:0] */
4307#define WM8995_WSEQ_DELAY1_WIDTH 4 /* WSEQ_DELAY1 - [3:0] */
4308
4309/*
4310 * R12296 (0x3008) - Write Sequencer 8
4311 */
4312#define WM8995_WSEQ_ADDR2_MASK 0x3FFF /* WSEQ_ADDR2 - [13:0] */
4313#define WM8995_WSEQ_ADDR2_SHIFT 0 /* WSEQ_ADDR2 - [13:0] */
4314#define WM8995_WSEQ_ADDR2_WIDTH 14 /* WSEQ_ADDR2 - [13:0] */
4315
4316/*
4317 * R12297 (0x3009) - Write Sequencer 9
4318 */
4319#define WM8995_WSEQ_DATA2_MASK 0x00FF /* WSEQ_DATA2 - [7:0] */
4320#define WM8995_WSEQ_DATA2_SHIFT 0 /* WSEQ_DATA2 - [7:0] */
4321#define WM8995_WSEQ_DATA2_WIDTH 8 /* WSEQ_DATA2 - [7:0] */
4322
4323/*
4324 * R12298 (0x300A) - Write Sequencer 10
4325 */
4326#define WM8995_WSEQ_DATA_WIDTH2_MASK 0x0700 /* WSEQ_DATA_WIDTH2 - [10:8] */
4327#define WM8995_WSEQ_DATA_WIDTH2_SHIFT 8 /* WSEQ_DATA_WIDTH2 - [10:8] */
4328#define WM8995_WSEQ_DATA_WIDTH2_WIDTH 3 /* WSEQ_DATA_WIDTH2 - [10:8] */
4329#define WM8995_WSEQ_DATA_START2_MASK 0x000F /* WSEQ_DATA_START2 - [3:0] */
4330#define WM8995_WSEQ_DATA_START2_SHIFT 0 /* WSEQ_DATA_START2 - [3:0] */
4331#define WM8995_WSEQ_DATA_START2_WIDTH 4 /* WSEQ_DATA_START2 - [3:0] */
4332
4333/*
4334 * R12299 (0x300B) - Write Sequencer 11
4335 */
4336#define WM8995_WSEQ_EOS2 0x0100 /* WSEQ_EOS2 */
4337#define WM8995_WSEQ_EOS2_MASK 0x0100 /* WSEQ_EOS2 */
4338#define WM8995_WSEQ_EOS2_SHIFT 8 /* WSEQ_EOS2 */
4339#define WM8995_WSEQ_EOS2_WIDTH 1 /* WSEQ_EOS2 */
4340#define WM8995_WSEQ_DELAY2_MASK 0x000F /* WSEQ_DELAY2 - [3:0] */
4341#define WM8995_WSEQ_DELAY2_SHIFT 0 /* WSEQ_DELAY2 - [3:0] */
4342#define WM8995_WSEQ_DELAY2_WIDTH 4 /* WSEQ_DELAY2 - [3:0] */
4343
4344/*
4345 * R12300 (0x300C) - Write Sequencer 12
4346 */
4347#define WM8995_WSEQ_ADDR3_MASK 0x3FFF /* WSEQ_ADDR3 - [13:0] */
4348#define WM8995_WSEQ_ADDR3_SHIFT 0 /* WSEQ_ADDR3 - [13:0] */
4349#define WM8995_WSEQ_ADDR3_WIDTH 14 /* WSEQ_ADDR3 - [13:0] */
4350
4351/*
4352 * R12301 (0x300D) - Write Sequencer 13
4353 */
4354#define WM8995_WSEQ_DATA3_MASK 0x00FF /* WSEQ_DATA3 - [7:0] */
4355#define WM8995_WSEQ_DATA3_SHIFT 0 /* WSEQ_DATA3 - [7:0] */
4356#define WM8995_WSEQ_DATA3_WIDTH 8 /* WSEQ_DATA3 - [7:0] */
4357
4358/*
4359 * R12302 (0x300E) - Write Sequencer 14
4360 */
4361#define WM8995_WSEQ_DATA_WIDTH3_MASK 0x0700 /* WSEQ_DATA_WIDTH3 - [10:8] */
4362#define WM8995_WSEQ_DATA_WIDTH3_SHIFT 8 /* WSEQ_DATA_WIDTH3 - [10:8] */
4363#define WM8995_WSEQ_DATA_WIDTH3_WIDTH 3 /* WSEQ_DATA_WIDTH3 - [10:8] */
4364#define WM8995_WSEQ_DATA_START3_MASK 0x000F /* WSEQ_DATA_START3 - [3:0] */
4365#define WM8995_WSEQ_DATA_START3_SHIFT 0 /* WSEQ_DATA_START3 - [3:0] */
4366#define WM8995_WSEQ_DATA_START3_WIDTH 4 /* WSEQ_DATA_START3 - [3:0] */
4367
4368/*
4369 * R12303 (0x300F) - Write Sequencer 15
4370 */
4371#define WM8995_WSEQ_EOS3 0x0100 /* WSEQ_EOS3 */
4372#define WM8995_WSEQ_EOS3_MASK 0x0100 /* WSEQ_EOS3 */
4373#define WM8995_WSEQ_EOS3_SHIFT 8 /* WSEQ_EOS3 */
4374#define WM8995_WSEQ_EOS3_WIDTH 1 /* WSEQ_EOS3 */
4375#define WM8995_WSEQ_DELAY3_MASK 0x000F /* WSEQ_DELAY3 - [3:0] */
4376#define WM8995_WSEQ_DELAY3_SHIFT 0 /* WSEQ_DELAY3 - [3:0] */
4377#define WM8995_WSEQ_DELAY3_WIDTH 4 /* WSEQ_DELAY3 - [3:0] */
4378
4379/*
4380 * R12304 (0x3010) - Write Sequencer 16
4381 */
4382#define WM8995_WSEQ_ADDR4_MASK 0x3FFF /* WSEQ_ADDR4 - [13:0] */
4383#define WM8995_WSEQ_ADDR4_SHIFT 0 /* WSEQ_ADDR4 - [13:0] */
4384#define WM8995_WSEQ_ADDR4_WIDTH 14 /* WSEQ_ADDR4 - [13:0] */
4385
4386/*
4387 * R12305 (0x3011) - Write Sequencer 17
4388 */
4389#define WM8995_WSEQ_DATA4_MASK 0x00FF /* WSEQ_DATA4 - [7:0] */
4390#define WM8995_WSEQ_DATA4_SHIFT 0 /* WSEQ_DATA4 - [7:0] */
4391#define WM8995_WSEQ_DATA4_WIDTH 8 /* WSEQ_DATA4 - [7:0] */
4392
4393/*
4394 * R12306 (0x3012) - Write Sequencer 18
4395 */
4396#define WM8995_WSEQ_DATA_WIDTH4_MASK 0x0700 /* WSEQ_DATA_WIDTH4 - [10:8] */
4397#define WM8995_WSEQ_DATA_WIDTH4_SHIFT 8 /* WSEQ_DATA_WIDTH4 - [10:8] */
4398#define WM8995_WSEQ_DATA_WIDTH4_WIDTH 3 /* WSEQ_DATA_WIDTH4 - [10:8] */
4399#define WM8995_WSEQ_DATA_START4_MASK 0x000F /* WSEQ_DATA_START4 - [3:0] */
4400#define WM8995_WSEQ_DATA_START4_SHIFT 0 /* WSEQ_DATA_START4 - [3:0] */
4401#define WM8995_WSEQ_DATA_START4_WIDTH 4 /* WSEQ_DATA_START4 - [3:0] */
4402
4403/*
4404 * R12307 (0x3013) - Write Sequencer 19
4405 */
4406#define WM8995_WSEQ_EOS4 0x0100 /* WSEQ_EOS4 */
4407#define WM8995_WSEQ_EOS4_MASK 0x0100 /* WSEQ_EOS4 */
4408#define WM8995_WSEQ_EOS4_SHIFT 8 /* WSEQ_EOS4 */
4409#define WM8995_WSEQ_EOS4_WIDTH 1 /* WSEQ_EOS4 */
4410#define WM8995_WSEQ_DELAY4_MASK 0x000F /* WSEQ_DELAY4 - [3:0] */
4411#define WM8995_WSEQ_DELAY4_SHIFT 0 /* WSEQ_DELAY4 - [3:0] */
4412#define WM8995_WSEQ_DELAY4_WIDTH 4 /* WSEQ_DELAY4 - [3:0] */
4413
4414/*
4415 * R12308 (0x3014) - Write Sequencer 20
4416 */
4417#define WM8995_WSEQ_ADDR5_MASK 0x3FFF /* WSEQ_ADDR5 - [13:0] */
4418#define WM8995_WSEQ_ADDR5_SHIFT 0 /* WSEQ_ADDR5 - [13:0] */
4419#define WM8995_WSEQ_ADDR5_WIDTH 14 /* WSEQ_ADDR5 - [13:0] */
4420
4421/*
4422 * R12309 (0x3015) - Write Sequencer 21
4423 */
4424#define WM8995_WSEQ_DATA5_MASK 0x00FF /* WSEQ_DATA5 - [7:0] */
4425#define WM8995_WSEQ_DATA5_SHIFT 0 /* WSEQ_DATA5 - [7:0] */
4426#define WM8995_WSEQ_DATA5_WIDTH 8 /* WSEQ_DATA5 - [7:0] */
4427
4428/*
4429 * R12310 (0x3016) - Write Sequencer 22
4430 */
4431#define WM8995_WSEQ_DATA_WIDTH5_MASK 0x0700 /* WSEQ_DATA_WIDTH5 - [10:8] */
4432#define WM8995_WSEQ_DATA_WIDTH5_SHIFT 8 /* WSEQ_DATA_WIDTH5 - [10:8] */
4433#define WM8995_WSEQ_DATA_WIDTH5_WIDTH 3 /* WSEQ_DATA_WIDTH5 - [10:8] */
4434#define WM8995_WSEQ_DATA_START5_MASK 0x000F /* WSEQ_DATA_START5 - [3:0] */
4435#define WM8995_WSEQ_DATA_START5_SHIFT 0 /* WSEQ_DATA_START5 - [3:0] */
4436#define WM8995_WSEQ_DATA_START5_WIDTH 4 /* WSEQ_DATA_START5 - [3:0] */
4437
4438/*
4439 * R12311 (0x3017) - Write Sequencer 23
4440 */
4441#define WM8995_WSEQ_EOS5 0x0100 /* WSEQ_EOS5 */
4442#define WM8995_WSEQ_EOS5_MASK 0x0100 /* WSEQ_EOS5 */
4443#define WM8995_WSEQ_EOS5_SHIFT 8 /* WSEQ_EOS5 */
4444#define WM8995_WSEQ_EOS5_WIDTH 1 /* WSEQ_EOS5 */
4445#define WM8995_WSEQ_DELAY5_MASK 0x000F /* WSEQ_DELAY5 - [3:0] */
4446#define WM8995_WSEQ_DELAY5_SHIFT 0 /* WSEQ_DELAY5 - [3:0] */
4447#define WM8995_WSEQ_DELAY5_WIDTH 4 /* WSEQ_DELAY5 - [3:0] */
4448
4449/*
4450 * R12312 (0x3018) - Write Sequencer 24
4451 */
4452#define WM8995_WSEQ_ADDR6_MASK 0x3FFF /* WSEQ_ADDR6 - [13:0] */
4453#define WM8995_WSEQ_ADDR6_SHIFT 0 /* WSEQ_ADDR6 - [13:0] */
4454#define WM8995_WSEQ_ADDR6_WIDTH 14 /* WSEQ_ADDR6 - [13:0] */
4455
4456/*
4457 * R12313 (0x3019) - Write Sequencer 25
4458 */
4459#define WM8995_WSEQ_DATA6_MASK 0x00FF /* WSEQ_DATA6 - [7:0] */
4460#define WM8995_WSEQ_DATA6_SHIFT 0 /* WSEQ_DATA6 - [7:0] */
4461#define WM8995_WSEQ_DATA6_WIDTH 8 /* WSEQ_DATA6 - [7:0] */
4462
4463/*
4464 * R12314 (0x301A) - Write Sequencer 26
4465 */
4466#define WM8995_WSEQ_DATA_WIDTH6_MASK 0x0700 /* WSEQ_DATA_WIDTH6 - [10:8] */
4467#define WM8995_WSEQ_DATA_WIDTH6_SHIFT 8 /* WSEQ_DATA_WIDTH6 - [10:8] */
4468#define WM8995_WSEQ_DATA_WIDTH6_WIDTH 3 /* WSEQ_DATA_WIDTH6 - [10:8] */
4469#define WM8995_WSEQ_DATA_START6_MASK 0x000F /* WSEQ_DATA_START6 - [3:0] */
4470#define WM8995_WSEQ_DATA_START6_SHIFT 0 /* WSEQ_DATA_START6 - [3:0] */
4471#define WM8995_WSEQ_DATA_START6_WIDTH 4 /* WSEQ_DATA_START6 - [3:0] */
4472
4473/*
4474 * R12315 (0x301B) - Write Sequencer 27
4475 */
4476#define WM8995_WSEQ_EOS6 0x0100 /* WSEQ_EOS6 */
4477#define WM8995_WSEQ_EOS6_MASK 0x0100 /* WSEQ_EOS6 */
4478#define WM8995_WSEQ_EOS6_SHIFT 8 /* WSEQ_EOS6 */
4479#define WM8995_WSEQ_EOS6_WIDTH 1 /* WSEQ_EOS6 */
4480#define WM8995_WSEQ_DELAY6_MASK 0x000F /* WSEQ_DELAY6 - [3:0] */
4481#define WM8995_WSEQ_DELAY6_SHIFT 0 /* WSEQ_DELAY6 - [3:0] */
4482#define WM8995_WSEQ_DELAY6_WIDTH 4 /* WSEQ_DELAY6 - [3:0] */
4483
4484/*
4485 * R12316 (0x301C) - Write Sequencer 28
4486 */
4487#define WM8995_WSEQ_ADDR7_MASK 0x3FFF /* WSEQ_ADDR7 - [13:0] */
4488#define WM8995_WSEQ_ADDR7_SHIFT 0 /* WSEQ_ADDR7 - [13:0] */
4489#define WM8995_WSEQ_ADDR7_WIDTH 14 /* WSEQ_ADDR7 - [13:0] */
4490
4491/*
4492 * R12317 (0x301D) - Write Sequencer 29
4493 */
4494#define WM8995_WSEQ_DATA7_MASK 0x00FF /* WSEQ_DATA7 - [7:0] */
4495#define WM8995_WSEQ_DATA7_SHIFT 0 /* WSEQ_DATA7 - [7:0] */
4496#define WM8995_WSEQ_DATA7_WIDTH 8 /* WSEQ_DATA7 - [7:0] */
4497
4498/*
4499 * R12318 (0x301E) - Write Sequencer 30
4500 */
4501#define WM8995_WSEQ_DATA_WIDTH7_MASK 0x0700 /* WSEQ_DATA_WIDTH7 - [10:8] */
4502#define WM8995_WSEQ_DATA_WIDTH7_SHIFT 8 /* WSEQ_DATA_WIDTH7 - [10:8] */
4503#define WM8995_WSEQ_DATA_WIDTH7_WIDTH 3 /* WSEQ_DATA_WIDTH7 - [10:8] */
4504#define WM8995_WSEQ_DATA_START7_MASK 0x000F /* WSEQ_DATA_START7 - [3:0] */
4505#define WM8995_WSEQ_DATA_START7_SHIFT 0 /* WSEQ_DATA_START7 - [3:0] */
4506#define WM8995_WSEQ_DATA_START7_WIDTH 4 /* WSEQ_DATA_START7 - [3:0] */
4507
4508/*
4509 * R12319 (0x301F) - Write Sequencer 31
4510 */
4511#define WM8995_WSEQ_EOS7 0x0100 /* WSEQ_EOS7 */
4512#define WM8995_WSEQ_EOS7_MASK 0x0100 /* WSEQ_EOS7 */
4513#define WM8995_WSEQ_EOS7_SHIFT 8 /* WSEQ_EOS7 */
4514#define WM8995_WSEQ_EOS7_WIDTH 1 /* WSEQ_EOS7 */
4515#define WM8995_WSEQ_DELAY7_MASK 0x000F /* WSEQ_DELAY7 - [3:0] */
4516#define WM8995_WSEQ_DELAY7_SHIFT 0 /* WSEQ_DELAY7 - [3:0] */
4517#define WM8995_WSEQ_DELAY7_WIDTH 4 /* WSEQ_DELAY7 - [3:0] */
4518
4519/*
4520 * R12320 (0x3020) - Write Sequencer 32
4521 */
4522#define WM8995_WSEQ_ADDR8_MASK 0x3FFF /* WSEQ_ADDR8 - [13:0] */
4523#define WM8995_WSEQ_ADDR8_SHIFT 0 /* WSEQ_ADDR8 - [13:0] */
4524#define WM8995_WSEQ_ADDR8_WIDTH 14 /* WSEQ_ADDR8 - [13:0] */
4525
4526/*
4527 * R12321 (0x3021) - Write Sequencer 33
4528 */
4529#define WM8995_WSEQ_DATA8_MASK 0x00FF /* WSEQ_DATA8 - [7:0] */
4530#define WM8995_WSEQ_DATA8_SHIFT 0 /* WSEQ_DATA8 - [7:0] */
4531#define WM8995_WSEQ_DATA8_WIDTH 8 /* WSEQ_DATA8 - [7:0] */
4532
4533/*
4534 * R12322 (0x3022) - Write Sequencer 34
4535 */
4536#define WM8995_WSEQ_DATA_WIDTH8_MASK 0x0700 /* WSEQ_DATA_WIDTH8 - [10:8] */
4537#define WM8995_WSEQ_DATA_WIDTH8_SHIFT 8 /* WSEQ_DATA_WIDTH8 - [10:8] */
4538#define WM8995_WSEQ_DATA_WIDTH8_WIDTH 3 /* WSEQ_DATA_WIDTH8 - [10:8] */
4539#define WM8995_WSEQ_DATA_START8_MASK 0x000F /* WSEQ_DATA_START8 - [3:0] */
4540#define WM8995_WSEQ_DATA_START8_SHIFT 0 /* WSEQ_DATA_START8 - [3:0] */
4541#define WM8995_WSEQ_DATA_START8_WIDTH 4 /* WSEQ_DATA_START8 - [3:0] */
4542
4543/*
4544 * R12323 (0x3023) - Write Sequencer 35
4545 */
4546#define WM8995_WSEQ_EOS8 0x0100 /* WSEQ_EOS8 */
4547#define WM8995_WSEQ_EOS8_MASK 0x0100 /* WSEQ_EOS8 */
4548#define WM8995_WSEQ_EOS8_SHIFT 8 /* WSEQ_EOS8 */
4549#define WM8995_WSEQ_EOS8_WIDTH 1 /* WSEQ_EOS8 */
4550#define WM8995_WSEQ_DELAY8_MASK 0x000F /* WSEQ_DELAY8 - [3:0] */
4551#define WM8995_WSEQ_DELAY8_SHIFT 0 /* WSEQ_DELAY8 - [3:0] */
4552#define WM8995_WSEQ_DELAY8_WIDTH 4 /* WSEQ_DELAY8 - [3:0] */
4553
4554/*
4555 * R12324 (0x3024) - Write Sequencer 36
4556 */
4557#define WM8995_WSEQ_ADDR9_MASK 0x3FFF /* WSEQ_ADDR9 - [13:0] */
4558#define WM8995_WSEQ_ADDR9_SHIFT 0 /* WSEQ_ADDR9 - [13:0] */
4559#define WM8995_WSEQ_ADDR9_WIDTH 14 /* WSEQ_ADDR9 - [13:0] */
4560
4561/*
4562 * R12325 (0x3025) - Write Sequencer 37
4563 */
4564#define WM8995_WSEQ_DATA9_MASK 0x00FF /* WSEQ_DATA9 - [7:0] */
4565#define WM8995_WSEQ_DATA9_SHIFT 0 /* WSEQ_DATA9 - [7:0] */
4566#define WM8995_WSEQ_DATA9_WIDTH 8 /* WSEQ_DATA9 - [7:0] */
4567
4568/*
4569 * R12326 (0x3026) - Write Sequencer 38
4570 */
4571#define WM8995_WSEQ_DATA_WIDTH9_MASK 0x0700 /* WSEQ_DATA_WIDTH9 - [10:8] */
4572#define WM8995_WSEQ_DATA_WIDTH9_SHIFT 8 /* WSEQ_DATA_WIDTH9 - [10:8] */
4573#define WM8995_WSEQ_DATA_WIDTH9_WIDTH 3 /* WSEQ_DATA_WIDTH9 - [10:8] */
4574#define WM8995_WSEQ_DATA_START9_MASK 0x000F /* WSEQ_DATA_START9 - [3:0] */
4575#define WM8995_WSEQ_DATA_START9_SHIFT 0 /* WSEQ_DATA_START9 - [3:0] */
4576#define WM8995_WSEQ_DATA_START9_WIDTH 4 /* WSEQ_DATA_START9 - [3:0] */
4577
4578/*
4579 * R12327 (0x3027) - Write Sequencer 39
4580 */
4581#define WM8995_WSEQ_EOS9 0x0100 /* WSEQ_EOS9 */
4582#define WM8995_WSEQ_EOS9_MASK 0x0100 /* WSEQ_EOS9 */
4583#define WM8995_WSEQ_EOS9_SHIFT 8 /* WSEQ_EOS9 */
4584#define WM8995_WSEQ_EOS9_WIDTH 1 /* WSEQ_EOS9 */
4585#define WM8995_WSEQ_DELAY9_MASK 0x000F /* WSEQ_DELAY9 - [3:0] */
4586#define WM8995_WSEQ_DELAY9_SHIFT 0 /* WSEQ_DELAY9 - [3:0] */
4587#define WM8995_WSEQ_DELAY9_WIDTH 4 /* WSEQ_DELAY9 - [3:0] */
4588
4589/*
4590 * R12328 (0x3028) - Write Sequencer 40
4591 */
4592#define WM8995_WSEQ_ADDR10_MASK 0x3FFF /* WSEQ_ADDR10 - [13:0] */
4593#define WM8995_WSEQ_ADDR10_SHIFT 0 /* WSEQ_ADDR10 - [13:0] */
4594#define WM8995_WSEQ_ADDR10_WIDTH 14 /* WSEQ_ADDR10 - [13:0] */
4595
4596/*
4597 * R12329 (0x3029) - Write Sequencer 41
4598 */
4599#define WM8995_WSEQ_DATA10_MASK 0x00FF /* WSEQ_DATA10 - [7:0] */
4600#define WM8995_WSEQ_DATA10_SHIFT 0 /* WSEQ_DATA10 - [7:0] */
4601#define WM8995_WSEQ_DATA10_WIDTH 8 /* WSEQ_DATA10 - [7:0] */
4602
4603/*
4604 * R12330 (0x302A) - Write Sequencer 42
4605 */
4606#define WM8995_WSEQ_DATA_WIDTH10_MASK 0x0700 /* WSEQ_DATA_WIDTH10 - [10:8] */
4607#define WM8995_WSEQ_DATA_WIDTH10_SHIFT 8 /* WSEQ_DATA_WIDTH10 - [10:8] */
4608#define WM8995_WSEQ_DATA_WIDTH10_WIDTH 3 /* WSEQ_DATA_WIDTH10 - [10:8] */
4609#define WM8995_WSEQ_DATA_START10_MASK 0x000F /* WSEQ_DATA_START10 - [3:0] */
4610#define WM8995_WSEQ_DATA_START10_SHIFT 0 /* WSEQ_DATA_START10 - [3:0] */
4611#define WM8995_WSEQ_DATA_START10_WIDTH 4 /* WSEQ_DATA_START10 - [3:0] */
4612
4613/*
4614 * R12331 (0x302B) - Write Sequencer 43
4615 */
4616#define WM8995_WSEQ_EOS10 0x0100 /* WSEQ_EOS10 */
4617#define WM8995_WSEQ_EOS10_MASK 0x0100 /* WSEQ_EOS10 */
4618#define WM8995_WSEQ_EOS10_SHIFT 8 /* WSEQ_EOS10 */
4619#define WM8995_WSEQ_EOS10_WIDTH 1 /* WSEQ_EOS10 */
4620#define WM8995_WSEQ_DELAY10_MASK 0x000F /* WSEQ_DELAY10 - [3:0] */
4621#define WM8995_WSEQ_DELAY10_SHIFT 0 /* WSEQ_DELAY10 - [3:0] */
4622#define WM8995_WSEQ_DELAY10_WIDTH 4 /* WSEQ_DELAY10 - [3:0] */
4623
4624/*
4625 * R12332 (0x302C) - Write Sequencer 44
4626 */
4627#define WM8995_WSEQ_ADDR11_MASK 0x3FFF /* WSEQ_ADDR11 - [13:0] */
4628#define WM8995_WSEQ_ADDR11_SHIFT 0 /* WSEQ_ADDR11 - [13:0] */
4629#define WM8995_WSEQ_ADDR11_WIDTH 14 /* WSEQ_ADDR11 - [13:0] */
4630
4631/*
4632 * R12333 (0x302D) - Write Sequencer 45
4633 */
4634#define WM8995_WSEQ_DATA11_MASK 0x00FF /* WSEQ_DATA11 - [7:0] */
4635#define WM8995_WSEQ_DATA11_SHIFT 0 /* WSEQ_DATA11 - [7:0] */
4636#define WM8995_WSEQ_DATA11_WIDTH 8 /* WSEQ_DATA11 - [7:0] */
4637
4638/*
4639 * R12334 (0x302E) - Write Sequencer 46
4640 */
4641#define WM8995_WSEQ_DATA_WIDTH11_MASK 0x0700 /* WSEQ_DATA_WIDTH11 - [10:8] */
4642#define WM8995_WSEQ_DATA_WIDTH11_SHIFT 8 /* WSEQ_DATA_WIDTH11 - [10:8] */
4643#define WM8995_WSEQ_DATA_WIDTH11_WIDTH 3 /* WSEQ_DATA_WIDTH11 - [10:8] */
4644#define WM8995_WSEQ_DATA_START11_MASK 0x000F /* WSEQ_DATA_START11 - [3:0] */
4645#define WM8995_WSEQ_DATA_START11_SHIFT 0 /* WSEQ_DATA_START11 - [3:0] */
4646#define WM8995_WSEQ_DATA_START11_WIDTH 4 /* WSEQ_DATA_START11 - [3:0] */
4647
4648/*
4649 * R12335 (0x302F) - Write Sequencer 47
4650 */
4651#define WM8995_WSEQ_EOS11 0x0100 /* WSEQ_EOS11 */
4652#define WM8995_WSEQ_EOS11_MASK 0x0100 /* WSEQ_EOS11 */
4653#define WM8995_WSEQ_EOS11_SHIFT 8 /* WSEQ_EOS11 */
4654#define WM8995_WSEQ_EOS11_WIDTH 1 /* WSEQ_EOS11 */
4655#define WM8995_WSEQ_DELAY11_MASK 0x000F /* WSEQ_DELAY11 - [3:0] */
4656#define WM8995_WSEQ_DELAY11_SHIFT 0 /* WSEQ_DELAY11 - [3:0] */
4657#define WM8995_WSEQ_DELAY11_WIDTH 4 /* WSEQ_DELAY11 - [3:0] */
4658
4659/*
4660 * R12336 (0x3030) - Write Sequencer 48
4661 */
4662#define WM8995_WSEQ_ADDR12_MASK 0x3FFF /* WSEQ_ADDR12 - [13:0] */
4663#define WM8995_WSEQ_ADDR12_SHIFT 0 /* WSEQ_ADDR12 - [13:0] */
4664#define WM8995_WSEQ_ADDR12_WIDTH 14 /* WSEQ_ADDR12 - [13:0] */
4665
4666/*
4667 * R12337 (0x3031) - Write Sequencer 49
4668 */
4669#define WM8995_WSEQ_DATA12_MASK 0x00FF /* WSEQ_DATA12 - [7:0] */
4670#define WM8995_WSEQ_DATA12_SHIFT 0 /* WSEQ_DATA12 - [7:0] */
4671#define WM8995_WSEQ_DATA12_WIDTH 8 /* WSEQ_DATA12 - [7:0] */
4672
4673/*
4674 * R12338 (0x3032) - Write Sequencer 50
4675 */
4676#define WM8995_WSEQ_DATA_WIDTH12_MASK 0x0700 /* WSEQ_DATA_WIDTH12 - [10:8] */
4677#define WM8995_WSEQ_DATA_WIDTH12_SHIFT 8 /* WSEQ_DATA_WIDTH12 - [10:8] */
4678#define WM8995_WSEQ_DATA_WIDTH12_WIDTH 3 /* WSEQ_DATA_WIDTH12 - [10:8] */
4679#define WM8995_WSEQ_DATA_START12_MASK 0x000F /* WSEQ_DATA_START12 - [3:0] */
4680#define WM8995_WSEQ_DATA_START12_SHIFT 0 /* WSEQ_DATA_START12 - [3:0] */
4681#define WM8995_WSEQ_DATA_START12_WIDTH 4 /* WSEQ_DATA_START12 - [3:0] */
4682
4683/*
4684 * R12339 (0x3033) - Write Sequencer 51
4685 */
4686#define WM8995_WSEQ_EOS12 0x0100 /* WSEQ_EOS12 */
4687#define WM8995_WSEQ_EOS12_MASK 0x0100 /* WSEQ_EOS12 */
4688#define WM8995_WSEQ_EOS12_SHIFT 8 /* WSEQ_EOS12 */
4689#define WM8995_WSEQ_EOS12_WIDTH 1 /* WSEQ_EOS12 */
4690#define WM8995_WSEQ_DELAY12_MASK 0x000F /* WSEQ_DELAY12 - [3:0] */
4691#define WM8995_WSEQ_DELAY12_SHIFT 0 /* WSEQ_DELAY12 - [3:0] */
4692#define WM8995_WSEQ_DELAY12_WIDTH 4 /* WSEQ_DELAY12 - [3:0] */
4693
4694/*
4695 * R12340 (0x3034) - Write Sequencer 52
4696 */
4697#define WM8995_WSEQ_ADDR13_MASK 0x3FFF /* WSEQ_ADDR13 - [13:0] */
4698#define WM8995_WSEQ_ADDR13_SHIFT 0 /* WSEQ_ADDR13 - [13:0] */
4699#define WM8995_WSEQ_ADDR13_WIDTH 14 /* WSEQ_ADDR13 - [13:0] */
4700
4701/*
4702 * R12341 (0x3035) - Write Sequencer 53
4703 */
4704#define WM8995_WSEQ_DATA13_MASK 0x00FF /* WSEQ_DATA13 - [7:0] */
4705#define WM8995_WSEQ_DATA13_SHIFT 0 /* WSEQ_DATA13 - [7:0] */
4706#define WM8995_WSEQ_DATA13_WIDTH 8 /* WSEQ_DATA13 - [7:0] */
4707
4708/*
4709 * R12342 (0x3036) - Write Sequencer 54
4710 */
4711#define WM8995_WSEQ_DATA_WIDTH13_MASK 0x0700 /* WSEQ_DATA_WIDTH13 - [10:8] */
4712#define WM8995_WSEQ_DATA_WIDTH13_SHIFT 8 /* WSEQ_DATA_WIDTH13 - [10:8] */
4713#define WM8995_WSEQ_DATA_WIDTH13_WIDTH 3 /* WSEQ_DATA_WIDTH13 - [10:8] */
4714#define WM8995_WSEQ_DATA_START13_MASK 0x000F /* WSEQ_DATA_START13 - [3:0] */
4715#define WM8995_WSEQ_DATA_START13_SHIFT 0 /* WSEQ_DATA_START13 - [3:0] */
4716#define WM8995_WSEQ_DATA_START13_WIDTH 4 /* WSEQ_DATA_START13 - [3:0] */
4717
4718/*
4719 * R12343 (0x3037) - Write Sequencer 55
4720 */
4721#define WM8995_WSEQ_EOS13 0x0100 /* WSEQ_EOS13 */
4722#define WM8995_WSEQ_EOS13_MASK 0x0100 /* WSEQ_EOS13 */
4723#define WM8995_WSEQ_EOS13_SHIFT 8 /* WSEQ_EOS13 */
4724#define WM8995_WSEQ_EOS13_WIDTH 1 /* WSEQ_EOS13 */
4725#define WM8995_WSEQ_DELAY13_MASK 0x000F /* WSEQ_DELAY13 - [3:0] */
4726#define WM8995_WSEQ_DELAY13_SHIFT 0 /* WSEQ_DELAY13 - [3:0] */
4727#define WM8995_WSEQ_DELAY13_WIDTH 4 /* WSEQ_DELAY13 - [3:0] */
4728
4729/*
4730 * R12344 (0x3038) - Write Sequencer 56
4731 */
4732#define WM8995_WSEQ_ADDR14_MASK 0x3FFF /* WSEQ_ADDR14 - [13:0] */
4733#define WM8995_WSEQ_ADDR14_SHIFT 0 /* WSEQ_ADDR14 - [13:0] */
4734#define WM8995_WSEQ_ADDR14_WIDTH 14 /* WSEQ_ADDR14 - [13:0] */
4735
4736/*
4737 * R12345 (0x3039) - Write Sequencer 57
4738 */
4739#define WM8995_WSEQ_DATA14_MASK 0x00FF /* WSEQ_DATA14 - [7:0] */
4740#define WM8995_WSEQ_DATA14_SHIFT 0 /* WSEQ_DATA14 - [7:0] */
4741#define WM8995_WSEQ_DATA14_WIDTH 8 /* WSEQ_DATA14 - [7:0] */
4742
4743/*
4744 * R12346 (0x303A) - Write Sequencer 58
4745 */
4746#define WM8995_WSEQ_DATA_WIDTH14_MASK 0x0700 /* WSEQ_DATA_WIDTH14 - [10:8] */
4747#define WM8995_WSEQ_DATA_WIDTH14_SHIFT 8 /* WSEQ_DATA_WIDTH14 - [10:8] */
4748#define WM8995_WSEQ_DATA_WIDTH14_WIDTH 3 /* WSEQ_DATA_WIDTH14 - [10:8] */
4749#define WM8995_WSEQ_DATA_START14_MASK 0x000F /* WSEQ_DATA_START14 - [3:0] */
4750#define WM8995_WSEQ_DATA_START14_SHIFT 0 /* WSEQ_DATA_START14 - [3:0] */
4751#define WM8995_WSEQ_DATA_START14_WIDTH 4 /* WSEQ_DATA_START14 - [3:0] */
4752
4753/*
4754 * R12347 (0x303B) - Write Sequencer 59
4755 */
4756#define WM8995_WSEQ_EOS14 0x0100 /* WSEQ_EOS14 */
4757#define WM8995_WSEQ_EOS14_MASK 0x0100 /* WSEQ_EOS14 */
4758#define WM8995_WSEQ_EOS14_SHIFT 8 /* WSEQ_EOS14 */
4759#define WM8995_WSEQ_EOS14_WIDTH 1 /* WSEQ_EOS14 */
4760#define WM8995_WSEQ_DELAY14_MASK 0x000F /* WSEQ_DELAY14 - [3:0] */
4761#define WM8995_WSEQ_DELAY14_SHIFT 0 /* WSEQ_DELAY14 - [3:0] */
4762#define WM8995_WSEQ_DELAY14_WIDTH 4 /* WSEQ_DELAY14 - [3:0] */
4763
4764/*
4765 * R12348 (0x303C) - Write Sequencer 60
4766 */
4767#define WM8995_WSEQ_ADDR15_MASK 0x3FFF /* WSEQ_ADDR15 - [13:0] */
4768#define WM8995_WSEQ_ADDR15_SHIFT 0 /* WSEQ_ADDR15 - [13:0] */
4769#define WM8995_WSEQ_ADDR15_WIDTH 14 /* WSEQ_ADDR15 - [13:0] */
4770
4771/*
4772 * R12349 (0x303D) - Write Sequencer 61
4773 */
4774#define WM8995_WSEQ_DATA15_MASK 0x00FF /* WSEQ_DATA15 - [7:0] */
4775#define WM8995_WSEQ_DATA15_SHIFT 0 /* WSEQ_DATA15 - [7:0] */
4776#define WM8995_WSEQ_DATA15_WIDTH 8 /* WSEQ_DATA15 - [7:0] */
4777
4778/*
4779 * R12350 (0x303E) - Write Sequencer 62
4780 */
4781#define WM8995_WSEQ_DATA_WIDTH15_MASK 0x0700 /* WSEQ_DATA_WIDTH15 - [10:8] */
4782#define WM8995_WSEQ_DATA_WIDTH15_SHIFT 8 /* WSEQ_DATA_WIDTH15 - [10:8] */
4783#define WM8995_WSEQ_DATA_WIDTH15_WIDTH 3 /* WSEQ_DATA_WIDTH15 - [10:8] */
4784#define WM8995_WSEQ_DATA_START15_MASK 0x000F /* WSEQ_DATA_START15 - [3:0] */
4785#define WM8995_WSEQ_DATA_START15_SHIFT 0 /* WSEQ_DATA_START15 - [3:0] */
4786#define WM8995_WSEQ_DATA_START15_WIDTH 4 /* WSEQ_DATA_START15 - [3:0] */
4787
4788/*
4789 * R12351 (0x303F) - Write Sequencer 63
4790 */
4791#define WM8995_WSEQ_EOS15 0x0100 /* WSEQ_EOS15 */
4792#define WM8995_WSEQ_EOS15_MASK 0x0100 /* WSEQ_EOS15 */
4793#define WM8995_WSEQ_EOS15_SHIFT 8 /* WSEQ_EOS15 */
4794#define WM8995_WSEQ_EOS15_WIDTH 1 /* WSEQ_EOS15 */
4795#define WM8995_WSEQ_DELAY15_MASK 0x000F /* WSEQ_DELAY15 - [3:0] */
4796#define WM8995_WSEQ_DELAY15_SHIFT 0 /* WSEQ_DELAY15 - [3:0] */
4797#define WM8995_WSEQ_DELAY15_WIDTH 4 /* WSEQ_DELAY15 - [3:0] */
4798
4799/*
4800 * R12352 (0x3040) - Write Sequencer 64
4801 */
4802#define WM8995_WSEQ_ADDR16_MASK 0x3FFF /* WSEQ_ADDR16 - [13:0] */
4803#define WM8995_WSEQ_ADDR16_SHIFT 0 /* WSEQ_ADDR16 - [13:0] */
4804#define WM8995_WSEQ_ADDR16_WIDTH 14 /* WSEQ_ADDR16 - [13:0] */
4805
4806/*
4807 * R12353 (0x3041) - Write Sequencer 65
4808 */
4809#define WM8995_WSEQ_DATA16_MASK 0x00FF /* WSEQ_DATA16 - [7:0] */
4810#define WM8995_WSEQ_DATA16_SHIFT 0 /* WSEQ_DATA16 - [7:0] */
4811#define WM8995_WSEQ_DATA16_WIDTH 8 /* WSEQ_DATA16 - [7:0] */
4812
4813/*
4814 * R12354 (0x3042) - Write Sequencer 66
4815 */
4816#define WM8995_WSEQ_DATA_WIDTH16_MASK 0x0700 /* WSEQ_DATA_WIDTH16 - [10:8] */
4817#define WM8995_WSEQ_DATA_WIDTH16_SHIFT 8 /* WSEQ_DATA_WIDTH16 - [10:8] */
4818#define WM8995_WSEQ_DATA_WIDTH16_WIDTH 3 /* WSEQ_DATA_WIDTH16 - [10:8] */
4819#define WM8995_WSEQ_DATA_START16_MASK 0x000F /* WSEQ_DATA_START16 - [3:0] */
4820#define WM8995_WSEQ_DATA_START16_SHIFT 0 /* WSEQ_DATA_START16 - [3:0] */
4821#define WM8995_WSEQ_DATA_START16_WIDTH 4 /* WSEQ_DATA_START16 - [3:0] */
4822
4823/*
4824 * R12355 (0x3043) - Write Sequencer 67
4825 */
4826#define WM8995_WSEQ_EOS16 0x0100 /* WSEQ_EOS16 */
4827#define WM8995_WSEQ_EOS16_MASK 0x0100 /* WSEQ_EOS16 */
4828#define WM8995_WSEQ_EOS16_SHIFT 8 /* WSEQ_EOS16 */
4829#define WM8995_WSEQ_EOS16_WIDTH 1 /* WSEQ_EOS16 */
4830#define WM8995_WSEQ_DELAY16_MASK 0x000F /* WSEQ_DELAY16 - [3:0] */
4831#define WM8995_WSEQ_DELAY16_SHIFT 0 /* WSEQ_DELAY16 - [3:0] */
4832#define WM8995_WSEQ_DELAY16_WIDTH 4 /* WSEQ_DELAY16 - [3:0] */
4833
4834/*
4835 * R12356 (0x3044) - Write Sequencer 68
4836 */
4837#define WM8995_WSEQ_ADDR17_MASK 0x3FFF /* WSEQ_ADDR17 - [13:0] */
4838#define WM8995_WSEQ_ADDR17_SHIFT 0 /* WSEQ_ADDR17 - [13:0] */
4839#define WM8995_WSEQ_ADDR17_WIDTH 14 /* WSEQ_ADDR17 - [13:0] */
4840
4841/*
4842 * R12357 (0x3045) - Write Sequencer 69
4843 */
4844#define WM8995_WSEQ_DATA17_MASK 0x00FF /* WSEQ_DATA17 - [7:0] */
4845#define WM8995_WSEQ_DATA17_SHIFT 0 /* WSEQ_DATA17 - [7:0] */
4846#define WM8995_WSEQ_DATA17_WIDTH 8 /* WSEQ_DATA17 - [7:0] */
4847
4848/*
4849 * R12358 (0x3046) - Write Sequencer 70
4850 */
4851#define WM8995_WSEQ_DATA_WIDTH17_MASK 0x0700 /* WSEQ_DATA_WIDTH17 - [10:8] */
4852#define WM8995_WSEQ_DATA_WIDTH17_SHIFT 8 /* WSEQ_DATA_WIDTH17 - [10:8] */
4853#define WM8995_WSEQ_DATA_WIDTH17_WIDTH 3 /* WSEQ_DATA_WIDTH17 - [10:8] */
4854#define WM8995_WSEQ_DATA_START17_MASK 0x000F /* WSEQ_DATA_START17 - [3:0] */
4855#define WM8995_WSEQ_DATA_START17_SHIFT 0 /* WSEQ_DATA_START17 - [3:0] */
4856#define WM8995_WSEQ_DATA_START17_WIDTH 4 /* WSEQ_DATA_START17 - [3:0] */
4857
4858/*
4859 * R12359 (0x3047) - Write Sequencer 71
4860 */
4861#define WM8995_WSEQ_EOS17 0x0100 /* WSEQ_EOS17 */
4862#define WM8995_WSEQ_EOS17_MASK 0x0100 /* WSEQ_EOS17 */
4863#define WM8995_WSEQ_EOS17_SHIFT 8 /* WSEQ_EOS17 */
4864#define WM8995_WSEQ_EOS17_WIDTH 1 /* WSEQ_EOS17 */
4865#define WM8995_WSEQ_DELAY17_MASK 0x000F /* WSEQ_DELAY17 - [3:0] */
4866#define WM8995_WSEQ_DELAY17_SHIFT 0 /* WSEQ_DELAY17 - [3:0] */
4867#define WM8995_WSEQ_DELAY17_WIDTH 4 /* WSEQ_DELAY17 - [3:0] */
4868
4869/*
4870 * R12360 (0x3048) - Write Sequencer 72
4871 */
4872#define WM8995_WSEQ_ADDR18_MASK 0x3FFF /* WSEQ_ADDR18 - [13:0] */
4873#define WM8995_WSEQ_ADDR18_SHIFT 0 /* WSEQ_ADDR18 - [13:0] */
4874#define WM8995_WSEQ_ADDR18_WIDTH 14 /* WSEQ_ADDR18 - [13:0] */
4875
4876/*
4877 * R12361 (0x3049) - Write Sequencer 73
4878 */
4879#define WM8995_WSEQ_DATA18_MASK 0x00FF /* WSEQ_DATA18 - [7:0] */
4880#define WM8995_WSEQ_DATA18_SHIFT 0 /* WSEQ_DATA18 - [7:0] */
4881#define WM8995_WSEQ_DATA18_WIDTH 8 /* WSEQ_DATA18 - [7:0] */
4882
4883/*
4884 * R12362 (0x304A) - Write Sequencer 74
4885 */
4886#define WM8995_WSEQ_DATA_WIDTH18_MASK 0x0700 /* WSEQ_DATA_WIDTH18 - [10:8] */
4887#define WM8995_WSEQ_DATA_WIDTH18_SHIFT 8 /* WSEQ_DATA_WIDTH18 - [10:8] */
4888#define WM8995_WSEQ_DATA_WIDTH18_WIDTH 3 /* WSEQ_DATA_WIDTH18 - [10:8] */
4889#define WM8995_WSEQ_DATA_START18_MASK 0x000F /* WSEQ_DATA_START18 - [3:0] */
4890#define WM8995_WSEQ_DATA_START18_SHIFT 0 /* WSEQ_DATA_START18 - [3:0] */
4891#define WM8995_WSEQ_DATA_START18_WIDTH 4 /* WSEQ_DATA_START18 - [3:0] */
4892
4893/*
4894 * R12363 (0x304B) - Write Sequencer 75
4895 */
4896#define WM8995_WSEQ_EOS18 0x0100 /* WSEQ_EOS18 */
4897#define WM8995_WSEQ_EOS18_MASK 0x0100 /* WSEQ_EOS18 */
4898#define WM8995_WSEQ_EOS18_SHIFT 8 /* WSEQ_EOS18 */
4899#define WM8995_WSEQ_EOS18_WIDTH 1 /* WSEQ_EOS18 */
4900#define WM8995_WSEQ_DELAY18_MASK 0x000F /* WSEQ_DELAY18 - [3:0] */
4901#define WM8995_WSEQ_DELAY18_SHIFT 0 /* WSEQ_DELAY18 - [3:0] */
4902#define WM8995_WSEQ_DELAY18_WIDTH 4 /* WSEQ_DELAY18 - [3:0] */
4903
4904/*
4905 * R12364 (0x304C) - Write Sequencer 76
4906 */
4907#define WM8995_WSEQ_ADDR19_MASK 0x3FFF /* WSEQ_ADDR19 - [13:0] */
4908#define WM8995_WSEQ_ADDR19_SHIFT 0 /* WSEQ_ADDR19 - [13:0] */
4909#define WM8995_WSEQ_ADDR19_WIDTH 14 /* WSEQ_ADDR19 - [13:0] */
4910
4911/*
4912 * R12365 (0x304D) - Write Sequencer 77
4913 */
4914#define WM8995_WSEQ_DATA19_MASK 0x00FF /* WSEQ_DATA19 - [7:0] */
4915#define WM8995_WSEQ_DATA19_SHIFT 0 /* WSEQ_DATA19 - [7:0] */
4916#define WM8995_WSEQ_DATA19_WIDTH 8 /* WSEQ_DATA19 - [7:0] */
4917
4918/*
4919 * R12366 (0x304E) - Write Sequencer 78
4920 */
4921#define WM8995_WSEQ_DATA_WIDTH19_MASK 0x0700 /* WSEQ_DATA_WIDTH19 - [10:8] */
4922#define WM8995_WSEQ_DATA_WIDTH19_SHIFT 8 /* WSEQ_DATA_WIDTH19 - [10:8] */
4923#define WM8995_WSEQ_DATA_WIDTH19_WIDTH 3 /* WSEQ_DATA_WIDTH19 - [10:8] */
4924#define WM8995_WSEQ_DATA_START19_MASK 0x000F /* WSEQ_DATA_START19 - [3:0] */
4925#define WM8995_WSEQ_DATA_START19_SHIFT 0 /* WSEQ_DATA_START19 - [3:0] */
4926#define WM8995_WSEQ_DATA_START19_WIDTH 4 /* WSEQ_DATA_START19 - [3:0] */
4927
4928/*
4929 * R12367 (0x304F) - Write Sequencer 79
4930 */
4931#define WM8995_WSEQ_EOS19 0x0100 /* WSEQ_EOS19 */
4932#define WM8995_WSEQ_EOS19_MASK 0x0100 /* WSEQ_EOS19 */
4933#define WM8995_WSEQ_EOS19_SHIFT 8 /* WSEQ_EOS19 */
4934#define WM8995_WSEQ_EOS19_WIDTH 1 /* WSEQ_EOS19 */
4935#define WM8995_WSEQ_DELAY19_MASK 0x000F /* WSEQ_DELAY19 - [3:0] */
4936#define WM8995_WSEQ_DELAY19_SHIFT 0 /* WSEQ_DELAY19 - [3:0] */
4937#define WM8995_WSEQ_DELAY19_WIDTH 4 /* WSEQ_DELAY19 - [3:0] */
4938
4939/*
4940 * R12368 (0x3050) - Write Sequencer 80
4941 */
4942#define WM8995_WSEQ_ADDR20_MASK 0x3FFF /* WSEQ_ADDR20 - [13:0] */
4943#define WM8995_WSEQ_ADDR20_SHIFT 0 /* WSEQ_ADDR20 - [13:0] */
4944#define WM8995_WSEQ_ADDR20_WIDTH 14 /* WSEQ_ADDR20 - [13:0] */
4945
4946/*
4947 * R12369 (0x3051) - Write Sequencer 81
4948 */
4949#define WM8995_WSEQ_DATA20_MASK 0x00FF /* WSEQ_DATA20 - [7:0] */
4950#define WM8995_WSEQ_DATA20_SHIFT 0 /* WSEQ_DATA20 - [7:0] */
4951#define WM8995_WSEQ_DATA20_WIDTH 8 /* WSEQ_DATA20 - [7:0] */
4952
4953/*
4954 * R12370 (0x3052) - Write Sequencer 82
4955 */
4956#define WM8995_WSEQ_DATA_WIDTH20_MASK 0x0700 /* WSEQ_DATA_WIDTH20 - [10:8] */
4957#define WM8995_WSEQ_DATA_WIDTH20_SHIFT 8 /* WSEQ_DATA_WIDTH20 - [10:8] */
4958#define WM8995_WSEQ_DATA_WIDTH20_WIDTH 3 /* WSEQ_DATA_WIDTH20 - [10:8] */
4959#define WM8995_WSEQ_DATA_START20_MASK 0x000F /* WSEQ_DATA_START20 - [3:0] */
4960#define WM8995_WSEQ_DATA_START20_SHIFT 0 /* WSEQ_DATA_START20 - [3:0] */
4961#define WM8995_WSEQ_DATA_START20_WIDTH 4 /* WSEQ_DATA_START20 - [3:0] */
4962
4963/*
4964 * R12371 (0x3053) - Write Sequencer 83
4965 */
4966#define WM8995_WSEQ_EOS20 0x0100 /* WSEQ_EOS20 */
4967#define WM8995_WSEQ_EOS20_MASK 0x0100 /* WSEQ_EOS20 */
4968#define WM8995_WSEQ_EOS20_SHIFT 8 /* WSEQ_EOS20 */
4969#define WM8995_WSEQ_EOS20_WIDTH 1 /* WSEQ_EOS20 */
4970#define WM8995_WSEQ_DELAY20_MASK 0x000F /* WSEQ_DELAY20 - [3:0] */
4971#define WM8995_WSEQ_DELAY20_SHIFT 0 /* WSEQ_DELAY20 - [3:0] */
4972#define WM8995_WSEQ_DELAY20_WIDTH 4 /* WSEQ_DELAY20 - [3:0] */
4973
4974/*
4975 * R12372 (0x3054) - Write Sequencer 84
4976 */
4977#define WM8995_WSEQ_ADDR21_MASK 0x3FFF /* WSEQ_ADDR21 - [13:0] */
4978#define WM8995_WSEQ_ADDR21_SHIFT 0 /* WSEQ_ADDR21 - [13:0] */
4979#define WM8995_WSEQ_ADDR21_WIDTH 14 /* WSEQ_ADDR21 - [13:0] */
4980
4981/*
4982 * R12373 (0x3055) - Write Sequencer 85
4983 */
4984#define WM8995_WSEQ_DATA21_MASK 0x00FF /* WSEQ_DATA21 - [7:0] */
4985#define WM8995_WSEQ_DATA21_SHIFT 0 /* WSEQ_DATA21 - [7:0] */
4986#define WM8995_WSEQ_DATA21_WIDTH 8 /* WSEQ_DATA21 - [7:0] */
4987
4988/*
4989 * R12374 (0x3056) - Write Sequencer 86
4990 */
4991#define WM8995_WSEQ_DATA_WIDTH21_MASK 0x0700 /* WSEQ_DATA_WIDTH21 - [10:8] */
4992#define WM8995_WSEQ_DATA_WIDTH21_SHIFT 8 /* WSEQ_DATA_WIDTH21 - [10:8] */
4993#define WM8995_WSEQ_DATA_WIDTH21_WIDTH 3 /* WSEQ_DATA_WIDTH21 - [10:8] */
4994#define WM8995_WSEQ_DATA_START21_MASK 0x000F /* WSEQ_DATA_START21 - [3:0] */
4995#define WM8995_WSEQ_DATA_START21_SHIFT 0 /* WSEQ_DATA_START21 - [3:0] */
4996#define WM8995_WSEQ_DATA_START21_WIDTH 4 /* WSEQ_DATA_START21 - [3:0] */
4997
4998/*
4999 * R12375 (0x3057) - Write Sequencer 87
5000 */
5001#define WM8995_WSEQ_EOS21 0x0100 /* WSEQ_EOS21 */
5002#define WM8995_WSEQ_EOS21_MASK 0x0100 /* WSEQ_EOS21 */
5003#define WM8995_WSEQ_EOS21_SHIFT 8 /* WSEQ_EOS21 */
5004#define WM8995_WSEQ_EOS21_WIDTH 1 /* WSEQ_EOS21 */
5005#define WM8995_WSEQ_DELAY21_MASK 0x000F /* WSEQ_DELAY21 - [3:0] */
5006#define WM8995_WSEQ_DELAY21_SHIFT 0 /* WSEQ_DELAY21 - [3:0] */
5007#define WM8995_WSEQ_DELAY21_WIDTH 4 /* WSEQ_DELAY21 - [3:0] */
5008
5009/*
5010 * R12376 (0x3058) - Write Sequencer 88
5011 */
5012#define WM8995_WSEQ_ADDR22_MASK 0x3FFF /* WSEQ_ADDR22 - [13:0] */
5013#define WM8995_WSEQ_ADDR22_SHIFT 0 /* WSEQ_ADDR22 - [13:0] */
5014#define WM8995_WSEQ_ADDR22_WIDTH 14 /* WSEQ_ADDR22 - [13:0] */
5015
5016/*
5017 * R12377 (0x3059) - Write Sequencer 89
5018 */
5019#define WM8995_WSEQ_DATA22_MASK 0x00FF /* WSEQ_DATA22 - [7:0] */
5020#define WM8995_WSEQ_DATA22_SHIFT 0 /* WSEQ_DATA22 - [7:0] */
5021#define WM8995_WSEQ_DATA22_WIDTH 8 /* WSEQ_DATA22 - [7:0] */
5022
5023/*
5024 * R12378 (0x305A) - Write Sequencer 90
5025 */
5026#define WM8995_WSEQ_DATA_WIDTH22_MASK 0x0700 /* WSEQ_DATA_WIDTH22 - [10:8] */
5027#define WM8995_WSEQ_DATA_WIDTH22_SHIFT 8 /* WSEQ_DATA_WIDTH22 - [10:8] */
5028#define WM8995_WSEQ_DATA_WIDTH22_WIDTH 3 /* WSEQ_DATA_WIDTH22 - [10:8] */
5029#define WM8995_WSEQ_DATA_START22_MASK 0x000F /* WSEQ_DATA_START22 - [3:0] */
5030#define WM8995_WSEQ_DATA_START22_SHIFT 0 /* WSEQ_DATA_START22 - [3:0] */
5031#define WM8995_WSEQ_DATA_START22_WIDTH 4 /* WSEQ_DATA_START22 - [3:0] */
5032
5033/*
5034 * R12379 (0x305B) - Write Sequencer 91
5035 */
5036#define WM8995_WSEQ_EOS22 0x0100 /* WSEQ_EOS22 */
5037#define WM8995_WSEQ_EOS22_MASK 0x0100 /* WSEQ_EOS22 */
5038#define WM8995_WSEQ_EOS22_SHIFT 8 /* WSEQ_EOS22 */
5039#define WM8995_WSEQ_EOS22_WIDTH 1 /* WSEQ_EOS22 */
5040#define WM8995_WSEQ_DELAY22_MASK 0x000F /* WSEQ_DELAY22 - [3:0] */
5041#define WM8995_WSEQ_DELAY22_SHIFT 0 /* WSEQ_DELAY22 - [3:0] */
5042#define WM8995_WSEQ_DELAY22_WIDTH 4 /* WSEQ_DELAY22 - [3:0] */
5043
5044/*
5045 * R12380 (0x305C) - Write Sequencer 92
5046 */
5047#define WM8995_WSEQ_ADDR23_MASK 0x3FFF /* WSEQ_ADDR23 - [13:0] */
5048#define WM8995_WSEQ_ADDR23_SHIFT 0 /* WSEQ_ADDR23 - [13:0] */
5049#define WM8995_WSEQ_ADDR23_WIDTH 14 /* WSEQ_ADDR23 - [13:0] */
5050
5051/*
5052 * R12381 (0x305D) - Write Sequencer 93
5053 */
5054#define WM8995_WSEQ_DATA23_MASK 0x00FF /* WSEQ_DATA23 - [7:0] */
5055#define WM8995_WSEQ_DATA23_SHIFT 0 /* WSEQ_DATA23 - [7:0] */
5056#define WM8995_WSEQ_DATA23_WIDTH 8 /* WSEQ_DATA23 - [7:0] */
5057
5058/*
5059 * R12382 (0x305E) - Write Sequencer 94
5060 */
5061#define WM8995_WSEQ_DATA_WIDTH23_MASK 0x0700 /* WSEQ_DATA_WIDTH23 - [10:8] */
5062#define WM8995_WSEQ_DATA_WIDTH23_SHIFT 8 /* WSEQ_DATA_WIDTH23 - [10:8] */
5063#define WM8995_WSEQ_DATA_WIDTH23_WIDTH 3 /* WSEQ_DATA_WIDTH23 - [10:8] */
5064#define WM8995_WSEQ_DATA_START23_MASK 0x000F /* WSEQ_DATA_START23 - [3:0] */
5065#define WM8995_WSEQ_DATA_START23_SHIFT 0 /* WSEQ_DATA_START23 - [3:0] */
5066#define WM8995_WSEQ_DATA_START23_WIDTH 4 /* WSEQ_DATA_START23 - [3:0] */
5067
5068/*
5069 * R12383 (0x305F) - Write Sequencer 95
5070 */
5071#define WM8995_WSEQ_EOS23 0x0100 /* WSEQ_EOS23 */
5072#define WM8995_WSEQ_EOS23_MASK 0x0100 /* WSEQ_EOS23 */
5073#define WM8995_WSEQ_EOS23_SHIFT 8 /* WSEQ_EOS23 */
5074#define WM8995_WSEQ_EOS23_WIDTH 1 /* WSEQ_EOS23 */
5075#define WM8995_WSEQ_DELAY23_MASK 0x000F /* WSEQ_DELAY23 - [3:0] */
5076#define WM8995_WSEQ_DELAY23_SHIFT 0 /* WSEQ_DELAY23 - [3:0] */
5077#define WM8995_WSEQ_DELAY23_WIDTH 4 /* WSEQ_DELAY23 - [3:0] */
5078
5079/*
5080 * R12384 (0x3060) - Write Sequencer 96
5081 */
5082#define WM8995_WSEQ_ADDR24_MASK 0x3FFF /* WSEQ_ADDR24 - [13:0] */
5083#define WM8995_WSEQ_ADDR24_SHIFT 0 /* WSEQ_ADDR24 - [13:0] */
5084#define WM8995_WSEQ_ADDR24_WIDTH 14 /* WSEQ_ADDR24 - [13:0] */
5085
5086/*
5087 * R12385 (0x3061) - Write Sequencer 97
5088 */
5089#define WM8995_WSEQ_DATA24_MASK 0x00FF /* WSEQ_DATA24 - [7:0] */
5090#define WM8995_WSEQ_DATA24_SHIFT 0 /* WSEQ_DATA24 - [7:0] */
5091#define WM8995_WSEQ_DATA24_WIDTH 8 /* WSEQ_DATA24 - [7:0] */
5092
5093/*
5094 * R12386 (0x3062) - Write Sequencer 98
5095 */
5096#define WM8995_WSEQ_DATA_WIDTH24_MASK 0x0700 /* WSEQ_DATA_WIDTH24 - [10:8] */
5097#define WM8995_WSEQ_DATA_WIDTH24_SHIFT 8 /* WSEQ_DATA_WIDTH24 - [10:8] */
5098#define WM8995_WSEQ_DATA_WIDTH24_WIDTH 3 /* WSEQ_DATA_WIDTH24 - [10:8] */
5099#define WM8995_WSEQ_DATA_START24_MASK 0x000F /* WSEQ_DATA_START24 - [3:0] */
5100#define WM8995_WSEQ_DATA_START24_SHIFT 0 /* WSEQ_DATA_START24 - [3:0] */
5101#define WM8995_WSEQ_DATA_START24_WIDTH 4 /* WSEQ_DATA_START24 - [3:0] */
5102
5103/*
5104 * R12387 (0x3063) - Write Sequencer 99
5105 */
5106#define WM8995_WSEQ_EOS24 0x0100 /* WSEQ_EOS24 */
5107#define WM8995_WSEQ_EOS24_MASK 0x0100 /* WSEQ_EOS24 */
5108#define WM8995_WSEQ_EOS24_SHIFT 8 /* WSEQ_EOS24 */
5109#define WM8995_WSEQ_EOS24_WIDTH 1 /* WSEQ_EOS24 */
5110#define WM8995_WSEQ_DELAY24_MASK 0x000F /* WSEQ_DELAY24 - [3:0] */
5111#define WM8995_WSEQ_DELAY24_SHIFT 0 /* WSEQ_DELAY24 - [3:0] */
5112#define WM8995_WSEQ_DELAY24_WIDTH 4 /* WSEQ_DELAY24 - [3:0] */
5113
5114/*
5115 * R12388 (0x3064) - Write Sequencer 100
5116 */
5117#define WM8995_WSEQ_ADDR25_MASK 0x3FFF /* WSEQ_ADDR25 - [13:0] */
5118#define WM8995_WSEQ_ADDR25_SHIFT 0 /* WSEQ_ADDR25 - [13:0] */
5119#define WM8995_WSEQ_ADDR25_WIDTH 14 /* WSEQ_ADDR25 - [13:0] */
5120
5121/*
5122 * R12389 (0x3065) - Write Sequencer 101
5123 */
5124#define WM8995_WSEQ_DATA25_MASK 0x00FF /* WSEQ_DATA25 - [7:0] */
5125#define WM8995_WSEQ_DATA25_SHIFT 0 /* WSEQ_DATA25 - [7:0] */
5126#define WM8995_WSEQ_DATA25_WIDTH 8 /* WSEQ_DATA25 - [7:0] */
5127
5128/*
5129 * R12390 (0x3066) - Write Sequencer 102
5130 */
5131#define WM8995_WSEQ_DATA_WIDTH25_MASK 0x0700 /* WSEQ_DATA_WIDTH25 - [10:8] */
5132#define WM8995_WSEQ_DATA_WIDTH25_SHIFT 8 /* WSEQ_DATA_WIDTH25 - [10:8] */
5133#define WM8995_WSEQ_DATA_WIDTH25_WIDTH 3 /* WSEQ_DATA_WIDTH25 - [10:8] */
5134#define WM8995_WSEQ_DATA_START25_MASK 0x000F /* WSEQ_DATA_START25 - [3:0] */
5135#define WM8995_WSEQ_DATA_START25_SHIFT 0 /* WSEQ_DATA_START25 - [3:0] */
5136#define WM8995_WSEQ_DATA_START25_WIDTH 4 /* WSEQ_DATA_START25 - [3:0] */
5137
5138/*
5139 * R12391 (0x3067) - Write Sequencer 103
5140 */
5141#define WM8995_WSEQ_EOS25 0x0100 /* WSEQ_EOS25 */
5142#define WM8995_WSEQ_EOS25_MASK 0x0100 /* WSEQ_EOS25 */
5143#define WM8995_WSEQ_EOS25_SHIFT 8 /* WSEQ_EOS25 */
5144#define WM8995_WSEQ_EOS25_WIDTH 1 /* WSEQ_EOS25 */
5145#define WM8995_WSEQ_DELAY25_MASK 0x000F /* WSEQ_DELAY25 - [3:0] */
5146#define WM8995_WSEQ_DELAY25_SHIFT 0 /* WSEQ_DELAY25 - [3:0] */
5147#define WM8995_WSEQ_DELAY25_WIDTH 4 /* WSEQ_DELAY25 - [3:0] */
5148
5149/*
5150 * R12392 (0x3068) - Write Sequencer 104
5151 */
5152#define WM8995_WSEQ_ADDR26_MASK 0x3FFF /* WSEQ_ADDR26 - [13:0] */
5153#define WM8995_WSEQ_ADDR26_SHIFT 0 /* WSEQ_ADDR26 - [13:0] */
5154#define WM8995_WSEQ_ADDR26_WIDTH 14 /* WSEQ_ADDR26 - [13:0] */
5155
5156/*
5157 * R12393 (0x3069) - Write Sequencer 105
5158 */
5159#define WM8995_WSEQ_DATA26_MASK 0x00FF /* WSEQ_DATA26 - [7:0] */
5160#define WM8995_WSEQ_DATA26_SHIFT 0 /* WSEQ_DATA26 - [7:0] */
5161#define WM8995_WSEQ_DATA26_WIDTH 8 /* WSEQ_DATA26 - [7:0] */
5162
5163/*
5164 * R12394 (0x306A) - Write Sequencer 106
5165 */
5166#define WM8995_WSEQ_DATA_WIDTH26_MASK 0x0700 /* WSEQ_DATA_WIDTH26 - [10:8] */
5167#define WM8995_WSEQ_DATA_WIDTH26_SHIFT 8 /* WSEQ_DATA_WIDTH26 - [10:8] */
5168#define WM8995_WSEQ_DATA_WIDTH26_WIDTH 3 /* WSEQ_DATA_WIDTH26 - [10:8] */
5169#define WM8995_WSEQ_DATA_START26_MASK 0x000F /* WSEQ_DATA_START26 - [3:0] */
5170#define WM8995_WSEQ_DATA_START26_SHIFT 0 /* WSEQ_DATA_START26 - [3:0] */
5171#define WM8995_WSEQ_DATA_START26_WIDTH 4 /* WSEQ_DATA_START26 - [3:0] */
5172
5173/*
5174 * R12395 (0x306B) - Write Sequencer 107
5175 */
5176#define WM8995_WSEQ_EOS26 0x0100 /* WSEQ_EOS26 */
5177#define WM8995_WSEQ_EOS26_MASK 0x0100 /* WSEQ_EOS26 */
5178#define WM8995_WSEQ_EOS26_SHIFT 8 /* WSEQ_EOS26 */
5179#define WM8995_WSEQ_EOS26_WIDTH 1 /* WSEQ_EOS26 */
5180#define WM8995_WSEQ_DELAY26_MASK 0x000F /* WSEQ_DELAY26 - [3:0] */
5181#define WM8995_WSEQ_DELAY26_SHIFT 0 /* WSEQ_DELAY26 - [3:0] */
5182#define WM8995_WSEQ_DELAY26_WIDTH 4 /* WSEQ_DELAY26 - [3:0] */
5183
5184/*
5185 * R12396 (0x306C) - Write Sequencer 108
5186 */
5187#define WM8995_WSEQ_ADDR27_MASK 0x3FFF /* WSEQ_ADDR27 - [13:0] */
5188#define WM8995_WSEQ_ADDR27_SHIFT 0 /* WSEQ_ADDR27 - [13:0] */
5189#define WM8995_WSEQ_ADDR27_WIDTH 14 /* WSEQ_ADDR27 - [13:0] */
5190
5191/*
5192 * R12397 (0x306D) - Write Sequencer 109
5193 */
5194#define WM8995_WSEQ_DATA27_MASK 0x00FF /* WSEQ_DATA27 - [7:0] */
5195#define WM8995_WSEQ_DATA27_SHIFT 0 /* WSEQ_DATA27 - [7:0] */
5196#define WM8995_WSEQ_DATA27_WIDTH 8 /* WSEQ_DATA27 - [7:0] */
5197
5198/*
5199 * R12398 (0x306E) - Write Sequencer 110
5200 */
5201#define WM8995_WSEQ_DATA_WIDTH27_MASK 0x0700 /* WSEQ_DATA_WIDTH27 - [10:8] */
5202#define WM8995_WSEQ_DATA_WIDTH27_SHIFT 8 /* WSEQ_DATA_WIDTH27 - [10:8] */
5203#define WM8995_WSEQ_DATA_WIDTH27_WIDTH 3 /* WSEQ_DATA_WIDTH27 - [10:8] */
5204#define WM8995_WSEQ_DATA_START27_MASK 0x000F /* WSEQ_DATA_START27 - [3:0] */
5205#define WM8995_WSEQ_DATA_START27_SHIFT 0 /* WSEQ_DATA_START27 - [3:0] */
5206#define WM8995_WSEQ_DATA_START27_WIDTH 4 /* WSEQ_DATA_START27 - [3:0] */
5207
5208/*
5209 * R12399 (0x306F) - Write Sequencer 111
5210 */
5211#define WM8995_WSEQ_EOS27 0x0100 /* WSEQ_EOS27 */
5212#define WM8995_WSEQ_EOS27_MASK 0x0100 /* WSEQ_EOS27 */
5213#define WM8995_WSEQ_EOS27_SHIFT 8 /* WSEQ_EOS27 */
5214#define WM8995_WSEQ_EOS27_WIDTH 1 /* WSEQ_EOS27 */
5215#define WM8995_WSEQ_DELAY27_MASK 0x000F /* WSEQ_DELAY27 - [3:0] */
5216#define WM8995_WSEQ_DELAY27_SHIFT 0 /* WSEQ_DELAY27 - [3:0] */
5217#define WM8995_WSEQ_DELAY27_WIDTH 4 /* WSEQ_DELAY27 - [3:0] */
5218
5219/*
5220 * R12400 (0x3070) - Write Sequencer 112
5221 */
5222#define WM8995_WSEQ_ADDR28_MASK 0x3FFF /* WSEQ_ADDR28 - [13:0] */
5223#define WM8995_WSEQ_ADDR28_SHIFT 0 /* WSEQ_ADDR28 - [13:0] */
5224#define WM8995_WSEQ_ADDR28_WIDTH 14 /* WSEQ_ADDR28 - [13:0] */
5225
5226/*
5227 * R12401 (0x3071) - Write Sequencer 113
5228 */
5229#define WM8995_WSEQ_DATA28_MASK 0x00FF /* WSEQ_DATA28 - [7:0] */
5230#define WM8995_WSEQ_DATA28_SHIFT 0 /* WSEQ_DATA28 - [7:0] */
5231#define WM8995_WSEQ_DATA28_WIDTH 8 /* WSEQ_DATA28 - [7:0] */
5232
5233/*
5234 * R12402 (0x3072) - Write Sequencer 114
5235 */
5236#define WM8995_WSEQ_DATA_WIDTH28_MASK 0x0700 /* WSEQ_DATA_WIDTH28 - [10:8] */
5237#define WM8995_WSEQ_DATA_WIDTH28_SHIFT 8 /* WSEQ_DATA_WIDTH28 - [10:8] */
5238#define WM8995_WSEQ_DATA_WIDTH28_WIDTH 3 /* WSEQ_DATA_WIDTH28 - [10:8] */
5239#define WM8995_WSEQ_DATA_START28_MASK 0x000F /* WSEQ_DATA_START28 - [3:0] */
5240#define WM8995_WSEQ_DATA_START28_SHIFT 0 /* WSEQ_DATA_START28 - [3:0] */
5241#define WM8995_WSEQ_DATA_START28_WIDTH 4 /* WSEQ_DATA_START28 - [3:0] */
5242
5243/*
5244 * R12403 (0x3073) - Write Sequencer 115
5245 */
5246#define WM8995_WSEQ_EOS28 0x0100 /* WSEQ_EOS28 */
5247#define WM8995_WSEQ_EOS28_MASK 0x0100 /* WSEQ_EOS28 */
5248#define WM8995_WSEQ_EOS28_SHIFT 8 /* WSEQ_EOS28 */
5249#define WM8995_WSEQ_EOS28_WIDTH 1 /* WSEQ_EOS28 */
5250#define WM8995_WSEQ_DELAY28_MASK 0x000F /* WSEQ_DELAY28 - [3:0] */
5251#define WM8995_WSEQ_DELAY28_SHIFT 0 /* WSEQ_DELAY28 - [3:0] */
5252#define WM8995_WSEQ_DELAY28_WIDTH 4 /* WSEQ_DELAY28 - [3:0] */
5253
5254/*
5255 * R12404 (0x3074) - Write Sequencer 116
5256 */
5257#define WM8995_WSEQ_ADDR29_MASK 0x3FFF /* WSEQ_ADDR29 - [13:0] */
5258#define WM8995_WSEQ_ADDR29_SHIFT 0 /* WSEQ_ADDR29 - [13:0] */
5259#define WM8995_WSEQ_ADDR29_WIDTH 14 /* WSEQ_ADDR29 - [13:0] */
5260
5261/*
5262 * R12405 (0x3075) - Write Sequencer 117
5263 */
5264#define WM8995_WSEQ_DATA29_MASK 0x00FF /* WSEQ_DATA29 - [7:0] */
5265#define WM8995_WSEQ_DATA29_SHIFT 0 /* WSEQ_DATA29 - [7:0] */
5266#define WM8995_WSEQ_DATA29_WIDTH 8 /* WSEQ_DATA29 - [7:0] */
5267
5268/*
5269 * R12406 (0x3076) - Write Sequencer 118
5270 */
5271#define WM8995_WSEQ_DATA_WIDTH29_MASK 0x0700 /* WSEQ_DATA_WIDTH29 - [10:8] */
5272#define WM8995_WSEQ_DATA_WIDTH29_SHIFT 8 /* WSEQ_DATA_WIDTH29 - [10:8] */
5273#define WM8995_WSEQ_DATA_WIDTH29_WIDTH 3 /* WSEQ_DATA_WIDTH29 - [10:8] */
5274#define WM8995_WSEQ_DATA_START29_MASK 0x000F /* WSEQ_DATA_START29 - [3:0] */
5275#define WM8995_WSEQ_DATA_START29_SHIFT 0 /* WSEQ_DATA_START29 - [3:0] */
5276#define WM8995_WSEQ_DATA_START29_WIDTH 4 /* WSEQ_DATA_START29 - [3:0] */
5277
5278/*
5279 * R12407 (0x3077) - Write Sequencer 119
5280 */
5281#define WM8995_WSEQ_EOS29 0x0100 /* WSEQ_EOS29 */
5282#define WM8995_WSEQ_EOS29_MASK 0x0100 /* WSEQ_EOS29 */
5283#define WM8995_WSEQ_EOS29_SHIFT 8 /* WSEQ_EOS29 */
5284#define WM8995_WSEQ_EOS29_WIDTH 1 /* WSEQ_EOS29 */
5285#define WM8995_WSEQ_DELAY29_MASK 0x000F /* WSEQ_DELAY29 - [3:0] */
5286#define WM8995_WSEQ_DELAY29_SHIFT 0 /* WSEQ_DELAY29 - [3:0] */
5287#define WM8995_WSEQ_DELAY29_WIDTH 4 /* WSEQ_DELAY29 - [3:0] */
5288
5289/*
5290 * R12408 (0x3078) - Write Sequencer 120
5291 */
5292#define WM8995_WSEQ_ADDR30_MASK 0x3FFF /* WSEQ_ADDR30 - [13:0] */
5293#define WM8995_WSEQ_ADDR30_SHIFT 0 /* WSEQ_ADDR30 - [13:0] */
5294#define WM8995_WSEQ_ADDR30_WIDTH 14 /* WSEQ_ADDR30 - [13:0] */
5295
5296/*
5297 * R12409 (0x3079) - Write Sequencer 121
5298 */
5299#define WM8995_WSEQ_DATA30_MASK 0x00FF /* WSEQ_DATA30 - [7:0] */
5300#define WM8995_WSEQ_DATA30_SHIFT 0 /* WSEQ_DATA30 - [7:0] */
5301#define WM8995_WSEQ_DATA30_WIDTH 8 /* WSEQ_DATA30 - [7:0] */
5302
5303/*
5304 * R12410 (0x307A) - Write Sequencer 122
5305 */
5306#define WM8995_WSEQ_DATA_WIDTH30_MASK 0x0700 /* WSEQ_DATA_WIDTH30 - [10:8] */
5307#define WM8995_WSEQ_DATA_WIDTH30_SHIFT 8 /* WSEQ_DATA_WIDTH30 - [10:8] */
5308#define WM8995_WSEQ_DATA_WIDTH30_WIDTH 3 /* WSEQ_DATA_WIDTH30 - [10:8] */
5309#define WM8995_WSEQ_DATA_START30_MASK 0x000F /* WSEQ_DATA_START30 - [3:0] */
5310#define WM8995_WSEQ_DATA_START30_SHIFT 0 /* WSEQ_DATA_START30 - [3:0] */
5311#define WM8995_WSEQ_DATA_START30_WIDTH 4 /* WSEQ_DATA_START30 - [3:0] */
5312
5313/*
5314 * R12411 (0x307B) - Write Sequencer 123
5315 */
5316#define WM8995_WSEQ_EOS30 0x0100 /* WSEQ_EOS30 */
5317#define WM8995_WSEQ_EOS30_MASK 0x0100 /* WSEQ_EOS30 */
5318#define WM8995_WSEQ_EOS30_SHIFT 8 /* WSEQ_EOS30 */
5319#define WM8995_WSEQ_EOS30_WIDTH 1 /* WSEQ_EOS30 */
5320#define WM8995_WSEQ_DELAY30_MASK 0x000F /* WSEQ_DELAY30 - [3:0] */
5321#define WM8995_WSEQ_DELAY30_SHIFT 0 /* WSEQ_DELAY30 - [3:0] */
5322#define WM8995_WSEQ_DELAY30_WIDTH 4 /* WSEQ_DELAY30 - [3:0] */
5323
5324/*
5325 * R12412 (0x307C) - Write Sequencer 124
5326 */
5327#define WM8995_WSEQ_ADDR31_MASK 0x3FFF /* WSEQ_ADDR31 - [13:0] */
5328#define WM8995_WSEQ_ADDR31_SHIFT 0 /* WSEQ_ADDR31 - [13:0] */
5329#define WM8995_WSEQ_ADDR31_WIDTH 14 /* WSEQ_ADDR31 - [13:0] */
5330
5331/*
5332 * R12413 (0x307D) - Write Sequencer 125
5333 */
5334#define WM8995_WSEQ_DATA31_MASK 0x00FF /* WSEQ_DATA31 - [7:0] */
5335#define WM8995_WSEQ_DATA31_SHIFT 0 /* WSEQ_DATA31 - [7:0] */
5336#define WM8995_WSEQ_DATA31_WIDTH 8 /* WSEQ_DATA31 - [7:0] */
5337
5338/*
5339 * R12414 (0x307E) - Write Sequencer 126
5340 */
5341#define WM8995_WSEQ_DATA_WIDTH31_MASK 0x0700 /* WSEQ_DATA_WIDTH31 - [10:8] */
5342#define WM8995_WSEQ_DATA_WIDTH31_SHIFT 8 /* WSEQ_DATA_WIDTH31 - [10:8] */
5343#define WM8995_WSEQ_DATA_WIDTH31_WIDTH 3 /* WSEQ_DATA_WIDTH31 - [10:8] */
5344#define WM8995_WSEQ_DATA_START31_MASK 0x000F /* WSEQ_DATA_START31 - [3:0] */
5345#define WM8995_WSEQ_DATA_START31_SHIFT 0 /* WSEQ_DATA_START31 - [3:0] */
5346#define WM8995_WSEQ_DATA_START31_WIDTH 4 /* WSEQ_DATA_START31 - [3:0] */
5347
5348/*
5349 * R12415 (0x307F) - Write Sequencer 127
5350 */
5351#define WM8995_WSEQ_EOS31 0x0100 /* WSEQ_EOS31 */
5352#define WM8995_WSEQ_EOS31_MASK 0x0100 /* WSEQ_EOS31 */
5353#define WM8995_WSEQ_EOS31_SHIFT 8 /* WSEQ_EOS31 */
5354#define WM8995_WSEQ_EOS31_WIDTH 1 /* WSEQ_EOS31 */
5355#define WM8995_WSEQ_DELAY31_MASK 0x000F /* WSEQ_DELAY31 - [3:0] */
5356#define WM8995_WSEQ_DELAY31_SHIFT 0 /* WSEQ_DELAY31 - [3:0] */
5357#define WM8995_WSEQ_DELAY31_WIDTH 4 /* WSEQ_DELAY31 - [3:0] */
5358
5359/*
5360 * R12416 (0x3080) - Write Sequencer 128
5361 */
5362#define WM8995_WSEQ_ADDR32_MASK 0x3FFF /* WSEQ_ADDR32 - [13:0] */
5363#define WM8995_WSEQ_ADDR32_SHIFT 0 /* WSEQ_ADDR32 - [13:0] */
5364#define WM8995_WSEQ_ADDR32_WIDTH 14 /* WSEQ_ADDR32 - [13:0] */
5365
5366/*
5367 * R12417 (0x3081) - Write Sequencer 129
5368 */
5369#define WM8995_WSEQ_DATA32_MASK 0x00FF /* WSEQ_DATA32 - [7:0] */
5370#define WM8995_WSEQ_DATA32_SHIFT 0 /* WSEQ_DATA32 - [7:0] */
5371#define WM8995_WSEQ_DATA32_WIDTH 8 /* WSEQ_DATA32 - [7:0] */
5372
5373/*
5374 * R12418 (0x3082) - Write Sequencer 130
5375 */
5376#define WM8995_WSEQ_DATA_WIDTH32_MASK 0x0700 /* WSEQ_DATA_WIDTH32 - [10:8] */
5377#define WM8995_WSEQ_DATA_WIDTH32_SHIFT 8 /* WSEQ_DATA_WIDTH32 - [10:8] */
5378#define WM8995_WSEQ_DATA_WIDTH32_WIDTH 3 /* WSEQ_DATA_WIDTH32 - [10:8] */
5379#define WM8995_WSEQ_DATA_START32_MASK 0x000F /* WSEQ_DATA_START32 - [3:0] */
5380#define WM8995_WSEQ_DATA_START32_SHIFT 0 /* WSEQ_DATA_START32 - [3:0] */
5381#define WM8995_WSEQ_DATA_START32_WIDTH 4 /* WSEQ_DATA_START32 - [3:0] */
5382
5383/*
5384 * R12419 (0x3083) - Write Sequencer 131
5385 */
5386#define WM8995_WSEQ_EOS32 0x0100 /* WSEQ_EOS32 */
5387#define WM8995_WSEQ_EOS32_MASK 0x0100 /* WSEQ_EOS32 */
5388#define WM8995_WSEQ_EOS32_SHIFT 8 /* WSEQ_EOS32 */
5389#define WM8995_WSEQ_EOS32_WIDTH 1 /* WSEQ_EOS32 */
5390#define WM8995_WSEQ_DELAY32_MASK 0x000F /* WSEQ_DELAY32 - [3:0] */
5391#define WM8995_WSEQ_DELAY32_SHIFT 0 /* WSEQ_DELAY32 - [3:0] */
5392#define WM8995_WSEQ_DELAY32_WIDTH 4 /* WSEQ_DELAY32 - [3:0] */
5393
5394/*
5395 * R12420 (0x3084) - Write Sequencer 132
5396 */
5397#define WM8995_WSEQ_ADDR33_MASK 0x3FFF /* WSEQ_ADDR33 - [13:0] */
5398#define WM8995_WSEQ_ADDR33_SHIFT 0 /* WSEQ_ADDR33 - [13:0] */
5399#define WM8995_WSEQ_ADDR33_WIDTH 14 /* WSEQ_ADDR33 - [13:0] */
5400
5401/*
5402 * R12421 (0x3085) - Write Sequencer 133
5403 */
5404#define WM8995_WSEQ_DATA33_MASK 0x00FF /* WSEQ_DATA33 - [7:0] */
5405#define WM8995_WSEQ_DATA33_SHIFT 0 /* WSEQ_DATA33 - [7:0] */
5406#define WM8995_WSEQ_DATA33_WIDTH 8 /* WSEQ_DATA33 - [7:0] */
5407
5408/*
5409 * R12422 (0x3086) - Write Sequencer 134
5410 */
5411#define WM8995_WSEQ_DATA_WIDTH33_MASK 0x0700 /* WSEQ_DATA_WIDTH33 - [10:8] */
5412#define WM8995_WSEQ_DATA_WIDTH33_SHIFT 8 /* WSEQ_DATA_WIDTH33 - [10:8] */
5413#define WM8995_WSEQ_DATA_WIDTH33_WIDTH 3 /* WSEQ_DATA_WIDTH33 - [10:8] */
5414#define WM8995_WSEQ_DATA_START33_MASK 0x000F /* WSEQ_DATA_START33 - [3:0] */
5415#define WM8995_WSEQ_DATA_START33_SHIFT 0 /* WSEQ_DATA_START33 - [3:0] */
5416#define WM8995_WSEQ_DATA_START33_WIDTH 4 /* WSEQ_DATA_START33 - [3:0] */
5417
5418/*
5419 * R12423 (0x3087) - Write Sequencer 135
5420 */
5421#define WM8995_WSEQ_EOS33 0x0100 /* WSEQ_EOS33 */
5422#define WM8995_WSEQ_EOS33_MASK 0x0100 /* WSEQ_EOS33 */
5423#define WM8995_WSEQ_EOS33_SHIFT 8 /* WSEQ_EOS33 */
5424#define WM8995_WSEQ_EOS33_WIDTH 1 /* WSEQ_EOS33 */
5425#define WM8995_WSEQ_DELAY33_MASK 0x000F /* WSEQ_DELAY33 - [3:0] */
5426#define WM8995_WSEQ_DELAY33_SHIFT 0 /* WSEQ_DELAY33 - [3:0] */
5427#define WM8995_WSEQ_DELAY33_WIDTH 4 /* WSEQ_DELAY33 - [3:0] */
5428
5429/*
5430 * R12424 (0x3088) - Write Sequencer 136
5431 */
5432#define WM8995_WSEQ_ADDR34_MASK 0x3FFF /* WSEQ_ADDR34 - [13:0] */
5433#define WM8995_WSEQ_ADDR34_SHIFT 0 /* WSEQ_ADDR34 - [13:0] */
5434#define WM8995_WSEQ_ADDR34_WIDTH 14 /* WSEQ_ADDR34 - [13:0] */
5435
5436/*
5437 * R12425 (0x3089) - Write Sequencer 137
5438 */
5439#define WM8995_WSEQ_DATA34_MASK 0x00FF /* WSEQ_DATA34 - [7:0] */
5440#define WM8995_WSEQ_DATA34_SHIFT 0 /* WSEQ_DATA34 - [7:0] */
5441#define WM8995_WSEQ_DATA34_WIDTH 8 /* WSEQ_DATA34 - [7:0] */
5442
5443/*
5444 * R12426 (0x308A) - Write Sequencer 138
5445 */
5446#define WM8995_WSEQ_DATA_WIDTH34_MASK 0x0700 /* WSEQ_DATA_WIDTH34 - [10:8] */
5447#define WM8995_WSEQ_DATA_WIDTH34_SHIFT 8 /* WSEQ_DATA_WIDTH34 - [10:8] */
5448#define WM8995_WSEQ_DATA_WIDTH34_WIDTH 3 /* WSEQ_DATA_WIDTH34 - [10:8] */
5449#define WM8995_WSEQ_DATA_START34_MASK 0x000F /* WSEQ_DATA_START34 - [3:0] */
5450#define WM8995_WSEQ_DATA_START34_SHIFT 0 /* WSEQ_DATA_START34 - [3:0] */
5451#define WM8995_WSEQ_DATA_START34_WIDTH 4 /* WSEQ_DATA_START34 - [3:0] */
5452
5453/*
5454 * R12427 (0x308B) - Write Sequencer 139
5455 */
5456#define WM8995_WSEQ_EOS34 0x0100 /* WSEQ_EOS34 */
5457#define WM8995_WSEQ_EOS34_MASK 0x0100 /* WSEQ_EOS34 */
5458#define WM8995_WSEQ_EOS34_SHIFT 8 /* WSEQ_EOS34 */
5459#define WM8995_WSEQ_EOS34_WIDTH 1 /* WSEQ_EOS34 */
5460#define WM8995_WSEQ_DELAY34_MASK 0x000F /* WSEQ_DELAY34 - [3:0] */
5461#define WM8995_WSEQ_DELAY34_SHIFT 0 /* WSEQ_DELAY34 - [3:0] */
5462#define WM8995_WSEQ_DELAY34_WIDTH 4 /* WSEQ_DELAY34 - [3:0] */
5463
5464/*
5465 * R12428 (0x308C) - Write Sequencer 140
5466 */
5467#define WM8995_WSEQ_ADDR35_MASK 0x3FFF /* WSEQ_ADDR35 - [13:0] */
5468#define WM8995_WSEQ_ADDR35_SHIFT 0 /* WSEQ_ADDR35 - [13:0] */
5469#define WM8995_WSEQ_ADDR35_WIDTH 14 /* WSEQ_ADDR35 - [13:0] */
5470
5471/*
5472 * R12429 (0x308D) - Write Sequencer 141
5473 */
5474#define WM8995_WSEQ_DATA35_MASK 0x00FF /* WSEQ_DATA35 - [7:0] */
5475#define WM8995_WSEQ_DATA35_SHIFT 0 /* WSEQ_DATA35 - [7:0] */
5476#define WM8995_WSEQ_DATA35_WIDTH 8 /* WSEQ_DATA35 - [7:0] */
5477
5478/*
5479 * R12430 (0x308E) - Write Sequencer 142
5480 */
5481#define WM8995_WSEQ_DATA_WIDTH35_MASK 0x0700 /* WSEQ_DATA_WIDTH35 - [10:8] */
5482#define WM8995_WSEQ_DATA_WIDTH35_SHIFT 8 /* WSEQ_DATA_WIDTH35 - [10:8] */
5483#define WM8995_WSEQ_DATA_WIDTH35_WIDTH 3 /* WSEQ_DATA_WIDTH35 - [10:8] */
5484#define WM8995_WSEQ_DATA_START35_MASK 0x000F /* WSEQ_DATA_START35 - [3:0] */
5485#define WM8995_WSEQ_DATA_START35_SHIFT 0 /* WSEQ_DATA_START35 - [3:0] */
5486#define WM8995_WSEQ_DATA_START35_WIDTH 4 /* WSEQ_DATA_START35 - [3:0] */
5487
5488/*
5489 * R12431 (0x308F) - Write Sequencer 143
5490 */
5491#define WM8995_WSEQ_EOS35 0x0100 /* WSEQ_EOS35 */
5492#define WM8995_WSEQ_EOS35_MASK 0x0100 /* WSEQ_EOS35 */
5493#define WM8995_WSEQ_EOS35_SHIFT 8 /* WSEQ_EOS35 */
5494#define WM8995_WSEQ_EOS35_WIDTH 1 /* WSEQ_EOS35 */
5495#define WM8995_WSEQ_DELAY35_MASK 0x000F /* WSEQ_DELAY35 - [3:0] */
5496#define WM8995_WSEQ_DELAY35_SHIFT 0 /* WSEQ_DELAY35 - [3:0] */
5497#define WM8995_WSEQ_DELAY35_WIDTH 4 /* WSEQ_DELAY35 - [3:0] */
5498
5499/*
5500 * R12432 (0x3090) - Write Sequencer 144
5501 */
5502#define WM8995_WSEQ_ADDR36_MASK 0x3FFF /* WSEQ_ADDR36 - [13:0] */
5503#define WM8995_WSEQ_ADDR36_SHIFT 0 /* WSEQ_ADDR36 - [13:0] */
5504#define WM8995_WSEQ_ADDR36_WIDTH 14 /* WSEQ_ADDR36 - [13:0] */
5505
5506/*
5507 * R12433 (0x3091) - Write Sequencer 145
5508 */
5509#define WM8995_WSEQ_DATA36_MASK 0x00FF /* WSEQ_DATA36 - [7:0] */
5510#define WM8995_WSEQ_DATA36_SHIFT 0 /* WSEQ_DATA36 - [7:0] */
5511#define WM8995_WSEQ_DATA36_WIDTH 8 /* WSEQ_DATA36 - [7:0] */
5512
5513/*
5514 * R12434 (0x3092) - Write Sequencer 146
5515 */
5516#define WM8995_WSEQ_DATA_WIDTH36_MASK 0x0700 /* WSEQ_DATA_WIDTH36 - [10:8] */
5517#define WM8995_WSEQ_DATA_WIDTH36_SHIFT 8 /* WSEQ_DATA_WIDTH36 - [10:8] */
5518#define WM8995_WSEQ_DATA_WIDTH36_WIDTH 3 /* WSEQ_DATA_WIDTH36 - [10:8] */
5519#define WM8995_WSEQ_DATA_START36_MASK 0x000F /* WSEQ_DATA_START36 - [3:0] */
5520#define WM8995_WSEQ_DATA_START36_SHIFT 0 /* WSEQ_DATA_START36 - [3:0] */
5521#define WM8995_WSEQ_DATA_START36_WIDTH 4 /* WSEQ_DATA_START36 - [3:0] */
5522
5523/*
5524 * R12435 (0x3093) - Write Sequencer 147
5525 */
5526#define WM8995_WSEQ_EOS36 0x0100 /* WSEQ_EOS36 */
5527#define WM8995_WSEQ_EOS36_MASK 0x0100 /* WSEQ_EOS36 */
5528#define WM8995_WSEQ_EOS36_SHIFT 8 /* WSEQ_EOS36 */
5529#define WM8995_WSEQ_EOS36_WIDTH 1 /* WSEQ_EOS36 */
5530#define WM8995_WSEQ_DELAY36_MASK 0x000F /* WSEQ_DELAY36 - [3:0] */
5531#define WM8995_WSEQ_DELAY36_SHIFT 0 /* WSEQ_DELAY36 - [3:0] */
5532#define WM8995_WSEQ_DELAY36_WIDTH 4 /* WSEQ_DELAY36 - [3:0] */
5533
5534/*
5535 * R12436 (0x3094) - Write Sequencer 148
5536 */
5537#define WM8995_WSEQ_ADDR37_MASK 0x3FFF /* WSEQ_ADDR37 - [13:0] */
5538#define WM8995_WSEQ_ADDR37_SHIFT 0 /* WSEQ_ADDR37 - [13:0] */
5539#define WM8995_WSEQ_ADDR37_WIDTH 14 /* WSEQ_ADDR37 - [13:0] */
5540
5541/*
5542 * R12437 (0x3095) - Write Sequencer 149
5543 */
5544#define WM8995_WSEQ_DATA37_MASK 0x00FF /* WSEQ_DATA37 - [7:0] */
5545#define WM8995_WSEQ_DATA37_SHIFT 0 /* WSEQ_DATA37 - [7:0] */
5546#define WM8995_WSEQ_DATA37_WIDTH 8 /* WSEQ_DATA37 - [7:0] */
5547
5548/*
5549 * R12438 (0x3096) - Write Sequencer 150
5550 */
5551#define WM8995_WSEQ_DATA_WIDTH37_MASK 0x0700 /* WSEQ_DATA_WIDTH37 - [10:8] */
5552#define WM8995_WSEQ_DATA_WIDTH37_SHIFT 8 /* WSEQ_DATA_WIDTH37 - [10:8] */
5553#define WM8995_WSEQ_DATA_WIDTH37_WIDTH 3 /* WSEQ_DATA_WIDTH37 - [10:8] */
5554#define WM8995_WSEQ_DATA_START37_MASK 0x000F /* WSEQ_DATA_START37 - [3:0] */
5555#define WM8995_WSEQ_DATA_START37_SHIFT 0 /* WSEQ_DATA_START37 - [3:0] */
5556#define WM8995_WSEQ_DATA_START37_WIDTH 4 /* WSEQ_DATA_START37 - [3:0] */
5557
5558/*
5559 * R12439 (0x3097) - Write Sequencer 151
5560 */
5561#define WM8995_WSEQ_EOS37 0x0100 /* WSEQ_EOS37 */
5562#define WM8995_WSEQ_EOS37_MASK 0x0100 /* WSEQ_EOS37 */
5563#define WM8995_WSEQ_EOS37_SHIFT 8 /* WSEQ_EOS37 */
5564#define WM8995_WSEQ_EOS37_WIDTH 1 /* WSEQ_EOS37 */
5565#define WM8995_WSEQ_DELAY37_MASK 0x000F /* WSEQ_DELAY37 - [3:0] */
5566#define WM8995_WSEQ_DELAY37_SHIFT 0 /* WSEQ_DELAY37 - [3:0] */
5567#define WM8995_WSEQ_DELAY37_WIDTH 4 /* WSEQ_DELAY37 - [3:0] */
5568
5569/*
5570 * R12440 (0x3098) - Write Sequencer 152
5571 */
5572#define WM8995_WSEQ_ADDR38_MASK 0x3FFF /* WSEQ_ADDR38 - [13:0] */
5573#define WM8995_WSEQ_ADDR38_SHIFT 0 /* WSEQ_ADDR38 - [13:0] */
5574#define WM8995_WSEQ_ADDR38_WIDTH 14 /* WSEQ_ADDR38 - [13:0] */
5575
5576/*
5577 * R12441 (0x3099) - Write Sequencer 153
5578 */
5579#define WM8995_WSEQ_DATA38_MASK 0x00FF /* WSEQ_DATA38 - [7:0] */
5580#define WM8995_WSEQ_DATA38_SHIFT 0 /* WSEQ_DATA38 - [7:0] */
5581#define WM8995_WSEQ_DATA38_WIDTH 8 /* WSEQ_DATA38 - [7:0] */
5582
5583/*
5584 * R12442 (0x309A) - Write Sequencer 154
5585 */
5586#define WM8995_WSEQ_DATA_WIDTH38_MASK 0x0700 /* WSEQ_DATA_WIDTH38 - [10:8] */
5587#define WM8995_WSEQ_DATA_WIDTH38_SHIFT 8 /* WSEQ_DATA_WIDTH38 - [10:8] */
5588#define WM8995_WSEQ_DATA_WIDTH38_WIDTH 3 /* WSEQ_DATA_WIDTH38 - [10:8] */
5589#define WM8995_WSEQ_DATA_START38_MASK 0x000F /* WSEQ_DATA_START38 - [3:0] */
5590#define WM8995_WSEQ_DATA_START38_SHIFT 0 /* WSEQ_DATA_START38 - [3:0] */
5591#define WM8995_WSEQ_DATA_START38_WIDTH 4 /* WSEQ_DATA_START38 - [3:0] */
5592
5593/*
5594 * R12443 (0x309B) - Write Sequencer 155
5595 */
5596#define WM8995_WSEQ_EOS38 0x0100 /* WSEQ_EOS38 */
5597#define WM8995_WSEQ_EOS38_MASK 0x0100 /* WSEQ_EOS38 */
5598#define WM8995_WSEQ_EOS38_SHIFT 8 /* WSEQ_EOS38 */
5599#define WM8995_WSEQ_EOS38_WIDTH 1 /* WSEQ_EOS38 */
5600#define WM8995_WSEQ_DELAY38_MASK 0x000F /* WSEQ_DELAY38 - [3:0] */
5601#define WM8995_WSEQ_DELAY38_SHIFT 0 /* WSEQ_DELAY38 - [3:0] */
5602#define WM8995_WSEQ_DELAY38_WIDTH 4 /* WSEQ_DELAY38 - [3:0] */
5603
5604/*
5605 * R12444 (0x309C) - Write Sequencer 156
5606 */
5607#define WM8995_WSEQ_ADDR39_MASK 0x3FFF /* WSEQ_ADDR39 - [13:0] */
5608#define WM8995_WSEQ_ADDR39_SHIFT 0 /* WSEQ_ADDR39 - [13:0] */
5609#define WM8995_WSEQ_ADDR39_WIDTH 14 /* WSEQ_ADDR39 - [13:0] */
5610
5611/*
5612 * R12445 (0x309D) - Write Sequencer 157
5613 */
5614#define WM8995_WSEQ_DATA39_MASK 0x00FF /* WSEQ_DATA39 - [7:0] */
5615#define WM8995_WSEQ_DATA39_SHIFT 0 /* WSEQ_DATA39 - [7:0] */
5616#define WM8995_WSEQ_DATA39_WIDTH 8 /* WSEQ_DATA39 - [7:0] */
5617
5618/*
5619 * R12446 (0x309E) - Write Sequencer 158
5620 */
5621#define WM8995_WSEQ_DATA_WIDTH39_MASK 0x0700 /* WSEQ_DATA_WIDTH39 - [10:8] */
5622#define WM8995_WSEQ_DATA_WIDTH39_SHIFT 8 /* WSEQ_DATA_WIDTH39 - [10:8] */
5623#define WM8995_WSEQ_DATA_WIDTH39_WIDTH 3 /* WSEQ_DATA_WIDTH39 - [10:8] */
5624#define WM8995_WSEQ_DATA_START39_MASK 0x000F /* WSEQ_DATA_START39 - [3:0] */
5625#define WM8995_WSEQ_DATA_START39_SHIFT 0 /* WSEQ_DATA_START39 - [3:0] */
5626#define WM8995_WSEQ_DATA_START39_WIDTH 4 /* WSEQ_DATA_START39 - [3:0] */
5627
5628/*
5629 * R12447 (0x309F) - Write Sequencer 159
5630 */
5631#define WM8995_WSEQ_EOS39 0x0100 /* WSEQ_EOS39 */
5632#define WM8995_WSEQ_EOS39_MASK 0x0100 /* WSEQ_EOS39 */
5633#define WM8995_WSEQ_EOS39_SHIFT 8 /* WSEQ_EOS39 */
5634#define WM8995_WSEQ_EOS39_WIDTH 1 /* WSEQ_EOS39 */
5635#define WM8995_WSEQ_DELAY39_MASK 0x000F /* WSEQ_DELAY39 - [3:0] */
5636#define WM8995_WSEQ_DELAY39_SHIFT 0 /* WSEQ_DELAY39 - [3:0] */
5637#define WM8995_WSEQ_DELAY39_WIDTH 4 /* WSEQ_DELAY39 - [3:0] */
5638
5639/*
5640 * R12448 (0x30A0) - Write Sequencer 160
5641 */
5642#define WM8995_WSEQ_ADDR40_MASK 0x3FFF /* WSEQ_ADDR40 - [13:0] */
5643#define WM8995_WSEQ_ADDR40_SHIFT 0 /* WSEQ_ADDR40 - [13:0] */
5644#define WM8995_WSEQ_ADDR40_WIDTH 14 /* WSEQ_ADDR40 - [13:0] */
5645
5646/*
5647 * R12449 (0x30A1) - Write Sequencer 161
5648 */
5649#define WM8995_WSEQ_DATA40_MASK 0x00FF /* WSEQ_DATA40 - [7:0] */
5650#define WM8995_WSEQ_DATA40_SHIFT 0 /* WSEQ_DATA40 - [7:0] */
5651#define WM8995_WSEQ_DATA40_WIDTH 8 /* WSEQ_DATA40 - [7:0] */
5652
5653/*
5654 * R12450 (0x30A2) - Write Sequencer 162
5655 */
5656#define WM8995_WSEQ_DATA_WIDTH40_MASK 0x0700 /* WSEQ_DATA_WIDTH40 - [10:8] */
5657#define WM8995_WSEQ_DATA_WIDTH40_SHIFT 8 /* WSEQ_DATA_WIDTH40 - [10:8] */
5658#define WM8995_WSEQ_DATA_WIDTH40_WIDTH 3 /* WSEQ_DATA_WIDTH40 - [10:8] */
5659#define WM8995_WSEQ_DATA_START40_MASK 0x000F /* WSEQ_DATA_START40 - [3:0] */
5660#define WM8995_WSEQ_DATA_START40_SHIFT 0 /* WSEQ_DATA_START40 - [3:0] */
5661#define WM8995_WSEQ_DATA_START40_WIDTH 4 /* WSEQ_DATA_START40 - [3:0] */
5662
5663/*
5664 * R12451 (0x30A3) - Write Sequencer 163
5665 */
5666#define WM8995_WSEQ_EOS40 0x0100 /* WSEQ_EOS40 */
5667#define WM8995_WSEQ_EOS40_MASK 0x0100 /* WSEQ_EOS40 */
5668#define WM8995_WSEQ_EOS40_SHIFT 8 /* WSEQ_EOS40 */
5669#define WM8995_WSEQ_EOS40_WIDTH 1 /* WSEQ_EOS40 */
5670#define WM8995_WSEQ_DELAY40_MASK 0x000F /* WSEQ_DELAY40 - [3:0] */
5671#define WM8995_WSEQ_DELAY40_SHIFT 0 /* WSEQ_DELAY40 - [3:0] */
5672#define WM8995_WSEQ_DELAY40_WIDTH 4 /* WSEQ_DELAY40 - [3:0] */
5673
5674/*
5675 * R12452 (0x30A4) - Write Sequencer 164
5676 */
5677#define WM8995_WSEQ_ADDR41_MASK 0x3FFF /* WSEQ_ADDR41 - [13:0] */
5678#define WM8995_WSEQ_ADDR41_SHIFT 0 /* WSEQ_ADDR41 - [13:0] */
5679#define WM8995_WSEQ_ADDR41_WIDTH 14 /* WSEQ_ADDR41 - [13:0] */
5680
5681/*
5682 * R12453 (0x30A5) - Write Sequencer 165
5683 */
5684#define WM8995_WSEQ_DATA41_MASK 0x00FF /* WSEQ_DATA41 - [7:0] */
5685#define WM8995_WSEQ_DATA41_SHIFT 0 /* WSEQ_DATA41 - [7:0] */
5686#define WM8995_WSEQ_DATA41_WIDTH 8 /* WSEQ_DATA41 - [7:0] */
5687
5688/*
5689 * R12454 (0x30A6) - Write Sequencer 166
5690 */
5691#define WM8995_WSEQ_DATA_WIDTH41_MASK 0x0700 /* WSEQ_DATA_WIDTH41 - [10:8] */
5692#define WM8995_WSEQ_DATA_WIDTH41_SHIFT 8 /* WSEQ_DATA_WIDTH41 - [10:8] */
5693#define WM8995_WSEQ_DATA_WIDTH41_WIDTH 3 /* WSEQ_DATA_WIDTH41 - [10:8] */
5694#define WM8995_WSEQ_DATA_START41_MASK 0x000F /* WSEQ_DATA_START41 - [3:0] */
5695#define WM8995_WSEQ_DATA_START41_SHIFT 0 /* WSEQ_DATA_START41 - [3:0] */
5696#define WM8995_WSEQ_DATA_START41_WIDTH 4 /* WSEQ_DATA_START41 - [3:0] */
5697
5698/*
5699 * R12455 (0x30A7) - Write Sequencer 167
5700 */
5701#define WM8995_WSEQ_EOS41 0x0100 /* WSEQ_EOS41 */
5702#define WM8995_WSEQ_EOS41_MASK 0x0100 /* WSEQ_EOS41 */
5703#define WM8995_WSEQ_EOS41_SHIFT 8 /* WSEQ_EOS41 */
5704#define WM8995_WSEQ_EOS41_WIDTH 1 /* WSEQ_EOS41 */
5705#define WM8995_WSEQ_DELAY41_MASK 0x000F /* WSEQ_DELAY41 - [3:0] */
5706#define WM8995_WSEQ_DELAY41_SHIFT 0 /* WSEQ_DELAY41 - [3:0] */
5707#define WM8995_WSEQ_DELAY41_WIDTH 4 /* WSEQ_DELAY41 - [3:0] */
5708
5709/*
5710 * R12456 (0x30A8) - Write Sequencer 168
5711 */
5712#define WM8995_WSEQ_ADDR42_MASK 0x3FFF /* WSEQ_ADDR42 - [13:0] */
5713#define WM8995_WSEQ_ADDR42_SHIFT 0 /* WSEQ_ADDR42 - [13:0] */
5714#define WM8995_WSEQ_ADDR42_WIDTH 14 /* WSEQ_ADDR42 - [13:0] */
5715
5716/*
5717 * R12457 (0x30A9) - Write Sequencer 169
5718 */
5719#define WM8995_WSEQ_DATA42_MASK 0x00FF /* WSEQ_DATA42 - [7:0] */
5720#define WM8995_WSEQ_DATA42_SHIFT 0 /* WSEQ_DATA42 - [7:0] */
5721#define WM8995_WSEQ_DATA42_WIDTH 8 /* WSEQ_DATA42 - [7:0] */
5722
5723/*
5724 * R12458 (0x30AA) - Write Sequencer 170
5725 */
5726#define WM8995_WSEQ_DATA_WIDTH42_MASK 0x0700 /* WSEQ_DATA_WIDTH42 - [10:8] */
5727#define WM8995_WSEQ_DATA_WIDTH42_SHIFT 8 /* WSEQ_DATA_WIDTH42 - [10:8] */
5728#define WM8995_WSEQ_DATA_WIDTH42_WIDTH 3 /* WSEQ_DATA_WIDTH42 - [10:8] */
5729#define WM8995_WSEQ_DATA_START42_MASK 0x000F /* WSEQ_DATA_START42 - [3:0] */
5730#define WM8995_WSEQ_DATA_START42_SHIFT 0 /* WSEQ_DATA_START42 - [3:0] */
5731#define WM8995_WSEQ_DATA_START42_WIDTH 4 /* WSEQ_DATA_START42 - [3:0] */
5732
5733/*
5734 * R12459 (0x30AB) - Write Sequencer 171
5735 */
5736#define WM8995_WSEQ_EOS42 0x0100 /* WSEQ_EOS42 */
5737#define WM8995_WSEQ_EOS42_MASK 0x0100 /* WSEQ_EOS42 */
5738#define WM8995_WSEQ_EOS42_SHIFT 8 /* WSEQ_EOS42 */
5739#define WM8995_WSEQ_EOS42_WIDTH 1 /* WSEQ_EOS42 */
5740#define WM8995_WSEQ_DELAY42_MASK 0x000F /* WSEQ_DELAY42 - [3:0] */
5741#define WM8995_WSEQ_DELAY42_SHIFT 0 /* WSEQ_DELAY42 - [3:0] */
5742#define WM8995_WSEQ_DELAY42_WIDTH 4 /* WSEQ_DELAY42 - [3:0] */
5743
5744/*
5745 * R12460 (0x30AC) - Write Sequencer 172
5746 */
5747#define WM8995_WSEQ_ADDR43_MASK 0x3FFF /* WSEQ_ADDR43 - [13:0] */
5748#define WM8995_WSEQ_ADDR43_SHIFT 0 /* WSEQ_ADDR43 - [13:0] */
5749#define WM8995_WSEQ_ADDR43_WIDTH 14 /* WSEQ_ADDR43 - [13:0] */
5750
5751/*
5752 * R12461 (0x30AD) - Write Sequencer 173
5753 */
5754#define WM8995_WSEQ_DATA43_MASK 0x00FF /* WSEQ_DATA43 - [7:0] */
5755#define WM8995_WSEQ_DATA43_SHIFT 0 /* WSEQ_DATA43 - [7:0] */
5756#define WM8995_WSEQ_DATA43_WIDTH 8 /* WSEQ_DATA43 - [7:0] */
5757
5758/*
5759 * R12462 (0x30AE) - Write Sequencer 174
5760 */
5761#define WM8995_WSEQ_DATA_WIDTH43_MASK 0x0700 /* WSEQ_DATA_WIDTH43 - [10:8] */
5762#define WM8995_WSEQ_DATA_WIDTH43_SHIFT 8 /* WSEQ_DATA_WIDTH43 - [10:8] */
5763#define WM8995_WSEQ_DATA_WIDTH43_WIDTH 3 /* WSEQ_DATA_WIDTH43 - [10:8] */
5764#define WM8995_WSEQ_DATA_START43_MASK 0x000F /* WSEQ_DATA_START43 - [3:0] */
5765#define WM8995_WSEQ_DATA_START43_SHIFT 0 /* WSEQ_DATA_START43 - [3:0] */
5766#define WM8995_WSEQ_DATA_START43_WIDTH 4 /* WSEQ_DATA_START43 - [3:0] */
5767
5768/*
5769 * R12463 (0x30AF) - Write Sequencer 175
5770 */
5771#define WM8995_WSEQ_EOS43 0x0100 /* WSEQ_EOS43 */
5772#define WM8995_WSEQ_EOS43_MASK 0x0100 /* WSEQ_EOS43 */
5773#define WM8995_WSEQ_EOS43_SHIFT 8 /* WSEQ_EOS43 */
5774#define WM8995_WSEQ_EOS43_WIDTH 1 /* WSEQ_EOS43 */
5775#define WM8995_WSEQ_DELAY43_MASK 0x000F /* WSEQ_DELAY43 - [3:0] */
5776#define WM8995_WSEQ_DELAY43_SHIFT 0 /* WSEQ_DELAY43 - [3:0] */
5777#define WM8995_WSEQ_DELAY43_WIDTH 4 /* WSEQ_DELAY43 - [3:0] */
5778
5779/*
5780 * R12464 (0x30B0) - Write Sequencer 176
5781 */
5782#define WM8995_WSEQ_ADDR44_MASK 0x3FFF /* WSEQ_ADDR44 - [13:0] */
5783#define WM8995_WSEQ_ADDR44_SHIFT 0 /* WSEQ_ADDR44 - [13:0] */
5784#define WM8995_WSEQ_ADDR44_WIDTH 14 /* WSEQ_ADDR44 - [13:0] */
5785
5786/*
5787 * R12465 (0x30B1) - Write Sequencer 177
5788 */
5789#define WM8995_WSEQ_DATA44_MASK 0x00FF /* WSEQ_DATA44 - [7:0] */
5790#define WM8995_WSEQ_DATA44_SHIFT 0 /* WSEQ_DATA44 - [7:0] */
5791#define WM8995_WSEQ_DATA44_WIDTH 8 /* WSEQ_DATA44 - [7:0] */
5792
5793/*
5794 * R12466 (0x30B2) - Write Sequencer 178
5795 */
5796#define WM8995_WSEQ_DATA_WIDTH44_MASK 0x0700 /* WSEQ_DATA_WIDTH44 - [10:8] */
5797#define WM8995_WSEQ_DATA_WIDTH44_SHIFT 8 /* WSEQ_DATA_WIDTH44 - [10:8] */
5798#define WM8995_WSEQ_DATA_WIDTH44_WIDTH 3 /* WSEQ_DATA_WIDTH44 - [10:8] */
5799#define WM8995_WSEQ_DATA_START44_MASK 0x000F /* WSEQ_DATA_START44 - [3:0] */
5800#define WM8995_WSEQ_DATA_START44_SHIFT 0 /* WSEQ_DATA_START44 - [3:0] */
5801#define WM8995_WSEQ_DATA_START44_WIDTH 4 /* WSEQ_DATA_START44 - [3:0] */
5802
5803/*
5804 * R12467 (0x30B3) - Write Sequencer 179
5805 */
5806#define WM8995_WSEQ_EOS44 0x0100 /* WSEQ_EOS44 */
5807#define WM8995_WSEQ_EOS44_MASK 0x0100 /* WSEQ_EOS44 */
5808#define WM8995_WSEQ_EOS44_SHIFT 8 /* WSEQ_EOS44 */
5809#define WM8995_WSEQ_EOS44_WIDTH 1 /* WSEQ_EOS44 */
5810#define WM8995_WSEQ_DELAY44_MASK 0x000F /* WSEQ_DELAY44 - [3:0] */
5811#define WM8995_WSEQ_DELAY44_SHIFT 0 /* WSEQ_DELAY44 - [3:0] */
5812#define WM8995_WSEQ_DELAY44_WIDTH 4 /* WSEQ_DELAY44 - [3:0] */
5813
5814/*
5815 * R12468 (0x30B4) - Write Sequencer 180
5816 */
5817#define WM8995_WSEQ_ADDR45_MASK 0x3FFF /* WSEQ_ADDR45 - [13:0] */
5818#define WM8995_WSEQ_ADDR45_SHIFT 0 /* WSEQ_ADDR45 - [13:0] */
5819#define WM8995_WSEQ_ADDR45_WIDTH 14 /* WSEQ_ADDR45 - [13:0] */
5820
5821/*
5822 * R12469 (0x30B5) - Write Sequencer 181
5823 */
5824#define WM8995_WSEQ_DATA45_MASK 0x00FF /* WSEQ_DATA45 - [7:0] */
5825#define WM8995_WSEQ_DATA45_SHIFT 0 /* WSEQ_DATA45 - [7:0] */
5826#define WM8995_WSEQ_DATA45_WIDTH 8 /* WSEQ_DATA45 - [7:0] */
5827
5828/*
5829 * R12470 (0x30B6) - Write Sequencer 182
5830 */
5831#define WM8995_WSEQ_DATA_WIDTH45_MASK 0x0700 /* WSEQ_DATA_WIDTH45 - [10:8] */
5832#define WM8995_WSEQ_DATA_WIDTH45_SHIFT 8 /* WSEQ_DATA_WIDTH45 - [10:8] */
5833#define WM8995_WSEQ_DATA_WIDTH45_WIDTH 3 /* WSEQ_DATA_WIDTH45 - [10:8] */
5834#define WM8995_WSEQ_DATA_START45_MASK 0x000F /* WSEQ_DATA_START45 - [3:0] */
5835#define WM8995_WSEQ_DATA_START45_SHIFT 0 /* WSEQ_DATA_START45 - [3:0] */
5836#define WM8995_WSEQ_DATA_START45_WIDTH 4 /* WSEQ_DATA_START45 - [3:0] */
5837
5838/*
5839 * R12471 (0x30B7) - Write Sequencer 183
5840 */
5841#define WM8995_WSEQ_EOS45 0x0100 /* WSEQ_EOS45 */
5842#define WM8995_WSEQ_EOS45_MASK 0x0100 /* WSEQ_EOS45 */
5843#define WM8995_WSEQ_EOS45_SHIFT 8 /* WSEQ_EOS45 */
5844#define WM8995_WSEQ_EOS45_WIDTH 1 /* WSEQ_EOS45 */
5845#define WM8995_WSEQ_DELAY45_MASK 0x000F /* WSEQ_DELAY45 - [3:0] */
5846#define WM8995_WSEQ_DELAY45_SHIFT 0 /* WSEQ_DELAY45 - [3:0] */
5847#define WM8995_WSEQ_DELAY45_WIDTH 4 /* WSEQ_DELAY45 - [3:0] */
5848
5849/*
5850 * R12472 (0x30B8) - Write Sequencer 184
5851 */
5852#define WM8995_WSEQ_ADDR46_MASK 0x3FFF /* WSEQ_ADDR46 - [13:0] */
5853#define WM8995_WSEQ_ADDR46_SHIFT 0 /* WSEQ_ADDR46 - [13:0] */
5854#define WM8995_WSEQ_ADDR46_WIDTH 14 /* WSEQ_ADDR46 - [13:0] */
5855
5856/*
5857 * R12473 (0x30B9) - Write Sequencer 185
5858 */
5859#define WM8995_WSEQ_DATA46_MASK 0x00FF /* WSEQ_DATA46 - [7:0] */
5860#define WM8995_WSEQ_DATA46_SHIFT 0 /* WSEQ_DATA46 - [7:0] */
5861#define WM8995_WSEQ_DATA46_WIDTH 8 /* WSEQ_DATA46 - [7:0] */
5862
5863/*
5864 * R12474 (0x30BA) - Write Sequencer 186
5865 */
5866#define WM8995_WSEQ_DATA_WIDTH46_MASK 0x0700 /* WSEQ_DATA_WIDTH46 - [10:8] */
5867#define WM8995_WSEQ_DATA_WIDTH46_SHIFT 8 /* WSEQ_DATA_WIDTH46 - [10:8] */
5868#define WM8995_WSEQ_DATA_WIDTH46_WIDTH 3 /* WSEQ_DATA_WIDTH46 - [10:8] */
5869#define WM8995_WSEQ_DATA_START46_MASK 0x000F /* WSEQ_DATA_START46 - [3:0] */
5870#define WM8995_WSEQ_DATA_START46_SHIFT 0 /* WSEQ_DATA_START46 - [3:0] */
5871#define WM8995_WSEQ_DATA_START46_WIDTH 4 /* WSEQ_DATA_START46 - [3:0] */
5872
5873/*
5874 * R12475 (0x30BB) - Write Sequencer 187
5875 */
5876#define WM8995_WSEQ_EOS46 0x0100 /* WSEQ_EOS46 */
5877#define WM8995_WSEQ_EOS46_MASK 0x0100 /* WSEQ_EOS46 */
5878#define WM8995_WSEQ_EOS46_SHIFT 8 /* WSEQ_EOS46 */
5879#define WM8995_WSEQ_EOS46_WIDTH 1 /* WSEQ_EOS46 */
5880#define WM8995_WSEQ_DELAY46_MASK 0x000F /* WSEQ_DELAY46 - [3:0] */
5881#define WM8995_WSEQ_DELAY46_SHIFT 0 /* WSEQ_DELAY46 - [3:0] */
5882#define WM8995_WSEQ_DELAY46_WIDTH 4 /* WSEQ_DELAY46 - [3:0] */
5883
5884/*
5885 * R12476 (0x30BC) - Write Sequencer 188
5886 */
5887#define WM8995_WSEQ_ADDR47_MASK 0x3FFF /* WSEQ_ADDR47 - [13:0] */
5888#define WM8995_WSEQ_ADDR47_SHIFT 0 /* WSEQ_ADDR47 - [13:0] */
5889#define WM8995_WSEQ_ADDR47_WIDTH 14 /* WSEQ_ADDR47 - [13:0] */
5890
5891/*
5892 * R12477 (0x30BD) - Write Sequencer 189
5893 */
5894#define WM8995_WSEQ_DATA47_MASK 0x00FF /* WSEQ_DATA47 - [7:0] */
5895#define WM8995_WSEQ_DATA47_SHIFT 0 /* WSEQ_DATA47 - [7:0] */
5896#define WM8995_WSEQ_DATA47_WIDTH 8 /* WSEQ_DATA47 - [7:0] */
5897
5898/*
5899 * R12478 (0x30BE) - Write Sequencer 190
5900 */
5901#define WM8995_WSEQ_DATA_WIDTH47_MASK 0x0700 /* WSEQ_DATA_WIDTH47 - [10:8] */
5902#define WM8995_WSEQ_DATA_WIDTH47_SHIFT 8 /* WSEQ_DATA_WIDTH47 - [10:8] */
5903#define WM8995_WSEQ_DATA_WIDTH47_WIDTH 3 /* WSEQ_DATA_WIDTH47 - [10:8] */
5904#define WM8995_WSEQ_DATA_START47_MASK 0x000F /* WSEQ_DATA_START47 - [3:0] */
5905#define WM8995_WSEQ_DATA_START47_SHIFT 0 /* WSEQ_DATA_START47 - [3:0] */
5906#define WM8995_WSEQ_DATA_START47_WIDTH 4 /* WSEQ_DATA_START47 - [3:0] */
5907
5908/*
5909 * R12479 (0x30BF) - Write Sequencer 191
5910 */
5911#define WM8995_WSEQ_EOS47 0x0100 /* WSEQ_EOS47 */
5912#define WM8995_WSEQ_EOS47_MASK 0x0100 /* WSEQ_EOS47 */
5913#define WM8995_WSEQ_EOS47_SHIFT 8 /* WSEQ_EOS47 */
5914#define WM8995_WSEQ_EOS47_WIDTH 1 /* WSEQ_EOS47 */
5915#define WM8995_WSEQ_DELAY47_MASK 0x000F /* WSEQ_DELAY47 - [3:0] */
5916#define WM8995_WSEQ_DELAY47_SHIFT 0 /* WSEQ_DELAY47 - [3:0] */
5917#define WM8995_WSEQ_DELAY47_WIDTH 4 /* WSEQ_DELAY47 - [3:0] */
5918
5919/*
5920 * R12480 (0x30C0) - Write Sequencer 192
5921 */
5922#define WM8995_WSEQ_ADDR48_MASK 0x3FFF /* WSEQ_ADDR48 - [13:0] */
5923#define WM8995_WSEQ_ADDR48_SHIFT 0 /* WSEQ_ADDR48 - [13:0] */
5924#define WM8995_WSEQ_ADDR48_WIDTH 14 /* WSEQ_ADDR48 - [13:0] */
5925
5926/*
5927 * R12481 (0x30C1) - Write Sequencer 193
5928 */
5929#define WM8995_WSEQ_DATA48_MASK 0x00FF /* WSEQ_DATA48 - [7:0] */
5930#define WM8995_WSEQ_DATA48_SHIFT 0 /* WSEQ_DATA48 - [7:0] */
5931#define WM8995_WSEQ_DATA48_WIDTH 8 /* WSEQ_DATA48 - [7:0] */
5932
5933/*
5934 * R12482 (0x30C2) - Write Sequencer 194
5935 */
5936#define WM8995_WSEQ_DATA_WIDTH48_MASK 0x0700 /* WSEQ_DATA_WIDTH48 - [10:8] */
5937#define WM8995_WSEQ_DATA_WIDTH48_SHIFT 8 /* WSEQ_DATA_WIDTH48 - [10:8] */
5938#define WM8995_WSEQ_DATA_WIDTH48_WIDTH 3 /* WSEQ_DATA_WIDTH48 - [10:8] */
5939#define WM8995_WSEQ_DATA_START48_MASK 0x000F /* WSEQ_DATA_START48 - [3:0] */
5940#define WM8995_WSEQ_DATA_START48_SHIFT 0 /* WSEQ_DATA_START48 - [3:0] */
5941#define WM8995_WSEQ_DATA_START48_WIDTH 4 /* WSEQ_DATA_START48 - [3:0] */
5942
5943/*
5944 * R12483 (0x30C3) - Write Sequencer 195
5945 */
5946#define WM8995_WSEQ_EOS48 0x0100 /* WSEQ_EOS48 */
5947#define WM8995_WSEQ_EOS48_MASK 0x0100 /* WSEQ_EOS48 */
5948#define WM8995_WSEQ_EOS48_SHIFT 8 /* WSEQ_EOS48 */
5949#define WM8995_WSEQ_EOS48_WIDTH 1 /* WSEQ_EOS48 */
5950#define WM8995_WSEQ_DELAY48_MASK 0x000F /* WSEQ_DELAY48 - [3:0] */
5951#define WM8995_WSEQ_DELAY48_SHIFT 0 /* WSEQ_DELAY48 - [3:0] */
5952#define WM8995_WSEQ_DELAY48_WIDTH 4 /* WSEQ_DELAY48 - [3:0] */
5953
5954/*
5955 * R12484 (0x30C4) - Write Sequencer 196
5956 */
5957#define WM8995_WSEQ_ADDR49_MASK 0x3FFF /* WSEQ_ADDR49 - [13:0] */
5958#define WM8995_WSEQ_ADDR49_SHIFT 0 /* WSEQ_ADDR49 - [13:0] */
5959#define WM8995_WSEQ_ADDR49_WIDTH 14 /* WSEQ_ADDR49 - [13:0] */
5960
5961/*
5962 * R12485 (0x30C5) - Write Sequencer 197
5963 */
5964#define WM8995_WSEQ_DATA49_MASK 0x00FF /* WSEQ_DATA49 - [7:0] */
5965#define WM8995_WSEQ_DATA49_SHIFT 0 /* WSEQ_DATA49 - [7:0] */
5966#define WM8995_WSEQ_DATA49_WIDTH 8 /* WSEQ_DATA49 - [7:0] */
5967
5968/*
5969 * R12486 (0x30C6) - Write Sequencer 198
5970 */
5971#define WM8995_WSEQ_DATA_WIDTH49_MASK 0x0700 /* WSEQ_DATA_WIDTH49 - [10:8] */
5972#define WM8995_WSEQ_DATA_WIDTH49_SHIFT 8 /* WSEQ_DATA_WIDTH49 - [10:8] */
5973#define WM8995_WSEQ_DATA_WIDTH49_WIDTH 3 /* WSEQ_DATA_WIDTH49 - [10:8] */
5974#define WM8995_WSEQ_DATA_START49_MASK 0x000F /* WSEQ_DATA_START49 - [3:0] */
5975#define WM8995_WSEQ_DATA_START49_SHIFT 0 /* WSEQ_DATA_START49 - [3:0] */
5976#define WM8995_WSEQ_DATA_START49_WIDTH 4 /* WSEQ_DATA_START49 - [3:0] */
5977
5978/*
5979 * R12487 (0x30C7) - Write Sequencer 199
5980 */
5981#define WM8995_WSEQ_EOS49 0x0100 /* WSEQ_EOS49 */
5982#define WM8995_WSEQ_EOS49_MASK 0x0100 /* WSEQ_EOS49 */
5983#define WM8995_WSEQ_EOS49_SHIFT 8 /* WSEQ_EOS49 */
5984#define WM8995_WSEQ_EOS49_WIDTH 1 /* WSEQ_EOS49 */
5985#define WM8995_WSEQ_DELAY49_MASK 0x000F /* WSEQ_DELAY49 - [3:0] */
5986#define WM8995_WSEQ_DELAY49_SHIFT 0 /* WSEQ_DELAY49 - [3:0] */
5987#define WM8995_WSEQ_DELAY49_WIDTH 4 /* WSEQ_DELAY49 - [3:0] */
5988
5989/*
5990 * R12488 (0x30C8) - Write Sequencer 200
5991 */
5992#define WM8995_WSEQ_ADDR50_MASK 0x3FFF /* WSEQ_ADDR50 - [13:0] */
5993#define WM8995_WSEQ_ADDR50_SHIFT 0 /* WSEQ_ADDR50 - [13:0] */
5994#define WM8995_WSEQ_ADDR50_WIDTH 14 /* WSEQ_ADDR50 - [13:0] */
5995
5996/*
5997 * R12489 (0x30C9) - Write Sequencer 201
5998 */
5999#define WM8995_WSEQ_DATA50_MASK 0x00FF /* WSEQ_DATA50 - [7:0] */
6000#define WM8995_WSEQ_DATA50_SHIFT 0 /* WSEQ_DATA50 - [7:0] */
6001#define WM8995_WSEQ_DATA50_WIDTH 8 /* WSEQ_DATA50 - [7:0] */
6002
6003/*
6004 * R12490 (0x30CA) - Write Sequencer 202
6005 */
6006#define WM8995_WSEQ_DATA_WIDTH50_MASK 0x0700 /* WSEQ_DATA_WIDTH50 - [10:8] */
6007#define WM8995_WSEQ_DATA_WIDTH50_SHIFT 8 /* WSEQ_DATA_WIDTH50 - [10:8] */
6008#define WM8995_WSEQ_DATA_WIDTH50_WIDTH 3 /* WSEQ_DATA_WIDTH50 - [10:8] */
6009#define WM8995_WSEQ_DATA_START50_MASK 0x000F /* WSEQ_DATA_START50 - [3:0] */
6010#define WM8995_WSEQ_DATA_START50_SHIFT 0 /* WSEQ_DATA_START50 - [3:0] */
6011#define WM8995_WSEQ_DATA_START50_WIDTH 4 /* WSEQ_DATA_START50 - [3:0] */
6012
6013/*
6014 * R12491 (0x30CB) - Write Sequencer 203
6015 */
6016#define WM8995_WSEQ_EOS50 0x0100 /* WSEQ_EOS50 */
6017#define WM8995_WSEQ_EOS50_MASK 0x0100 /* WSEQ_EOS50 */
6018#define WM8995_WSEQ_EOS50_SHIFT 8 /* WSEQ_EOS50 */
6019#define WM8995_WSEQ_EOS50_WIDTH 1 /* WSEQ_EOS50 */
6020#define WM8995_WSEQ_DELAY50_MASK 0x000F /* WSEQ_DELAY50 - [3:0] */
6021#define WM8995_WSEQ_DELAY50_SHIFT 0 /* WSEQ_DELAY50 - [3:0] */
6022#define WM8995_WSEQ_DELAY50_WIDTH 4 /* WSEQ_DELAY50 - [3:0] */
6023
6024/*
6025 * R12492 (0x30CC) - Write Sequencer 204
6026 */
6027#define WM8995_WSEQ_ADDR51_MASK 0x3FFF /* WSEQ_ADDR51 - [13:0] */
6028#define WM8995_WSEQ_ADDR51_SHIFT 0 /* WSEQ_ADDR51 - [13:0] */
6029#define WM8995_WSEQ_ADDR51_WIDTH 14 /* WSEQ_ADDR51 - [13:0] */
6030
6031/*
6032 * R12493 (0x30CD) - Write Sequencer 205
6033 */
6034#define WM8995_WSEQ_DATA51_MASK 0x00FF /* WSEQ_DATA51 - [7:0] */
6035#define WM8995_WSEQ_DATA51_SHIFT 0 /* WSEQ_DATA51 - [7:0] */
6036#define WM8995_WSEQ_DATA51_WIDTH 8 /* WSEQ_DATA51 - [7:0] */
6037
6038/*
6039 * R12494 (0x30CE) - Write Sequencer 206
6040 */
6041#define WM8995_WSEQ_DATA_WIDTH51_MASK 0x0700 /* WSEQ_DATA_WIDTH51 - [10:8] */
6042#define WM8995_WSEQ_DATA_WIDTH51_SHIFT 8 /* WSEQ_DATA_WIDTH51 - [10:8] */
6043#define WM8995_WSEQ_DATA_WIDTH51_WIDTH 3 /* WSEQ_DATA_WIDTH51 - [10:8] */
6044#define WM8995_WSEQ_DATA_START51_MASK 0x000F /* WSEQ_DATA_START51 - [3:0] */
6045#define WM8995_WSEQ_DATA_START51_SHIFT 0 /* WSEQ_DATA_START51 - [3:0] */
6046#define WM8995_WSEQ_DATA_START51_WIDTH 4 /* WSEQ_DATA_START51 - [3:0] */
6047
6048/*
6049 * R12495 (0x30CF) - Write Sequencer 207
6050 */
6051#define WM8995_WSEQ_EOS51 0x0100 /* WSEQ_EOS51 */
6052#define WM8995_WSEQ_EOS51_MASK 0x0100 /* WSEQ_EOS51 */
6053#define WM8995_WSEQ_EOS51_SHIFT 8 /* WSEQ_EOS51 */
6054#define WM8995_WSEQ_EOS51_WIDTH 1 /* WSEQ_EOS51 */
6055#define WM8995_WSEQ_DELAY51_MASK 0x000F /* WSEQ_DELAY51 - [3:0] */
6056#define WM8995_WSEQ_DELAY51_SHIFT 0 /* WSEQ_DELAY51 - [3:0] */
6057#define WM8995_WSEQ_DELAY51_WIDTH 4 /* WSEQ_DELAY51 - [3:0] */
6058
6059/*
6060 * R12496 (0x30D0) - Write Sequencer 208
6061 */
6062#define WM8995_WSEQ_ADDR52_MASK 0x3FFF /* WSEQ_ADDR52 - [13:0] */
6063#define WM8995_WSEQ_ADDR52_SHIFT 0 /* WSEQ_ADDR52 - [13:0] */
6064#define WM8995_WSEQ_ADDR52_WIDTH 14 /* WSEQ_ADDR52 - [13:0] */
6065
6066/*
6067 * R12497 (0x30D1) - Write Sequencer 209
6068 */
6069#define WM8995_WSEQ_DATA52_MASK 0x00FF /* WSEQ_DATA52 - [7:0] */
6070#define WM8995_WSEQ_DATA52_SHIFT 0 /* WSEQ_DATA52 - [7:0] */
6071#define WM8995_WSEQ_DATA52_WIDTH 8 /* WSEQ_DATA52 - [7:0] */
6072
6073/*
6074 * R12498 (0x30D2) - Write Sequencer 210
6075 */
6076#define WM8995_WSEQ_DATA_WIDTH52_MASK 0x0700 /* WSEQ_DATA_WIDTH52 - [10:8] */
6077#define WM8995_WSEQ_DATA_WIDTH52_SHIFT 8 /* WSEQ_DATA_WIDTH52 - [10:8] */
6078#define WM8995_WSEQ_DATA_WIDTH52_WIDTH 3 /* WSEQ_DATA_WIDTH52 - [10:8] */
6079#define WM8995_WSEQ_DATA_START52_MASK 0x000F /* WSEQ_DATA_START52 - [3:0] */
6080#define WM8995_WSEQ_DATA_START52_SHIFT 0 /* WSEQ_DATA_START52 - [3:0] */
6081#define WM8995_WSEQ_DATA_START52_WIDTH 4 /* WSEQ_DATA_START52 - [3:0] */
6082
6083/*
6084 * R12499 (0x30D3) - Write Sequencer 211
6085 */
6086#define WM8995_WSEQ_EOS52 0x0100 /* WSEQ_EOS52 */
6087#define WM8995_WSEQ_EOS52_MASK 0x0100 /* WSEQ_EOS52 */
6088#define WM8995_WSEQ_EOS52_SHIFT 8 /* WSEQ_EOS52 */
6089#define WM8995_WSEQ_EOS52_WIDTH 1 /* WSEQ_EOS52 */
6090#define WM8995_WSEQ_DELAY52_MASK 0x000F /* WSEQ_DELAY52 - [3:0] */
6091#define WM8995_WSEQ_DELAY52_SHIFT 0 /* WSEQ_DELAY52 - [3:0] */
6092#define WM8995_WSEQ_DELAY52_WIDTH 4 /* WSEQ_DELAY52 - [3:0] */
6093
6094/*
6095 * R12500 (0x30D4) - Write Sequencer 212
6096 */
6097#define WM8995_WSEQ_ADDR53_MASK 0x3FFF /* WSEQ_ADDR53 - [13:0] */
6098#define WM8995_WSEQ_ADDR53_SHIFT 0 /* WSEQ_ADDR53 - [13:0] */
6099#define WM8995_WSEQ_ADDR53_WIDTH 14 /* WSEQ_ADDR53 - [13:0] */
6100
6101/*
6102 * R12501 (0x30D5) - Write Sequencer 213
6103 */
6104#define WM8995_WSEQ_DATA53_MASK 0x00FF /* WSEQ_DATA53 - [7:0] */
6105#define WM8995_WSEQ_DATA53_SHIFT 0 /* WSEQ_DATA53 - [7:0] */
6106#define WM8995_WSEQ_DATA53_WIDTH 8 /* WSEQ_DATA53 - [7:0] */
6107
6108/*
6109 * R12502 (0x30D6) - Write Sequencer 214
6110 */
6111#define WM8995_WSEQ_DATA_WIDTH53_MASK 0x0700 /* WSEQ_DATA_WIDTH53 - [10:8] */
6112#define WM8995_WSEQ_DATA_WIDTH53_SHIFT 8 /* WSEQ_DATA_WIDTH53 - [10:8] */
6113#define WM8995_WSEQ_DATA_WIDTH53_WIDTH 3 /* WSEQ_DATA_WIDTH53 - [10:8] */
6114#define WM8995_WSEQ_DATA_START53_MASK 0x000F /* WSEQ_DATA_START53 - [3:0] */
6115#define WM8995_WSEQ_DATA_START53_SHIFT 0 /* WSEQ_DATA_START53 - [3:0] */
6116#define WM8995_WSEQ_DATA_START53_WIDTH 4 /* WSEQ_DATA_START53 - [3:0] */
6117
6118/*
6119 * R12503 (0x30D7) - Write Sequencer 215
6120 */
6121#define WM8995_WSEQ_EOS53 0x0100 /* WSEQ_EOS53 */
6122#define WM8995_WSEQ_EOS53_MASK 0x0100 /* WSEQ_EOS53 */
6123#define WM8995_WSEQ_EOS53_SHIFT 8 /* WSEQ_EOS53 */
6124#define WM8995_WSEQ_EOS53_WIDTH 1 /* WSEQ_EOS53 */
6125#define WM8995_WSEQ_DELAY53_MASK 0x000F /* WSEQ_DELAY53 - [3:0] */
6126#define WM8995_WSEQ_DELAY53_SHIFT 0 /* WSEQ_DELAY53 - [3:0] */
6127#define WM8995_WSEQ_DELAY53_WIDTH 4 /* WSEQ_DELAY53 - [3:0] */
6128
6129/*
6130 * R12504 (0x30D8) - Write Sequencer 216
6131 */
6132#define WM8995_WSEQ_ADDR54_MASK 0x3FFF /* WSEQ_ADDR54 - [13:0] */
6133#define WM8995_WSEQ_ADDR54_SHIFT 0 /* WSEQ_ADDR54 - [13:0] */
6134#define WM8995_WSEQ_ADDR54_WIDTH 14 /* WSEQ_ADDR54 - [13:0] */
6135
6136/*
6137 * R12505 (0x30D9) - Write Sequencer 217
6138 */
6139#define WM8995_WSEQ_DATA54_MASK 0x00FF /* WSEQ_DATA54 - [7:0] */
6140#define WM8995_WSEQ_DATA54_SHIFT 0 /* WSEQ_DATA54 - [7:0] */
6141#define WM8995_WSEQ_DATA54_WIDTH 8 /* WSEQ_DATA54 - [7:0] */
6142
6143/*
6144 * R12506 (0x30DA) - Write Sequencer 218
6145 */
6146#define WM8995_WSEQ_DATA_WIDTH54_MASK 0x0700 /* WSEQ_DATA_WIDTH54 - [10:8] */
6147#define WM8995_WSEQ_DATA_WIDTH54_SHIFT 8 /* WSEQ_DATA_WIDTH54 - [10:8] */
6148#define WM8995_WSEQ_DATA_WIDTH54_WIDTH 3 /* WSEQ_DATA_WIDTH54 - [10:8] */
6149#define WM8995_WSEQ_DATA_START54_MASK 0x000F /* WSEQ_DATA_START54 - [3:0] */
6150#define WM8995_WSEQ_DATA_START54_SHIFT 0 /* WSEQ_DATA_START54 - [3:0] */
6151#define WM8995_WSEQ_DATA_START54_WIDTH 4 /* WSEQ_DATA_START54 - [3:0] */
6152
6153/*
6154 * R12507 (0x30DB) - Write Sequencer 219
6155 */
6156#define WM8995_WSEQ_EOS54 0x0100 /* WSEQ_EOS54 */
6157#define WM8995_WSEQ_EOS54_MASK 0x0100 /* WSEQ_EOS54 */
6158#define WM8995_WSEQ_EOS54_SHIFT 8 /* WSEQ_EOS54 */
6159#define WM8995_WSEQ_EOS54_WIDTH 1 /* WSEQ_EOS54 */
6160#define WM8995_WSEQ_DELAY54_MASK 0x000F /* WSEQ_DELAY54 - [3:0] */
6161#define WM8995_WSEQ_DELAY54_SHIFT 0 /* WSEQ_DELAY54 - [3:0] */
6162#define WM8995_WSEQ_DELAY54_WIDTH 4 /* WSEQ_DELAY54 - [3:0] */
6163
6164/*
6165 * R12508 (0x30DC) - Write Sequencer 220
6166 */
6167#define WM8995_WSEQ_ADDR55_MASK 0x3FFF /* WSEQ_ADDR55 - [13:0] */
6168#define WM8995_WSEQ_ADDR55_SHIFT 0 /* WSEQ_ADDR55 - [13:0] */
6169#define WM8995_WSEQ_ADDR55_WIDTH 14 /* WSEQ_ADDR55 - [13:0] */
6170
6171/*
6172 * R12509 (0x30DD) - Write Sequencer 221
6173 */
6174#define WM8995_WSEQ_DATA55_MASK 0x00FF /* WSEQ_DATA55 - [7:0] */
6175#define WM8995_WSEQ_DATA55_SHIFT 0 /* WSEQ_DATA55 - [7:0] */
6176#define WM8995_WSEQ_DATA55_WIDTH 8 /* WSEQ_DATA55 - [7:0] */
6177
6178/*
6179 * R12510 (0x30DE) - Write Sequencer 222
6180 */
6181#define WM8995_WSEQ_DATA_WIDTH55_MASK 0x0700 /* WSEQ_DATA_WIDTH55 - [10:8] */
6182#define WM8995_WSEQ_DATA_WIDTH55_SHIFT 8 /* WSEQ_DATA_WIDTH55 - [10:8] */
6183#define WM8995_WSEQ_DATA_WIDTH55_WIDTH 3 /* WSEQ_DATA_WIDTH55 - [10:8] */
6184#define WM8995_WSEQ_DATA_START55_MASK 0x000F /* WSEQ_DATA_START55 - [3:0] */
6185#define WM8995_WSEQ_DATA_START55_SHIFT 0 /* WSEQ_DATA_START55 - [3:0] */
6186#define WM8995_WSEQ_DATA_START55_WIDTH 4 /* WSEQ_DATA_START55 - [3:0] */
6187
6188/*
6189 * R12511 (0x30DF) - Write Sequencer 223
6190 */
6191#define WM8995_WSEQ_EOS55 0x0100 /* WSEQ_EOS55 */
6192#define WM8995_WSEQ_EOS55_MASK 0x0100 /* WSEQ_EOS55 */
6193#define WM8995_WSEQ_EOS55_SHIFT 8 /* WSEQ_EOS55 */
6194#define WM8995_WSEQ_EOS55_WIDTH 1 /* WSEQ_EOS55 */
6195#define WM8995_WSEQ_DELAY55_MASK 0x000F /* WSEQ_DELAY55 - [3:0] */
6196#define WM8995_WSEQ_DELAY55_SHIFT 0 /* WSEQ_DELAY55 - [3:0] */
6197#define WM8995_WSEQ_DELAY55_WIDTH 4 /* WSEQ_DELAY55 - [3:0] */
6198
6199/*
6200 * R12512 (0x30E0) - Write Sequencer 224
6201 */
6202#define WM8995_WSEQ_ADDR56_MASK 0x3FFF /* WSEQ_ADDR56 - [13:0] */
6203#define WM8995_WSEQ_ADDR56_SHIFT 0 /* WSEQ_ADDR56 - [13:0] */
6204#define WM8995_WSEQ_ADDR56_WIDTH 14 /* WSEQ_ADDR56 - [13:0] */
6205
6206/*
6207 * R12513 (0x30E1) - Write Sequencer 225
6208 */
6209#define WM8995_WSEQ_DATA56_MASK 0x00FF /* WSEQ_DATA56 - [7:0] */
6210#define WM8995_WSEQ_DATA56_SHIFT 0 /* WSEQ_DATA56 - [7:0] */
6211#define WM8995_WSEQ_DATA56_WIDTH 8 /* WSEQ_DATA56 - [7:0] */
6212
6213/*
6214 * R12514 (0x30E2) - Write Sequencer 226
6215 */
6216#define WM8995_WSEQ_DATA_WIDTH56_MASK 0x0700 /* WSEQ_DATA_WIDTH56 - [10:8] */
6217#define WM8995_WSEQ_DATA_WIDTH56_SHIFT 8 /* WSEQ_DATA_WIDTH56 - [10:8] */
6218#define WM8995_WSEQ_DATA_WIDTH56_WIDTH 3 /* WSEQ_DATA_WIDTH56 - [10:8] */
6219#define WM8995_WSEQ_DATA_START56_MASK 0x000F /* WSEQ_DATA_START56 - [3:0] */
6220#define WM8995_WSEQ_DATA_START56_SHIFT 0 /* WSEQ_DATA_START56 - [3:0] */
6221#define WM8995_WSEQ_DATA_START56_WIDTH 4 /* WSEQ_DATA_START56 - [3:0] */
6222
6223/*
6224 * R12515 (0x30E3) - Write Sequencer 227
6225 */
6226#define WM8995_WSEQ_EOS56 0x0100 /* WSEQ_EOS56 */
6227#define WM8995_WSEQ_EOS56_MASK 0x0100 /* WSEQ_EOS56 */
6228#define WM8995_WSEQ_EOS56_SHIFT 8 /* WSEQ_EOS56 */
6229#define WM8995_WSEQ_EOS56_WIDTH 1 /* WSEQ_EOS56 */
6230#define WM8995_WSEQ_DELAY56_MASK 0x000F /* WSEQ_DELAY56 - [3:0] */
6231#define WM8995_WSEQ_DELAY56_SHIFT 0 /* WSEQ_DELAY56 - [3:0] */
6232#define WM8995_WSEQ_DELAY56_WIDTH 4 /* WSEQ_DELAY56 - [3:0] */
6233
6234/*
6235 * R12516 (0x30E4) - Write Sequencer 228
6236 */
6237#define WM8995_WSEQ_ADDR57_MASK 0x3FFF /* WSEQ_ADDR57 - [13:0] */
6238#define WM8995_WSEQ_ADDR57_SHIFT 0 /* WSEQ_ADDR57 - [13:0] */
6239#define WM8995_WSEQ_ADDR57_WIDTH 14 /* WSEQ_ADDR57 - [13:0] */
6240
6241/*
6242 * R12517 (0x30E5) - Write Sequencer 229
6243 */
6244#define WM8995_WSEQ_DATA57_MASK 0x00FF /* WSEQ_DATA57 - [7:0] */
6245#define WM8995_WSEQ_DATA57_SHIFT 0 /* WSEQ_DATA57 - [7:0] */
6246#define WM8995_WSEQ_DATA57_WIDTH 8 /* WSEQ_DATA57 - [7:0] */
6247
6248/*
6249 * R12518 (0x30E6) - Write Sequencer 230
6250 */
6251#define WM8995_WSEQ_DATA_WIDTH57_MASK 0x0700 /* WSEQ_DATA_WIDTH57 - [10:8] */
6252#define WM8995_WSEQ_DATA_WIDTH57_SHIFT 8 /* WSEQ_DATA_WIDTH57 - [10:8] */
6253#define WM8995_WSEQ_DATA_WIDTH57_WIDTH 3 /* WSEQ_DATA_WIDTH57 - [10:8] */
6254#define WM8995_WSEQ_DATA_START57_MASK 0x000F /* WSEQ_DATA_START57 - [3:0] */
6255#define WM8995_WSEQ_DATA_START57_SHIFT 0 /* WSEQ_DATA_START57 - [3:0] */
6256#define WM8995_WSEQ_DATA_START57_WIDTH 4 /* WSEQ_DATA_START57 - [3:0] */
6257
6258/*
6259 * R12519 (0x30E7) - Write Sequencer 231
6260 */
6261#define WM8995_WSEQ_EOS57 0x0100 /* WSEQ_EOS57 */
6262#define WM8995_WSEQ_EOS57_MASK 0x0100 /* WSEQ_EOS57 */
6263#define WM8995_WSEQ_EOS57_SHIFT 8 /* WSEQ_EOS57 */
6264#define WM8995_WSEQ_EOS57_WIDTH 1 /* WSEQ_EOS57 */
6265#define WM8995_WSEQ_DELAY57_MASK 0x000F /* WSEQ_DELAY57 - [3:0] */
6266#define WM8995_WSEQ_DELAY57_SHIFT 0 /* WSEQ_DELAY57 - [3:0] */
6267#define WM8995_WSEQ_DELAY57_WIDTH 4 /* WSEQ_DELAY57 - [3:0] */
6268
6269/*
6270 * R12520 (0x30E8) - Write Sequencer 232
6271 */
6272#define WM8995_WSEQ_ADDR58_MASK 0x3FFF /* WSEQ_ADDR58 - [13:0] */
6273#define WM8995_WSEQ_ADDR58_SHIFT 0 /* WSEQ_ADDR58 - [13:0] */
6274#define WM8995_WSEQ_ADDR58_WIDTH 14 /* WSEQ_ADDR58 - [13:0] */
6275
6276/*
6277 * R12521 (0x30E9) - Write Sequencer 233
6278 */
6279#define WM8995_WSEQ_DATA58_MASK 0x00FF /* WSEQ_DATA58 - [7:0] */
6280#define WM8995_WSEQ_DATA58_SHIFT 0 /* WSEQ_DATA58 - [7:0] */
6281#define WM8995_WSEQ_DATA58_WIDTH 8 /* WSEQ_DATA58 - [7:0] */
6282
6283/*
6284 * R12522 (0x30EA) - Write Sequencer 234
6285 */
6286#define WM8995_WSEQ_DATA_WIDTH58_MASK 0x0700 /* WSEQ_DATA_WIDTH58 - [10:8] */
6287#define WM8995_WSEQ_DATA_WIDTH58_SHIFT 8 /* WSEQ_DATA_WIDTH58 - [10:8] */
6288#define WM8995_WSEQ_DATA_WIDTH58_WIDTH 3 /* WSEQ_DATA_WIDTH58 - [10:8] */
6289#define WM8995_WSEQ_DATA_START58_MASK 0x000F /* WSEQ_DATA_START58 - [3:0] */
6290#define WM8995_WSEQ_DATA_START58_SHIFT 0 /* WSEQ_DATA_START58 - [3:0] */
6291#define WM8995_WSEQ_DATA_START58_WIDTH 4 /* WSEQ_DATA_START58 - [3:0] */
6292
6293/*
6294 * R12523 (0x30EB) - Write Sequencer 235
6295 */
6296#define WM8995_WSEQ_EOS58 0x0100 /* WSEQ_EOS58 */
6297#define WM8995_WSEQ_EOS58_MASK 0x0100 /* WSEQ_EOS58 */
6298#define WM8995_WSEQ_EOS58_SHIFT 8 /* WSEQ_EOS58 */
6299#define WM8995_WSEQ_EOS58_WIDTH 1 /* WSEQ_EOS58 */
6300#define WM8995_WSEQ_DELAY58_MASK 0x000F /* WSEQ_DELAY58 - [3:0] */
6301#define WM8995_WSEQ_DELAY58_SHIFT 0 /* WSEQ_DELAY58 - [3:0] */
6302#define WM8995_WSEQ_DELAY58_WIDTH 4 /* WSEQ_DELAY58 - [3:0] */
6303
6304/*
6305 * R12524 (0x30EC) - Write Sequencer 236
6306 */
6307#define WM8995_WSEQ_ADDR59_MASK 0x3FFF /* WSEQ_ADDR59 - [13:0] */
6308#define WM8995_WSEQ_ADDR59_SHIFT 0 /* WSEQ_ADDR59 - [13:0] */
6309#define WM8995_WSEQ_ADDR59_WIDTH 14 /* WSEQ_ADDR59 - [13:0] */
6310
6311/*
6312 * R12525 (0x30ED) - Write Sequencer 237
6313 */
6314#define WM8995_WSEQ_DATA59_MASK 0x00FF /* WSEQ_DATA59 - [7:0] */
6315#define WM8995_WSEQ_DATA59_SHIFT 0 /* WSEQ_DATA59 - [7:0] */
6316#define WM8995_WSEQ_DATA59_WIDTH 8 /* WSEQ_DATA59 - [7:0] */
6317
6318/*
6319 * R12526 (0x30EE) - Write Sequencer 238
6320 */
6321#define WM8995_WSEQ_DATA_WIDTH59_MASK 0x0700 /* WSEQ_DATA_WIDTH59 - [10:8] */
6322#define WM8995_WSEQ_DATA_WIDTH59_SHIFT 8 /* WSEQ_DATA_WIDTH59 - [10:8] */
6323#define WM8995_WSEQ_DATA_WIDTH59_WIDTH 3 /* WSEQ_DATA_WIDTH59 - [10:8] */
6324#define WM8995_WSEQ_DATA_START59_MASK 0x000F /* WSEQ_DATA_START59 - [3:0] */
6325#define WM8995_WSEQ_DATA_START59_SHIFT 0 /* WSEQ_DATA_START59 - [3:0] */
6326#define WM8995_WSEQ_DATA_START59_WIDTH 4 /* WSEQ_DATA_START59 - [3:0] */
6327
6328/*
6329 * R12527 (0x30EF) - Write Sequencer 239
6330 */
6331#define WM8995_WSEQ_EOS59 0x0100 /* WSEQ_EOS59 */
6332#define WM8995_WSEQ_EOS59_MASK 0x0100 /* WSEQ_EOS59 */
6333#define WM8995_WSEQ_EOS59_SHIFT 8 /* WSEQ_EOS59 */
6334#define WM8995_WSEQ_EOS59_WIDTH 1 /* WSEQ_EOS59 */
6335#define WM8995_WSEQ_DELAY59_MASK 0x000F /* WSEQ_DELAY59 - [3:0] */
6336#define WM8995_WSEQ_DELAY59_SHIFT 0 /* WSEQ_DELAY59 - [3:0] */
6337#define WM8995_WSEQ_DELAY59_WIDTH 4 /* WSEQ_DELAY59 - [3:0] */
6338
6339/*
6340 * R12528 (0x30F0) - Write Sequencer 240
6341 */
6342#define WM8995_WSEQ_ADDR60_MASK 0x3FFF /* WSEQ_ADDR60 - [13:0] */
6343#define WM8995_WSEQ_ADDR60_SHIFT 0 /* WSEQ_ADDR60 - [13:0] */
6344#define WM8995_WSEQ_ADDR60_WIDTH 14 /* WSEQ_ADDR60 - [13:0] */
6345
6346/*
6347 * R12529 (0x30F1) - Write Sequencer 241
6348 */
6349#define WM8995_WSEQ_DATA60_MASK 0x00FF /* WSEQ_DATA60 - [7:0] */
6350#define WM8995_WSEQ_DATA60_SHIFT 0 /* WSEQ_DATA60 - [7:0] */
6351#define WM8995_WSEQ_DATA60_WIDTH 8 /* WSEQ_DATA60 - [7:0] */
6352
6353/*
6354 * R12530 (0x30F2) - Write Sequencer 242
6355 */
6356#define WM8995_WSEQ_DATA_WIDTH60_MASK 0x0700 /* WSEQ_DATA_WIDTH60 - [10:8] */
6357#define WM8995_WSEQ_DATA_WIDTH60_SHIFT 8 /* WSEQ_DATA_WIDTH60 - [10:8] */
6358#define WM8995_WSEQ_DATA_WIDTH60_WIDTH 3 /* WSEQ_DATA_WIDTH60 - [10:8] */
6359#define WM8995_WSEQ_DATA_START60_MASK 0x000F /* WSEQ_DATA_START60 - [3:0] */
6360#define WM8995_WSEQ_DATA_START60_SHIFT 0 /* WSEQ_DATA_START60 - [3:0] */
6361#define WM8995_WSEQ_DATA_START60_WIDTH 4 /* WSEQ_DATA_START60 - [3:0] */
6362
6363/*
6364 * R12531 (0x30F3) - Write Sequencer 243
6365 */
6366#define WM8995_WSEQ_EOS60 0x0100 /* WSEQ_EOS60 */
6367#define WM8995_WSEQ_EOS60_MASK 0x0100 /* WSEQ_EOS60 */
6368#define WM8995_WSEQ_EOS60_SHIFT 8 /* WSEQ_EOS60 */
6369#define WM8995_WSEQ_EOS60_WIDTH 1 /* WSEQ_EOS60 */
6370#define WM8995_WSEQ_DELAY60_MASK 0x000F /* WSEQ_DELAY60 - [3:0] */
6371#define WM8995_WSEQ_DELAY60_SHIFT 0 /* WSEQ_DELAY60 - [3:0] */
6372#define WM8995_WSEQ_DELAY60_WIDTH 4 /* WSEQ_DELAY60 - [3:0] */
6373
6374/*
6375 * R12532 (0x30F4) - Write Sequencer 244
6376 */
6377#define WM8995_WSEQ_ADDR61_MASK 0x3FFF /* WSEQ_ADDR61 - [13:0] */
6378#define WM8995_WSEQ_ADDR61_SHIFT 0 /* WSEQ_ADDR61 - [13:0] */
6379#define WM8995_WSEQ_ADDR61_WIDTH 14 /* WSEQ_ADDR61 - [13:0] */
6380
6381/*
6382 * R12533 (0x30F5) - Write Sequencer 245
6383 */
6384#define WM8995_WSEQ_DATA61_MASK 0x00FF /* WSEQ_DATA61 - [7:0] */
6385#define WM8995_WSEQ_DATA61_SHIFT 0 /* WSEQ_DATA61 - [7:0] */
6386#define WM8995_WSEQ_DATA61_WIDTH 8 /* WSEQ_DATA61 - [7:0] */
6387
6388/*
6389 * R12534 (0x30F6) - Write Sequencer 246
6390 */
6391#define WM8995_WSEQ_DATA_WIDTH61_MASK 0x0700 /* WSEQ_DATA_WIDTH61 - [10:8] */
6392#define WM8995_WSEQ_DATA_WIDTH61_SHIFT 8 /* WSEQ_DATA_WIDTH61 - [10:8] */
6393#define WM8995_WSEQ_DATA_WIDTH61_WIDTH 3 /* WSEQ_DATA_WIDTH61 - [10:8] */
6394#define WM8995_WSEQ_DATA_START61_MASK 0x000F /* WSEQ_DATA_START61 - [3:0] */
6395#define WM8995_WSEQ_DATA_START61_SHIFT 0 /* WSEQ_DATA_START61 - [3:0] */
6396#define WM8995_WSEQ_DATA_START61_WIDTH 4 /* WSEQ_DATA_START61 - [3:0] */
6397
6398/*
6399 * R12535 (0x30F7) - Write Sequencer 247
6400 */
6401#define WM8995_WSEQ_EOS61 0x0100 /* WSEQ_EOS61 */
6402#define WM8995_WSEQ_EOS61_MASK 0x0100 /* WSEQ_EOS61 */
6403#define WM8995_WSEQ_EOS61_SHIFT 8 /* WSEQ_EOS61 */
6404#define WM8995_WSEQ_EOS61_WIDTH 1 /* WSEQ_EOS61 */
6405#define WM8995_WSEQ_DELAY61_MASK 0x000F /* WSEQ_DELAY61 - [3:0] */
6406#define WM8995_WSEQ_DELAY61_SHIFT 0 /* WSEQ_DELAY61 - [3:0] */
6407#define WM8995_WSEQ_DELAY61_WIDTH 4 /* WSEQ_DELAY61 - [3:0] */
6408
6409/*
6410 * R12536 (0x30F8) - Write Sequencer 248
6411 */
6412#define WM8995_WSEQ_ADDR62_MASK 0x3FFF /* WSEQ_ADDR62 - [13:0] */
6413#define WM8995_WSEQ_ADDR62_SHIFT 0 /* WSEQ_ADDR62 - [13:0] */
6414#define WM8995_WSEQ_ADDR62_WIDTH 14 /* WSEQ_ADDR62 - [13:0] */
6415
6416/*
6417 * R12537 (0x30F9) - Write Sequencer 249
6418 */
6419#define WM8995_WSEQ_DATA62_MASK 0x00FF /* WSEQ_DATA62 - [7:0] */
6420#define WM8995_WSEQ_DATA62_SHIFT 0 /* WSEQ_DATA62 - [7:0] */
6421#define WM8995_WSEQ_DATA62_WIDTH 8 /* WSEQ_DATA62 - [7:0] */
6422
6423/*
6424 * R12538 (0x30FA) - Write Sequencer 250
6425 */
6426#define WM8995_WSEQ_DATA_WIDTH62_MASK 0x0700 /* WSEQ_DATA_WIDTH62 - [10:8] */
6427#define WM8995_WSEQ_DATA_WIDTH62_SHIFT 8 /* WSEQ_DATA_WIDTH62 - [10:8] */
6428#define WM8995_WSEQ_DATA_WIDTH62_WIDTH 3 /* WSEQ_DATA_WIDTH62 - [10:8] */
6429#define WM8995_WSEQ_DATA_START62_MASK 0x000F /* WSEQ_DATA_START62 - [3:0] */
6430#define WM8995_WSEQ_DATA_START62_SHIFT 0 /* WSEQ_DATA_START62 - [3:0] */
6431#define WM8995_WSEQ_DATA_START62_WIDTH 4 /* WSEQ_DATA_START62 - [3:0] */
6432
6433/*
6434 * R12539 (0x30FB) - Write Sequencer 251
6435 */
6436#define WM8995_WSEQ_EOS62 0x0100 /* WSEQ_EOS62 */
6437#define WM8995_WSEQ_EOS62_MASK 0x0100 /* WSEQ_EOS62 */
6438#define WM8995_WSEQ_EOS62_SHIFT 8 /* WSEQ_EOS62 */
6439#define WM8995_WSEQ_EOS62_WIDTH 1 /* WSEQ_EOS62 */
6440#define WM8995_WSEQ_DELAY62_MASK 0x000F /* WSEQ_DELAY62 - [3:0] */
6441#define WM8995_WSEQ_DELAY62_SHIFT 0 /* WSEQ_DELAY62 - [3:0] */
6442#define WM8995_WSEQ_DELAY62_WIDTH 4 /* WSEQ_DELAY62 - [3:0] */
6443
6444/*
6445 * R12540 (0x30FC) - Write Sequencer 252
6446 */
6447#define WM8995_WSEQ_ADDR63_MASK 0x3FFF /* WSEQ_ADDR63 - [13:0] */
6448#define WM8995_WSEQ_ADDR63_SHIFT 0 /* WSEQ_ADDR63 - [13:0] */
6449#define WM8995_WSEQ_ADDR63_WIDTH 14 /* WSEQ_ADDR63 - [13:0] */
6450
6451/*
6452 * R12541 (0x30FD) - Write Sequencer 253
6453 */
6454#define WM8995_WSEQ_DATA63_MASK 0x00FF /* WSEQ_DATA63 - [7:0] */
6455#define WM8995_WSEQ_DATA63_SHIFT 0 /* WSEQ_DATA63 - [7:0] */
6456#define WM8995_WSEQ_DATA63_WIDTH 8 /* WSEQ_DATA63 - [7:0] */
6457
6458/*
6459 * R12542 (0x30FE) - Write Sequencer 254
6460 */
6461#define WM8995_WSEQ_DATA_WIDTH63_MASK 0x0700 /* WSEQ_DATA_WIDTH63 - [10:8] */
6462#define WM8995_WSEQ_DATA_WIDTH63_SHIFT 8 /* WSEQ_DATA_WIDTH63 - [10:8] */
6463#define WM8995_WSEQ_DATA_WIDTH63_WIDTH 3 /* WSEQ_DATA_WIDTH63 - [10:8] */
6464#define WM8995_WSEQ_DATA_START63_MASK 0x000F /* WSEQ_DATA_START63 - [3:0] */
6465#define WM8995_WSEQ_DATA_START63_SHIFT 0 /* WSEQ_DATA_START63 - [3:0] */
6466#define WM8995_WSEQ_DATA_START63_WIDTH 4 /* WSEQ_DATA_START63 - [3:0] */
6467
6468/*
6469 * R12543 (0x30FF) - Write Sequencer 255
6470 */
6471#define WM8995_WSEQ_EOS63 0x0100 /* WSEQ_EOS63 */
6472#define WM8995_WSEQ_EOS63_MASK 0x0100 /* WSEQ_EOS63 */
6473#define WM8995_WSEQ_EOS63_SHIFT 8 /* WSEQ_EOS63 */
6474#define WM8995_WSEQ_EOS63_WIDTH 1 /* WSEQ_EOS63 */
6475#define WM8995_WSEQ_DELAY63_MASK 0x000F /* WSEQ_DELAY63 - [3:0] */
6476#define WM8995_WSEQ_DELAY63_SHIFT 0 /* WSEQ_DELAY63 - [3:0] */
6477#define WM8995_WSEQ_DELAY63_WIDTH 4 /* WSEQ_DELAY63 - [3:0] */
6478
6479/*
6480 * R12544 (0x3100) - Write Sequencer 256
6481 */
6482#define WM8995_WSEQ_ADDR64_MASK 0x3FFF /* WSEQ_ADDR64 - [13:0] */
6483#define WM8995_WSEQ_ADDR64_SHIFT 0 /* WSEQ_ADDR64 - [13:0] */
6484#define WM8995_WSEQ_ADDR64_WIDTH 14 /* WSEQ_ADDR64 - [13:0] */
6485
6486/*
6487 * R12545 (0x3101) - Write Sequencer 257
6488 */
6489#define WM8995_WSEQ_DATA64_MASK 0x00FF /* WSEQ_DATA64 - [7:0] */
6490#define WM8995_WSEQ_DATA64_SHIFT 0 /* WSEQ_DATA64 - [7:0] */
6491#define WM8995_WSEQ_DATA64_WIDTH 8 /* WSEQ_DATA64 - [7:0] */
6492
6493/*
6494 * R12546 (0x3102) - Write Sequencer 258
6495 */
6496#define WM8995_WSEQ_DATA_WIDTH64_MASK 0x0700 /* WSEQ_DATA_WIDTH64 - [10:8] */
6497#define WM8995_WSEQ_DATA_WIDTH64_SHIFT 8 /* WSEQ_DATA_WIDTH64 - [10:8] */
6498#define WM8995_WSEQ_DATA_WIDTH64_WIDTH 3 /* WSEQ_DATA_WIDTH64 - [10:8] */
6499#define WM8995_WSEQ_DATA_START64_MASK 0x000F /* WSEQ_DATA_START64 - [3:0] */
6500#define WM8995_WSEQ_DATA_START64_SHIFT 0 /* WSEQ_DATA_START64 - [3:0] */
6501#define WM8995_WSEQ_DATA_START64_WIDTH 4 /* WSEQ_DATA_START64 - [3:0] */
6502
6503/*
6504 * R12547 (0x3103) - Write Sequencer 259
6505 */
6506#define WM8995_WSEQ_EOS64 0x0100 /* WSEQ_EOS64 */
6507#define WM8995_WSEQ_EOS64_MASK 0x0100 /* WSEQ_EOS64 */
6508#define WM8995_WSEQ_EOS64_SHIFT 8 /* WSEQ_EOS64 */
6509#define WM8995_WSEQ_EOS64_WIDTH 1 /* WSEQ_EOS64 */
6510#define WM8995_WSEQ_DELAY64_MASK 0x000F /* WSEQ_DELAY64 - [3:0] */
6511#define WM8995_WSEQ_DELAY64_SHIFT 0 /* WSEQ_DELAY64 - [3:0] */
6512#define WM8995_WSEQ_DELAY64_WIDTH 4 /* WSEQ_DELAY64 - [3:0] */
6513
6514/*
6515 * R12548 (0x3104) - Write Sequencer 260
6516 */
6517#define WM8995_WSEQ_ADDR65_MASK 0x3FFF /* WSEQ_ADDR65 - [13:0] */
6518#define WM8995_WSEQ_ADDR65_SHIFT 0 /* WSEQ_ADDR65 - [13:0] */
6519#define WM8995_WSEQ_ADDR65_WIDTH 14 /* WSEQ_ADDR65 - [13:0] */
6520
6521/*
6522 * R12549 (0x3105) - Write Sequencer 261
6523 */
6524#define WM8995_WSEQ_DATA65_MASK 0x00FF /* WSEQ_DATA65 - [7:0] */
6525#define WM8995_WSEQ_DATA65_SHIFT 0 /* WSEQ_DATA65 - [7:0] */
6526#define WM8995_WSEQ_DATA65_WIDTH 8 /* WSEQ_DATA65 - [7:0] */
6527
6528/*
6529 * R12550 (0x3106) - Write Sequencer 262
6530 */
6531#define WM8995_WSEQ_DATA_WIDTH65_MASK 0x0700 /* WSEQ_DATA_WIDTH65 - [10:8] */
6532#define WM8995_WSEQ_DATA_WIDTH65_SHIFT 8 /* WSEQ_DATA_WIDTH65 - [10:8] */
6533#define WM8995_WSEQ_DATA_WIDTH65_WIDTH 3 /* WSEQ_DATA_WIDTH65 - [10:8] */
6534#define WM8995_WSEQ_DATA_START65_MASK 0x000F /* WSEQ_DATA_START65 - [3:0] */
6535#define WM8995_WSEQ_DATA_START65_SHIFT 0 /* WSEQ_DATA_START65 - [3:0] */
6536#define WM8995_WSEQ_DATA_START65_WIDTH 4 /* WSEQ_DATA_START65 - [3:0] */
6537
6538/*
6539 * R12551 (0x3107) - Write Sequencer 263
6540 */
6541#define WM8995_WSEQ_EOS65 0x0100 /* WSEQ_EOS65 */
6542#define WM8995_WSEQ_EOS65_MASK 0x0100 /* WSEQ_EOS65 */
6543#define WM8995_WSEQ_EOS65_SHIFT 8 /* WSEQ_EOS65 */
6544#define WM8995_WSEQ_EOS65_WIDTH 1 /* WSEQ_EOS65 */
6545#define WM8995_WSEQ_DELAY65_MASK 0x000F /* WSEQ_DELAY65 - [3:0] */
6546#define WM8995_WSEQ_DELAY65_SHIFT 0 /* WSEQ_DELAY65 - [3:0] */
6547#define WM8995_WSEQ_DELAY65_WIDTH 4 /* WSEQ_DELAY65 - [3:0] */
6548
6549/*
6550 * R12552 (0x3108) - Write Sequencer 264
6551 */
6552#define WM8995_WSEQ_ADDR66_MASK 0x3FFF /* WSEQ_ADDR66 - [13:0] */
6553#define WM8995_WSEQ_ADDR66_SHIFT 0 /* WSEQ_ADDR66 - [13:0] */
6554#define WM8995_WSEQ_ADDR66_WIDTH 14 /* WSEQ_ADDR66 - [13:0] */
6555
6556/*
6557 * R12553 (0x3109) - Write Sequencer 265
6558 */
6559#define WM8995_WSEQ_DATA66_MASK 0x00FF /* WSEQ_DATA66 - [7:0] */
6560#define WM8995_WSEQ_DATA66_SHIFT 0 /* WSEQ_DATA66 - [7:0] */
6561#define WM8995_WSEQ_DATA66_WIDTH 8 /* WSEQ_DATA66 - [7:0] */
6562
6563/*
6564 * R12554 (0x310A) - Write Sequencer 266
6565 */
6566#define WM8995_WSEQ_DATA_WIDTH66_MASK 0x0700 /* WSEQ_DATA_WIDTH66 - [10:8] */
6567#define WM8995_WSEQ_DATA_WIDTH66_SHIFT 8 /* WSEQ_DATA_WIDTH66 - [10:8] */
6568#define WM8995_WSEQ_DATA_WIDTH66_WIDTH 3 /* WSEQ_DATA_WIDTH66 - [10:8] */
6569#define WM8995_WSEQ_DATA_START66_MASK 0x000F /* WSEQ_DATA_START66 - [3:0] */
6570#define WM8995_WSEQ_DATA_START66_SHIFT 0 /* WSEQ_DATA_START66 - [3:0] */
6571#define WM8995_WSEQ_DATA_START66_WIDTH 4 /* WSEQ_DATA_START66 - [3:0] */
6572
6573/*
6574 * R12555 (0x310B) - Write Sequencer 267
6575 */
6576#define WM8995_WSEQ_EOS66 0x0100 /* WSEQ_EOS66 */
6577#define WM8995_WSEQ_EOS66_MASK 0x0100 /* WSEQ_EOS66 */
6578#define WM8995_WSEQ_EOS66_SHIFT 8 /* WSEQ_EOS66 */
6579#define WM8995_WSEQ_EOS66_WIDTH 1 /* WSEQ_EOS66 */
6580#define WM8995_WSEQ_DELAY66_MASK 0x000F /* WSEQ_DELAY66 - [3:0] */
6581#define WM8995_WSEQ_DELAY66_SHIFT 0 /* WSEQ_DELAY66 - [3:0] */
6582#define WM8995_WSEQ_DELAY66_WIDTH 4 /* WSEQ_DELAY66 - [3:0] */
6583
6584/*
6585 * R12556 (0x310C) - Write Sequencer 268
6586 */
6587#define WM8995_WSEQ_ADDR67_MASK 0x3FFF /* WSEQ_ADDR67 - [13:0] */
6588#define WM8995_WSEQ_ADDR67_SHIFT 0 /* WSEQ_ADDR67 - [13:0] */
6589#define WM8995_WSEQ_ADDR67_WIDTH 14 /* WSEQ_ADDR67 - [13:0] */
6590
6591/*
6592 * R12557 (0x310D) - Write Sequencer 269
6593 */
6594#define WM8995_WSEQ_DATA67_MASK 0x00FF /* WSEQ_DATA67 - [7:0] */
6595#define WM8995_WSEQ_DATA67_SHIFT 0 /* WSEQ_DATA67 - [7:0] */
6596#define WM8995_WSEQ_DATA67_WIDTH 8 /* WSEQ_DATA67 - [7:0] */
6597
6598/*
6599 * R12558 (0x310E) - Write Sequencer 270
6600 */
6601#define WM8995_WSEQ_DATA_WIDTH67_MASK 0x0700 /* WSEQ_DATA_WIDTH67 - [10:8] */
6602#define WM8995_WSEQ_DATA_WIDTH67_SHIFT 8 /* WSEQ_DATA_WIDTH67 - [10:8] */
6603#define WM8995_WSEQ_DATA_WIDTH67_WIDTH 3 /* WSEQ_DATA_WIDTH67 - [10:8] */
6604#define WM8995_WSEQ_DATA_START67_MASK 0x000F /* WSEQ_DATA_START67 - [3:0] */
6605#define WM8995_WSEQ_DATA_START67_SHIFT 0 /* WSEQ_DATA_START67 - [3:0] */
6606#define WM8995_WSEQ_DATA_START67_WIDTH 4 /* WSEQ_DATA_START67 - [3:0] */
6607
6608/*
6609 * R12559 (0x310F) - Write Sequencer 271
6610 */
6611#define WM8995_WSEQ_EOS67 0x0100 /* WSEQ_EOS67 */
6612#define WM8995_WSEQ_EOS67_MASK 0x0100 /* WSEQ_EOS67 */
6613#define WM8995_WSEQ_EOS67_SHIFT 8 /* WSEQ_EOS67 */
6614#define WM8995_WSEQ_EOS67_WIDTH 1 /* WSEQ_EOS67 */
6615#define WM8995_WSEQ_DELAY67_MASK 0x000F /* WSEQ_DELAY67 - [3:0] */
6616#define WM8995_WSEQ_DELAY67_SHIFT 0 /* WSEQ_DELAY67 - [3:0] */
6617#define WM8995_WSEQ_DELAY67_WIDTH 4 /* WSEQ_DELAY67 - [3:0] */
6618
6619/*
6620 * R12560 (0x3110) - Write Sequencer 272
6621 */
6622#define WM8995_WSEQ_ADDR68_MASK 0x3FFF /* WSEQ_ADDR68 - [13:0] */
6623#define WM8995_WSEQ_ADDR68_SHIFT 0 /* WSEQ_ADDR68 - [13:0] */
6624#define WM8995_WSEQ_ADDR68_WIDTH 14 /* WSEQ_ADDR68 - [13:0] */
6625
6626/*
6627 * R12561 (0x3111) - Write Sequencer 273
6628 */
6629#define WM8995_WSEQ_DATA68_MASK 0x00FF /* WSEQ_DATA68 - [7:0] */
6630#define WM8995_WSEQ_DATA68_SHIFT 0 /* WSEQ_DATA68 - [7:0] */
6631#define WM8995_WSEQ_DATA68_WIDTH 8 /* WSEQ_DATA68 - [7:0] */
6632
6633/*
6634 * R12562 (0x3112) - Write Sequencer 274
6635 */
6636#define WM8995_WSEQ_DATA_WIDTH68_MASK 0x0700 /* WSEQ_DATA_WIDTH68 - [10:8] */
6637#define WM8995_WSEQ_DATA_WIDTH68_SHIFT 8 /* WSEQ_DATA_WIDTH68 - [10:8] */
6638#define WM8995_WSEQ_DATA_WIDTH68_WIDTH 3 /* WSEQ_DATA_WIDTH68 - [10:8] */
6639#define WM8995_WSEQ_DATA_START68_MASK 0x000F /* WSEQ_DATA_START68 - [3:0] */
6640#define WM8995_WSEQ_DATA_START68_SHIFT 0 /* WSEQ_DATA_START68 - [3:0] */
6641#define WM8995_WSEQ_DATA_START68_WIDTH 4 /* WSEQ_DATA_START68 - [3:0] */
6642
6643/*
6644 * R12563 (0x3113) - Write Sequencer 275
6645 */
6646#define WM8995_WSEQ_EOS68 0x0100 /* WSEQ_EOS68 */
6647#define WM8995_WSEQ_EOS68_MASK 0x0100 /* WSEQ_EOS68 */
6648#define WM8995_WSEQ_EOS68_SHIFT 8 /* WSEQ_EOS68 */
6649#define WM8995_WSEQ_EOS68_WIDTH 1 /* WSEQ_EOS68 */
6650#define WM8995_WSEQ_DELAY68_MASK 0x000F /* WSEQ_DELAY68 - [3:0] */
6651#define WM8995_WSEQ_DELAY68_SHIFT 0 /* WSEQ_DELAY68 - [3:0] */
6652#define WM8995_WSEQ_DELAY68_WIDTH 4 /* WSEQ_DELAY68 - [3:0] */
6653
6654/*
6655 * R12564 (0x3114) - Write Sequencer 276
6656 */
6657#define WM8995_WSEQ_ADDR69_MASK 0x3FFF /* WSEQ_ADDR69 - [13:0] */
6658#define WM8995_WSEQ_ADDR69_SHIFT 0 /* WSEQ_ADDR69 - [13:0] */
6659#define WM8995_WSEQ_ADDR69_WIDTH 14 /* WSEQ_ADDR69 - [13:0] */
6660
6661/*
6662 * R12565 (0x3115) - Write Sequencer 277
6663 */
6664#define WM8995_WSEQ_DATA69_MASK 0x00FF /* WSEQ_DATA69 - [7:0] */
6665#define WM8995_WSEQ_DATA69_SHIFT 0 /* WSEQ_DATA69 - [7:0] */
6666#define WM8995_WSEQ_DATA69_WIDTH 8 /* WSEQ_DATA69 - [7:0] */
6667
6668/*
6669 * R12566 (0x3116) - Write Sequencer 278
6670 */
6671#define WM8995_WSEQ_DATA_WIDTH69_MASK 0x0700 /* WSEQ_DATA_WIDTH69 - [10:8] */
6672#define WM8995_WSEQ_DATA_WIDTH69_SHIFT 8 /* WSEQ_DATA_WIDTH69 - [10:8] */
6673#define WM8995_WSEQ_DATA_WIDTH69_WIDTH 3 /* WSEQ_DATA_WIDTH69 - [10:8] */
6674#define WM8995_WSEQ_DATA_START69_MASK 0x000F /* WSEQ_DATA_START69 - [3:0] */
6675#define WM8995_WSEQ_DATA_START69_SHIFT 0 /* WSEQ_DATA_START69 - [3:0] */
6676#define WM8995_WSEQ_DATA_START69_WIDTH 4 /* WSEQ_DATA_START69 - [3:0] */
6677
6678/*
6679 * R12567 (0x3117) - Write Sequencer 279
6680 */
6681#define WM8995_WSEQ_EOS69 0x0100 /* WSEQ_EOS69 */
6682#define WM8995_WSEQ_EOS69_MASK 0x0100 /* WSEQ_EOS69 */
6683#define WM8995_WSEQ_EOS69_SHIFT 8 /* WSEQ_EOS69 */
6684#define WM8995_WSEQ_EOS69_WIDTH 1 /* WSEQ_EOS69 */
6685#define WM8995_WSEQ_DELAY69_MASK 0x000F /* WSEQ_DELAY69 - [3:0] */
6686#define WM8995_WSEQ_DELAY69_SHIFT 0 /* WSEQ_DELAY69 - [3:0] */
6687#define WM8995_WSEQ_DELAY69_WIDTH 4 /* WSEQ_DELAY69 - [3:0] */
6688
6689/*
6690 * R12568 (0x3118) - Write Sequencer 280
6691 */
6692#define WM8995_WSEQ_ADDR70_MASK 0x3FFF /* WSEQ_ADDR70 - [13:0] */
6693#define WM8995_WSEQ_ADDR70_SHIFT 0 /* WSEQ_ADDR70 - [13:0] */
6694#define WM8995_WSEQ_ADDR70_WIDTH 14 /* WSEQ_ADDR70 - [13:0] */
6695
6696/*
6697 * R12569 (0x3119) - Write Sequencer 281
6698 */
6699#define WM8995_WSEQ_DATA70_MASK 0x00FF /* WSEQ_DATA70 - [7:0] */
6700#define WM8995_WSEQ_DATA70_SHIFT 0 /* WSEQ_DATA70 - [7:0] */
6701#define WM8995_WSEQ_DATA70_WIDTH 8 /* WSEQ_DATA70 - [7:0] */
6702
6703/*
6704 * R12570 (0x311A) - Write Sequencer 282
6705 */
6706#define WM8995_WSEQ_DATA_WIDTH70_MASK 0x0700 /* WSEQ_DATA_WIDTH70 - [10:8] */
6707#define WM8995_WSEQ_DATA_WIDTH70_SHIFT 8 /* WSEQ_DATA_WIDTH70 - [10:8] */
6708#define WM8995_WSEQ_DATA_WIDTH70_WIDTH 3 /* WSEQ_DATA_WIDTH70 - [10:8] */
6709#define WM8995_WSEQ_DATA_START70_MASK 0x000F /* WSEQ_DATA_START70 - [3:0] */
6710#define WM8995_WSEQ_DATA_START70_SHIFT 0 /* WSEQ_DATA_START70 - [3:0] */
6711#define WM8995_WSEQ_DATA_START70_WIDTH 4 /* WSEQ_DATA_START70 - [3:0] */
6712
6713/*
6714 * R12571 (0x311B) - Write Sequencer 283
6715 */
6716#define WM8995_WSEQ_EOS70 0x0100 /* WSEQ_EOS70 */
6717#define WM8995_WSEQ_EOS70_MASK 0x0100 /* WSEQ_EOS70 */
6718#define WM8995_WSEQ_EOS70_SHIFT 8 /* WSEQ_EOS70 */
6719#define WM8995_WSEQ_EOS70_WIDTH 1 /* WSEQ_EOS70 */
6720#define WM8995_WSEQ_DELAY70_MASK 0x000F /* WSEQ_DELAY70 - [3:0] */
6721#define WM8995_WSEQ_DELAY70_SHIFT 0 /* WSEQ_DELAY70 - [3:0] */
6722#define WM8995_WSEQ_DELAY70_WIDTH 4 /* WSEQ_DELAY70 - [3:0] */
6723
6724/*
6725 * R12572 (0x311C) - Write Sequencer 284
6726 */
6727#define WM8995_WSEQ_ADDR71_MASK 0x3FFF /* WSEQ_ADDR71 - [13:0] */
6728#define WM8995_WSEQ_ADDR71_SHIFT 0 /* WSEQ_ADDR71 - [13:0] */
6729#define WM8995_WSEQ_ADDR71_WIDTH 14 /* WSEQ_ADDR71 - [13:0] */
6730
6731/*
6732 * R12573 (0x311D) - Write Sequencer 285
6733 */
6734#define WM8995_WSEQ_DATA71_MASK 0x00FF /* WSEQ_DATA71 - [7:0] */
6735#define WM8995_WSEQ_DATA71_SHIFT 0 /* WSEQ_DATA71 - [7:0] */
6736#define WM8995_WSEQ_DATA71_WIDTH 8 /* WSEQ_DATA71 - [7:0] */
6737
6738/*
6739 * R12574 (0x311E) - Write Sequencer 286
6740 */
6741#define WM8995_WSEQ_DATA_WIDTH71_MASK 0x0700 /* WSEQ_DATA_WIDTH71 - [10:8] */
6742#define WM8995_WSEQ_DATA_WIDTH71_SHIFT 8 /* WSEQ_DATA_WIDTH71 - [10:8] */
6743#define WM8995_WSEQ_DATA_WIDTH71_WIDTH 3 /* WSEQ_DATA_WIDTH71 - [10:8] */
6744#define WM8995_WSEQ_DATA_START71_MASK 0x000F /* WSEQ_DATA_START71 - [3:0] */
6745#define WM8995_WSEQ_DATA_START71_SHIFT 0 /* WSEQ_DATA_START71 - [3:0] */
6746#define WM8995_WSEQ_DATA_START71_WIDTH 4 /* WSEQ_DATA_START71 - [3:0] */
6747
6748/*
6749 * R12575 (0x311F) - Write Sequencer 287
6750 */
6751#define WM8995_WSEQ_EOS71 0x0100 /* WSEQ_EOS71 */
6752#define WM8995_WSEQ_EOS71_MASK 0x0100 /* WSEQ_EOS71 */
6753#define WM8995_WSEQ_EOS71_SHIFT 8 /* WSEQ_EOS71 */
6754#define WM8995_WSEQ_EOS71_WIDTH 1 /* WSEQ_EOS71 */
6755#define WM8995_WSEQ_DELAY71_MASK 0x000F /* WSEQ_DELAY71 - [3:0] */
6756#define WM8995_WSEQ_DELAY71_SHIFT 0 /* WSEQ_DELAY71 - [3:0] */
6757#define WM8995_WSEQ_DELAY71_WIDTH 4 /* WSEQ_DELAY71 - [3:0] */
6758
6759/*
6760 * R12576 (0x3120) - Write Sequencer 288
6761 */
6762#define WM8995_WSEQ_ADDR72_MASK 0x3FFF /* WSEQ_ADDR72 - [13:0] */
6763#define WM8995_WSEQ_ADDR72_SHIFT 0 /* WSEQ_ADDR72 - [13:0] */
6764#define WM8995_WSEQ_ADDR72_WIDTH 14 /* WSEQ_ADDR72 - [13:0] */
6765
6766/*
6767 * R12577 (0x3121) - Write Sequencer 289
6768 */
6769#define WM8995_WSEQ_DATA72_MASK 0x00FF /* WSEQ_DATA72 - [7:0] */
6770#define WM8995_WSEQ_DATA72_SHIFT 0 /* WSEQ_DATA72 - [7:0] */
6771#define WM8995_WSEQ_DATA72_WIDTH 8 /* WSEQ_DATA72 - [7:0] */
6772
6773/*
6774 * R12578 (0x3122) - Write Sequencer 290
6775 */
6776#define WM8995_WSEQ_DATA_WIDTH72_MASK 0x0700 /* WSEQ_DATA_WIDTH72 - [10:8] */
6777#define WM8995_WSEQ_DATA_WIDTH72_SHIFT 8 /* WSEQ_DATA_WIDTH72 - [10:8] */
6778#define WM8995_WSEQ_DATA_WIDTH72_WIDTH 3 /* WSEQ_DATA_WIDTH72 - [10:8] */
6779#define WM8995_WSEQ_DATA_START72_MASK 0x000F /* WSEQ_DATA_START72 - [3:0] */
6780#define WM8995_WSEQ_DATA_START72_SHIFT 0 /* WSEQ_DATA_START72 - [3:0] */
6781#define WM8995_WSEQ_DATA_START72_WIDTH 4 /* WSEQ_DATA_START72 - [3:0] */
6782
6783/*
6784 * R12579 (0x3123) - Write Sequencer 291
6785 */
6786#define WM8995_WSEQ_EOS72 0x0100 /* WSEQ_EOS72 */
6787#define WM8995_WSEQ_EOS72_MASK 0x0100 /* WSEQ_EOS72 */
6788#define WM8995_WSEQ_EOS72_SHIFT 8 /* WSEQ_EOS72 */
6789#define WM8995_WSEQ_EOS72_WIDTH 1 /* WSEQ_EOS72 */
6790#define WM8995_WSEQ_DELAY72_MASK 0x000F /* WSEQ_DELAY72 - [3:0] */
6791#define WM8995_WSEQ_DELAY72_SHIFT 0 /* WSEQ_DELAY72 - [3:0] */
6792#define WM8995_WSEQ_DELAY72_WIDTH 4 /* WSEQ_DELAY72 - [3:0] */
6793
6794/*
6795 * R12580 (0x3124) - Write Sequencer 292
6796 */
6797#define WM8995_WSEQ_ADDR73_MASK 0x3FFF /* WSEQ_ADDR73 - [13:0] */
6798#define WM8995_WSEQ_ADDR73_SHIFT 0 /* WSEQ_ADDR73 - [13:0] */
6799#define WM8995_WSEQ_ADDR73_WIDTH 14 /* WSEQ_ADDR73 - [13:0] */
6800
6801/*
6802 * R12581 (0x3125) - Write Sequencer 293
6803 */
6804#define WM8995_WSEQ_DATA73_MASK 0x00FF /* WSEQ_DATA73 - [7:0] */
6805#define WM8995_WSEQ_DATA73_SHIFT 0 /* WSEQ_DATA73 - [7:0] */
6806#define WM8995_WSEQ_DATA73_WIDTH 8 /* WSEQ_DATA73 - [7:0] */
6807
6808/*
6809 * R12582 (0x3126) - Write Sequencer 294
6810 */
6811#define WM8995_WSEQ_DATA_WIDTH73_MASK 0x0700 /* WSEQ_DATA_WIDTH73 - [10:8] */
6812#define WM8995_WSEQ_DATA_WIDTH73_SHIFT 8 /* WSEQ_DATA_WIDTH73 - [10:8] */
6813#define WM8995_WSEQ_DATA_WIDTH73_WIDTH 3 /* WSEQ_DATA_WIDTH73 - [10:8] */
6814#define WM8995_WSEQ_DATA_START73_MASK 0x000F /* WSEQ_DATA_START73 - [3:0] */
6815#define WM8995_WSEQ_DATA_START73_SHIFT 0 /* WSEQ_DATA_START73 - [3:0] */
6816#define WM8995_WSEQ_DATA_START73_WIDTH 4 /* WSEQ_DATA_START73 - [3:0] */
6817
6818/*
6819 * R12583 (0x3127) - Write Sequencer 295
6820 */
6821#define WM8995_WSEQ_EOS73 0x0100 /* WSEQ_EOS73 */
6822#define WM8995_WSEQ_EOS73_MASK 0x0100 /* WSEQ_EOS73 */
6823#define WM8995_WSEQ_EOS73_SHIFT 8 /* WSEQ_EOS73 */
6824#define WM8995_WSEQ_EOS73_WIDTH 1 /* WSEQ_EOS73 */
6825#define WM8995_WSEQ_DELAY73_MASK 0x000F /* WSEQ_DELAY73 - [3:0] */
6826#define WM8995_WSEQ_DELAY73_SHIFT 0 /* WSEQ_DELAY73 - [3:0] */
6827#define WM8995_WSEQ_DELAY73_WIDTH 4 /* WSEQ_DELAY73 - [3:0] */
6828
6829/*
6830 * R12584 (0x3128) - Write Sequencer 296
6831 */
6832#define WM8995_WSEQ_ADDR74_MASK 0x3FFF /* WSEQ_ADDR74 - [13:0] */
6833#define WM8995_WSEQ_ADDR74_SHIFT 0 /* WSEQ_ADDR74 - [13:0] */
6834#define WM8995_WSEQ_ADDR74_WIDTH 14 /* WSEQ_ADDR74 - [13:0] */
6835
6836/*
6837 * R12585 (0x3129) - Write Sequencer 297
6838 */
6839#define WM8995_WSEQ_DATA74_MASK 0x00FF /* WSEQ_DATA74 - [7:0] */
6840#define WM8995_WSEQ_DATA74_SHIFT 0 /* WSEQ_DATA74 - [7:0] */
6841#define WM8995_WSEQ_DATA74_WIDTH 8 /* WSEQ_DATA74 - [7:0] */
6842
6843/*
6844 * R12586 (0x312A) - Write Sequencer 298
6845 */
6846#define WM8995_WSEQ_DATA_WIDTH74_MASK 0x0700 /* WSEQ_DATA_WIDTH74 - [10:8] */
6847#define WM8995_WSEQ_DATA_WIDTH74_SHIFT 8 /* WSEQ_DATA_WIDTH74 - [10:8] */
6848#define WM8995_WSEQ_DATA_WIDTH74_WIDTH 3 /* WSEQ_DATA_WIDTH74 - [10:8] */
6849#define WM8995_WSEQ_DATA_START74_MASK 0x000F /* WSEQ_DATA_START74 - [3:0] */
6850#define WM8995_WSEQ_DATA_START74_SHIFT 0 /* WSEQ_DATA_START74 - [3:0] */
6851#define WM8995_WSEQ_DATA_START74_WIDTH 4 /* WSEQ_DATA_START74 - [3:0] */
6852
6853/*
6854 * R12587 (0x312B) - Write Sequencer 299
6855 */
6856#define WM8995_WSEQ_EOS74 0x0100 /* WSEQ_EOS74 */
6857#define WM8995_WSEQ_EOS74_MASK 0x0100 /* WSEQ_EOS74 */
6858#define WM8995_WSEQ_EOS74_SHIFT 8 /* WSEQ_EOS74 */
6859#define WM8995_WSEQ_EOS74_WIDTH 1 /* WSEQ_EOS74 */
6860#define WM8995_WSEQ_DELAY74_MASK 0x000F /* WSEQ_DELAY74 - [3:0] */
6861#define WM8995_WSEQ_DELAY74_SHIFT 0 /* WSEQ_DELAY74 - [3:0] */
6862#define WM8995_WSEQ_DELAY74_WIDTH 4 /* WSEQ_DELAY74 - [3:0] */
6863
6864/*
6865 * R12588 (0x312C) - Write Sequencer 300
6866 */
6867#define WM8995_WSEQ_ADDR75_MASK 0x3FFF /* WSEQ_ADDR75 - [13:0] */
6868#define WM8995_WSEQ_ADDR75_SHIFT 0 /* WSEQ_ADDR75 - [13:0] */
6869#define WM8995_WSEQ_ADDR75_WIDTH 14 /* WSEQ_ADDR75 - [13:0] */
6870
6871/*
6872 * R12589 (0x312D) - Write Sequencer 301
6873 */
6874#define WM8995_WSEQ_DATA75_MASK 0x00FF /* WSEQ_DATA75 - [7:0] */
6875#define WM8995_WSEQ_DATA75_SHIFT 0 /* WSEQ_DATA75 - [7:0] */
6876#define WM8995_WSEQ_DATA75_WIDTH 8 /* WSEQ_DATA75 - [7:0] */
6877
6878/*
6879 * R12590 (0x312E) - Write Sequencer 302
6880 */
6881#define WM8995_WSEQ_DATA_WIDTH75_MASK 0x0700 /* WSEQ_DATA_WIDTH75 - [10:8] */
6882#define WM8995_WSEQ_DATA_WIDTH75_SHIFT 8 /* WSEQ_DATA_WIDTH75 - [10:8] */
6883#define WM8995_WSEQ_DATA_WIDTH75_WIDTH 3 /* WSEQ_DATA_WIDTH75 - [10:8] */
6884#define WM8995_WSEQ_DATA_START75_MASK 0x000F /* WSEQ_DATA_START75 - [3:0] */
6885#define WM8995_WSEQ_DATA_START75_SHIFT 0 /* WSEQ_DATA_START75 - [3:0] */
6886#define WM8995_WSEQ_DATA_START75_WIDTH 4 /* WSEQ_DATA_START75 - [3:0] */
6887
6888/*
6889 * R12591 (0x312F) - Write Sequencer 303
6890 */
6891#define WM8995_WSEQ_EOS75 0x0100 /* WSEQ_EOS75 */
6892#define WM8995_WSEQ_EOS75_MASK 0x0100 /* WSEQ_EOS75 */
6893#define WM8995_WSEQ_EOS75_SHIFT 8 /* WSEQ_EOS75 */
6894#define WM8995_WSEQ_EOS75_WIDTH 1 /* WSEQ_EOS75 */
6895#define WM8995_WSEQ_DELAY75_MASK 0x000F /* WSEQ_DELAY75 - [3:0] */
6896#define WM8995_WSEQ_DELAY75_SHIFT 0 /* WSEQ_DELAY75 - [3:0] */
6897#define WM8995_WSEQ_DELAY75_WIDTH 4 /* WSEQ_DELAY75 - [3:0] */
6898
6899/*
6900 * R12592 (0x3130) - Write Sequencer 304
6901 */
6902#define WM8995_WSEQ_ADDR76_MASK 0x3FFF /* WSEQ_ADDR76 - [13:0] */
6903#define WM8995_WSEQ_ADDR76_SHIFT 0 /* WSEQ_ADDR76 - [13:0] */
6904#define WM8995_WSEQ_ADDR76_WIDTH 14 /* WSEQ_ADDR76 - [13:0] */
6905
6906/*
6907 * R12593 (0x3131) - Write Sequencer 305
6908 */
6909#define WM8995_WSEQ_DATA76_MASK 0x00FF /* WSEQ_DATA76 - [7:0] */
6910#define WM8995_WSEQ_DATA76_SHIFT 0 /* WSEQ_DATA76 - [7:0] */
6911#define WM8995_WSEQ_DATA76_WIDTH 8 /* WSEQ_DATA76 - [7:0] */
6912
6913/*
6914 * R12594 (0x3132) - Write Sequencer 306
6915 */
6916#define WM8995_WSEQ_DATA_WIDTH76_MASK 0x0700 /* WSEQ_DATA_WIDTH76 - [10:8] */
6917#define WM8995_WSEQ_DATA_WIDTH76_SHIFT 8 /* WSEQ_DATA_WIDTH76 - [10:8] */
6918#define WM8995_WSEQ_DATA_WIDTH76_WIDTH 3 /* WSEQ_DATA_WIDTH76 - [10:8] */
6919#define WM8995_WSEQ_DATA_START76_MASK 0x000F /* WSEQ_DATA_START76 - [3:0] */
6920#define WM8995_WSEQ_DATA_START76_SHIFT 0 /* WSEQ_DATA_START76 - [3:0] */
6921#define WM8995_WSEQ_DATA_START76_WIDTH 4 /* WSEQ_DATA_START76 - [3:0] */
6922
6923/*
6924 * R12595 (0x3133) - Write Sequencer 307
6925 */
6926#define WM8995_WSEQ_EOS76 0x0100 /* WSEQ_EOS76 */
6927#define WM8995_WSEQ_EOS76_MASK 0x0100 /* WSEQ_EOS76 */
6928#define WM8995_WSEQ_EOS76_SHIFT 8 /* WSEQ_EOS76 */
6929#define WM8995_WSEQ_EOS76_WIDTH 1 /* WSEQ_EOS76 */
6930#define WM8995_WSEQ_DELAY76_MASK 0x000F /* WSEQ_DELAY76 - [3:0] */
6931#define WM8995_WSEQ_DELAY76_SHIFT 0 /* WSEQ_DELAY76 - [3:0] */
6932#define WM8995_WSEQ_DELAY76_WIDTH 4 /* WSEQ_DELAY76 - [3:0] */
6933
6934/*
6935 * R12596 (0x3134) - Write Sequencer 308
6936 */
6937#define WM8995_WSEQ_ADDR77_MASK 0x3FFF /* WSEQ_ADDR77 - [13:0] */
6938#define WM8995_WSEQ_ADDR77_SHIFT 0 /* WSEQ_ADDR77 - [13:0] */
6939#define WM8995_WSEQ_ADDR77_WIDTH 14 /* WSEQ_ADDR77 - [13:0] */
6940
6941/*
6942 * R12597 (0x3135) - Write Sequencer 309
6943 */
6944#define WM8995_WSEQ_DATA77_MASK 0x00FF /* WSEQ_DATA77 - [7:0] */
6945#define WM8995_WSEQ_DATA77_SHIFT 0 /* WSEQ_DATA77 - [7:0] */
6946#define WM8995_WSEQ_DATA77_WIDTH 8 /* WSEQ_DATA77 - [7:0] */
6947
6948/*
6949 * R12598 (0x3136) - Write Sequencer 310
6950 */
6951#define WM8995_WSEQ_DATA_WIDTH77_MASK 0x0700 /* WSEQ_DATA_WIDTH77 - [10:8] */
6952#define WM8995_WSEQ_DATA_WIDTH77_SHIFT 8 /* WSEQ_DATA_WIDTH77 - [10:8] */
6953#define WM8995_WSEQ_DATA_WIDTH77_WIDTH 3 /* WSEQ_DATA_WIDTH77 - [10:8] */
6954#define WM8995_WSEQ_DATA_START77_MASK 0x000F /* WSEQ_DATA_START77 - [3:0] */
6955#define WM8995_WSEQ_DATA_START77_SHIFT 0 /* WSEQ_DATA_START77 - [3:0] */
6956#define WM8995_WSEQ_DATA_START77_WIDTH 4 /* WSEQ_DATA_START77 - [3:0] */
6957
6958/*
6959 * R12599 (0x3137) - Write Sequencer 311
6960 */
6961#define WM8995_WSEQ_EOS77 0x0100 /* WSEQ_EOS77 */
6962#define WM8995_WSEQ_EOS77_MASK 0x0100 /* WSEQ_EOS77 */
6963#define WM8995_WSEQ_EOS77_SHIFT 8 /* WSEQ_EOS77 */
6964#define WM8995_WSEQ_EOS77_WIDTH 1 /* WSEQ_EOS77 */
6965#define WM8995_WSEQ_DELAY77_MASK 0x000F /* WSEQ_DELAY77 - [3:0] */
6966#define WM8995_WSEQ_DELAY77_SHIFT 0 /* WSEQ_DELAY77 - [3:0] */
6967#define WM8995_WSEQ_DELAY77_WIDTH 4 /* WSEQ_DELAY77 - [3:0] */
6968
6969/*
6970 * R12600 (0x3138) - Write Sequencer 312
6971 */
6972#define WM8995_WSEQ_ADDR78_MASK 0x3FFF /* WSEQ_ADDR78 - [13:0] */
6973#define WM8995_WSEQ_ADDR78_SHIFT 0 /* WSEQ_ADDR78 - [13:0] */
6974#define WM8995_WSEQ_ADDR78_WIDTH 14 /* WSEQ_ADDR78 - [13:0] */
6975
6976/*
6977 * R12601 (0x3139) - Write Sequencer 313
6978 */
6979#define WM8995_WSEQ_DATA78_MASK 0x00FF /* WSEQ_DATA78 - [7:0] */
6980#define WM8995_WSEQ_DATA78_SHIFT 0 /* WSEQ_DATA78 - [7:0] */
6981#define WM8995_WSEQ_DATA78_WIDTH 8 /* WSEQ_DATA78 - [7:0] */
6982
6983/*
6984 * R12602 (0x313A) - Write Sequencer 314
6985 */
6986#define WM8995_WSEQ_DATA_WIDTH78_MASK 0x0700 /* WSEQ_DATA_WIDTH78 - [10:8] */
6987#define WM8995_WSEQ_DATA_WIDTH78_SHIFT 8 /* WSEQ_DATA_WIDTH78 - [10:8] */
6988#define WM8995_WSEQ_DATA_WIDTH78_WIDTH 3 /* WSEQ_DATA_WIDTH78 - [10:8] */
6989#define WM8995_WSEQ_DATA_START78_MASK 0x000F /* WSEQ_DATA_START78 - [3:0] */
6990#define WM8995_WSEQ_DATA_START78_SHIFT 0 /* WSEQ_DATA_START78 - [3:0] */
6991#define WM8995_WSEQ_DATA_START78_WIDTH 4 /* WSEQ_DATA_START78 - [3:0] */
6992
6993/*
6994 * R12603 (0x313B) - Write Sequencer 315
6995 */
6996#define WM8995_WSEQ_EOS78 0x0100 /* WSEQ_EOS78 */
6997#define WM8995_WSEQ_EOS78_MASK 0x0100 /* WSEQ_EOS78 */
6998#define WM8995_WSEQ_EOS78_SHIFT 8 /* WSEQ_EOS78 */
6999#define WM8995_WSEQ_EOS78_WIDTH 1 /* WSEQ_EOS78 */
7000#define WM8995_WSEQ_DELAY78_MASK 0x000F /* WSEQ_DELAY78 - [3:0] */
7001#define WM8995_WSEQ_DELAY78_SHIFT 0 /* WSEQ_DELAY78 - [3:0] */
7002#define WM8995_WSEQ_DELAY78_WIDTH 4 /* WSEQ_DELAY78 - [3:0] */
7003
7004/*
7005 * R12604 (0x313C) - Write Sequencer 316
7006 */
7007#define WM8995_WSEQ_ADDR79_MASK 0x3FFF /* WSEQ_ADDR79 - [13:0] */
7008#define WM8995_WSEQ_ADDR79_SHIFT 0 /* WSEQ_ADDR79 - [13:0] */
7009#define WM8995_WSEQ_ADDR79_WIDTH 14 /* WSEQ_ADDR79 - [13:0] */
7010
7011/*
7012 * R12605 (0x313D) - Write Sequencer 317
7013 */
7014#define WM8995_WSEQ_DATA79_MASK 0x00FF /* WSEQ_DATA79 - [7:0] */
7015#define WM8995_WSEQ_DATA79_SHIFT 0 /* WSEQ_DATA79 - [7:0] */
7016#define WM8995_WSEQ_DATA79_WIDTH 8 /* WSEQ_DATA79 - [7:0] */
7017
7018/*
7019 * R12606 (0x313E) - Write Sequencer 318
7020 */
7021#define WM8995_WSEQ_DATA_WIDTH79_MASK 0x0700 /* WSEQ_DATA_WIDTH79 - [10:8] */
7022#define WM8995_WSEQ_DATA_WIDTH79_SHIFT 8 /* WSEQ_DATA_WIDTH79 - [10:8] */
7023#define WM8995_WSEQ_DATA_WIDTH79_WIDTH 3 /* WSEQ_DATA_WIDTH79 - [10:8] */
7024#define WM8995_WSEQ_DATA_START79_MASK 0x000F /* WSEQ_DATA_START79 - [3:0] */
7025#define WM8995_WSEQ_DATA_START79_SHIFT 0 /* WSEQ_DATA_START79 - [3:0] */
7026#define WM8995_WSEQ_DATA_START79_WIDTH 4 /* WSEQ_DATA_START79 - [3:0] */
7027
7028/*
7029 * R12607 (0x313F) - Write Sequencer 319
7030 */
7031#define WM8995_WSEQ_EOS79 0x0100 /* WSEQ_EOS79 */
7032#define WM8995_WSEQ_EOS79_MASK 0x0100 /* WSEQ_EOS79 */
7033#define WM8995_WSEQ_EOS79_SHIFT 8 /* WSEQ_EOS79 */
7034#define WM8995_WSEQ_EOS79_WIDTH 1 /* WSEQ_EOS79 */
7035#define WM8995_WSEQ_DELAY79_MASK 0x000F /* WSEQ_DELAY79 - [3:0] */
7036#define WM8995_WSEQ_DELAY79_SHIFT 0 /* WSEQ_DELAY79 - [3:0] */
7037#define WM8995_WSEQ_DELAY79_WIDTH 4 /* WSEQ_DELAY79 - [3:0] */
7038
7039/*
7040 * R12608 (0x3140) - Write Sequencer 320
7041 */
7042#define WM8995_WSEQ_ADDR80_MASK 0x3FFF /* WSEQ_ADDR80 - [13:0] */
7043#define WM8995_WSEQ_ADDR80_SHIFT 0 /* WSEQ_ADDR80 - [13:0] */
7044#define WM8995_WSEQ_ADDR80_WIDTH 14 /* WSEQ_ADDR80 - [13:0] */
7045
7046/*
7047 * R12609 (0x3141) - Write Sequencer 321
7048 */
7049#define WM8995_WSEQ_DATA80_MASK 0x00FF /* WSEQ_DATA80 - [7:0] */
7050#define WM8995_WSEQ_DATA80_SHIFT 0 /* WSEQ_DATA80 - [7:0] */
7051#define WM8995_WSEQ_DATA80_WIDTH 8 /* WSEQ_DATA80 - [7:0] */
7052
7053/*
7054 * R12610 (0x3142) - Write Sequencer 322
7055 */
7056#define WM8995_WSEQ_DATA_WIDTH80_MASK 0x0700 /* WSEQ_DATA_WIDTH80 - [10:8] */
7057#define WM8995_WSEQ_DATA_WIDTH80_SHIFT 8 /* WSEQ_DATA_WIDTH80 - [10:8] */
7058#define WM8995_WSEQ_DATA_WIDTH80_WIDTH 3 /* WSEQ_DATA_WIDTH80 - [10:8] */
7059#define WM8995_WSEQ_DATA_START80_MASK 0x000F /* WSEQ_DATA_START80 - [3:0] */
7060#define WM8995_WSEQ_DATA_START80_SHIFT 0 /* WSEQ_DATA_START80 - [3:0] */
7061#define WM8995_WSEQ_DATA_START80_WIDTH 4 /* WSEQ_DATA_START80 - [3:0] */
7062
7063/*
7064 * R12611 (0x3143) - Write Sequencer 323
7065 */
7066#define WM8995_WSEQ_EOS80 0x0100 /* WSEQ_EOS80 */
7067#define WM8995_WSEQ_EOS80_MASK 0x0100 /* WSEQ_EOS80 */
7068#define WM8995_WSEQ_EOS80_SHIFT 8 /* WSEQ_EOS80 */
7069#define WM8995_WSEQ_EOS80_WIDTH 1 /* WSEQ_EOS80 */
7070#define WM8995_WSEQ_DELAY80_MASK 0x000F /* WSEQ_DELAY80 - [3:0] */
7071#define WM8995_WSEQ_DELAY80_SHIFT 0 /* WSEQ_DELAY80 - [3:0] */
7072#define WM8995_WSEQ_DELAY80_WIDTH 4 /* WSEQ_DELAY80 - [3:0] */
7073
7074/*
7075 * R12612 (0x3144) - Write Sequencer 324
7076 */
7077#define WM8995_WSEQ_ADDR81_MASK 0x3FFF /* WSEQ_ADDR81 - [13:0] */
7078#define WM8995_WSEQ_ADDR81_SHIFT 0 /* WSEQ_ADDR81 - [13:0] */
7079#define WM8995_WSEQ_ADDR81_WIDTH 14 /* WSEQ_ADDR81 - [13:0] */
7080
7081/*
7082 * R12613 (0x3145) - Write Sequencer 325
7083 */
7084#define WM8995_WSEQ_DATA81_MASK 0x00FF /* WSEQ_DATA81 - [7:0] */
7085#define WM8995_WSEQ_DATA81_SHIFT 0 /* WSEQ_DATA81 - [7:0] */
7086#define WM8995_WSEQ_DATA81_WIDTH 8 /* WSEQ_DATA81 - [7:0] */
7087
7088/*
7089 * R12614 (0x3146) - Write Sequencer 326
7090 */
7091#define WM8995_WSEQ_DATA_WIDTH81_MASK 0x0700 /* WSEQ_DATA_WIDTH81 - [10:8] */
7092#define WM8995_WSEQ_DATA_WIDTH81_SHIFT 8 /* WSEQ_DATA_WIDTH81 - [10:8] */
7093#define WM8995_WSEQ_DATA_WIDTH81_WIDTH 3 /* WSEQ_DATA_WIDTH81 - [10:8] */
7094#define WM8995_WSEQ_DATA_START81_MASK 0x000F /* WSEQ_DATA_START81 - [3:0] */
7095#define WM8995_WSEQ_DATA_START81_SHIFT 0 /* WSEQ_DATA_START81 - [3:0] */
7096#define WM8995_WSEQ_DATA_START81_WIDTH 4 /* WSEQ_DATA_START81 - [3:0] */
7097
7098/*
7099 * R12615 (0x3147) - Write Sequencer 327
7100 */
7101#define WM8995_WSEQ_EOS81 0x0100 /* WSEQ_EOS81 */
7102#define WM8995_WSEQ_EOS81_MASK 0x0100 /* WSEQ_EOS81 */
7103#define WM8995_WSEQ_EOS81_SHIFT 8 /* WSEQ_EOS81 */
7104#define WM8995_WSEQ_EOS81_WIDTH 1 /* WSEQ_EOS81 */
7105#define WM8995_WSEQ_DELAY81_MASK 0x000F /* WSEQ_DELAY81 - [3:0] */
7106#define WM8995_WSEQ_DELAY81_SHIFT 0 /* WSEQ_DELAY81 - [3:0] */
7107#define WM8995_WSEQ_DELAY81_WIDTH 4 /* WSEQ_DELAY81 - [3:0] */
7108
7109/*
7110 * R12616 (0x3148) - Write Sequencer 328
7111 */
7112#define WM8995_WSEQ_ADDR82_MASK 0x3FFF /* WSEQ_ADDR82 - [13:0] */
7113#define WM8995_WSEQ_ADDR82_SHIFT 0 /* WSEQ_ADDR82 - [13:0] */
7114#define WM8995_WSEQ_ADDR82_WIDTH 14 /* WSEQ_ADDR82 - [13:0] */
7115
7116/*
7117 * R12617 (0x3149) - Write Sequencer 329
7118 */
7119#define WM8995_WSEQ_DATA82_MASK 0x00FF /* WSEQ_DATA82 - [7:0] */
7120#define WM8995_WSEQ_DATA82_SHIFT 0 /* WSEQ_DATA82 - [7:0] */
7121#define WM8995_WSEQ_DATA82_WIDTH 8 /* WSEQ_DATA82 - [7:0] */
7122
7123/*
7124 * R12618 (0x314A) - Write Sequencer 330
7125 */
7126#define WM8995_WSEQ_DATA_WIDTH82_MASK 0x0700 /* WSEQ_DATA_WIDTH82 - [10:8] */
7127#define WM8995_WSEQ_DATA_WIDTH82_SHIFT 8 /* WSEQ_DATA_WIDTH82 - [10:8] */
7128#define WM8995_WSEQ_DATA_WIDTH82_WIDTH 3 /* WSEQ_DATA_WIDTH82 - [10:8] */
7129#define WM8995_WSEQ_DATA_START82_MASK 0x000F /* WSEQ_DATA_START82 - [3:0] */
7130#define WM8995_WSEQ_DATA_START82_SHIFT 0 /* WSEQ_DATA_START82 - [3:0] */
7131#define WM8995_WSEQ_DATA_START82_WIDTH 4 /* WSEQ_DATA_START82 - [3:0] */
7132
7133/*
7134 * R12619 (0x314B) - Write Sequencer 331
7135 */
7136#define WM8995_WSEQ_EOS82 0x0100 /* WSEQ_EOS82 */
7137#define WM8995_WSEQ_EOS82_MASK 0x0100 /* WSEQ_EOS82 */
7138#define WM8995_WSEQ_EOS82_SHIFT 8 /* WSEQ_EOS82 */
7139#define WM8995_WSEQ_EOS82_WIDTH 1 /* WSEQ_EOS82 */
7140#define WM8995_WSEQ_DELAY82_MASK 0x000F /* WSEQ_DELAY82 - [3:0] */
7141#define WM8995_WSEQ_DELAY82_SHIFT 0 /* WSEQ_DELAY82 - [3:0] */
7142#define WM8995_WSEQ_DELAY82_WIDTH 4 /* WSEQ_DELAY82 - [3:0] */
7143
7144/*
7145 * R12620 (0x314C) - Write Sequencer 332
7146 */
7147#define WM8995_WSEQ_ADDR83_MASK 0x3FFF /* WSEQ_ADDR83 - [13:0] */
7148#define WM8995_WSEQ_ADDR83_SHIFT 0 /* WSEQ_ADDR83 - [13:0] */
7149#define WM8995_WSEQ_ADDR83_WIDTH 14 /* WSEQ_ADDR83 - [13:0] */
7150
7151/*
7152 * R12621 (0x314D) - Write Sequencer 333
7153 */
7154#define WM8995_WSEQ_DATA83_MASK 0x00FF /* WSEQ_DATA83 - [7:0] */
7155#define WM8995_WSEQ_DATA83_SHIFT 0 /* WSEQ_DATA83 - [7:0] */
7156#define WM8995_WSEQ_DATA83_WIDTH 8 /* WSEQ_DATA83 - [7:0] */
7157
7158/*
7159 * R12622 (0x314E) - Write Sequencer 334
7160 */
7161#define WM8995_WSEQ_DATA_WIDTH83_MASK 0x0700 /* WSEQ_DATA_WIDTH83 - [10:8] */
7162#define WM8995_WSEQ_DATA_WIDTH83_SHIFT 8 /* WSEQ_DATA_WIDTH83 - [10:8] */
7163#define WM8995_WSEQ_DATA_WIDTH83_WIDTH 3 /* WSEQ_DATA_WIDTH83 - [10:8] */
7164#define WM8995_WSEQ_DATA_START83_MASK 0x000F /* WSEQ_DATA_START83 - [3:0] */
7165#define WM8995_WSEQ_DATA_START83_SHIFT 0 /* WSEQ_DATA_START83 - [3:0] */
7166#define WM8995_WSEQ_DATA_START83_WIDTH 4 /* WSEQ_DATA_START83 - [3:0] */
7167
7168/*
7169 * R12623 (0x314F) - Write Sequencer 335
7170 */
7171#define WM8995_WSEQ_EOS83 0x0100 /* WSEQ_EOS83 */
7172#define WM8995_WSEQ_EOS83_MASK 0x0100 /* WSEQ_EOS83 */
7173#define WM8995_WSEQ_EOS83_SHIFT 8 /* WSEQ_EOS83 */
7174#define WM8995_WSEQ_EOS83_WIDTH 1 /* WSEQ_EOS83 */
7175#define WM8995_WSEQ_DELAY83_MASK 0x000F /* WSEQ_DELAY83 - [3:0] */
7176#define WM8995_WSEQ_DELAY83_SHIFT 0 /* WSEQ_DELAY83 - [3:0] */
7177#define WM8995_WSEQ_DELAY83_WIDTH 4 /* WSEQ_DELAY83 - [3:0] */
7178
7179/*
7180 * R12624 (0x3150) - Write Sequencer 336
7181 */
7182#define WM8995_WSEQ_ADDR84_MASK 0x3FFF /* WSEQ_ADDR84 - [13:0] */
7183#define WM8995_WSEQ_ADDR84_SHIFT 0 /* WSEQ_ADDR84 - [13:0] */
7184#define WM8995_WSEQ_ADDR84_WIDTH 14 /* WSEQ_ADDR84 - [13:0] */
7185
7186/*
7187 * R12625 (0x3151) - Write Sequencer 337
7188 */
7189#define WM8995_WSEQ_DATA84_MASK 0x00FF /* WSEQ_DATA84 - [7:0] */
7190#define WM8995_WSEQ_DATA84_SHIFT 0 /* WSEQ_DATA84 - [7:0] */
7191#define WM8995_WSEQ_DATA84_WIDTH 8 /* WSEQ_DATA84 - [7:0] */
7192
7193/*
7194 * R12626 (0x3152) - Write Sequencer 338
7195 */
7196#define WM8995_WSEQ_DATA_WIDTH84_MASK 0x0700 /* WSEQ_DATA_WIDTH84 - [10:8] */
7197#define WM8995_WSEQ_DATA_WIDTH84_SHIFT 8 /* WSEQ_DATA_WIDTH84 - [10:8] */
7198#define WM8995_WSEQ_DATA_WIDTH84_WIDTH 3 /* WSEQ_DATA_WIDTH84 - [10:8] */
7199#define WM8995_WSEQ_DATA_START84_MASK 0x000F /* WSEQ_DATA_START84 - [3:0] */
7200#define WM8995_WSEQ_DATA_START84_SHIFT 0 /* WSEQ_DATA_START84 - [3:0] */
7201#define WM8995_WSEQ_DATA_START84_WIDTH 4 /* WSEQ_DATA_START84 - [3:0] */
7202
7203/*
7204 * R12627 (0x3153) - Write Sequencer 339
7205 */
7206#define WM8995_WSEQ_EOS84 0x0100 /* WSEQ_EOS84 */
7207#define WM8995_WSEQ_EOS84_MASK 0x0100 /* WSEQ_EOS84 */
7208#define WM8995_WSEQ_EOS84_SHIFT 8 /* WSEQ_EOS84 */
7209#define WM8995_WSEQ_EOS84_WIDTH 1 /* WSEQ_EOS84 */
7210#define WM8995_WSEQ_DELAY84_MASK 0x000F /* WSEQ_DELAY84 - [3:0] */
7211#define WM8995_WSEQ_DELAY84_SHIFT 0 /* WSEQ_DELAY84 - [3:0] */
7212#define WM8995_WSEQ_DELAY84_WIDTH 4 /* WSEQ_DELAY84 - [3:0] */
7213
7214/*
7215 * R12628 (0x3154) - Write Sequencer 340
7216 */
7217#define WM8995_WSEQ_ADDR85_MASK 0x3FFF /* WSEQ_ADDR85 - [13:0] */
7218#define WM8995_WSEQ_ADDR85_SHIFT 0 /* WSEQ_ADDR85 - [13:0] */
7219#define WM8995_WSEQ_ADDR85_WIDTH 14 /* WSEQ_ADDR85 - [13:0] */
7220
7221/*
7222 * R12629 (0x3155) - Write Sequencer 341
7223 */
7224#define WM8995_WSEQ_DATA85_MASK 0x00FF /* WSEQ_DATA85 - [7:0] */
7225#define WM8995_WSEQ_DATA85_SHIFT 0 /* WSEQ_DATA85 - [7:0] */
7226#define WM8995_WSEQ_DATA85_WIDTH 8 /* WSEQ_DATA85 - [7:0] */
7227
7228/*
7229 * R12630 (0x3156) - Write Sequencer 342
7230 */
7231#define WM8995_WSEQ_DATA_WIDTH85_MASK 0x0700 /* WSEQ_DATA_WIDTH85 - [10:8] */
7232#define WM8995_WSEQ_DATA_WIDTH85_SHIFT 8 /* WSEQ_DATA_WIDTH85 - [10:8] */
7233#define WM8995_WSEQ_DATA_WIDTH85_WIDTH 3 /* WSEQ_DATA_WIDTH85 - [10:8] */
7234#define WM8995_WSEQ_DATA_START85_MASK 0x000F /* WSEQ_DATA_START85 - [3:0] */
7235#define WM8995_WSEQ_DATA_START85_SHIFT 0 /* WSEQ_DATA_START85 - [3:0] */
7236#define WM8995_WSEQ_DATA_START85_WIDTH 4 /* WSEQ_DATA_START85 - [3:0] */
7237
7238/*
7239 * R12631 (0x3157) - Write Sequencer 343
7240 */
7241#define WM8995_WSEQ_EOS85 0x0100 /* WSEQ_EOS85 */
7242#define WM8995_WSEQ_EOS85_MASK 0x0100 /* WSEQ_EOS85 */
7243#define WM8995_WSEQ_EOS85_SHIFT 8 /* WSEQ_EOS85 */
7244#define WM8995_WSEQ_EOS85_WIDTH 1 /* WSEQ_EOS85 */
7245#define WM8995_WSEQ_DELAY85_MASK 0x000F /* WSEQ_DELAY85 - [3:0] */
7246#define WM8995_WSEQ_DELAY85_SHIFT 0 /* WSEQ_DELAY85 - [3:0] */
7247#define WM8995_WSEQ_DELAY85_WIDTH 4 /* WSEQ_DELAY85 - [3:0] */
7248
7249/*
7250 * R12632 (0x3158) - Write Sequencer 344
7251 */
7252#define WM8995_WSEQ_ADDR86_MASK 0x3FFF /* WSEQ_ADDR86 - [13:0] */
7253#define WM8995_WSEQ_ADDR86_SHIFT 0 /* WSEQ_ADDR86 - [13:0] */
7254#define WM8995_WSEQ_ADDR86_WIDTH 14 /* WSEQ_ADDR86 - [13:0] */
7255
7256/*
7257 * R12633 (0x3159) - Write Sequencer 345
7258 */
7259#define WM8995_WSEQ_DATA86_MASK 0x00FF /* WSEQ_DATA86 - [7:0] */
7260#define WM8995_WSEQ_DATA86_SHIFT 0 /* WSEQ_DATA86 - [7:0] */
7261#define WM8995_WSEQ_DATA86_WIDTH 8 /* WSEQ_DATA86 - [7:0] */
7262
7263/*
7264 * R12634 (0x315A) - Write Sequencer 346
7265 */
7266#define WM8995_WSEQ_DATA_WIDTH86_MASK 0x0700 /* WSEQ_DATA_WIDTH86 - [10:8] */
7267#define WM8995_WSEQ_DATA_WIDTH86_SHIFT 8 /* WSEQ_DATA_WIDTH86 - [10:8] */
7268#define WM8995_WSEQ_DATA_WIDTH86_WIDTH 3 /* WSEQ_DATA_WIDTH86 - [10:8] */
7269#define WM8995_WSEQ_DATA_START86_MASK 0x000F /* WSEQ_DATA_START86 - [3:0] */
7270#define WM8995_WSEQ_DATA_START86_SHIFT 0 /* WSEQ_DATA_START86 - [3:0] */
7271#define WM8995_WSEQ_DATA_START86_WIDTH 4 /* WSEQ_DATA_START86 - [3:0] */
7272
7273/*
7274 * R12635 (0x315B) - Write Sequencer 347
7275 */
7276#define WM8995_WSEQ_EOS86 0x0100 /* WSEQ_EOS86 */
7277#define WM8995_WSEQ_EOS86_MASK 0x0100 /* WSEQ_EOS86 */
7278#define WM8995_WSEQ_EOS86_SHIFT 8 /* WSEQ_EOS86 */
7279#define WM8995_WSEQ_EOS86_WIDTH 1 /* WSEQ_EOS86 */
7280#define WM8995_WSEQ_DELAY86_MASK 0x000F /* WSEQ_DELAY86 - [3:0] */
7281#define WM8995_WSEQ_DELAY86_SHIFT 0 /* WSEQ_DELAY86 - [3:0] */
7282#define WM8995_WSEQ_DELAY86_WIDTH 4 /* WSEQ_DELAY86 - [3:0] */
7283
7284/*
7285 * R12636 (0x315C) - Write Sequencer 348
7286 */
7287#define WM8995_WSEQ_ADDR87_MASK 0x3FFF /* WSEQ_ADDR87 - [13:0] */
7288#define WM8995_WSEQ_ADDR87_SHIFT 0 /* WSEQ_ADDR87 - [13:0] */
7289#define WM8995_WSEQ_ADDR87_WIDTH 14 /* WSEQ_ADDR87 - [13:0] */
7290
7291/*
7292 * R12637 (0x315D) - Write Sequencer 349
7293 */
7294#define WM8995_WSEQ_DATA87_MASK 0x00FF /* WSEQ_DATA87 - [7:0] */
7295#define WM8995_WSEQ_DATA87_SHIFT 0 /* WSEQ_DATA87 - [7:0] */
7296#define WM8995_WSEQ_DATA87_WIDTH 8 /* WSEQ_DATA87 - [7:0] */
7297
7298/*
7299 * R12638 (0x315E) - Write Sequencer 350
7300 */
7301#define WM8995_WSEQ_DATA_WIDTH87_MASK 0x0700 /* WSEQ_DATA_WIDTH87 - [10:8] */
7302#define WM8995_WSEQ_DATA_WIDTH87_SHIFT 8 /* WSEQ_DATA_WIDTH87 - [10:8] */
7303#define WM8995_WSEQ_DATA_WIDTH87_WIDTH 3 /* WSEQ_DATA_WIDTH87 - [10:8] */
7304#define WM8995_WSEQ_DATA_START87_MASK 0x000F /* WSEQ_DATA_START87 - [3:0] */
7305#define WM8995_WSEQ_DATA_START87_SHIFT 0 /* WSEQ_DATA_START87 - [3:0] */
7306#define WM8995_WSEQ_DATA_START87_WIDTH 4 /* WSEQ_DATA_START87 - [3:0] */
7307
7308/*
7309 * R12639 (0x315F) - Write Sequencer 351
7310 */
7311#define WM8995_WSEQ_EOS87 0x0100 /* WSEQ_EOS87 */
7312#define WM8995_WSEQ_EOS87_MASK 0x0100 /* WSEQ_EOS87 */
7313#define WM8995_WSEQ_EOS87_SHIFT 8 /* WSEQ_EOS87 */
7314#define WM8995_WSEQ_EOS87_WIDTH 1 /* WSEQ_EOS87 */
7315#define WM8995_WSEQ_DELAY87_MASK 0x000F /* WSEQ_DELAY87 - [3:0] */
7316#define WM8995_WSEQ_DELAY87_SHIFT 0 /* WSEQ_DELAY87 - [3:0] */
7317#define WM8995_WSEQ_DELAY87_WIDTH 4 /* WSEQ_DELAY87 - [3:0] */
7318
7319/*
7320 * R12640 (0x3160) - Write Sequencer 352
7321 */
7322#define WM8995_WSEQ_ADDR88_MASK 0x3FFF /* WSEQ_ADDR88 - [13:0] */
7323#define WM8995_WSEQ_ADDR88_SHIFT 0 /* WSEQ_ADDR88 - [13:0] */
7324#define WM8995_WSEQ_ADDR88_WIDTH 14 /* WSEQ_ADDR88 - [13:0] */
7325
7326/*
7327 * R12641 (0x3161) - Write Sequencer 353
7328 */
7329#define WM8995_WSEQ_DATA88_MASK 0x00FF /* WSEQ_DATA88 - [7:0] */
7330#define WM8995_WSEQ_DATA88_SHIFT 0 /* WSEQ_DATA88 - [7:0] */
7331#define WM8995_WSEQ_DATA88_WIDTH 8 /* WSEQ_DATA88 - [7:0] */
7332
7333/*
7334 * R12642 (0x3162) - Write Sequencer 354
7335 */
7336#define WM8995_WSEQ_DATA_WIDTH88_MASK 0x0700 /* WSEQ_DATA_WIDTH88 - [10:8] */
7337#define WM8995_WSEQ_DATA_WIDTH88_SHIFT 8 /* WSEQ_DATA_WIDTH88 - [10:8] */
7338#define WM8995_WSEQ_DATA_WIDTH88_WIDTH 3 /* WSEQ_DATA_WIDTH88 - [10:8] */
7339#define WM8995_WSEQ_DATA_START88_MASK 0x000F /* WSEQ_DATA_START88 - [3:0] */
7340#define WM8995_WSEQ_DATA_START88_SHIFT 0 /* WSEQ_DATA_START88 - [3:0] */
7341#define WM8995_WSEQ_DATA_START88_WIDTH 4 /* WSEQ_DATA_START88 - [3:0] */
7342
7343/*
7344 * R12643 (0x3163) - Write Sequencer 355
7345 */
7346#define WM8995_WSEQ_EOS88 0x0100 /* WSEQ_EOS88 */
7347#define WM8995_WSEQ_EOS88_MASK 0x0100 /* WSEQ_EOS88 */
7348#define WM8995_WSEQ_EOS88_SHIFT 8 /* WSEQ_EOS88 */
7349#define WM8995_WSEQ_EOS88_WIDTH 1 /* WSEQ_EOS88 */
7350#define WM8995_WSEQ_DELAY88_MASK 0x000F /* WSEQ_DELAY88 - [3:0] */
7351#define WM8995_WSEQ_DELAY88_SHIFT 0 /* WSEQ_DELAY88 - [3:0] */
7352#define WM8995_WSEQ_DELAY88_WIDTH 4 /* WSEQ_DELAY88 - [3:0] */
7353
7354/*
7355 * R12644 (0x3164) - Write Sequencer 356
7356 */
7357#define WM8995_WSEQ_ADDR89_MASK 0x3FFF /* WSEQ_ADDR89 - [13:0] */
7358#define WM8995_WSEQ_ADDR89_SHIFT 0 /* WSEQ_ADDR89 - [13:0] */
7359#define WM8995_WSEQ_ADDR89_WIDTH 14 /* WSEQ_ADDR89 - [13:0] */
7360
7361/*
7362 * R12645 (0x3165) - Write Sequencer 357
7363 */
7364#define WM8995_WSEQ_DATA89_MASK 0x00FF /* WSEQ_DATA89 - [7:0] */
7365#define WM8995_WSEQ_DATA89_SHIFT 0 /* WSEQ_DATA89 - [7:0] */
7366#define WM8995_WSEQ_DATA89_WIDTH 8 /* WSEQ_DATA89 - [7:0] */
7367
7368/*
7369 * R12646 (0x3166) - Write Sequencer 358
7370 */
7371#define WM8995_WSEQ_DATA_WIDTH89_MASK 0x0700 /* WSEQ_DATA_WIDTH89 - [10:8] */
7372#define WM8995_WSEQ_DATA_WIDTH89_SHIFT 8 /* WSEQ_DATA_WIDTH89 - [10:8] */
7373#define WM8995_WSEQ_DATA_WIDTH89_WIDTH 3 /* WSEQ_DATA_WIDTH89 - [10:8] */
7374#define WM8995_WSEQ_DATA_START89_MASK 0x000F /* WSEQ_DATA_START89 - [3:0] */
7375#define WM8995_WSEQ_DATA_START89_SHIFT 0 /* WSEQ_DATA_START89 - [3:0] */
7376#define WM8995_WSEQ_DATA_START89_WIDTH 4 /* WSEQ_DATA_START89 - [3:0] */
7377
7378/*
7379 * R12647 (0x3167) - Write Sequencer 359
7380 */
7381#define WM8995_WSEQ_EOS89 0x0100 /* WSEQ_EOS89 */
7382#define WM8995_WSEQ_EOS89_MASK 0x0100 /* WSEQ_EOS89 */
7383#define WM8995_WSEQ_EOS89_SHIFT 8 /* WSEQ_EOS89 */
7384#define WM8995_WSEQ_EOS89_WIDTH 1 /* WSEQ_EOS89 */
7385#define WM8995_WSEQ_DELAY89_MASK 0x000F /* WSEQ_DELAY89 - [3:0] */
7386#define WM8995_WSEQ_DELAY89_SHIFT 0 /* WSEQ_DELAY89 - [3:0] */
7387#define WM8995_WSEQ_DELAY89_WIDTH 4 /* WSEQ_DELAY89 - [3:0] */
7388
7389/*
7390 * R12648 (0x3168) - Write Sequencer 360
7391 */
7392#define WM8995_WSEQ_ADDR90_MASK 0x3FFF /* WSEQ_ADDR90 - [13:0] */
7393#define WM8995_WSEQ_ADDR90_SHIFT 0 /* WSEQ_ADDR90 - [13:0] */
7394#define WM8995_WSEQ_ADDR90_WIDTH 14 /* WSEQ_ADDR90 - [13:0] */
7395
7396/*
7397 * R12649 (0x3169) - Write Sequencer 361
7398 */
7399#define WM8995_WSEQ_DATA90_MASK 0x00FF /* WSEQ_DATA90 - [7:0] */
7400#define WM8995_WSEQ_DATA90_SHIFT 0 /* WSEQ_DATA90 - [7:0] */
7401#define WM8995_WSEQ_DATA90_WIDTH 8 /* WSEQ_DATA90 - [7:0] */
7402
7403/*
7404 * R12650 (0x316A) - Write Sequencer 362
7405 */
7406#define WM8995_WSEQ_DATA_WIDTH90_MASK 0x0700 /* WSEQ_DATA_WIDTH90 - [10:8] */
7407#define WM8995_WSEQ_DATA_WIDTH90_SHIFT 8 /* WSEQ_DATA_WIDTH90 - [10:8] */
7408#define WM8995_WSEQ_DATA_WIDTH90_WIDTH 3 /* WSEQ_DATA_WIDTH90 - [10:8] */
7409#define WM8995_WSEQ_DATA_START90_MASK 0x000F /* WSEQ_DATA_START90 - [3:0] */
7410#define WM8995_WSEQ_DATA_START90_SHIFT 0 /* WSEQ_DATA_START90 - [3:0] */
7411#define WM8995_WSEQ_DATA_START90_WIDTH 4 /* WSEQ_DATA_START90 - [3:0] */
7412
7413/*
7414 * R12651 (0x316B) - Write Sequencer 363
7415 */
7416#define WM8995_WSEQ_EOS90 0x0100 /* WSEQ_EOS90 */
7417#define WM8995_WSEQ_EOS90_MASK 0x0100 /* WSEQ_EOS90 */
7418#define WM8995_WSEQ_EOS90_SHIFT 8 /* WSEQ_EOS90 */
7419#define WM8995_WSEQ_EOS90_WIDTH 1 /* WSEQ_EOS90 */
7420#define WM8995_WSEQ_DELAY90_MASK 0x000F /* WSEQ_DELAY90 - [3:0] */
7421#define WM8995_WSEQ_DELAY90_SHIFT 0 /* WSEQ_DELAY90 - [3:0] */
7422#define WM8995_WSEQ_DELAY90_WIDTH 4 /* WSEQ_DELAY90 - [3:0] */
7423
7424/*
7425 * R12652 (0x316C) - Write Sequencer 364
7426 */
7427#define WM8995_WSEQ_ADDR91_MASK 0x3FFF /* WSEQ_ADDR91 - [13:0] */
7428#define WM8995_WSEQ_ADDR91_SHIFT 0 /* WSEQ_ADDR91 - [13:0] */
7429#define WM8995_WSEQ_ADDR91_WIDTH 14 /* WSEQ_ADDR91 - [13:0] */
7430
7431/*
7432 * R12653 (0x316D) - Write Sequencer 365
7433 */
7434#define WM8995_WSEQ_DATA91_MASK 0x00FF /* WSEQ_DATA91 - [7:0] */
7435#define WM8995_WSEQ_DATA91_SHIFT 0 /* WSEQ_DATA91 - [7:0] */
7436#define WM8995_WSEQ_DATA91_WIDTH 8 /* WSEQ_DATA91 - [7:0] */
7437
7438/*
7439 * R12654 (0x316E) - Write Sequencer 366
7440 */
7441#define WM8995_WSEQ_DATA_WIDTH91_MASK 0x0700 /* WSEQ_DATA_WIDTH91 - [10:8] */
7442#define WM8995_WSEQ_DATA_WIDTH91_SHIFT 8 /* WSEQ_DATA_WIDTH91 - [10:8] */
7443#define WM8995_WSEQ_DATA_WIDTH91_WIDTH 3 /* WSEQ_DATA_WIDTH91 - [10:8] */
7444#define WM8995_WSEQ_DATA_START91_MASK 0x000F /* WSEQ_DATA_START91 - [3:0] */
7445#define WM8995_WSEQ_DATA_START91_SHIFT 0 /* WSEQ_DATA_START91 - [3:0] */
7446#define WM8995_WSEQ_DATA_START91_WIDTH 4 /* WSEQ_DATA_START91 - [3:0] */
7447
7448/*
7449 * R12655 (0x316F) - Write Sequencer 367
7450 */
7451#define WM8995_WSEQ_EOS91 0x0100 /* WSEQ_EOS91 */
7452#define WM8995_WSEQ_EOS91_MASK 0x0100 /* WSEQ_EOS91 */
7453#define WM8995_WSEQ_EOS91_SHIFT 8 /* WSEQ_EOS91 */
7454#define WM8995_WSEQ_EOS91_WIDTH 1 /* WSEQ_EOS91 */
7455#define WM8995_WSEQ_DELAY91_MASK 0x000F /* WSEQ_DELAY91 - [3:0] */
7456#define WM8995_WSEQ_DELAY91_SHIFT 0 /* WSEQ_DELAY91 - [3:0] */
7457#define WM8995_WSEQ_DELAY91_WIDTH 4 /* WSEQ_DELAY91 - [3:0] */
7458
7459/*
7460 * R12656 (0x3170) - Write Sequencer 368
7461 */
7462#define WM8995_WSEQ_ADDR92_MASK 0x3FFF /* WSEQ_ADDR92 - [13:0] */
7463#define WM8995_WSEQ_ADDR92_SHIFT 0 /* WSEQ_ADDR92 - [13:0] */
7464#define WM8995_WSEQ_ADDR92_WIDTH 14 /* WSEQ_ADDR92 - [13:0] */
7465
7466/*
7467 * R12657 (0x3171) - Write Sequencer 369
7468 */
7469#define WM8995_WSEQ_DATA92_MASK 0x00FF /* WSEQ_DATA92 - [7:0] */
7470#define WM8995_WSEQ_DATA92_SHIFT 0 /* WSEQ_DATA92 - [7:0] */
7471#define WM8995_WSEQ_DATA92_WIDTH 8 /* WSEQ_DATA92 - [7:0] */
7472
7473/*
7474 * R12658 (0x3172) - Write Sequencer 370
7475 */
7476#define WM8995_WSEQ_DATA_WIDTH92_MASK 0x0700 /* WSEQ_DATA_WIDTH92 - [10:8] */
7477#define WM8995_WSEQ_DATA_WIDTH92_SHIFT 8 /* WSEQ_DATA_WIDTH92 - [10:8] */
7478#define WM8995_WSEQ_DATA_WIDTH92_WIDTH 3 /* WSEQ_DATA_WIDTH92 - [10:8] */
7479#define WM8995_WSEQ_DATA_START92_MASK 0x000F /* WSEQ_DATA_START92 - [3:0] */
7480#define WM8995_WSEQ_DATA_START92_SHIFT 0 /* WSEQ_DATA_START92 - [3:0] */
7481#define WM8995_WSEQ_DATA_START92_WIDTH 4 /* WSEQ_DATA_START92 - [3:0] */
7482
7483/*
7484 * R12659 (0x3173) - Write Sequencer 371
7485 */
7486#define WM8995_WSEQ_EOS92 0x0100 /* WSEQ_EOS92 */
7487#define WM8995_WSEQ_EOS92_MASK 0x0100 /* WSEQ_EOS92 */
7488#define WM8995_WSEQ_EOS92_SHIFT 8 /* WSEQ_EOS92 */
7489#define WM8995_WSEQ_EOS92_WIDTH 1 /* WSEQ_EOS92 */
7490#define WM8995_WSEQ_DELAY92_MASK 0x000F /* WSEQ_DELAY92 - [3:0] */
7491#define WM8995_WSEQ_DELAY92_SHIFT 0 /* WSEQ_DELAY92 - [3:0] */
7492#define WM8995_WSEQ_DELAY92_WIDTH 4 /* WSEQ_DELAY92 - [3:0] */
7493
7494/*
7495 * R12660 (0x3174) - Write Sequencer 372
7496 */
7497#define WM8995_WSEQ_ADDR93_MASK 0x3FFF /* WSEQ_ADDR93 - [13:0] */
7498#define WM8995_WSEQ_ADDR93_SHIFT 0 /* WSEQ_ADDR93 - [13:0] */
7499#define WM8995_WSEQ_ADDR93_WIDTH 14 /* WSEQ_ADDR93 - [13:0] */
7500
7501/*
7502 * R12661 (0x3175) - Write Sequencer 373
7503 */
7504#define WM8995_WSEQ_DATA93_MASK 0x00FF /* WSEQ_DATA93 - [7:0] */
7505#define WM8995_WSEQ_DATA93_SHIFT 0 /* WSEQ_DATA93 - [7:0] */
7506#define WM8995_WSEQ_DATA93_WIDTH 8 /* WSEQ_DATA93 - [7:0] */
7507
7508/*
7509 * R12662 (0x3176) - Write Sequencer 374
7510 */
7511#define WM8995_WSEQ_DATA_WIDTH93_MASK 0x0700 /* WSEQ_DATA_WIDTH93 - [10:8] */
7512#define WM8995_WSEQ_DATA_WIDTH93_SHIFT 8 /* WSEQ_DATA_WIDTH93 - [10:8] */
7513#define WM8995_WSEQ_DATA_WIDTH93_WIDTH 3 /* WSEQ_DATA_WIDTH93 - [10:8] */
7514#define WM8995_WSEQ_DATA_START93_MASK 0x000F /* WSEQ_DATA_START93 - [3:0] */
7515#define WM8995_WSEQ_DATA_START93_SHIFT 0 /* WSEQ_DATA_START93 - [3:0] */
7516#define WM8995_WSEQ_DATA_START93_WIDTH 4 /* WSEQ_DATA_START93 - [3:0] */
7517
7518/*
7519 * R12663 (0x3177) - Write Sequencer 375
7520 */
7521#define WM8995_WSEQ_EOS93 0x0100 /* WSEQ_EOS93 */
7522#define WM8995_WSEQ_EOS93_MASK 0x0100 /* WSEQ_EOS93 */
7523#define WM8995_WSEQ_EOS93_SHIFT 8 /* WSEQ_EOS93 */
7524#define WM8995_WSEQ_EOS93_WIDTH 1 /* WSEQ_EOS93 */
7525#define WM8995_WSEQ_DELAY93_MASK 0x000F /* WSEQ_DELAY93 - [3:0] */
7526#define WM8995_WSEQ_DELAY93_SHIFT 0 /* WSEQ_DELAY93 - [3:0] */
7527#define WM8995_WSEQ_DELAY93_WIDTH 4 /* WSEQ_DELAY93 - [3:0] */
7528
7529/*
7530 * R12664 (0x3178) - Write Sequencer 376
7531 */
7532#define WM8995_WSEQ_ADDR94_MASK 0x3FFF /* WSEQ_ADDR94 - [13:0] */
7533#define WM8995_WSEQ_ADDR94_SHIFT 0 /* WSEQ_ADDR94 - [13:0] */
7534#define WM8995_WSEQ_ADDR94_WIDTH 14 /* WSEQ_ADDR94 - [13:0] */
7535
7536/*
7537 * R12665 (0x3179) - Write Sequencer 377
7538 */
7539#define WM8995_WSEQ_DATA94_MASK 0x00FF /* WSEQ_DATA94 - [7:0] */
7540#define WM8995_WSEQ_DATA94_SHIFT 0 /* WSEQ_DATA94 - [7:0] */
7541#define WM8995_WSEQ_DATA94_WIDTH 8 /* WSEQ_DATA94 - [7:0] */
7542
7543/*
7544 * R12666 (0x317A) - Write Sequencer 378
7545 */
7546#define WM8995_WSEQ_DATA_WIDTH94_MASK 0x0700 /* WSEQ_DATA_WIDTH94 - [10:8] */
7547#define WM8995_WSEQ_DATA_WIDTH94_SHIFT 8 /* WSEQ_DATA_WIDTH94 - [10:8] */
7548#define WM8995_WSEQ_DATA_WIDTH94_WIDTH 3 /* WSEQ_DATA_WIDTH94 - [10:8] */
7549#define WM8995_WSEQ_DATA_START94_MASK 0x000F /* WSEQ_DATA_START94 - [3:0] */
7550#define WM8995_WSEQ_DATA_START94_SHIFT 0 /* WSEQ_DATA_START94 - [3:0] */
7551#define WM8995_WSEQ_DATA_START94_WIDTH 4 /* WSEQ_DATA_START94 - [3:0] */
7552
7553/*
7554 * R12667 (0x317B) - Write Sequencer 379
7555 */
7556#define WM8995_WSEQ_EOS94 0x0100 /* WSEQ_EOS94 */
7557#define WM8995_WSEQ_EOS94_MASK 0x0100 /* WSEQ_EOS94 */
7558#define WM8995_WSEQ_EOS94_SHIFT 8 /* WSEQ_EOS94 */
7559#define WM8995_WSEQ_EOS94_WIDTH 1 /* WSEQ_EOS94 */
7560#define WM8995_WSEQ_DELAY94_MASK 0x000F /* WSEQ_DELAY94 - [3:0] */
7561#define WM8995_WSEQ_DELAY94_SHIFT 0 /* WSEQ_DELAY94 - [3:0] */
7562#define WM8995_WSEQ_DELAY94_WIDTH 4 /* WSEQ_DELAY94 - [3:0] */
7563
7564/*
7565 * R12668 (0x317C) - Write Sequencer 380
7566 */
7567#define WM8995_WSEQ_ADDR95_MASK 0x3FFF /* WSEQ_ADDR95 - [13:0] */
7568#define WM8995_WSEQ_ADDR95_SHIFT 0 /* WSEQ_ADDR95 - [13:0] */
7569#define WM8995_WSEQ_ADDR95_WIDTH 14 /* WSEQ_ADDR95 - [13:0] */
7570
7571/*
7572 * R12669 (0x317D) - Write Sequencer 381
7573 */
7574#define WM8995_WSEQ_DATA95_MASK 0x00FF /* WSEQ_DATA95 - [7:0] */
7575#define WM8995_WSEQ_DATA95_SHIFT 0 /* WSEQ_DATA95 - [7:0] */
7576#define WM8995_WSEQ_DATA95_WIDTH 8 /* WSEQ_DATA95 - [7:0] */
7577
7578/*
7579 * R12670 (0x317E) - Write Sequencer 382
7580 */
7581#define WM8995_WSEQ_DATA_WIDTH95_MASK 0x0700 /* WSEQ_DATA_WIDTH95 - [10:8] */
7582#define WM8995_WSEQ_DATA_WIDTH95_SHIFT 8 /* WSEQ_DATA_WIDTH95 - [10:8] */
7583#define WM8995_WSEQ_DATA_WIDTH95_WIDTH 3 /* WSEQ_DATA_WIDTH95 - [10:8] */
7584#define WM8995_WSEQ_DATA_START95_MASK 0x000F /* WSEQ_DATA_START95 - [3:0] */
7585#define WM8995_WSEQ_DATA_START95_SHIFT 0 /* WSEQ_DATA_START95 - [3:0] */
7586#define WM8995_WSEQ_DATA_START95_WIDTH 4 /* WSEQ_DATA_START95 - [3:0] */
7587
7588/*
7589 * R12671 (0x317F) - Write Sequencer 383
7590 */
7591#define WM8995_WSEQ_EOS95 0x0100 /* WSEQ_EOS95 */
7592#define WM8995_WSEQ_EOS95_MASK 0x0100 /* WSEQ_EOS95 */
7593#define WM8995_WSEQ_EOS95_SHIFT 8 /* WSEQ_EOS95 */
7594#define WM8995_WSEQ_EOS95_WIDTH 1 /* WSEQ_EOS95 */
7595#define WM8995_WSEQ_DELAY95_MASK 0x000F /* WSEQ_DELAY95 - [3:0] */
7596#define WM8995_WSEQ_DELAY95_SHIFT 0 /* WSEQ_DELAY95 - [3:0] */
7597#define WM8995_WSEQ_DELAY95_WIDTH 4 /* WSEQ_DELAY95 - [3:0] */
7598
7599/*
7600 * R12672 (0x3180) - Write Sequencer 384
7601 */
7602#define WM8995_WSEQ_ADDR96_MASK 0x3FFF /* WSEQ_ADDR96 - [13:0] */
7603#define WM8995_WSEQ_ADDR96_SHIFT 0 /* WSEQ_ADDR96 - [13:0] */
7604#define WM8995_WSEQ_ADDR96_WIDTH 14 /* WSEQ_ADDR96 - [13:0] */
7605
7606/*
7607 * R12673 (0x3181) - Write Sequencer 385
7608 */
7609#define WM8995_WSEQ_DATA96_MASK 0x00FF /* WSEQ_DATA96 - [7:0] */
7610#define WM8995_WSEQ_DATA96_SHIFT 0 /* WSEQ_DATA96 - [7:0] */
7611#define WM8995_WSEQ_DATA96_WIDTH 8 /* WSEQ_DATA96 - [7:0] */
7612
7613/*
7614 * R12674 (0x3182) - Write Sequencer 386
7615 */
7616#define WM8995_WSEQ_DATA_WIDTH96_MASK 0x0700 /* WSEQ_DATA_WIDTH96 - [10:8] */
7617#define WM8995_WSEQ_DATA_WIDTH96_SHIFT 8 /* WSEQ_DATA_WIDTH96 - [10:8] */
7618#define WM8995_WSEQ_DATA_WIDTH96_WIDTH 3 /* WSEQ_DATA_WIDTH96 - [10:8] */
7619#define WM8995_WSEQ_DATA_START96_MASK 0x000F /* WSEQ_DATA_START96 - [3:0] */
7620#define WM8995_WSEQ_DATA_START96_SHIFT 0 /* WSEQ_DATA_START96 - [3:0] */
7621#define WM8995_WSEQ_DATA_START96_WIDTH 4 /* WSEQ_DATA_START96 - [3:0] */
7622
7623/*
7624 * R12675 (0x3183) - Write Sequencer 387
7625 */
7626#define WM8995_WSEQ_EOS96 0x0100 /* WSEQ_EOS96 */
7627#define WM8995_WSEQ_EOS96_MASK 0x0100 /* WSEQ_EOS96 */
7628#define WM8995_WSEQ_EOS96_SHIFT 8 /* WSEQ_EOS96 */
7629#define WM8995_WSEQ_EOS96_WIDTH 1 /* WSEQ_EOS96 */
7630#define WM8995_WSEQ_DELAY96_MASK 0x000F /* WSEQ_DELAY96 - [3:0] */
7631#define WM8995_WSEQ_DELAY96_SHIFT 0 /* WSEQ_DELAY96 - [3:0] */
7632#define WM8995_WSEQ_DELAY96_WIDTH 4 /* WSEQ_DELAY96 - [3:0] */
7633
7634/*
7635 * R12676 (0x3184) - Write Sequencer 388
7636 */
7637#define WM8995_WSEQ_ADDR97_MASK 0x3FFF /* WSEQ_ADDR97 - [13:0] */
7638#define WM8995_WSEQ_ADDR97_SHIFT 0 /* WSEQ_ADDR97 - [13:0] */
7639#define WM8995_WSEQ_ADDR97_WIDTH 14 /* WSEQ_ADDR97 - [13:0] */
7640
7641/*
7642 * R12677 (0x3185) - Write Sequencer 389
7643 */
7644#define WM8995_WSEQ_DATA97_MASK 0x00FF /* WSEQ_DATA97 - [7:0] */
7645#define WM8995_WSEQ_DATA97_SHIFT 0 /* WSEQ_DATA97 - [7:0] */
7646#define WM8995_WSEQ_DATA97_WIDTH 8 /* WSEQ_DATA97 - [7:0] */
7647
7648/*
7649 * R12678 (0x3186) - Write Sequencer 390
7650 */
7651#define WM8995_WSEQ_DATA_WIDTH97_MASK 0x0700 /* WSEQ_DATA_WIDTH97 - [10:8] */
7652#define WM8995_WSEQ_DATA_WIDTH97_SHIFT 8 /* WSEQ_DATA_WIDTH97 - [10:8] */
7653#define WM8995_WSEQ_DATA_WIDTH97_WIDTH 3 /* WSEQ_DATA_WIDTH97 - [10:8] */
7654#define WM8995_WSEQ_DATA_START97_MASK 0x000F /* WSEQ_DATA_START97 - [3:0] */
7655#define WM8995_WSEQ_DATA_START97_SHIFT 0 /* WSEQ_DATA_START97 - [3:0] */
7656#define WM8995_WSEQ_DATA_START97_WIDTH 4 /* WSEQ_DATA_START97 - [3:0] */
7657
7658/*
7659 * R12679 (0x3187) - Write Sequencer 391
7660 */
7661#define WM8995_WSEQ_EOS97 0x0100 /* WSEQ_EOS97 */
7662#define WM8995_WSEQ_EOS97_MASK 0x0100 /* WSEQ_EOS97 */
7663#define WM8995_WSEQ_EOS97_SHIFT 8 /* WSEQ_EOS97 */
7664#define WM8995_WSEQ_EOS97_WIDTH 1 /* WSEQ_EOS97 */
7665#define WM8995_WSEQ_DELAY97_MASK 0x000F /* WSEQ_DELAY97 - [3:0] */
7666#define WM8995_WSEQ_DELAY97_SHIFT 0 /* WSEQ_DELAY97 - [3:0] */
7667#define WM8995_WSEQ_DELAY97_WIDTH 4 /* WSEQ_DELAY97 - [3:0] */
7668
7669/*
7670 * R12680 (0x3188) - Write Sequencer 392
7671 */
7672#define WM8995_WSEQ_ADDR98_MASK 0x3FFF /* WSEQ_ADDR98 - [13:0] */
7673#define WM8995_WSEQ_ADDR98_SHIFT 0 /* WSEQ_ADDR98 - [13:0] */
7674#define WM8995_WSEQ_ADDR98_WIDTH 14 /* WSEQ_ADDR98 - [13:0] */
7675
7676/*
7677 * R12681 (0x3189) - Write Sequencer 393
7678 */
7679#define WM8995_WSEQ_DATA98_MASK 0x00FF /* WSEQ_DATA98 - [7:0] */
7680#define WM8995_WSEQ_DATA98_SHIFT 0 /* WSEQ_DATA98 - [7:0] */
7681#define WM8995_WSEQ_DATA98_WIDTH 8 /* WSEQ_DATA98 - [7:0] */
7682
7683/*
7684 * R12682 (0x318A) - Write Sequencer 394
7685 */
7686#define WM8995_WSEQ_DATA_WIDTH98_MASK 0x0700 /* WSEQ_DATA_WIDTH98 - [10:8] */
7687#define WM8995_WSEQ_DATA_WIDTH98_SHIFT 8 /* WSEQ_DATA_WIDTH98 - [10:8] */
7688#define WM8995_WSEQ_DATA_WIDTH98_WIDTH 3 /* WSEQ_DATA_WIDTH98 - [10:8] */
7689#define WM8995_WSEQ_DATA_START98_MASK 0x000F /* WSEQ_DATA_START98 - [3:0] */
7690#define WM8995_WSEQ_DATA_START98_SHIFT 0 /* WSEQ_DATA_START98 - [3:0] */
7691#define WM8995_WSEQ_DATA_START98_WIDTH 4 /* WSEQ_DATA_START98 - [3:0] */
7692
7693/*
7694 * R12683 (0x318B) - Write Sequencer 395
7695 */
7696#define WM8995_WSEQ_EOS98 0x0100 /* WSEQ_EOS98 */
7697#define WM8995_WSEQ_EOS98_MASK 0x0100 /* WSEQ_EOS98 */
7698#define WM8995_WSEQ_EOS98_SHIFT 8 /* WSEQ_EOS98 */
7699#define WM8995_WSEQ_EOS98_WIDTH 1 /* WSEQ_EOS98 */
7700#define WM8995_WSEQ_DELAY98_MASK 0x000F /* WSEQ_DELAY98 - [3:0] */
7701#define WM8995_WSEQ_DELAY98_SHIFT 0 /* WSEQ_DELAY98 - [3:0] */
7702#define WM8995_WSEQ_DELAY98_WIDTH 4 /* WSEQ_DELAY98 - [3:0] */
7703
7704/*
7705 * R12684 (0x318C) - Write Sequencer 396
7706 */
7707#define WM8995_WSEQ_ADDR99_MASK 0x3FFF /* WSEQ_ADDR99 - [13:0] */
7708#define WM8995_WSEQ_ADDR99_SHIFT 0 /* WSEQ_ADDR99 - [13:0] */
7709#define WM8995_WSEQ_ADDR99_WIDTH 14 /* WSEQ_ADDR99 - [13:0] */
7710
7711/*
7712 * R12685 (0x318D) - Write Sequencer 397
7713 */
7714#define WM8995_WSEQ_DATA99_MASK 0x00FF /* WSEQ_DATA99 - [7:0] */
7715#define WM8995_WSEQ_DATA99_SHIFT 0 /* WSEQ_DATA99 - [7:0] */
7716#define WM8995_WSEQ_DATA99_WIDTH 8 /* WSEQ_DATA99 - [7:0] */
7717
7718/*
7719 * R12686 (0x318E) - Write Sequencer 398
7720 */
7721#define WM8995_WSEQ_DATA_WIDTH99_MASK 0x0700 /* WSEQ_DATA_WIDTH99 - [10:8] */
7722#define WM8995_WSEQ_DATA_WIDTH99_SHIFT 8 /* WSEQ_DATA_WIDTH99 - [10:8] */
7723#define WM8995_WSEQ_DATA_WIDTH99_WIDTH 3 /* WSEQ_DATA_WIDTH99 - [10:8] */
7724#define WM8995_WSEQ_DATA_START99_MASK 0x000F /* WSEQ_DATA_START99 - [3:0] */
7725#define WM8995_WSEQ_DATA_START99_SHIFT 0 /* WSEQ_DATA_START99 - [3:0] */
7726#define WM8995_WSEQ_DATA_START99_WIDTH 4 /* WSEQ_DATA_START99 - [3:0] */
7727
7728/*
7729 * R12687 (0x318F) - Write Sequencer 399
7730 */
7731#define WM8995_WSEQ_EOS99 0x0100 /* WSEQ_EOS99 */
7732#define WM8995_WSEQ_EOS99_MASK 0x0100 /* WSEQ_EOS99 */
7733#define WM8995_WSEQ_EOS99_SHIFT 8 /* WSEQ_EOS99 */
7734#define WM8995_WSEQ_EOS99_WIDTH 1 /* WSEQ_EOS99 */
7735#define WM8995_WSEQ_DELAY99_MASK 0x000F /* WSEQ_DELAY99 - [3:0] */
7736#define WM8995_WSEQ_DELAY99_SHIFT 0 /* WSEQ_DELAY99 - [3:0] */
7737#define WM8995_WSEQ_DELAY99_WIDTH 4 /* WSEQ_DELAY99 - [3:0] */
7738
7739/*
7740 * R12688 (0x3190) - Write Sequencer 400
7741 */
7742#define WM8995_WSEQ_ADDR100_MASK 0x3FFF /* WSEQ_ADDR100 - [13:0] */
7743#define WM8995_WSEQ_ADDR100_SHIFT 0 /* WSEQ_ADDR100 - [13:0] */
7744#define WM8995_WSEQ_ADDR100_WIDTH 14 /* WSEQ_ADDR100 - [13:0] */
7745
7746/*
7747 * R12689 (0x3191) - Write Sequencer 401
7748 */
7749#define WM8995_WSEQ_DATA100_MASK 0x00FF /* WSEQ_DATA100 - [7:0] */
7750#define WM8995_WSEQ_DATA100_SHIFT 0 /* WSEQ_DATA100 - [7:0] */
7751#define WM8995_WSEQ_DATA100_WIDTH 8 /* WSEQ_DATA100 - [7:0] */
7752
7753/*
7754 * R12690 (0x3192) - Write Sequencer 402
7755 */
7756#define WM8995_WSEQ_DATA_WIDTH100_MASK 0x0700 /* WSEQ_DATA_WIDTH100 - [10:8] */
7757#define WM8995_WSEQ_DATA_WIDTH100_SHIFT 8 /* WSEQ_DATA_WIDTH100 - [10:8] */
7758#define WM8995_WSEQ_DATA_WIDTH100_WIDTH 3 /* WSEQ_DATA_WIDTH100 - [10:8] */
7759#define WM8995_WSEQ_DATA_START100_MASK 0x000F /* WSEQ_DATA_START100 - [3:0] */
7760#define WM8995_WSEQ_DATA_START100_SHIFT 0 /* WSEQ_DATA_START100 - [3:0] */
7761#define WM8995_WSEQ_DATA_START100_WIDTH 4 /* WSEQ_DATA_START100 - [3:0] */
7762
7763/*
7764 * R12691 (0x3193) - Write Sequencer 403
7765 */
7766#define WM8995_WSEQ_EOS100 0x0100 /* WSEQ_EOS100 */
7767#define WM8995_WSEQ_EOS100_MASK 0x0100 /* WSEQ_EOS100 */
7768#define WM8995_WSEQ_EOS100_SHIFT 8 /* WSEQ_EOS100 */
7769#define WM8995_WSEQ_EOS100_WIDTH 1 /* WSEQ_EOS100 */
7770#define WM8995_WSEQ_DELAY100_MASK 0x000F /* WSEQ_DELAY100 - [3:0] */
7771#define WM8995_WSEQ_DELAY100_SHIFT 0 /* WSEQ_DELAY100 - [3:0] */
7772#define WM8995_WSEQ_DELAY100_WIDTH 4 /* WSEQ_DELAY100 - [3:0] */
7773
7774/*
7775 * R12692 (0x3194) - Write Sequencer 404
7776 */
7777#define WM8995_WSEQ_ADDR101_MASK 0x3FFF /* WSEQ_ADDR101 - [13:0] */
7778#define WM8995_WSEQ_ADDR101_SHIFT 0 /* WSEQ_ADDR101 - [13:0] */
7779#define WM8995_WSEQ_ADDR101_WIDTH 14 /* WSEQ_ADDR101 - [13:0] */
7780
7781/*
7782 * R12693 (0x3195) - Write Sequencer 405
7783 */
7784#define WM8995_WSEQ_DATA101_MASK 0x00FF /* WSEQ_DATA101 - [7:0] */
7785#define WM8995_WSEQ_DATA101_SHIFT 0 /* WSEQ_DATA101 - [7:0] */
7786#define WM8995_WSEQ_DATA101_WIDTH 8 /* WSEQ_DATA101 - [7:0] */
7787
7788/*
7789 * R12694 (0x3196) - Write Sequencer 406
7790 */
7791#define WM8995_WSEQ_DATA_WIDTH101_MASK 0x0700 /* WSEQ_DATA_WIDTH101 - [10:8] */
7792#define WM8995_WSEQ_DATA_WIDTH101_SHIFT 8 /* WSEQ_DATA_WIDTH101 - [10:8] */
7793#define WM8995_WSEQ_DATA_WIDTH101_WIDTH 3 /* WSEQ_DATA_WIDTH101 - [10:8] */
7794#define WM8995_WSEQ_DATA_START101_MASK 0x000F /* WSEQ_DATA_START101 - [3:0] */
7795#define WM8995_WSEQ_DATA_START101_SHIFT 0 /* WSEQ_DATA_START101 - [3:0] */
7796#define WM8995_WSEQ_DATA_START101_WIDTH 4 /* WSEQ_DATA_START101 - [3:0] */
7797
7798/*
7799 * R12695 (0x3197) - Write Sequencer 407
7800 */
7801#define WM8995_WSEQ_EOS101 0x0100 /* WSEQ_EOS101 */
7802#define WM8995_WSEQ_EOS101_MASK 0x0100 /* WSEQ_EOS101 */
7803#define WM8995_WSEQ_EOS101_SHIFT 8 /* WSEQ_EOS101 */
7804#define WM8995_WSEQ_EOS101_WIDTH 1 /* WSEQ_EOS101 */
7805#define WM8995_WSEQ_DELAY101_MASK 0x000F /* WSEQ_DELAY101 - [3:0] */
7806#define WM8995_WSEQ_DELAY101_SHIFT 0 /* WSEQ_DELAY101 - [3:0] */
7807#define WM8995_WSEQ_DELAY101_WIDTH 4 /* WSEQ_DELAY101 - [3:0] */
7808
7809/*
7810 * R12696 (0x3198) - Write Sequencer 408
7811 */
7812#define WM8995_WSEQ_ADDR102_MASK 0x3FFF /* WSEQ_ADDR102 - [13:0] */
7813#define WM8995_WSEQ_ADDR102_SHIFT 0 /* WSEQ_ADDR102 - [13:0] */
7814#define WM8995_WSEQ_ADDR102_WIDTH 14 /* WSEQ_ADDR102 - [13:0] */
7815
7816/*
7817 * R12697 (0x3199) - Write Sequencer 409
7818 */
7819#define WM8995_WSEQ_DATA102_MASK 0x00FF /* WSEQ_DATA102 - [7:0] */
7820#define WM8995_WSEQ_DATA102_SHIFT 0 /* WSEQ_DATA102 - [7:0] */
7821#define WM8995_WSEQ_DATA102_WIDTH 8 /* WSEQ_DATA102 - [7:0] */
7822
7823/*
7824 * R12698 (0x319A) - Write Sequencer 410
7825 */
7826#define WM8995_WSEQ_DATA_WIDTH102_MASK 0x0700 /* WSEQ_DATA_WIDTH102 - [10:8] */
7827#define WM8995_WSEQ_DATA_WIDTH102_SHIFT 8 /* WSEQ_DATA_WIDTH102 - [10:8] */
7828#define WM8995_WSEQ_DATA_WIDTH102_WIDTH 3 /* WSEQ_DATA_WIDTH102 - [10:8] */
7829#define WM8995_WSEQ_DATA_START102_MASK 0x000F /* WSEQ_DATA_START102 - [3:0] */
7830#define WM8995_WSEQ_DATA_START102_SHIFT 0 /* WSEQ_DATA_START102 - [3:0] */
7831#define WM8995_WSEQ_DATA_START102_WIDTH 4 /* WSEQ_DATA_START102 - [3:0] */
7832
7833/*
7834 * R12699 (0x319B) - Write Sequencer 411
7835 */
7836#define WM8995_WSEQ_EOS102 0x0100 /* WSEQ_EOS102 */
7837#define WM8995_WSEQ_EOS102_MASK 0x0100 /* WSEQ_EOS102 */
7838#define WM8995_WSEQ_EOS102_SHIFT 8 /* WSEQ_EOS102 */
7839#define WM8995_WSEQ_EOS102_WIDTH 1 /* WSEQ_EOS102 */
7840#define WM8995_WSEQ_DELAY102_MASK 0x000F /* WSEQ_DELAY102 - [3:0] */
7841#define WM8995_WSEQ_DELAY102_SHIFT 0 /* WSEQ_DELAY102 - [3:0] */
7842#define WM8995_WSEQ_DELAY102_WIDTH 4 /* WSEQ_DELAY102 - [3:0] */
7843
7844/*
7845 * R12700 (0x319C) - Write Sequencer 412
7846 */
7847#define WM8995_WSEQ_ADDR103_MASK 0x3FFF /* WSEQ_ADDR103 - [13:0] */
7848#define WM8995_WSEQ_ADDR103_SHIFT 0 /* WSEQ_ADDR103 - [13:0] */
7849#define WM8995_WSEQ_ADDR103_WIDTH 14 /* WSEQ_ADDR103 - [13:0] */
7850
7851/*
7852 * R12701 (0x319D) - Write Sequencer 413
7853 */
7854#define WM8995_WSEQ_DATA103_MASK 0x00FF /* WSEQ_DATA103 - [7:0] */
7855#define WM8995_WSEQ_DATA103_SHIFT 0 /* WSEQ_DATA103 - [7:0] */
7856#define WM8995_WSEQ_DATA103_WIDTH 8 /* WSEQ_DATA103 - [7:0] */
7857
7858/*
7859 * R12702 (0x319E) - Write Sequencer 414
7860 */
7861#define WM8995_WSEQ_DATA_WIDTH103_MASK 0x0700 /* WSEQ_DATA_WIDTH103 - [10:8] */
7862#define WM8995_WSEQ_DATA_WIDTH103_SHIFT 8 /* WSEQ_DATA_WIDTH103 - [10:8] */
7863#define WM8995_WSEQ_DATA_WIDTH103_WIDTH 3 /* WSEQ_DATA_WIDTH103 - [10:8] */
7864#define WM8995_WSEQ_DATA_START103_MASK 0x000F /* WSEQ_DATA_START103 - [3:0] */
7865#define WM8995_WSEQ_DATA_START103_SHIFT 0 /* WSEQ_DATA_START103 - [3:0] */
7866#define WM8995_WSEQ_DATA_START103_WIDTH 4 /* WSEQ_DATA_START103 - [3:0] */
7867
7868/*
7869 * R12703 (0x319F) - Write Sequencer 415
7870 */
7871#define WM8995_WSEQ_EOS103 0x0100 /* WSEQ_EOS103 */
7872#define WM8995_WSEQ_EOS103_MASK 0x0100 /* WSEQ_EOS103 */
7873#define WM8995_WSEQ_EOS103_SHIFT 8 /* WSEQ_EOS103 */
7874#define WM8995_WSEQ_EOS103_WIDTH 1 /* WSEQ_EOS103 */
7875#define WM8995_WSEQ_DELAY103_MASK 0x000F /* WSEQ_DELAY103 - [3:0] */
7876#define WM8995_WSEQ_DELAY103_SHIFT 0 /* WSEQ_DELAY103 - [3:0] */
7877#define WM8995_WSEQ_DELAY103_WIDTH 4 /* WSEQ_DELAY103 - [3:0] */
7878
7879/*
7880 * R12704 (0x31A0) - Write Sequencer 416
7881 */
7882#define WM8995_WSEQ_ADDR104_MASK 0x3FFF /* WSEQ_ADDR104 - [13:0] */
7883#define WM8995_WSEQ_ADDR104_SHIFT 0 /* WSEQ_ADDR104 - [13:0] */
7884#define WM8995_WSEQ_ADDR104_WIDTH 14 /* WSEQ_ADDR104 - [13:0] */
7885
7886/*
7887 * R12705 (0x31A1) - Write Sequencer 417
7888 */
7889#define WM8995_WSEQ_DATA104_MASK 0x00FF /* WSEQ_DATA104 - [7:0] */
7890#define WM8995_WSEQ_DATA104_SHIFT 0 /* WSEQ_DATA104 - [7:0] */
7891#define WM8995_WSEQ_DATA104_WIDTH 8 /* WSEQ_DATA104 - [7:0] */
7892
7893/*
7894 * R12706 (0x31A2) - Write Sequencer 418
7895 */
7896#define WM8995_WSEQ_DATA_WIDTH104_MASK 0x0700 /* WSEQ_DATA_WIDTH104 - [10:8] */
7897#define WM8995_WSEQ_DATA_WIDTH104_SHIFT 8 /* WSEQ_DATA_WIDTH104 - [10:8] */
7898#define WM8995_WSEQ_DATA_WIDTH104_WIDTH 3 /* WSEQ_DATA_WIDTH104 - [10:8] */
7899#define WM8995_WSEQ_DATA_START104_MASK 0x000F /* WSEQ_DATA_START104 - [3:0] */
7900#define WM8995_WSEQ_DATA_START104_SHIFT 0 /* WSEQ_DATA_START104 - [3:0] */
7901#define WM8995_WSEQ_DATA_START104_WIDTH 4 /* WSEQ_DATA_START104 - [3:0] */
7902
7903/*
7904 * R12707 (0x31A3) - Write Sequencer 419
7905 */
7906#define WM8995_WSEQ_EOS104 0x0100 /* WSEQ_EOS104 */
7907#define WM8995_WSEQ_EOS104_MASK 0x0100 /* WSEQ_EOS104 */
7908#define WM8995_WSEQ_EOS104_SHIFT 8 /* WSEQ_EOS104 */
7909#define WM8995_WSEQ_EOS104_WIDTH 1 /* WSEQ_EOS104 */
7910#define WM8995_WSEQ_DELAY104_MASK 0x000F /* WSEQ_DELAY104 - [3:0] */
7911#define WM8995_WSEQ_DELAY104_SHIFT 0 /* WSEQ_DELAY104 - [3:0] */
7912#define WM8995_WSEQ_DELAY104_WIDTH 4 /* WSEQ_DELAY104 - [3:0] */
7913
7914/*
7915 * R12708 (0x31A4) - Write Sequencer 420
7916 */
7917#define WM8995_WSEQ_ADDR105_MASK 0x3FFF /* WSEQ_ADDR105 - [13:0] */
7918#define WM8995_WSEQ_ADDR105_SHIFT 0 /* WSEQ_ADDR105 - [13:0] */
7919#define WM8995_WSEQ_ADDR105_WIDTH 14 /* WSEQ_ADDR105 - [13:0] */
7920
7921/*
7922 * R12709 (0x31A5) - Write Sequencer 421
7923 */
7924#define WM8995_WSEQ_DATA105_MASK 0x00FF /* WSEQ_DATA105 - [7:0] */
7925#define WM8995_WSEQ_DATA105_SHIFT 0 /* WSEQ_DATA105 - [7:0] */
7926#define WM8995_WSEQ_DATA105_WIDTH 8 /* WSEQ_DATA105 - [7:0] */
7927
7928/*
7929 * R12710 (0x31A6) - Write Sequencer 422
7930 */
7931#define WM8995_WSEQ_DATA_WIDTH105_MASK 0x0700 /* WSEQ_DATA_WIDTH105 - [10:8] */
7932#define WM8995_WSEQ_DATA_WIDTH105_SHIFT 8 /* WSEQ_DATA_WIDTH105 - [10:8] */
7933#define WM8995_WSEQ_DATA_WIDTH105_WIDTH 3 /* WSEQ_DATA_WIDTH105 - [10:8] */
7934#define WM8995_WSEQ_DATA_START105_MASK 0x000F /* WSEQ_DATA_START105 - [3:0] */
7935#define WM8995_WSEQ_DATA_START105_SHIFT 0 /* WSEQ_DATA_START105 - [3:0] */
7936#define WM8995_WSEQ_DATA_START105_WIDTH 4 /* WSEQ_DATA_START105 - [3:0] */
7937
7938/*
7939 * R12711 (0x31A7) - Write Sequencer 423
7940 */
7941#define WM8995_WSEQ_EOS105 0x0100 /* WSEQ_EOS105 */
7942#define WM8995_WSEQ_EOS105_MASK 0x0100 /* WSEQ_EOS105 */
7943#define WM8995_WSEQ_EOS105_SHIFT 8 /* WSEQ_EOS105 */
7944#define WM8995_WSEQ_EOS105_WIDTH 1 /* WSEQ_EOS105 */
7945#define WM8995_WSEQ_DELAY105_MASK 0x000F /* WSEQ_DELAY105 - [3:0] */
7946#define WM8995_WSEQ_DELAY105_SHIFT 0 /* WSEQ_DELAY105 - [3:0] */
7947#define WM8995_WSEQ_DELAY105_WIDTH 4 /* WSEQ_DELAY105 - [3:0] */
7948
7949/*
7950 * R12712 (0x31A8) - Write Sequencer 424
7951 */
7952#define WM8995_WSEQ_ADDR106_MASK 0x3FFF /* WSEQ_ADDR106 - [13:0] */
7953#define WM8995_WSEQ_ADDR106_SHIFT 0 /* WSEQ_ADDR106 - [13:0] */
7954#define WM8995_WSEQ_ADDR106_WIDTH 14 /* WSEQ_ADDR106 - [13:0] */
7955
7956/*
7957 * R12713 (0x31A9) - Write Sequencer 425
7958 */
7959#define WM8995_WSEQ_DATA106_MASK 0x00FF /* WSEQ_DATA106 - [7:0] */
7960#define WM8995_WSEQ_DATA106_SHIFT 0 /* WSEQ_DATA106 - [7:0] */
7961#define WM8995_WSEQ_DATA106_WIDTH 8 /* WSEQ_DATA106 - [7:0] */
7962
7963/*
7964 * R12714 (0x31AA) - Write Sequencer 426
7965 */
7966#define WM8995_WSEQ_DATA_WIDTH106_MASK 0x0700 /* WSEQ_DATA_WIDTH106 - [10:8] */
7967#define WM8995_WSEQ_DATA_WIDTH106_SHIFT 8 /* WSEQ_DATA_WIDTH106 - [10:8] */
7968#define WM8995_WSEQ_DATA_WIDTH106_WIDTH 3 /* WSEQ_DATA_WIDTH106 - [10:8] */
7969#define WM8995_WSEQ_DATA_START106_MASK 0x000F /* WSEQ_DATA_START106 - [3:0] */
7970#define WM8995_WSEQ_DATA_START106_SHIFT 0 /* WSEQ_DATA_START106 - [3:0] */
7971#define WM8995_WSEQ_DATA_START106_WIDTH 4 /* WSEQ_DATA_START106 - [3:0] */
7972
7973/*
7974 * R12715 (0x31AB) - Write Sequencer 427
7975 */
7976#define WM8995_WSEQ_EOS106 0x0100 /* WSEQ_EOS106 */
7977#define WM8995_WSEQ_EOS106_MASK 0x0100 /* WSEQ_EOS106 */
7978#define WM8995_WSEQ_EOS106_SHIFT 8 /* WSEQ_EOS106 */
7979#define WM8995_WSEQ_EOS106_WIDTH 1 /* WSEQ_EOS106 */
7980#define WM8995_WSEQ_DELAY106_MASK 0x000F /* WSEQ_DELAY106 - [3:0] */
7981#define WM8995_WSEQ_DELAY106_SHIFT 0 /* WSEQ_DELAY106 - [3:0] */
7982#define WM8995_WSEQ_DELAY106_WIDTH 4 /* WSEQ_DELAY106 - [3:0] */
7983
7984/*
7985 * R12716 (0x31AC) - Write Sequencer 428
7986 */
7987#define WM8995_WSEQ_ADDR107_MASK 0x3FFF /* WSEQ_ADDR107 - [13:0] */
7988#define WM8995_WSEQ_ADDR107_SHIFT 0 /* WSEQ_ADDR107 - [13:0] */
7989#define WM8995_WSEQ_ADDR107_WIDTH 14 /* WSEQ_ADDR107 - [13:0] */
7990
7991/*
7992 * R12717 (0x31AD) - Write Sequencer 429
7993 */
7994#define WM8995_WSEQ_DATA107_MASK 0x00FF /* WSEQ_DATA107 - [7:0] */
7995#define WM8995_WSEQ_DATA107_SHIFT 0 /* WSEQ_DATA107 - [7:0] */
7996#define WM8995_WSEQ_DATA107_WIDTH 8 /* WSEQ_DATA107 - [7:0] */
7997
7998/*
7999 * R12718 (0x31AE) - Write Sequencer 430
8000 */
8001#define WM8995_WSEQ_DATA_WIDTH107_MASK 0x0700 /* WSEQ_DATA_WIDTH107 - [10:8] */
8002#define WM8995_WSEQ_DATA_WIDTH107_SHIFT 8 /* WSEQ_DATA_WIDTH107 - [10:8] */
8003#define WM8995_WSEQ_DATA_WIDTH107_WIDTH 3 /* WSEQ_DATA_WIDTH107 - [10:8] */
8004#define WM8995_WSEQ_DATA_START107_MASK 0x000F /* WSEQ_DATA_START107 - [3:0] */
8005#define WM8995_WSEQ_DATA_START107_SHIFT 0 /* WSEQ_DATA_START107 - [3:0] */
8006#define WM8995_WSEQ_DATA_START107_WIDTH 4 /* WSEQ_DATA_START107 - [3:0] */
8007
8008/*
8009 * R12719 (0x31AF) - Write Sequencer 431
8010 */
8011#define WM8995_WSEQ_EOS107 0x0100 /* WSEQ_EOS107 */
8012#define WM8995_WSEQ_EOS107_MASK 0x0100 /* WSEQ_EOS107 */
8013#define WM8995_WSEQ_EOS107_SHIFT 8 /* WSEQ_EOS107 */
8014#define WM8995_WSEQ_EOS107_WIDTH 1 /* WSEQ_EOS107 */
8015#define WM8995_WSEQ_DELAY107_MASK 0x000F /* WSEQ_DELAY107 - [3:0] */
8016#define WM8995_WSEQ_DELAY107_SHIFT 0 /* WSEQ_DELAY107 - [3:0] */
8017#define WM8995_WSEQ_DELAY107_WIDTH 4 /* WSEQ_DELAY107 - [3:0] */
8018
8019/*
8020 * R12720 (0x31B0) - Write Sequencer 432
8021 */
8022#define WM8995_WSEQ_ADDR108_MASK 0x3FFF /* WSEQ_ADDR108 - [13:0] */
8023#define WM8995_WSEQ_ADDR108_SHIFT 0 /* WSEQ_ADDR108 - [13:0] */
8024#define WM8995_WSEQ_ADDR108_WIDTH 14 /* WSEQ_ADDR108 - [13:0] */
8025
8026/*
8027 * R12721 (0x31B1) - Write Sequencer 433
8028 */
8029#define WM8995_WSEQ_DATA108_MASK 0x00FF /* WSEQ_DATA108 - [7:0] */
8030#define WM8995_WSEQ_DATA108_SHIFT 0 /* WSEQ_DATA108 - [7:0] */
8031#define WM8995_WSEQ_DATA108_WIDTH 8 /* WSEQ_DATA108 - [7:0] */
8032
8033/*
8034 * R12722 (0x31B2) - Write Sequencer 434
8035 */
8036#define WM8995_WSEQ_DATA_WIDTH108_MASK 0x0700 /* WSEQ_DATA_WIDTH108 - [10:8] */
8037#define WM8995_WSEQ_DATA_WIDTH108_SHIFT 8 /* WSEQ_DATA_WIDTH108 - [10:8] */
8038#define WM8995_WSEQ_DATA_WIDTH108_WIDTH 3 /* WSEQ_DATA_WIDTH108 - [10:8] */
8039#define WM8995_WSEQ_DATA_START108_MASK 0x000F /* WSEQ_DATA_START108 - [3:0] */
8040#define WM8995_WSEQ_DATA_START108_SHIFT 0 /* WSEQ_DATA_START108 - [3:0] */
8041#define WM8995_WSEQ_DATA_START108_WIDTH 4 /* WSEQ_DATA_START108 - [3:0] */
8042
8043/*
8044 * R12723 (0x31B3) - Write Sequencer 435
8045 */
8046#define WM8995_WSEQ_EOS108 0x0100 /* WSEQ_EOS108 */
8047#define WM8995_WSEQ_EOS108_MASK 0x0100 /* WSEQ_EOS108 */
8048#define WM8995_WSEQ_EOS108_SHIFT 8 /* WSEQ_EOS108 */
8049#define WM8995_WSEQ_EOS108_WIDTH 1 /* WSEQ_EOS108 */
8050#define WM8995_WSEQ_DELAY108_MASK 0x000F /* WSEQ_DELAY108 - [3:0] */
8051#define WM8995_WSEQ_DELAY108_SHIFT 0 /* WSEQ_DELAY108 - [3:0] */
8052#define WM8995_WSEQ_DELAY108_WIDTH 4 /* WSEQ_DELAY108 - [3:0] */
8053
8054/*
8055 * R12724 (0x31B4) - Write Sequencer 436
8056 */
8057#define WM8995_WSEQ_ADDR109_MASK 0x3FFF /* WSEQ_ADDR109 - [13:0] */
8058#define WM8995_WSEQ_ADDR109_SHIFT 0 /* WSEQ_ADDR109 - [13:0] */
8059#define WM8995_WSEQ_ADDR109_WIDTH 14 /* WSEQ_ADDR109 - [13:0] */
8060
8061/*
8062 * R12725 (0x31B5) - Write Sequencer 437
8063 */
8064#define WM8995_WSEQ_DATA109_MASK 0x00FF /* WSEQ_DATA109 - [7:0] */
8065#define WM8995_WSEQ_DATA109_SHIFT 0 /* WSEQ_DATA109 - [7:0] */
8066#define WM8995_WSEQ_DATA109_WIDTH 8 /* WSEQ_DATA109 - [7:0] */
8067
8068/*
8069 * R12726 (0x31B6) - Write Sequencer 438
8070 */
8071#define WM8995_WSEQ_DATA_WIDTH109_MASK 0x0700 /* WSEQ_DATA_WIDTH109 - [10:8] */
8072#define WM8995_WSEQ_DATA_WIDTH109_SHIFT 8 /* WSEQ_DATA_WIDTH109 - [10:8] */
8073#define WM8995_WSEQ_DATA_WIDTH109_WIDTH 3 /* WSEQ_DATA_WIDTH109 - [10:8] */
8074#define WM8995_WSEQ_DATA_START109_MASK 0x000F /* WSEQ_DATA_START109 - [3:0] */
8075#define WM8995_WSEQ_DATA_START109_SHIFT 0 /* WSEQ_DATA_START109 - [3:0] */
8076#define WM8995_WSEQ_DATA_START109_WIDTH 4 /* WSEQ_DATA_START109 - [3:0] */
8077
8078/*
8079 * R12727 (0x31B7) - Write Sequencer 439
8080 */
8081#define WM8995_WSEQ_EOS109 0x0100 /* WSEQ_EOS109 */
8082#define WM8995_WSEQ_EOS109_MASK 0x0100 /* WSEQ_EOS109 */
8083#define WM8995_WSEQ_EOS109_SHIFT 8 /* WSEQ_EOS109 */
8084#define WM8995_WSEQ_EOS109_WIDTH 1 /* WSEQ_EOS109 */
8085#define WM8995_WSEQ_DELAY109_MASK 0x000F /* WSEQ_DELAY109 - [3:0] */
8086#define WM8995_WSEQ_DELAY109_SHIFT 0 /* WSEQ_DELAY109 - [3:0] */
8087#define WM8995_WSEQ_DELAY109_WIDTH 4 /* WSEQ_DELAY109 - [3:0] */
8088
8089/*
8090 * R12728 (0x31B8) - Write Sequencer 440
8091 */
8092#define WM8995_WSEQ_ADDR110_MASK 0x3FFF /* WSEQ_ADDR110 - [13:0] */
8093#define WM8995_WSEQ_ADDR110_SHIFT 0 /* WSEQ_ADDR110 - [13:0] */
8094#define WM8995_WSEQ_ADDR110_WIDTH 14 /* WSEQ_ADDR110 - [13:0] */
8095
8096/*
8097 * R12729 (0x31B9) - Write Sequencer 441
8098 */
8099#define WM8995_WSEQ_DATA110_MASK 0x00FF /* WSEQ_DATA110 - [7:0] */
8100#define WM8995_WSEQ_DATA110_SHIFT 0 /* WSEQ_DATA110 - [7:0] */
8101#define WM8995_WSEQ_DATA110_WIDTH 8 /* WSEQ_DATA110 - [7:0] */
8102
8103/*
8104 * R12730 (0x31BA) - Write Sequencer 442
8105 */
8106#define WM8995_WSEQ_DATA_WIDTH110_MASK 0x0700 /* WSEQ_DATA_WIDTH110 - [10:8] */
8107#define WM8995_WSEQ_DATA_WIDTH110_SHIFT 8 /* WSEQ_DATA_WIDTH110 - [10:8] */
8108#define WM8995_WSEQ_DATA_WIDTH110_WIDTH 3 /* WSEQ_DATA_WIDTH110 - [10:8] */
8109#define WM8995_WSEQ_DATA_START110_MASK 0x000F /* WSEQ_DATA_START110 - [3:0] */
8110#define WM8995_WSEQ_DATA_START110_SHIFT 0 /* WSEQ_DATA_START110 - [3:0] */
8111#define WM8995_WSEQ_DATA_START110_WIDTH 4 /* WSEQ_DATA_START110 - [3:0] */
8112
8113/*
8114 * R12731 (0x31BB) - Write Sequencer 443
8115 */
8116#define WM8995_WSEQ_EOS110 0x0100 /* WSEQ_EOS110 */
8117#define WM8995_WSEQ_EOS110_MASK 0x0100 /* WSEQ_EOS110 */
8118#define WM8995_WSEQ_EOS110_SHIFT 8 /* WSEQ_EOS110 */
8119#define WM8995_WSEQ_EOS110_WIDTH 1 /* WSEQ_EOS110 */
8120#define WM8995_WSEQ_DELAY110_MASK 0x000F /* WSEQ_DELAY110 - [3:0] */
8121#define WM8995_WSEQ_DELAY110_SHIFT 0 /* WSEQ_DELAY110 - [3:0] */
8122#define WM8995_WSEQ_DELAY110_WIDTH 4 /* WSEQ_DELAY110 - [3:0] */
8123
8124/*
8125 * R12732 (0x31BC) - Write Sequencer 444
8126 */
8127#define WM8995_WSEQ_ADDR111_MASK 0x3FFF /* WSEQ_ADDR111 - [13:0] */
8128#define WM8995_WSEQ_ADDR111_SHIFT 0 /* WSEQ_ADDR111 - [13:0] */
8129#define WM8995_WSEQ_ADDR111_WIDTH 14 /* WSEQ_ADDR111 - [13:0] */
8130
8131/*
8132 * R12733 (0x31BD) - Write Sequencer 445
8133 */
8134#define WM8995_WSEQ_DATA111_MASK 0x00FF /* WSEQ_DATA111 - [7:0] */
8135#define WM8995_WSEQ_DATA111_SHIFT 0 /* WSEQ_DATA111 - [7:0] */
8136#define WM8995_WSEQ_DATA111_WIDTH 8 /* WSEQ_DATA111 - [7:0] */
8137
8138/*
8139 * R12734 (0x31BE) - Write Sequencer 446
8140 */
8141#define WM8995_WSEQ_DATA_WIDTH111_MASK 0x0700 /* WSEQ_DATA_WIDTH111 - [10:8] */
8142#define WM8995_WSEQ_DATA_WIDTH111_SHIFT 8 /* WSEQ_DATA_WIDTH111 - [10:8] */
8143#define WM8995_WSEQ_DATA_WIDTH111_WIDTH 3 /* WSEQ_DATA_WIDTH111 - [10:8] */
8144#define WM8995_WSEQ_DATA_START111_MASK 0x000F /* WSEQ_DATA_START111 - [3:0] */
8145#define WM8995_WSEQ_DATA_START111_SHIFT 0 /* WSEQ_DATA_START111 - [3:0] */
8146#define WM8995_WSEQ_DATA_START111_WIDTH 4 /* WSEQ_DATA_START111 - [3:0] */
8147
8148/*
8149 * R12735 (0x31BF) - Write Sequencer 447
8150 */
8151#define WM8995_WSEQ_EOS111 0x0100 /* WSEQ_EOS111 */
8152#define WM8995_WSEQ_EOS111_MASK 0x0100 /* WSEQ_EOS111 */
8153#define WM8995_WSEQ_EOS111_SHIFT 8 /* WSEQ_EOS111 */
8154#define WM8995_WSEQ_EOS111_WIDTH 1 /* WSEQ_EOS111 */
8155#define WM8995_WSEQ_DELAY111_MASK 0x000F /* WSEQ_DELAY111 - [3:0] */
8156#define WM8995_WSEQ_DELAY111_SHIFT 0 /* WSEQ_DELAY111 - [3:0] */
8157#define WM8995_WSEQ_DELAY111_WIDTH 4 /* WSEQ_DELAY111 - [3:0] */
8158
8159/*
8160 * R12736 (0x31C0) - Write Sequencer 448
8161 */
8162#define WM8995_WSEQ_ADDR112_MASK 0x3FFF /* WSEQ_ADDR112 - [13:0] */
8163#define WM8995_WSEQ_ADDR112_SHIFT 0 /* WSEQ_ADDR112 - [13:0] */
8164#define WM8995_WSEQ_ADDR112_WIDTH 14 /* WSEQ_ADDR112 - [13:0] */
8165
8166/*
8167 * R12737 (0x31C1) - Write Sequencer 449
8168 */
8169#define WM8995_WSEQ_DATA112_MASK 0x00FF /* WSEQ_DATA112 - [7:0] */
8170#define WM8995_WSEQ_DATA112_SHIFT 0 /* WSEQ_DATA112 - [7:0] */
8171#define WM8995_WSEQ_DATA112_WIDTH 8 /* WSEQ_DATA112 - [7:0] */
8172
8173/*
8174 * R12738 (0x31C2) - Write Sequencer 450
8175 */
8176#define WM8995_WSEQ_DATA_WIDTH112_MASK 0x0700 /* WSEQ_DATA_WIDTH112 - [10:8] */
8177#define WM8995_WSEQ_DATA_WIDTH112_SHIFT 8 /* WSEQ_DATA_WIDTH112 - [10:8] */
8178#define WM8995_WSEQ_DATA_WIDTH112_WIDTH 3 /* WSEQ_DATA_WIDTH112 - [10:8] */
8179#define WM8995_WSEQ_DATA_START112_MASK 0x000F /* WSEQ_DATA_START112 - [3:0] */
8180#define WM8995_WSEQ_DATA_START112_SHIFT 0 /* WSEQ_DATA_START112 - [3:0] */
8181#define WM8995_WSEQ_DATA_START112_WIDTH 4 /* WSEQ_DATA_START112 - [3:0] */
8182
8183/*
8184 * R12739 (0x31C3) - Write Sequencer 451
8185 */
8186#define WM8995_WSEQ_EOS112 0x0100 /* WSEQ_EOS112 */
8187#define WM8995_WSEQ_EOS112_MASK 0x0100 /* WSEQ_EOS112 */
8188#define WM8995_WSEQ_EOS112_SHIFT 8 /* WSEQ_EOS112 */
8189#define WM8995_WSEQ_EOS112_WIDTH 1 /* WSEQ_EOS112 */
8190#define WM8995_WSEQ_DELAY112_MASK 0x000F /* WSEQ_DELAY112 - [3:0] */
8191#define WM8995_WSEQ_DELAY112_SHIFT 0 /* WSEQ_DELAY112 - [3:0] */
8192#define WM8995_WSEQ_DELAY112_WIDTH 4 /* WSEQ_DELAY112 - [3:0] */
8193
8194/*
8195 * R12740 (0x31C4) - Write Sequencer 452
8196 */
8197#define WM8995_WSEQ_ADDR113_MASK 0x3FFF /* WSEQ_ADDR113 - [13:0] */
8198#define WM8995_WSEQ_ADDR113_SHIFT 0 /* WSEQ_ADDR113 - [13:0] */
8199#define WM8995_WSEQ_ADDR113_WIDTH 14 /* WSEQ_ADDR113 - [13:0] */
8200
8201/*
8202 * R12741 (0x31C5) - Write Sequencer 453
8203 */
8204#define WM8995_WSEQ_DATA113_MASK 0x00FF /* WSEQ_DATA113 - [7:0] */
8205#define WM8995_WSEQ_DATA113_SHIFT 0 /* WSEQ_DATA113 - [7:0] */
8206#define WM8995_WSEQ_DATA113_WIDTH 8 /* WSEQ_DATA113 - [7:0] */
8207
8208/*
8209 * R12742 (0x31C6) - Write Sequencer 454
8210 */
8211#define WM8995_WSEQ_DATA_WIDTH113_MASK 0x0700 /* WSEQ_DATA_WIDTH113 - [10:8] */
8212#define WM8995_WSEQ_DATA_WIDTH113_SHIFT 8 /* WSEQ_DATA_WIDTH113 - [10:8] */
8213#define WM8995_WSEQ_DATA_WIDTH113_WIDTH 3 /* WSEQ_DATA_WIDTH113 - [10:8] */
8214#define WM8995_WSEQ_DATA_START113_MASK 0x000F /* WSEQ_DATA_START113 - [3:0] */
8215#define WM8995_WSEQ_DATA_START113_SHIFT 0 /* WSEQ_DATA_START113 - [3:0] */
8216#define WM8995_WSEQ_DATA_START113_WIDTH 4 /* WSEQ_DATA_START113 - [3:0] */
8217
8218/*
8219 * R12743 (0x31C7) - Write Sequencer 455
8220 */
8221#define WM8995_WSEQ_EOS113 0x0100 /* WSEQ_EOS113 */
8222#define WM8995_WSEQ_EOS113_MASK 0x0100 /* WSEQ_EOS113 */
8223#define WM8995_WSEQ_EOS113_SHIFT 8 /* WSEQ_EOS113 */
8224#define WM8995_WSEQ_EOS113_WIDTH 1 /* WSEQ_EOS113 */
8225#define WM8995_WSEQ_DELAY113_MASK 0x000F /* WSEQ_DELAY113 - [3:0] */
8226#define WM8995_WSEQ_DELAY113_SHIFT 0 /* WSEQ_DELAY113 - [3:0] */
8227#define WM8995_WSEQ_DELAY113_WIDTH 4 /* WSEQ_DELAY113 - [3:0] */
8228
8229/*
8230 * R12744 (0x31C8) - Write Sequencer 456
8231 */
8232#define WM8995_WSEQ_ADDR114_MASK 0x3FFF /* WSEQ_ADDR114 - [13:0] */
8233#define WM8995_WSEQ_ADDR114_SHIFT 0 /* WSEQ_ADDR114 - [13:0] */
8234#define WM8995_WSEQ_ADDR114_WIDTH 14 /* WSEQ_ADDR114 - [13:0] */
8235
8236/*
8237 * R12745 (0x31C9) - Write Sequencer 457
8238 */
8239#define WM8995_WSEQ_DATA114_MASK 0x00FF /* WSEQ_DATA114 - [7:0] */
8240#define WM8995_WSEQ_DATA114_SHIFT 0 /* WSEQ_DATA114 - [7:0] */
8241#define WM8995_WSEQ_DATA114_WIDTH 8 /* WSEQ_DATA114 - [7:0] */
8242
8243/*
8244 * R12746 (0x31CA) - Write Sequencer 458
8245 */
8246#define WM8995_WSEQ_DATA_WIDTH114_MASK 0x0700 /* WSEQ_DATA_WIDTH114 - [10:8] */
8247#define WM8995_WSEQ_DATA_WIDTH114_SHIFT 8 /* WSEQ_DATA_WIDTH114 - [10:8] */
8248#define WM8995_WSEQ_DATA_WIDTH114_WIDTH 3 /* WSEQ_DATA_WIDTH114 - [10:8] */
8249#define WM8995_WSEQ_DATA_START114_MASK 0x000F /* WSEQ_DATA_START114 - [3:0] */
8250#define WM8995_WSEQ_DATA_START114_SHIFT 0 /* WSEQ_DATA_START114 - [3:0] */
8251#define WM8995_WSEQ_DATA_START114_WIDTH 4 /* WSEQ_DATA_START114 - [3:0] */
8252
8253/*
8254 * R12747 (0x31CB) - Write Sequencer 459
8255 */
8256#define WM8995_WSEQ_EOS114 0x0100 /* WSEQ_EOS114 */
8257#define WM8995_WSEQ_EOS114_MASK 0x0100 /* WSEQ_EOS114 */
8258#define WM8995_WSEQ_EOS114_SHIFT 8 /* WSEQ_EOS114 */
8259#define WM8995_WSEQ_EOS114_WIDTH 1 /* WSEQ_EOS114 */
8260#define WM8995_WSEQ_DELAY114_MASK 0x000F /* WSEQ_DELAY114 - [3:0] */
8261#define WM8995_WSEQ_DELAY114_SHIFT 0 /* WSEQ_DELAY114 - [3:0] */
8262#define WM8995_WSEQ_DELAY114_WIDTH 4 /* WSEQ_DELAY114 - [3:0] */
8263
8264/*
8265 * R12748 (0x31CC) - Write Sequencer 460
8266 */
8267#define WM8995_WSEQ_ADDR115_MASK 0x3FFF /* WSEQ_ADDR115 - [13:0] */
8268#define WM8995_WSEQ_ADDR115_SHIFT 0 /* WSEQ_ADDR115 - [13:0] */
8269#define WM8995_WSEQ_ADDR115_WIDTH 14 /* WSEQ_ADDR115 - [13:0] */
8270
8271/*
8272 * R12749 (0x31CD) - Write Sequencer 461
8273 */
8274#define WM8995_WSEQ_DATA115_MASK 0x00FF /* WSEQ_DATA115 - [7:0] */
8275#define WM8995_WSEQ_DATA115_SHIFT 0 /* WSEQ_DATA115 - [7:0] */
8276#define WM8995_WSEQ_DATA115_WIDTH 8 /* WSEQ_DATA115 - [7:0] */
8277
8278/*
8279 * R12750 (0x31CE) - Write Sequencer 462
8280 */
8281#define WM8995_WSEQ_DATA_WIDTH115_MASK 0x0700 /* WSEQ_DATA_WIDTH115 - [10:8] */
8282#define WM8995_WSEQ_DATA_WIDTH115_SHIFT 8 /* WSEQ_DATA_WIDTH115 - [10:8] */
8283#define WM8995_WSEQ_DATA_WIDTH115_WIDTH 3 /* WSEQ_DATA_WIDTH115 - [10:8] */
8284#define WM8995_WSEQ_DATA_START115_MASK 0x000F /* WSEQ_DATA_START115 - [3:0] */
8285#define WM8995_WSEQ_DATA_START115_SHIFT 0 /* WSEQ_DATA_START115 - [3:0] */
8286#define WM8995_WSEQ_DATA_START115_WIDTH 4 /* WSEQ_DATA_START115 - [3:0] */
8287
8288/*
8289 * R12751 (0x31CF) - Write Sequencer 463
8290 */
8291#define WM8995_WSEQ_EOS115 0x0100 /* WSEQ_EOS115 */
8292#define WM8995_WSEQ_EOS115_MASK 0x0100 /* WSEQ_EOS115 */
8293#define WM8995_WSEQ_EOS115_SHIFT 8 /* WSEQ_EOS115 */
8294#define WM8995_WSEQ_EOS115_WIDTH 1 /* WSEQ_EOS115 */
8295#define WM8995_WSEQ_DELAY115_MASK 0x000F /* WSEQ_DELAY115 - [3:0] */
8296#define WM8995_WSEQ_DELAY115_SHIFT 0 /* WSEQ_DELAY115 - [3:0] */
8297#define WM8995_WSEQ_DELAY115_WIDTH 4 /* WSEQ_DELAY115 - [3:0] */
8298
8299/*
8300 * R12752 (0x31D0) - Write Sequencer 464
8301 */
8302#define WM8995_WSEQ_ADDR116_MASK 0x3FFF /* WSEQ_ADDR116 - [13:0] */
8303#define WM8995_WSEQ_ADDR116_SHIFT 0 /* WSEQ_ADDR116 - [13:0] */
8304#define WM8995_WSEQ_ADDR116_WIDTH 14 /* WSEQ_ADDR116 - [13:0] */
8305
8306/*
8307 * R12753 (0x31D1) - Write Sequencer 465
8308 */
8309#define WM8995_WSEQ_DATA116_MASK 0x00FF /* WSEQ_DATA116 - [7:0] */
8310#define WM8995_WSEQ_DATA116_SHIFT 0 /* WSEQ_DATA116 - [7:0] */
8311#define WM8995_WSEQ_DATA116_WIDTH 8 /* WSEQ_DATA116 - [7:0] */
8312
8313/*
8314 * R12754 (0x31D2) - Write Sequencer 466
8315 */
8316#define WM8995_WSEQ_DATA_WIDTH116_MASK 0x0700 /* WSEQ_DATA_WIDTH116 - [10:8] */
8317#define WM8995_WSEQ_DATA_WIDTH116_SHIFT 8 /* WSEQ_DATA_WIDTH116 - [10:8] */
8318#define WM8995_WSEQ_DATA_WIDTH116_WIDTH 3 /* WSEQ_DATA_WIDTH116 - [10:8] */
8319#define WM8995_WSEQ_DATA_START116_MASK 0x000F /* WSEQ_DATA_START116 - [3:0] */
8320#define WM8995_WSEQ_DATA_START116_SHIFT 0 /* WSEQ_DATA_START116 - [3:0] */
8321#define WM8995_WSEQ_DATA_START116_WIDTH 4 /* WSEQ_DATA_START116 - [3:0] */
8322
8323/*
8324 * R12755 (0x31D3) - Write Sequencer 467
8325 */
8326#define WM8995_WSEQ_EOS116 0x0100 /* WSEQ_EOS116 */
8327#define WM8995_WSEQ_EOS116_MASK 0x0100 /* WSEQ_EOS116 */
8328#define WM8995_WSEQ_EOS116_SHIFT 8 /* WSEQ_EOS116 */
8329#define WM8995_WSEQ_EOS116_WIDTH 1 /* WSEQ_EOS116 */
8330#define WM8995_WSEQ_DELAY116_MASK 0x000F /* WSEQ_DELAY116 - [3:0] */
8331#define WM8995_WSEQ_DELAY116_SHIFT 0 /* WSEQ_DELAY116 - [3:0] */
8332#define WM8995_WSEQ_DELAY116_WIDTH 4 /* WSEQ_DELAY116 - [3:0] */
8333
8334/*
8335 * R12756 (0x31D4) - Write Sequencer 468
8336 */
8337#define WM8995_WSEQ_ADDR117_MASK 0x3FFF /* WSEQ_ADDR117 - [13:0] */
8338#define WM8995_WSEQ_ADDR117_SHIFT 0 /* WSEQ_ADDR117 - [13:0] */
8339#define WM8995_WSEQ_ADDR117_WIDTH 14 /* WSEQ_ADDR117 - [13:0] */
8340
8341/*
8342 * R12757 (0x31D5) - Write Sequencer 469
8343 */
8344#define WM8995_WSEQ_DATA117_MASK 0x00FF /* WSEQ_DATA117 - [7:0] */
8345#define WM8995_WSEQ_DATA117_SHIFT 0 /* WSEQ_DATA117 - [7:0] */
8346#define WM8995_WSEQ_DATA117_WIDTH 8 /* WSEQ_DATA117 - [7:0] */
8347
8348/*
8349 * R12758 (0x31D6) - Write Sequencer 470
8350 */
8351#define WM8995_WSEQ_DATA_WIDTH117_MASK 0x0700 /* WSEQ_DATA_WIDTH117 - [10:8] */
8352#define WM8995_WSEQ_DATA_WIDTH117_SHIFT 8 /* WSEQ_DATA_WIDTH117 - [10:8] */
8353#define WM8995_WSEQ_DATA_WIDTH117_WIDTH 3 /* WSEQ_DATA_WIDTH117 - [10:8] */
8354#define WM8995_WSEQ_DATA_START117_MASK 0x000F /* WSEQ_DATA_START117 - [3:0] */
8355#define WM8995_WSEQ_DATA_START117_SHIFT 0 /* WSEQ_DATA_START117 - [3:0] */
8356#define WM8995_WSEQ_DATA_START117_WIDTH 4 /* WSEQ_DATA_START117 - [3:0] */
8357
8358/*
8359 * R12759 (0x31D7) - Write Sequencer 471
8360 */
8361#define WM8995_WSEQ_EOS117 0x0100 /* WSEQ_EOS117 */
8362#define WM8995_WSEQ_EOS117_MASK 0x0100 /* WSEQ_EOS117 */
8363#define WM8995_WSEQ_EOS117_SHIFT 8 /* WSEQ_EOS117 */
8364#define WM8995_WSEQ_EOS117_WIDTH 1 /* WSEQ_EOS117 */
8365#define WM8995_WSEQ_DELAY117_MASK 0x000F /* WSEQ_DELAY117 - [3:0] */
8366#define WM8995_WSEQ_DELAY117_SHIFT 0 /* WSEQ_DELAY117 - [3:0] */
8367#define WM8995_WSEQ_DELAY117_WIDTH 4 /* WSEQ_DELAY117 - [3:0] */
8368
8369/*
8370 * R12760 (0x31D8) - Write Sequencer 472
8371 */
8372#define WM8995_WSEQ_ADDR118_MASK 0x3FFF /* WSEQ_ADDR118 - [13:0] */
8373#define WM8995_WSEQ_ADDR118_SHIFT 0 /* WSEQ_ADDR118 - [13:0] */
8374#define WM8995_WSEQ_ADDR118_WIDTH 14 /* WSEQ_ADDR118 - [13:0] */
8375
8376/*
8377 * R12761 (0x31D9) - Write Sequencer 473
8378 */
8379#define WM8995_WSEQ_DATA118_MASK 0x00FF /* WSEQ_DATA118 - [7:0] */
8380#define WM8995_WSEQ_DATA118_SHIFT 0 /* WSEQ_DATA118 - [7:0] */
8381#define WM8995_WSEQ_DATA118_WIDTH 8 /* WSEQ_DATA118 - [7:0] */
8382
8383/*
8384 * R12762 (0x31DA) - Write Sequencer 474
8385 */
8386#define WM8995_WSEQ_DATA_WIDTH118_MASK 0x0700 /* WSEQ_DATA_WIDTH118 - [10:8] */
8387#define WM8995_WSEQ_DATA_WIDTH118_SHIFT 8 /* WSEQ_DATA_WIDTH118 - [10:8] */
8388#define WM8995_WSEQ_DATA_WIDTH118_WIDTH 3 /* WSEQ_DATA_WIDTH118 - [10:8] */
8389#define WM8995_WSEQ_DATA_START118_MASK 0x000F /* WSEQ_DATA_START118 - [3:0] */
8390#define WM8995_WSEQ_DATA_START118_SHIFT 0 /* WSEQ_DATA_START118 - [3:0] */
8391#define WM8995_WSEQ_DATA_START118_WIDTH 4 /* WSEQ_DATA_START118 - [3:0] */
8392
8393/*
8394 * R12763 (0x31DB) - Write Sequencer 475
8395 */
8396#define WM8995_WSEQ_EOS118 0x0100 /* WSEQ_EOS118 */
8397#define WM8995_WSEQ_EOS118_MASK 0x0100 /* WSEQ_EOS118 */
8398#define WM8995_WSEQ_EOS118_SHIFT 8 /* WSEQ_EOS118 */
8399#define WM8995_WSEQ_EOS118_WIDTH 1 /* WSEQ_EOS118 */
8400#define WM8995_WSEQ_DELAY118_MASK 0x000F /* WSEQ_DELAY118 - [3:0] */
8401#define WM8995_WSEQ_DELAY118_SHIFT 0 /* WSEQ_DELAY118 - [3:0] */
8402#define WM8995_WSEQ_DELAY118_WIDTH 4 /* WSEQ_DELAY118 - [3:0] */
8403
8404/*
8405 * R12764 (0x31DC) - Write Sequencer 476
8406 */
8407#define WM8995_WSEQ_ADDR119_MASK 0x3FFF /* WSEQ_ADDR119 - [13:0] */
8408#define WM8995_WSEQ_ADDR119_SHIFT 0 /* WSEQ_ADDR119 - [13:0] */
8409#define WM8995_WSEQ_ADDR119_WIDTH 14 /* WSEQ_ADDR119 - [13:0] */
8410
8411/*
8412 * R12765 (0x31DD) - Write Sequencer 477
8413 */
8414#define WM8995_WSEQ_DATA119_MASK 0x00FF /* WSEQ_DATA119 - [7:0] */
8415#define WM8995_WSEQ_DATA119_SHIFT 0 /* WSEQ_DATA119 - [7:0] */
8416#define WM8995_WSEQ_DATA119_WIDTH 8 /* WSEQ_DATA119 - [7:0] */
8417
8418/*
8419 * R12766 (0x31DE) - Write Sequencer 478
8420 */
8421#define WM8995_WSEQ_DATA_WIDTH119_MASK 0x0700 /* WSEQ_DATA_WIDTH119 - [10:8] */
8422#define WM8995_WSEQ_DATA_WIDTH119_SHIFT 8 /* WSEQ_DATA_WIDTH119 - [10:8] */
8423#define WM8995_WSEQ_DATA_WIDTH119_WIDTH 3 /* WSEQ_DATA_WIDTH119 - [10:8] */
8424#define WM8995_WSEQ_DATA_START119_MASK 0x000F /* WSEQ_DATA_START119 - [3:0] */
8425#define WM8995_WSEQ_DATA_START119_SHIFT 0 /* WSEQ_DATA_START119 - [3:0] */
8426#define WM8995_WSEQ_DATA_START119_WIDTH 4 /* WSEQ_DATA_START119 - [3:0] */
8427
8428/*
8429 * R12767 (0x31DF) - Write Sequencer 479
8430 */
8431#define WM8995_WSEQ_EOS119 0x0100 /* WSEQ_EOS119 */
8432#define WM8995_WSEQ_EOS119_MASK 0x0100 /* WSEQ_EOS119 */
8433#define WM8995_WSEQ_EOS119_SHIFT 8 /* WSEQ_EOS119 */
8434#define WM8995_WSEQ_EOS119_WIDTH 1 /* WSEQ_EOS119 */
8435#define WM8995_WSEQ_DELAY119_MASK 0x000F /* WSEQ_DELAY119 - [3:0] */
8436#define WM8995_WSEQ_DELAY119_SHIFT 0 /* WSEQ_DELAY119 - [3:0] */
8437#define WM8995_WSEQ_DELAY119_WIDTH 4 /* WSEQ_DELAY119 - [3:0] */
8438
8439/*
8440 * R12768 (0x31E0) - Write Sequencer 480
8441 */
8442#define WM8995_WSEQ_ADDR120_MASK 0x3FFF /* WSEQ_ADDR120 - [13:0] */
8443#define WM8995_WSEQ_ADDR120_SHIFT 0 /* WSEQ_ADDR120 - [13:0] */
8444#define WM8995_WSEQ_ADDR120_WIDTH 14 /* WSEQ_ADDR120 - [13:0] */
8445
8446/*
8447 * R12769 (0x31E1) - Write Sequencer 481
8448 */
8449#define WM8995_WSEQ_DATA120_MASK 0x00FF /* WSEQ_DATA120 - [7:0] */
8450#define WM8995_WSEQ_DATA120_SHIFT 0 /* WSEQ_DATA120 - [7:0] */
8451#define WM8995_WSEQ_DATA120_WIDTH 8 /* WSEQ_DATA120 - [7:0] */
8452
8453/*
8454 * R12770 (0x31E2) - Write Sequencer 482
8455 */
8456#define WM8995_WSEQ_DATA_WIDTH120_MASK 0x0700 /* WSEQ_DATA_WIDTH120 - [10:8] */
8457#define WM8995_WSEQ_DATA_WIDTH120_SHIFT 8 /* WSEQ_DATA_WIDTH120 - [10:8] */
8458#define WM8995_WSEQ_DATA_WIDTH120_WIDTH 3 /* WSEQ_DATA_WIDTH120 - [10:8] */
8459#define WM8995_WSEQ_DATA_START120_MASK 0x000F /* WSEQ_DATA_START120 - [3:0] */
8460#define WM8995_WSEQ_DATA_START120_SHIFT 0 /* WSEQ_DATA_START120 - [3:0] */
8461#define WM8995_WSEQ_DATA_START120_WIDTH 4 /* WSEQ_DATA_START120 - [3:0] */
8462
8463/*
8464 * R12771 (0x31E3) - Write Sequencer 483
8465 */
8466#define WM8995_WSEQ_EOS120 0x0100 /* WSEQ_EOS120 */
8467#define WM8995_WSEQ_EOS120_MASK 0x0100 /* WSEQ_EOS120 */
8468#define WM8995_WSEQ_EOS120_SHIFT 8 /* WSEQ_EOS120 */
8469#define WM8995_WSEQ_EOS120_WIDTH 1 /* WSEQ_EOS120 */
8470#define WM8995_WSEQ_DELAY120_MASK 0x000F /* WSEQ_DELAY120 - [3:0] */
8471#define WM8995_WSEQ_DELAY120_SHIFT 0 /* WSEQ_DELAY120 - [3:0] */
8472#define WM8995_WSEQ_DELAY120_WIDTH 4 /* WSEQ_DELAY120 - [3:0] */
8473
8474/*
8475 * R12772 (0x31E4) - Write Sequencer 484
8476 */
8477#define WM8995_WSEQ_ADDR121_MASK 0x3FFF /* WSEQ_ADDR121 - [13:0] */
8478#define WM8995_WSEQ_ADDR121_SHIFT 0 /* WSEQ_ADDR121 - [13:0] */
8479#define WM8995_WSEQ_ADDR121_WIDTH 14 /* WSEQ_ADDR121 - [13:0] */
8480
8481/*
8482 * R12773 (0x31E5) - Write Sequencer 485
8483 */
8484#define WM8995_WSEQ_DATA121_MASK 0x00FF /* WSEQ_DATA121 - [7:0] */
8485#define WM8995_WSEQ_DATA121_SHIFT 0 /* WSEQ_DATA121 - [7:0] */
8486#define WM8995_WSEQ_DATA121_WIDTH 8 /* WSEQ_DATA121 - [7:0] */
8487
8488/*
8489 * R12774 (0x31E6) - Write Sequencer 486
8490 */
8491#define WM8995_WSEQ_DATA_WIDTH121_MASK 0x0700 /* WSEQ_DATA_WIDTH121 - [10:8] */
8492#define WM8995_WSEQ_DATA_WIDTH121_SHIFT 8 /* WSEQ_DATA_WIDTH121 - [10:8] */
8493#define WM8995_WSEQ_DATA_WIDTH121_WIDTH 3 /* WSEQ_DATA_WIDTH121 - [10:8] */
8494#define WM8995_WSEQ_DATA_START121_MASK 0x000F /* WSEQ_DATA_START121 - [3:0] */
8495#define WM8995_WSEQ_DATA_START121_SHIFT 0 /* WSEQ_DATA_START121 - [3:0] */
8496#define WM8995_WSEQ_DATA_START121_WIDTH 4 /* WSEQ_DATA_START121 - [3:0] */
8497
8498/*
8499 * R12775 (0x31E7) - Write Sequencer 487
8500 */
8501#define WM8995_WSEQ_EOS121 0x0100 /* WSEQ_EOS121 */
8502#define WM8995_WSEQ_EOS121_MASK 0x0100 /* WSEQ_EOS121 */
8503#define WM8995_WSEQ_EOS121_SHIFT 8 /* WSEQ_EOS121 */
8504#define WM8995_WSEQ_EOS121_WIDTH 1 /* WSEQ_EOS121 */
8505#define WM8995_WSEQ_DELAY121_MASK 0x000F /* WSEQ_DELAY121 - [3:0] */
8506#define WM8995_WSEQ_DELAY121_SHIFT 0 /* WSEQ_DELAY121 - [3:0] */
8507#define WM8995_WSEQ_DELAY121_WIDTH 4 /* WSEQ_DELAY121 - [3:0] */
8508
8509/*
8510 * R12776 (0x31E8) - Write Sequencer 488
8511 */
8512#define WM8995_WSEQ_ADDR122_MASK 0x3FFF /* WSEQ_ADDR122 - [13:0] */
8513#define WM8995_WSEQ_ADDR122_SHIFT 0 /* WSEQ_ADDR122 - [13:0] */
8514#define WM8995_WSEQ_ADDR122_WIDTH 14 /* WSEQ_ADDR122 - [13:0] */
8515
8516/*
8517 * R12777 (0x31E9) - Write Sequencer 489
8518 */
8519#define WM8995_WSEQ_DATA122_MASK 0x00FF /* WSEQ_DATA122 - [7:0] */
8520#define WM8995_WSEQ_DATA122_SHIFT 0 /* WSEQ_DATA122 - [7:0] */
8521#define WM8995_WSEQ_DATA122_WIDTH 8 /* WSEQ_DATA122 - [7:0] */
8522
8523/*
8524 * R12778 (0x31EA) - Write Sequencer 490
8525 */
8526#define WM8995_WSEQ_DATA_WIDTH122_MASK 0x0700 /* WSEQ_DATA_WIDTH122 - [10:8] */
8527#define WM8995_WSEQ_DATA_WIDTH122_SHIFT 8 /* WSEQ_DATA_WIDTH122 - [10:8] */
8528#define WM8995_WSEQ_DATA_WIDTH122_WIDTH 3 /* WSEQ_DATA_WIDTH122 - [10:8] */
8529#define WM8995_WSEQ_DATA_START122_MASK 0x000F /* WSEQ_DATA_START122 - [3:0] */
8530#define WM8995_WSEQ_DATA_START122_SHIFT 0 /* WSEQ_DATA_START122 - [3:0] */
8531#define WM8995_WSEQ_DATA_START122_WIDTH 4 /* WSEQ_DATA_START122 - [3:0] */
8532
8533/*
8534 * R12779 (0x31EB) - Write Sequencer 491
8535 */
8536#define WM8995_WSEQ_EOS122 0x0100 /* WSEQ_EOS122 */
8537#define WM8995_WSEQ_EOS122_MASK 0x0100 /* WSEQ_EOS122 */
8538#define WM8995_WSEQ_EOS122_SHIFT 8 /* WSEQ_EOS122 */
8539#define WM8995_WSEQ_EOS122_WIDTH 1 /* WSEQ_EOS122 */
8540#define WM8995_WSEQ_DELAY122_MASK 0x000F /* WSEQ_DELAY122 - [3:0] */
8541#define WM8995_WSEQ_DELAY122_SHIFT 0 /* WSEQ_DELAY122 - [3:0] */
8542#define WM8995_WSEQ_DELAY122_WIDTH 4 /* WSEQ_DELAY122 - [3:0] */
8543
8544/*
8545 * R12780 (0x31EC) - Write Sequencer 492
8546 */
8547#define WM8995_WSEQ_ADDR123_MASK 0x3FFF /* WSEQ_ADDR123 - [13:0] */
8548#define WM8995_WSEQ_ADDR123_SHIFT 0 /* WSEQ_ADDR123 - [13:0] */
8549#define WM8995_WSEQ_ADDR123_WIDTH 14 /* WSEQ_ADDR123 - [13:0] */
8550
8551/*
8552 * R12781 (0x31ED) - Write Sequencer 493
8553 */
8554#define WM8995_WSEQ_DATA123_MASK 0x00FF /* WSEQ_DATA123 - [7:0] */
8555#define WM8995_WSEQ_DATA123_SHIFT 0 /* WSEQ_DATA123 - [7:0] */
8556#define WM8995_WSEQ_DATA123_WIDTH 8 /* WSEQ_DATA123 - [7:0] */
8557
8558/*
8559 * R12782 (0x31EE) - Write Sequencer 494
8560 */
8561#define WM8995_WSEQ_DATA_WIDTH123_MASK 0x0700 /* WSEQ_DATA_WIDTH123 - [10:8] */
8562#define WM8995_WSEQ_DATA_WIDTH123_SHIFT 8 /* WSEQ_DATA_WIDTH123 - [10:8] */
8563#define WM8995_WSEQ_DATA_WIDTH123_WIDTH 3 /* WSEQ_DATA_WIDTH123 - [10:8] */
8564#define WM8995_WSEQ_DATA_START123_MASK 0x000F /* WSEQ_DATA_START123 - [3:0] */
8565#define WM8995_WSEQ_DATA_START123_SHIFT 0 /* WSEQ_DATA_START123 - [3:0] */
8566#define WM8995_WSEQ_DATA_START123_WIDTH 4 /* WSEQ_DATA_START123 - [3:0] */
8567
8568/*
8569 * R12783 (0x31EF) - Write Sequencer 495
8570 */
8571#define WM8995_WSEQ_EOS123 0x0100 /* WSEQ_EOS123 */
8572#define WM8995_WSEQ_EOS123_MASK 0x0100 /* WSEQ_EOS123 */
8573#define WM8995_WSEQ_EOS123_SHIFT 8 /* WSEQ_EOS123 */
8574#define WM8995_WSEQ_EOS123_WIDTH 1 /* WSEQ_EOS123 */
8575#define WM8995_WSEQ_DELAY123_MASK 0x000F /* WSEQ_DELAY123 - [3:0] */
8576#define WM8995_WSEQ_DELAY123_SHIFT 0 /* WSEQ_DELAY123 - [3:0] */
8577#define WM8995_WSEQ_DELAY123_WIDTH 4 /* WSEQ_DELAY123 - [3:0] */
8578
8579/*
8580 * R12784 (0x31F0) - Write Sequencer 496
8581 */
8582#define WM8995_WSEQ_ADDR124_MASK 0x3FFF /* WSEQ_ADDR124 - [13:0] */
8583#define WM8995_WSEQ_ADDR124_SHIFT 0 /* WSEQ_ADDR124 - [13:0] */
8584#define WM8995_WSEQ_ADDR124_WIDTH 14 /* WSEQ_ADDR124 - [13:0] */
8585
8586/*
8587 * R12785 (0x31F1) - Write Sequencer 497
8588 */
8589#define WM8995_WSEQ_DATA124_MASK 0x00FF /* WSEQ_DATA124 - [7:0] */
8590#define WM8995_WSEQ_DATA124_SHIFT 0 /* WSEQ_DATA124 - [7:0] */
8591#define WM8995_WSEQ_DATA124_WIDTH 8 /* WSEQ_DATA124 - [7:0] */
8592
8593/*
8594 * R12786 (0x31F2) - Write Sequencer 498
8595 */
8596#define WM8995_WSEQ_DATA_WIDTH124_MASK 0x0700 /* WSEQ_DATA_WIDTH124 - [10:8] */
8597#define WM8995_WSEQ_DATA_WIDTH124_SHIFT 8 /* WSEQ_DATA_WIDTH124 - [10:8] */
8598#define WM8995_WSEQ_DATA_WIDTH124_WIDTH 3 /* WSEQ_DATA_WIDTH124 - [10:8] */
8599#define WM8995_WSEQ_DATA_START124_MASK 0x000F /* WSEQ_DATA_START124 - [3:0] */
8600#define WM8995_WSEQ_DATA_START124_SHIFT 0 /* WSEQ_DATA_START124 - [3:0] */
8601#define WM8995_WSEQ_DATA_START124_WIDTH 4 /* WSEQ_DATA_START124 - [3:0] */
8602
8603/*
8604 * R12787 (0x31F3) - Write Sequencer 499
8605 */
8606#define WM8995_WSEQ_EOS124 0x0100 /* WSEQ_EOS124 */
8607#define WM8995_WSEQ_EOS124_MASK 0x0100 /* WSEQ_EOS124 */
8608#define WM8995_WSEQ_EOS124_SHIFT 8 /* WSEQ_EOS124 */
8609#define WM8995_WSEQ_EOS124_WIDTH 1 /* WSEQ_EOS124 */
8610#define WM8995_WSEQ_DELAY124_MASK 0x000F /* WSEQ_DELAY124 - [3:0] */
8611#define WM8995_WSEQ_DELAY124_SHIFT 0 /* WSEQ_DELAY124 - [3:0] */
8612#define WM8995_WSEQ_DELAY124_WIDTH 4 /* WSEQ_DELAY124 - [3:0] */
8613
8614/*
8615 * R12788 (0x31F4) - Write Sequencer 500
8616 */
8617#define WM8995_WSEQ_ADDR125_MASK 0x3FFF /* WSEQ_ADDR125 - [13:0] */
8618#define WM8995_WSEQ_ADDR125_SHIFT 0 /* WSEQ_ADDR125 - [13:0] */
8619#define WM8995_WSEQ_ADDR125_WIDTH 14 /* WSEQ_ADDR125 - [13:0] */
8620
8621/*
8622 * R12789 (0x31F5) - Write Sequencer 501
8623 */
8624#define WM8995_WSEQ_DATA125_MASK 0x00FF /* WSEQ_DATA125 - [7:0] */
8625#define WM8995_WSEQ_DATA125_SHIFT 0 /* WSEQ_DATA125 - [7:0] */
8626#define WM8995_WSEQ_DATA125_WIDTH 8 /* WSEQ_DATA125 - [7:0] */
8627
8628/*
8629 * R12790 (0x31F6) - Write Sequencer 502
8630 */
8631#define WM8995_WSEQ_DATA_WIDTH125_MASK 0x0700 /* WSEQ_DATA_WIDTH125 - [10:8] */
8632#define WM8995_WSEQ_DATA_WIDTH125_SHIFT 8 /* WSEQ_DATA_WIDTH125 - [10:8] */
8633#define WM8995_WSEQ_DATA_WIDTH125_WIDTH 3 /* WSEQ_DATA_WIDTH125 - [10:8] */
8634#define WM8995_WSEQ_DATA_START125_MASK 0x000F /* WSEQ_DATA_START125 - [3:0] */
8635#define WM8995_WSEQ_DATA_START125_SHIFT 0 /* WSEQ_DATA_START125 - [3:0] */
8636#define WM8995_WSEQ_DATA_START125_WIDTH 4 /* WSEQ_DATA_START125 - [3:0] */
8637
8638/*
8639 * R12791 (0x31F7) - Write Sequencer 503
8640 */
8641#define WM8995_WSEQ_EOS125 0x0100 /* WSEQ_EOS125 */
8642#define WM8995_WSEQ_EOS125_MASK 0x0100 /* WSEQ_EOS125 */
8643#define WM8995_WSEQ_EOS125_SHIFT 8 /* WSEQ_EOS125 */
8644#define WM8995_WSEQ_EOS125_WIDTH 1 /* WSEQ_EOS125 */
8645#define WM8995_WSEQ_DELAY125_MASK 0x000F /* WSEQ_DELAY125 - [3:0] */
8646#define WM8995_WSEQ_DELAY125_SHIFT 0 /* WSEQ_DELAY125 - [3:0] */
8647#define WM8995_WSEQ_DELAY125_WIDTH 4 /* WSEQ_DELAY125 - [3:0] */
8648
8649/*
8650 * R12792 (0x31F8) - Write Sequencer 504
8651 */
8652#define WM8995_WSEQ_ADDR126_MASK 0x3FFF /* WSEQ_ADDR126 - [13:0] */
8653#define WM8995_WSEQ_ADDR126_SHIFT 0 /* WSEQ_ADDR126 - [13:0] */
8654#define WM8995_WSEQ_ADDR126_WIDTH 14 /* WSEQ_ADDR126 - [13:0] */
8655
8656/*
8657 * R12793 (0x31F9) - Write Sequencer 505
8658 */
8659#define WM8995_WSEQ_DATA126_MASK 0x00FF /* WSEQ_DATA126 - [7:0] */
8660#define WM8995_WSEQ_DATA126_SHIFT 0 /* WSEQ_DATA126 - [7:0] */
8661#define WM8995_WSEQ_DATA126_WIDTH 8 /* WSEQ_DATA126 - [7:0] */
8662
8663/*
8664 * R12794 (0x31FA) - Write Sequencer 506
8665 */
8666#define WM8995_WSEQ_DATA_WIDTH126_MASK 0x0700 /* WSEQ_DATA_WIDTH126 - [10:8] */
8667#define WM8995_WSEQ_DATA_WIDTH126_SHIFT 8 /* WSEQ_DATA_WIDTH126 - [10:8] */
8668#define WM8995_WSEQ_DATA_WIDTH126_WIDTH 3 /* WSEQ_DATA_WIDTH126 - [10:8] */
8669#define WM8995_WSEQ_DATA_START126_MASK 0x000F /* WSEQ_DATA_START126 - [3:0] */
8670#define WM8995_WSEQ_DATA_START126_SHIFT 0 /* WSEQ_DATA_START126 - [3:0] */
8671#define WM8995_WSEQ_DATA_START126_WIDTH 4 /* WSEQ_DATA_START126 - [3:0] */
8672
8673/*
8674 * R12795 (0x31FB) - Write Sequencer 507
8675 */
8676#define WM8995_WSEQ_EOS126 0x0100 /* WSEQ_EOS126 */
8677#define WM8995_WSEQ_EOS126_MASK 0x0100 /* WSEQ_EOS126 */
8678#define WM8995_WSEQ_EOS126_SHIFT 8 /* WSEQ_EOS126 */
8679#define WM8995_WSEQ_EOS126_WIDTH 1 /* WSEQ_EOS126 */
8680#define WM8995_WSEQ_DELAY126_MASK 0x000F /* WSEQ_DELAY126 - [3:0] */
8681#define WM8995_WSEQ_DELAY126_SHIFT 0 /* WSEQ_DELAY126 - [3:0] */
8682#define WM8995_WSEQ_DELAY126_WIDTH 4 /* WSEQ_DELAY126 - [3:0] */
8683
8684/*
8685 * R12796 (0x31FC) - Write Sequencer 508
8686 */
8687#define WM8995_WSEQ_ADDR127_MASK 0x3FFF /* WSEQ_ADDR127 - [13:0] */
8688#define WM8995_WSEQ_ADDR127_SHIFT 0 /* WSEQ_ADDR127 - [13:0] */
8689#define WM8995_WSEQ_ADDR127_WIDTH 14 /* WSEQ_ADDR127 - [13:0] */
8690
8691/*
8692 * R12797 (0x31FD) - Write Sequencer 509
8693 */
8694#define WM8995_WSEQ_DATA127_MASK 0x00FF /* WSEQ_DATA127 - [7:0] */
8695#define WM8995_WSEQ_DATA127_SHIFT 0 /* WSEQ_DATA127 - [7:0] */
8696#define WM8995_WSEQ_DATA127_WIDTH 8 /* WSEQ_DATA127 - [7:0] */
8697
8698/*
8699 * R12798 (0x31FE) - Write Sequencer 510
8700 */
8701#define WM8995_WSEQ_DATA_WIDTH127_MASK 0x0700 /* WSEQ_DATA_WIDTH127 - [10:8] */
8702#define WM8995_WSEQ_DATA_WIDTH127_SHIFT 8 /* WSEQ_DATA_WIDTH127 - [10:8] */
8703#define WM8995_WSEQ_DATA_WIDTH127_WIDTH 3 /* WSEQ_DATA_WIDTH127 - [10:8] */
8704#define WM8995_WSEQ_DATA_START127_MASK 0x000F /* WSEQ_DATA_START127 - [3:0] */
8705#define WM8995_WSEQ_DATA_START127_SHIFT 0 /* WSEQ_DATA_START127 - [3:0] */
8706#define WM8995_WSEQ_DATA_START127_WIDTH 4 /* WSEQ_DATA_START127 - [3:0] */
8707
8708/*
8709 * R12799 (0x31FF) - Write Sequencer 511
8710 */
8711#define WM8995_WSEQ_EOS127 0x0100 /* WSEQ_EOS127 */
8712#define WM8995_WSEQ_EOS127_MASK 0x0100 /* WSEQ_EOS127 */
8713#define WM8995_WSEQ_EOS127_SHIFT 8 /* WSEQ_EOS127 */
8714#define WM8995_WSEQ_EOS127_WIDTH 1 /* WSEQ_EOS127 */
8715#define WM8995_WSEQ_DELAY127_MASK 0x000F /* WSEQ_DELAY127 - [3:0] */
8716#define WM8995_WSEQ_DELAY127_SHIFT 0 /* WSEQ_DELAY127 - [3:0] */
8717#define WM8995_WSEQ_DELAY127_WIDTH 4 /* WSEQ_DELAY127 - [3:0] */
8718
8719#define WM8995_CLASS_W_SWITCH(xname, reg, shift, max, invert) \ 4239#define WM8995_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
8720{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 4240{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
8721 .info = snd_soc_info_volsw, \ 4241 .info = snd_soc_info_volsw, \