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authorIvo van Doorn <ivdoorn@gmail.com>2008-02-17 11:33:24 -0500
committerJohn W. Linville <linville@tuxdriver.com>2008-02-29 15:37:22 -0500
commit30b3a23c2594e122e7086f97b5252a87eaf8a817 (patch)
tree6c97b928fce785471236543fe71bce3b6d0324cb
parente542239f639fa4e7b13a949d39d44ff1eccf7e3a (diff)
rt2x00: Fix Descriptor DMA initialization
As Adam Baker reported the DMA address for the descriptor base was incorrectly initialized in the PCI drivers. Instead of the DMA base for the descriptor, the DMA base for the data was passed resulting in a broken TX/RX state for PCI drivers. Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r--drivers/net/wireless/rt2x00/rt2400pci.c21
-rw-r--r--drivers/net/wireless/rt2x00/rt2500pci.c18
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00pci.c38
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00pci.h6
-rw-r--r--drivers/net/wireless/rt2x00/rt61pci.c21
5 files changed, 63 insertions, 41 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.c b/drivers/net/wireless/rt2x00/rt2400pci.c
index 52ccb85fed65..28663c00b770 100644
--- a/drivers/net/wireless/rt2x00/rt2400pci.c
+++ b/drivers/net/wireless/rt2x00/rt2400pci.c
@@ -597,11 +597,12 @@ static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
597 u32 word; 597 u32 word;
598 598
599 rt2x00_desc_read(priv_rx->desc, 2, &word); 599 rt2x00_desc_read(priv_rx->desc, 2, &word);
600 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->queue->data_size); 600 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
601 entry->queue->data_size);
601 rt2x00_desc_write(priv_rx->desc, 2, word); 602 rt2x00_desc_write(priv_rx->desc, 2, word);
602 603
603 rt2x00_desc_read(priv_rx->desc, 1, &word); 604 rt2x00_desc_read(priv_rx->desc, 1, &word);
604 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->dma); 605 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
605 rt2x00_desc_write(priv_rx->desc, 1, word); 606 rt2x00_desc_write(priv_rx->desc, 1, word);
606 607
607 rt2x00_desc_read(priv_rx->desc, 0, &word); 608 rt2x00_desc_read(priv_rx->desc, 0, &word);
@@ -616,7 +617,7 @@ static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
616 u32 word; 617 u32 word;
617 618
618 rt2x00_desc_read(priv_tx->desc, 1, &word); 619 rt2x00_desc_read(priv_tx->desc, 1, &word);
619 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->dma); 620 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
620 rt2x00_desc_write(priv_tx->desc, 1, word); 621 rt2x00_desc_write(priv_tx->desc, 1, word);
621 622
622 rt2x00_desc_read(priv_tx->desc, 2, &word); 623 rt2x00_desc_read(priv_tx->desc, 2, &word);
@@ -648,22 +649,26 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
648 649
649 priv_tx = rt2x00dev->tx[1].entries[0].priv_data; 650 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
650 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg); 651 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
651 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER, priv_tx->dma); 652 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
653 priv_tx->desc_dma);
652 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg); 654 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
653 655
654 priv_tx = rt2x00dev->tx[0].entries[0].priv_data; 656 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
655 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg); 657 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
656 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER, priv_tx->dma); 658 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
659 priv_tx->desc_dma);
657 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); 660 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
658 661
659 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data; 662 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
660 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg); 663 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
661 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER, priv_tx->dma); 664 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
665 priv_tx->desc_dma);
662 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); 666 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
663 667
664 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data; 668 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
665 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg); 669 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
666 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER, priv_tx->dma); 670 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
671 priv_tx->desc_dma);
667 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg); 672 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
668 673
669 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg); 674 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
@@ -673,7 +678,7 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
673 678
674 priv_rx = rt2x00dev->rx->entries[0].priv_data; 679 priv_rx = rt2x00dev->rx->entries[0].priv_data;
675 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg); 680 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
676 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_tx->dma); 681 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_tx->desc_dma);
677 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg); 682 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
678 683
679 return 0; 684 return 0;
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.c b/drivers/net/wireless/rt2x00/rt2500pci.c
index 3bf85604ca69..ec7300e4fc56 100644
--- a/drivers/net/wireless/rt2x00/rt2500pci.c
+++ b/drivers/net/wireless/rt2x00/rt2500pci.c
@@ -691,7 +691,7 @@ static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
691 u32 word; 691 u32 word;
692 692
693 rt2x00_desc_read(priv_rx->desc, 1, &word); 693 rt2x00_desc_read(priv_rx->desc, 1, &word);
694 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->dma); 694 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
695 rt2x00_desc_write(priv_rx->desc, 1, word); 695 rt2x00_desc_write(priv_rx->desc, 1, word);
696 696
697 rt2x00_desc_read(priv_rx->desc, 0, &word); 697 rt2x00_desc_read(priv_rx->desc, 0, &word);
@@ -706,7 +706,7 @@ static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
706 u32 word; 706 u32 word;
707 707
708 rt2x00_desc_read(priv_tx->desc, 1, &word); 708 rt2x00_desc_read(priv_tx->desc, 1, &word);
709 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->dma); 709 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
710 rt2x00_desc_write(priv_tx->desc, 1, word); 710 rt2x00_desc_write(priv_tx->desc, 1, word);
711 711
712 rt2x00_desc_read(priv_tx->desc, 0, &word); 712 rt2x00_desc_read(priv_tx->desc, 0, &word);
@@ -733,22 +733,26 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
733 733
734 priv_tx = rt2x00dev->tx[1].entries[0].priv_data; 734 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
735 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg); 735 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
736 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER, priv_tx->dma); 736 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
737 priv_tx->desc_dma);
737 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg); 738 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
738 739
739 priv_tx = rt2x00dev->tx[0].entries[0].priv_data; 740 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
740 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg); 741 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
741 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER, priv_tx->dma); 742 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
743 priv_tx->desc_dma);
742 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); 744 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
743 745
744 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data; 746 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
745 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg); 747 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
746 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER, priv_tx->dma); 748 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
749 priv_tx->desc_dma);
747 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); 750 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
748 751
749 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data; 752 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
750 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg); 753 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
751 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER, priv_tx->dma); 754 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
755 priv_tx->desc_dma);
752 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg); 756 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
753 757
754 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg); 758 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
@@ -758,7 +762,7 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
758 762
759 priv_rx = rt2x00dev->rx->entries[0].priv_data; 763 priv_rx = rt2x00dev->rx->entries[0].priv_data;
760 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg); 764 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
761 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_tx->dma); 765 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_tx->desc_dma);
762 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg); 766 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
763 767
764 return 0; 768 return 0;
diff --git a/drivers/net/wireless/rt2x00/rt2x00pci.c b/drivers/net/wireless/rt2x00/rt2x00pci.c
index 7d2f406937cd..1960d938d73b 100644
--- a/drivers/net/wireless/rt2x00/rt2x00pci.c
+++ b/drivers/net/wireless/rt2x00/rt2x00pci.c
@@ -218,40 +218,44 @@ static int rt2x00pci_alloc_queue_dma(struct rt2x00_dev *rt2x00dev,
218 struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev); 218 struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
219 struct queue_entry_priv_pci_rx *priv_rx; 219 struct queue_entry_priv_pci_rx *priv_rx;
220 struct queue_entry_priv_pci_tx *priv_tx; 220 struct queue_entry_priv_pci_tx *priv_tx;
221 void *desc; 221 void *addr;
222 dma_addr_t dma;
223 void *desc_addr;
224 dma_addr_t desc_dma;
222 void *data_addr; 225 void *data_addr;
223 void *data;
224 dma_addr_t data_dma; 226 dma_addr_t data_dma;
225 dma_addr_t dma;
226 unsigned int i; 227 unsigned int i;
227 228
228 /* 229 /*
229 * Allocate DMA memory for descriptor and buffer. 230 * Allocate DMA memory for descriptor and buffer.
230 */ 231 */
231 data_addr = pci_alloc_consistent(pci_dev, dma_size(queue), &data_dma); 232 addr = pci_alloc_consistent(pci_dev, dma_size(queue), &dma);
232 if (!data_addr) 233 if (!addr)
233 return -ENOMEM; 234 return -ENOMEM;
234 235
235 memset(data_addr, 0, dma_size(queue)); 236 memset(addr, 0, dma_size(queue));
236 237
237 /* 238 /*
238 * Initialize all queue entries to contain valid addresses. 239 * Initialize all queue entries to contain valid addresses.
239 */ 240 */
240 for (i = 0; i < queue->limit; i++) { 241 for (i = 0; i < queue->limit; i++) {
241 desc = desc_offset(queue, data_addr, i); 242 desc_addr = desc_offset(queue, addr, i);
242 data = data_offset(queue, data_addr, i); 243 desc_dma = desc_offset(queue, dma, i);
243 dma = data_offset(queue, data_dma, i); 244 data_addr = data_offset(queue, addr, i);
245 data_dma = data_offset(queue, dma, i);
244 246
245 if (queue->qid == QID_RX) { 247 if (queue->qid == QID_RX) {
246 priv_rx = queue->entries[i].priv_data; 248 priv_rx = queue->entries[i].priv_data;
247 priv_rx->desc = desc; 249 priv_rx->desc = desc_addr;
248 priv_rx->data = data; 250 priv_rx->desc_dma = desc_dma;
249 priv_rx->dma = dma; 251 priv_rx->data = data_addr;
252 priv_rx->data_dma = data_dma;
250 } else { 253 } else {
251 priv_tx = queue->entries[i].priv_data; 254 priv_tx = queue->entries[i].priv_data;
252 priv_tx->desc = desc; 255 priv_tx->desc = desc_addr;
253 priv_tx->data = data; 256 priv_tx->desc_dma = desc_dma;
254 priv_tx->dma = dma; 257 priv_tx->data = data_addr;
258 priv_tx->data_dma = data_dma;
255 } 259 }
256 } 260 }
257 261
@@ -270,13 +274,13 @@ static void rt2x00pci_free_queue_dma(struct rt2x00_dev *rt2x00dev,
270 if (queue->qid == QID_RX) { 274 if (queue->qid == QID_RX) {
271 priv_rx = queue->entries[0].priv_data; 275 priv_rx = queue->entries[0].priv_data;
272 data_addr = priv_rx->data; 276 data_addr = priv_rx->data;
273 data_dma = priv_rx->dma; 277 data_dma = priv_rx->data_dma;
274 278
275 priv_rx->data = NULL; 279 priv_rx->data = NULL;
276 } else { 280 } else {
277 priv_tx = queue->entries[0].priv_data; 281 priv_tx = queue->entries[0].priv_data;
278 data_addr = priv_tx->data; 282 data_addr = priv_tx->data;
279 data_dma = priv_tx->dma; 283 data_dma = priv_tx->data_dma;
280 284
281 priv_tx->data = NULL; 285 priv_tx->data = NULL;
282 } 286 }
diff --git a/drivers/net/wireless/rt2x00/rt2x00pci.h b/drivers/net/wireless/rt2x00/rt2x00pci.h
index 8932b31d2624..9d1cdb99431c 100644
--- a/drivers/net/wireless/rt2x00/rt2x00pci.h
+++ b/drivers/net/wireless/rt2x00/rt2x00pci.h
@@ -103,9 +103,10 @@ int rt2x00pci_write_tx_data(struct rt2x00_dev *rt2x00dev,
103 */ 103 */
104struct queue_entry_priv_pci_rx { 104struct queue_entry_priv_pci_rx {
105 __le32 *desc; 105 __le32 *desc;
106 dma_addr_t desc_dma;
106 107
107 void *data; 108 void *data;
108 dma_addr_t dma; 109 dma_addr_t data_dma;
109}; 110};
110 111
111/** 112/**
@@ -118,9 +119,10 @@ struct queue_entry_priv_pci_rx {
118 */ 119 */
119struct queue_entry_priv_pci_tx { 120struct queue_entry_priv_pci_tx {
120 __le32 *desc; 121 __le32 *desc;
122 dma_addr_t desc_dma;
121 123
122 void *data; 124 void *data;
123 dma_addr_t dma; 125 dma_addr_t data_dma;
124 126
125 struct ieee80211_tx_control control; 127 struct ieee80211_tx_control control;
126}; 128};
diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c
index 75f61f3c47b6..dcc694eb8b3b 100644
--- a/drivers/net/wireless/rt2x00/rt61pci.c
+++ b/drivers/net/wireless/rt2x00/rt61pci.c
@@ -975,7 +975,8 @@ static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
975 u32 word; 975 u32 word;
976 976
977 rt2x00_desc_read(priv_rx->desc, 5, &word); 977 rt2x00_desc_read(priv_rx->desc, 5, &word);
978 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS, priv_rx->dma); 978 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
979 priv_rx->data_dma);
979 rt2x00_desc_write(priv_rx->desc, 5, word); 980 rt2x00_desc_write(priv_rx->desc, 5, word);
980 981
981 rt2x00_desc_read(priv_rx->desc, 0, &word); 982 rt2x00_desc_read(priv_rx->desc, 0, &word);
@@ -999,7 +1000,8 @@ static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
999 rt2x00_desc_write(priv_tx->desc, 5, word); 1000 rt2x00_desc_write(priv_tx->desc, 5, word);
1000 1001
1001 rt2x00_desc_read(priv_tx->desc, 6, &word); 1002 rt2x00_desc_read(priv_tx->desc, 6, &word);
1002 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, priv_tx->dma); 1003 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1004 priv_tx->data_dma);
1003 rt2x00_desc_write(priv_tx->desc, 6, word); 1005 rt2x00_desc_write(priv_tx->desc, 6, word);
1004 1006
1005 rt2x00_desc_read(priv_tx->desc, 0, &word); 1007 rt2x00_desc_read(priv_tx->desc, 0, &word);
@@ -1035,22 +1037,26 @@ static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1035 1037
1036 priv_tx = rt2x00dev->tx[0].entries[0].priv_data; 1038 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
1037 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg); 1039 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1038 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER, priv_tx->dma); 1040 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1041 priv_tx->desc_dma);
1039 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg); 1042 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1040 1043
1041 priv_tx = rt2x00dev->tx[1].entries[0].priv_data; 1044 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
1042 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg); 1045 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1043 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER, priv_tx->dma); 1046 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1047 priv_tx->desc_dma);
1044 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg); 1048 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1045 1049
1046 priv_tx = rt2x00dev->tx[2].entries[0].priv_data; 1050 priv_tx = rt2x00dev->tx[2].entries[0].priv_data;
1047 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg); 1051 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1048 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER, priv_tx->dma); 1052 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1053 priv_tx->desc_dma);
1049 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg); 1054 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1050 1055
1051 priv_tx = rt2x00dev->tx[3].entries[0].priv_data; 1056 priv_tx = rt2x00dev->tx[3].entries[0].priv_data;
1052 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg); 1057 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1053 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER, priv_tx->dma); 1058 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1059 priv_tx->desc_dma);
1054 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg); 1060 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1055 1061
1056 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg); 1062 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
@@ -1062,7 +1068,8 @@ static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1062 1068
1063 priv_rx = rt2x00dev->rx->entries[0].priv_data; 1069 priv_rx = rt2x00dev->rx->entries[0].priv_data;
1064 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg); 1070 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1065 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER, priv_rx->dma); 1071 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1072 priv_rx->desc_dma);
1066 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg); 1073 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1067 1074
1068 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg); 1075 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);