diff options
| author | Krzysztof Hałasa <khc@pm.waw.pl> | 2009-11-14 13:44:44 -0500 |
|---|---|---|
| committer | Krzysztof Hałasa <khc@pm.waw.pl> | 2009-12-05 10:58:38 -0500 |
| commit | 28f85cd3f65808cde50bb0e395043f38c3efa1cb (patch) | |
| tree | c1b826bbd2b01bba8bcf3a57604a8e89c634991d | |
| parent | efec194f576eebca8b0b3ac6e96fea05ae4567c9 (diff) | |
IXP4xx: Rename indirect MMIO primitives from __ixp4xx_* to __indirect_*.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
| -rw-r--r-- | arch/arm/mach-ixp4xx/include/mach/io.h | 107 |
1 files changed, 50 insertions, 57 deletions
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h index eb9c7489a999..061a1f144a01 100644 --- a/arch/arm/mach-ixp4xx/include/mach/io.h +++ b/arch/arm/mach-ixp4xx/include/mach/io.h | |||
| @@ -55,8 +55,8 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); | |||
| 55 | * access registers. If something outside of PCI is ioremap'd, we | 55 | * access registers. If something outside of PCI is ioremap'd, we |
| 56 | * fallback to the default. | 56 | * fallback to the default. |
| 57 | */ | 57 | */ |
| 58 | static inline void __iomem * | 58 | static inline void __iomem * __indirect_ioremap(unsigned long addr, size_t size, |
| 59 | __ixp4xx_ioremap(unsigned long addr, size_t size, unsigned int mtype) | 59 | unsigned int mtype) |
| 60 | { | 60 | { |
| 61 | if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff)) | 61 | if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff)) |
| 62 | return __arm_ioremap(addr, size, mtype); | 62 | return __arm_ioremap(addr, size, mtype); |
| @@ -64,34 +64,32 @@ __ixp4xx_ioremap(unsigned long addr, size_t size, unsigned int mtype) | |||
| 64 | return (void __iomem *)addr; | 64 | return (void __iomem *)addr; |
| 65 | } | 65 | } |
| 66 | 66 | ||
| 67 | static inline void | 67 | static inline void __indirect_iounmap(void __iomem *addr) |
| 68 | __ixp4xx_iounmap(void __iomem *addr) | ||
| 69 | { | 68 | { |
| 70 | if ((__force u32)addr >= VMALLOC_START) | 69 | if ((__force u32)addr >= VMALLOC_START) |
| 71 | __iounmap(addr); | 70 | __iounmap(addr); |
| 72 | } | 71 | } |
| 73 | 72 | ||
| 74 | #define __arch_ioremap(a, s, f) __ixp4xx_ioremap(a, s, f) | 73 | #define __arch_ioremap(a, s, f) __indirect_ioremap(a, s, f) |
| 75 | #define __arch_iounmap(a) __ixp4xx_iounmap(a) | 74 | #define __arch_iounmap(a) __indirect_iounmap(a) |
| 76 | 75 | ||
| 77 | #define writeb(v, p) __ixp4xx_writeb(v, p) | 76 | #define writeb(v, p) __indirect_writeb(v, p) |
| 78 | #define writew(v, p) __ixp4xx_writew(v, p) | 77 | #define writew(v, p) __indirect_writew(v, p) |
| 79 | #define writel(v, p) __ixp4xx_writel(v, p) | 78 | #define writel(v, p) __indirect_writel(v, p) |
| 80 | 79 | ||
| 81 | #define writesb(p, v, l) __ixp4xx_writesb(p, v, l) | 80 | #define writesb(p, v, l) __indirect_writesb(p, v, l) |
| 82 | #define writesw(p, v, l) __ixp4xx_writesw(p, v, l) | 81 | #define writesw(p, v, l) __indirect_writesw(p, v, l) |
| 83 | #define writesl(p, v, l) __ixp4xx_writesl(p, v, l) | 82 | #define writesl(p, v, l) __indirect_writesl(p, v, l) |
| 84 | |||
| 85 | #define readb(p) __ixp4xx_readb(p) | ||
| 86 | #define readw(p) __ixp4xx_readw(p) | ||
| 87 | #define readl(p) __ixp4xx_readl(p) | ||
| 88 | |||
| 89 | #define readsb(p, v, l) __ixp4xx_readsb(p, v, l) | ||
| 90 | #define readsw(p, v, l) __ixp4xx_readsw(p, v, l) | ||
| 91 | #define readsl(p, v, l) __ixp4xx_readsl(p, v, l) | ||
| 92 | 83 | ||
| 93 | static inline void | 84 | #define readb(p) __indirect_readb(p) |
| 94 | __ixp4xx_writeb(u8 value, volatile void __iomem *p) | 85 | #define readw(p) __indirect_readw(p) |
| 86 | #define readl(p) __indirect_readl(p) | ||
| 87 | |||
| 88 | #define readsb(p, v, l) __indirect_readsb(p, v, l) | ||
| 89 | #define readsw(p, v, l) __indirect_readsw(p, v, l) | ||
| 90 | #define readsl(p, v, l) __indirect_readsl(p, v, l) | ||
| 91 | |||
| 92 | static inline void __indirect_writeb(u8 value, volatile void __iomem *p) | ||
| 95 | { | 93 | { |
| 96 | u32 addr = (u32)p; | 94 | u32 addr = (u32)p; |
| 97 | u32 n, byte_enables, data; | 95 | u32 n, byte_enables, data; |
| @@ -107,15 +105,14 @@ __ixp4xx_writeb(u8 value, volatile void __iomem *p) | |||
| 107 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); | 105 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); |
| 108 | } | 106 | } |
| 109 | 107 | ||
| 110 | static inline void | 108 | static inline void __indirect_writesb(volatile void __iomem *bus_addr, |
| 111 | __ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count) | 109 | const u8 *vaddr, int count) |
| 112 | { | 110 | { |
| 113 | while (count--) | 111 | while (count--) |
| 114 | writeb(*vaddr++, bus_addr); | 112 | writeb(*vaddr++, bus_addr); |
| 115 | } | 113 | } |
| 116 | 114 | ||
| 117 | static inline void | 115 | static inline void __indirect_writew(u16 value, volatile void __iomem *p) |
| 118 | __ixp4xx_writew(u16 value, volatile void __iomem *p) | ||
| 119 | { | 116 | { |
| 120 | u32 addr = (u32)p; | 117 | u32 addr = (u32)p; |
| 121 | u32 n, byte_enables, data; | 118 | u32 n, byte_enables, data; |
| @@ -131,15 +128,14 @@ __ixp4xx_writew(u16 value, volatile void __iomem *p) | |||
| 131 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); | 128 | ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); |
| 132 | } | 129 | } |
| 133 | 130 | ||
| 134 | static inline void | 131 | static inline void __indirect_writesw(volatile void __iomem *bus_addr, |
| 135 | __ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count) | 132 | const u16 *vaddr, int count) |
| 136 | { | 133 | { |
| 137 | while (count--) | 134 | while (count--) |
| 138 | writew(*vaddr++, bus_addr); | 135 | writew(*vaddr++, bus_addr); |
| 139 | } | 136 | } |
| 140 | 137 | ||
| 141 | static inline void | 138 | static inline void __indirect_writel(u32 value, volatile void __iomem *p) |
| 142 | __ixp4xx_writel(u32 value, volatile void __iomem *p) | ||
| 143 | { | 139 | { |
| 144 | u32 addr = (__force u32)p; | 140 | u32 addr = (__force u32)p; |
| 145 | if (addr >= VMALLOC_START) { | 141 | if (addr >= VMALLOC_START) { |
| @@ -150,15 +146,14 @@ __ixp4xx_writel(u32 value, volatile void __iomem *p) | |||
| 150 | ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value); | 146 | ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value); |
| 151 | } | 147 | } |
| 152 | 148 | ||
| 153 | static inline void | 149 | static inline void __indirect_writesl(volatile void __iomem *bus_addr, |
| 154 | __ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count) | 150 | const u32 *vaddr, int count) |
| 155 | { | 151 | { |
| 156 | while (count--) | 152 | while (count--) |
| 157 | writel(*vaddr++, bus_addr); | 153 | writel(*vaddr++, bus_addr); |
| 158 | } | 154 | } |
| 159 | 155 | ||
| 160 | static inline unsigned char | 156 | static inline unsigned char __indirect_readb(const volatile void __iomem *p) |
| 161 | __ixp4xx_readb(const volatile void __iomem *p) | ||
| 162 | { | 157 | { |
| 163 | u32 addr = (u32)p; | 158 | u32 addr = (u32)p; |
| 164 | u32 n, byte_enables, data; | 159 | u32 n, byte_enables, data; |
| @@ -174,15 +169,14 @@ __ixp4xx_readb(const volatile void __iomem *p) | |||
| 174 | return data >> (8*n); | 169 | return data >> (8*n); |
| 175 | } | 170 | } |
| 176 | 171 | ||
| 177 | static inline void | 172 | static inline void __indirect_readsb(const volatile void __iomem *bus_addr, |
| 178 | __ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count) | 173 | u8 *vaddr, u32 count) |
| 179 | { | 174 | { |
| 180 | while (count--) | 175 | while (count--) |
| 181 | *vaddr++ = readb(bus_addr); | 176 | *vaddr++ = readb(bus_addr); |
| 182 | } | 177 | } |
| 183 | 178 | ||
| 184 | static inline unsigned short | 179 | static inline unsigned short __indirect_readw(const volatile void __iomem *p) |
| 185 | __ixp4xx_readw(const volatile void __iomem *p) | ||
| 186 | { | 180 | { |
| 187 | u32 addr = (u32)p; | 181 | u32 addr = (u32)p; |
| 188 | u32 n, byte_enables, data; | 182 | u32 n, byte_enables, data; |
| @@ -198,15 +192,14 @@ __ixp4xx_readw(const volatile void __iomem *p) | |||
| 198 | return data>>(8*n); | 192 | return data>>(8*n); |
| 199 | } | 193 | } |
| 200 | 194 | ||
| 201 | static inline void | 195 | static inline void __indirect_readsw(const volatile void __iomem *bus_addr, |
| 202 | __ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count) | 196 | u16 *vaddr, u32 count) |
| 203 | { | 197 | { |
| 204 | while (count--) | 198 | while (count--) |
| 205 | *vaddr++ = readw(bus_addr); | 199 | *vaddr++ = readw(bus_addr); |
| 206 | } | 200 | } |
| 207 | 201 | ||
| 208 | static inline unsigned long | 202 | static inline unsigned long __indirect_readl(const volatile void __iomem *p) |
| 209 | __ixp4xx_readl(const volatile void __iomem *p) | ||
| 210 | { | 203 | { |
| 211 | u32 addr = (__force u32)p; | 204 | u32 addr = (__force u32)p; |
| 212 | u32 data; | 205 | u32 data; |
| @@ -220,8 +213,8 @@ __ixp4xx_readl(const volatile void __iomem *p) | |||
| 220 | return data; | 213 | return data; |
| 221 | } | 214 | } |
| 222 | 215 | ||
| 223 | static inline void | 216 | static inline void __indirect_readsl(const volatile void __iomem *bus_addr, |
| 224 | __ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count) | 217 | u32 *vaddr, u32 count) |
| 225 | { | 218 | { |
| 226 | while (count--) | 219 | while (count--) |
| 227 | *vaddr++ = readl(bus_addr); | 220 | *vaddr++ = readl(bus_addr); |
| @@ -235,7 +228,7 @@ __ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count) | |||
| 235 | #define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l)) | 228 | #define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l)) |
| 236 | #define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l)) | 229 | #define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l)) |
| 237 | 230 | ||
| 238 | #endif | 231 | #endif /* CONFIG_IXP4XX_INDIRECT_PCI */ |
| 239 | 232 | ||
| 240 | #ifndef CONFIG_PCI | 233 | #ifndef CONFIG_PCI |
| 241 | 234 | ||
| @@ -385,7 +378,7 @@ __ixp4xx_ioread8(const void __iomem *addr) | |||
| 385 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 378 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
| 386 | return (unsigned int)__raw_readb(port); | 379 | return (unsigned int)__raw_readb(port); |
| 387 | #else | 380 | #else |
| 388 | return (unsigned int)__ixp4xx_readb(addr); | 381 | return (unsigned int)__indirect_readb(addr); |
| 389 | #endif | 382 | #endif |
| 390 | } | 383 | } |
| 391 | 384 | ||
| @@ -399,7 +392,7 @@ __ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) | |||
| 399 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 392 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
| 400 | __raw_readsb(addr, vaddr, count); | 393 | __raw_readsb(addr, vaddr, count); |
| 401 | #else | 394 | #else |
| 402 | __ixp4xx_readsb(addr, vaddr, count); | 395 | __indirect_readsb(addr, vaddr, count); |
| 403 | #endif | 396 | #endif |
| 404 | } | 397 | } |
| 405 | 398 | ||
| @@ -413,7 +406,7 @@ __ixp4xx_ioread16(const void __iomem *addr) | |||
| 413 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 406 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
| 414 | return le16_to_cpu(__raw_readw((u32)port)); | 407 | return le16_to_cpu(__raw_readw((u32)port)); |
| 415 | #else | 408 | #else |
| 416 | return (unsigned int)__ixp4xx_readw(addr); | 409 | return (unsigned int)__indirect_readw(addr); |
| 417 | #endif | 410 | #endif |
| 418 | } | 411 | } |
| 419 | 412 | ||
| @@ -427,7 +420,7 @@ __ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count) | |||
| 427 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 420 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
| 428 | __raw_readsw(addr, vaddr, count); | 421 | __raw_readsw(addr, vaddr, count); |
| 429 | #else | 422 | #else |
| 430 | __ixp4xx_readsw(addr, vaddr, count); | 423 | __indirect_readsw(addr, vaddr, count); |
| 431 | #endif | 424 | #endif |
| 432 | } | 425 | } |
| 433 | 426 | ||
| @@ -441,7 +434,7 @@ __ixp4xx_ioread32(const void __iomem *addr) | |||
| 441 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 434 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
| 442 | return le32_to_cpu((__force __le32)__raw_readl(addr)); | 435 | return le32_to_cpu((__force __le32)__raw_readl(addr)); |
| 443 | #else | 436 | #else |
| 444 | return (unsigned int)__ixp4xx_readl(addr); | 437 | return (unsigned int)__indirect_readl(addr); |
| 445 | #endif | 438 | #endif |
| 446 | } | 439 | } |
| 447 | } | 440 | } |
| @@ -456,7 +449,7 @@ __ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count) | |||
| 456 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 449 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
| 457 | __raw_readsl(addr, vaddr, count); | 450 | __raw_readsl(addr, vaddr, count); |
| 458 | #else | 451 | #else |
| 459 | __ixp4xx_readsl(addr, vaddr, count); | 452 | __indirect_readsl(addr, vaddr, count); |
| 460 | #endif | 453 | #endif |
| 461 | } | 454 | } |
| 462 | 455 | ||
| @@ -470,7 +463,7 @@ __ixp4xx_iowrite8(u8 value, void __iomem *addr) | |||
| 470 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 463 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
| 471 | __raw_writeb(value, port); | 464 | __raw_writeb(value, port); |
| 472 | #else | 465 | #else |
| 473 | __ixp4xx_writeb(value, addr); | 466 | __indirect_writeb(value, addr); |
| 474 | #endif | 467 | #endif |
| 475 | } | 468 | } |
| 476 | 469 | ||
| @@ -484,7 +477,7 @@ __ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count) | |||
| 484 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 477 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
| 485 | __raw_writesb(addr, vaddr, count); | 478 | __raw_writesb(addr, vaddr, count); |
| 486 | #else | 479 | #else |
| 487 | __ixp4xx_writesb(addr, vaddr, count); | 480 | __indirect_writesb(addr, vaddr, count); |
| 488 | #endif | 481 | #endif |
| 489 | } | 482 | } |
| 490 | 483 | ||
| @@ -498,7 +491,7 @@ __ixp4xx_iowrite16(u16 value, void __iomem *addr) | |||
| 498 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 491 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
| 499 | __raw_writew(cpu_to_le16(value), addr); | 492 | __raw_writew(cpu_to_le16(value), addr); |
| 500 | #else | 493 | #else |
| 501 | __ixp4xx_writew(value, addr); | 494 | __indirect_writew(value, addr); |
| 502 | #endif | 495 | #endif |
| 503 | } | 496 | } |
| 504 | 497 | ||
| @@ -512,7 +505,7 @@ __ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count) | |||
| 512 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 505 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
| 513 | __raw_writesw(addr, vaddr, count); | 506 | __raw_writesw(addr, vaddr, count); |
| 514 | #else | 507 | #else |
| 515 | __ixp4xx_writesw(addr, vaddr, count); | 508 | __indirect_writesw(addr, vaddr, count); |
| 516 | #endif | 509 | #endif |
| 517 | } | 510 | } |
| 518 | 511 | ||
| @@ -526,7 +519,7 @@ __ixp4xx_iowrite32(u32 value, void __iomem *addr) | |||
| 526 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 519 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
| 527 | __raw_writel((u32 __force)cpu_to_le32(value), addr); | 520 | __raw_writel((u32 __force)cpu_to_le32(value), addr); |
| 528 | #else | 521 | #else |
| 529 | __ixp4xx_writel(value, addr); | 522 | __indirect_writel(value, addr); |
| 530 | #endif | 523 | #endif |
| 531 | } | 524 | } |
| 532 | 525 | ||
| @@ -540,7 +533,7 @@ __ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count) | |||
| 540 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 533 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
| 541 | __raw_writesl(addr, vaddr, count); | 534 | __raw_writesl(addr, vaddr, count); |
| 542 | #else | 535 | #else |
| 543 | __ixp4xx_writesl(addr, vaddr, count); | 536 | __indirect_writesl(addr, vaddr, count); |
| 544 | #endif | 537 | #endif |
| 545 | } | 538 | } |
| 546 | 539 | ||
