intel-iommu: set compatibility format interrupt

When extended interrupt mode (x2apic mode) is not supported in a
system, it must set compatibility format interrupt to bypass
interrupt remapping, otherwise compatibility format interrupts
will be blocked.

This will be used when interrupt remapping is enabled while x2apic
is not supported.

Signed-off-by: Weidong Han <weidong.han@intel.com>
Acked-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>

2 files changed, 17 insertions, 0 deletions

diff --git a/drivers/pci/intr_remapping.c b/drivers/pci/intr_remapping.c
index c26633d7e7da..ef25caade54b 100644
--- a/drivers/pci/intr_remapping.c
+++ b/drivers/pci/intr_remapping.c
@@ -415,12 +415,27 @@ static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
 
         /* Set interrupt-remapping table pointer */
         cmd = iommu->gcmd | DMA_GCMD_SIRTP;
+        iommu->gcmd |= DMA_GCMD_SIRTP;
         writel(cmd, iommu->reg + DMAR_GCMD_REG);
 
         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
                       readl, (sts & DMA_GSTS_IRTPS), sts);
         spin_unlock_irqrestore(&iommu->register_lock, flags);
 
+        if (mode == 0) {
+                spin_lock_irqsave(&iommu->register_lock, flags);
+
+                /* enable comaptiblity format interrupt pass through */
+                cmd = iommu->gcmd | DMA_GCMD_CFI;
+                iommu->gcmd |= DMA_GCMD_CFI;
+                writel(cmd, iommu->reg + DMAR_GCMD_REG);
+
+                IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
+                              readl, (sts & DMA_GSTS_CFIS), sts);
+
+                spin_unlock_irqrestore(&iommu->register_lock, flags);
+        }
+
         /*
          * global invalidation of interrupt entry cache before enabling
          * interrupt-remapping.
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index 3771cd1f876e..aa8c53171233 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -164,6 +164,7 @@ static inline void dmar_writeq(void __iomem *addr, u64 val)
 #define DMA_GCMD_QIE (((u32)1) << 26)
 #define DMA_GCMD_SIRTP (((u32)1) << 24)
 #define DMA_GCMD_IRE (((u32) 1) << 25)
+#define DMA_GCMD_CFI (((u32) 1) << 23)
 
 /* GSTS_REG */
 #define DMA_GSTS_TES (((u32)1) << 31)
@@ -174,6 +175,7 @@ static inline void dmar_writeq(void __iomem *addr, u64 val)
 #define DMA_GSTS_QIES (((u32)1) << 26)
 #define DMA_GSTS_IRTPS (((u32)1) << 24)
 #define DMA_GSTS_IRES (((u32)1) << 25)
+#define DMA_GSTS_CFIS (((u32)1) << 23)
 
 /* CCMD_REG */
 #define DMA_CCMD_ICC (((u64)1) << 63)