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authorCharulatha V <charu@ti.com>2011-02-17 12:53:10 -0500
committerTony Lindgren <tony@atomide.com>2011-02-17 12:53:10 -0500
commit0f616a4e17ea244f882056656964b792edde8364 (patch)
tree38f0c36ff7a04e76975fe11ac83b306729abfc57
parent7f904c78d65e5cff8d9e76567797a7a7fe2fd774 (diff)
OMAP3: hwmod data: Add McSPI
Update omap3 hwmod data file with McSPI info. Signed-off-by: Charulatha V <charu@ti.com> Signed-off-by: Govindraj.R <govindraj.raja@ti.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c280
1 files changed, 280 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 8d8181334f86..800eda4adb54 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -22,6 +22,7 @@
22#include <plat/i2c.h> 22#include <plat/i2c.h>
23#include <plat/gpio.h> 23#include <plat/gpio.h>
24#include <plat/smartreflex.h> 24#include <plat/smartreflex.h>
25#include <plat/mcspi.h>
25 26
26#include "omap_hwmod_common_data.h" 27#include "omap_hwmod_common_data.h"
27 28
@@ -55,6 +56,10 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod;
55static struct omap_hwmod omap3xxx_gpio6_hwmod; 56static struct omap_hwmod omap3xxx_gpio6_hwmod;
56static struct omap_hwmod omap34xx_sr1_hwmod; 57static struct omap_hwmod omap34xx_sr1_hwmod;
57static struct omap_hwmod omap34xx_sr2_hwmod; 58static struct omap_hwmod omap34xx_sr2_hwmod;
59static struct omap_hwmod omap34xx_mcspi1;
60static struct omap_hwmod omap34xx_mcspi2;
61static struct omap_hwmod omap34xx_mcspi3;
62static struct omap_hwmod omap34xx_mcspi4;
58 63
59static struct omap_hwmod omap3xxx_dma_system_hwmod; 64static struct omap_hwmod omap3xxx_dma_system_hwmod;
60 65
@@ -1356,6 +1361,275 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
1356 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), 1361 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1357}; 1362};
1358 1363
1364/* l4 core -> mcspi1 interface */
1365static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
1366 {
1367 .pa_start = 0x48098000,
1368 .pa_end = 0x480980ff,
1369 .flags = ADDR_TYPE_RT,
1370 },
1371};
1372
1373static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
1374 .master = &omap3xxx_l4_core_hwmod,
1375 .slave = &omap34xx_mcspi1,
1376 .clk = "mcspi1_ick",
1377 .addr = omap34xx_mcspi1_addr_space,
1378 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
1379 .user = OCP_USER_MPU | OCP_USER_SDMA,
1380};
1381
1382/* l4 core -> mcspi2 interface */
1383static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
1384 {
1385 .pa_start = 0x4809a000,
1386 .pa_end = 0x4809a0ff,
1387 .flags = ADDR_TYPE_RT,
1388 },
1389};
1390
1391static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
1392 .master = &omap3xxx_l4_core_hwmod,
1393 .slave = &omap34xx_mcspi2,
1394 .clk = "mcspi2_ick",
1395 .addr = omap34xx_mcspi2_addr_space,
1396 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
1397 .user = OCP_USER_MPU | OCP_USER_SDMA,
1398};
1399
1400/* l4 core -> mcspi3 interface */
1401static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
1402 {
1403 .pa_start = 0x480b8000,
1404 .pa_end = 0x480b80ff,
1405 .flags = ADDR_TYPE_RT,
1406 },
1407};
1408
1409static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
1410 .master = &omap3xxx_l4_core_hwmod,
1411 .slave = &omap34xx_mcspi3,
1412 .clk = "mcspi3_ick",
1413 .addr = omap34xx_mcspi3_addr_space,
1414 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
1415 .user = OCP_USER_MPU | OCP_USER_SDMA,
1416};
1417
1418/* l4 core -> mcspi4 interface */
1419static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
1420 {
1421 .pa_start = 0x480ba000,
1422 .pa_end = 0x480ba0ff,
1423 .flags = ADDR_TYPE_RT,
1424 },
1425};
1426
1427static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
1428 .master = &omap3xxx_l4_core_hwmod,
1429 .slave = &omap34xx_mcspi4,
1430 .clk = "mcspi4_ick",
1431 .addr = omap34xx_mcspi4_addr_space,
1432 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
1433 .user = OCP_USER_MPU | OCP_USER_SDMA,
1434};
1435
1436/*
1437 * 'mcspi' class
1438 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1439 * bus
1440 */
1441
1442static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1443 .rev_offs = 0x0000,
1444 .sysc_offs = 0x0010,
1445 .syss_offs = 0x0014,
1446 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1447 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1448 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1449 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1450 .sysc_fields = &omap_hwmod_sysc_type1,
1451};
1452
1453static struct omap_hwmod_class omap34xx_mcspi_class = {
1454 .name = "mcspi",
1455 .sysc = &omap34xx_mcspi_sysc,
1456 .rev = OMAP3_MCSPI_REV,
1457};
1458
1459/* mcspi1 */
1460static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
1461 { .name = "irq", .irq = 65 },
1462};
1463
1464static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
1465 { .name = "tx0", .dma_req = 35 },
1466 { .name = "rx0", .dma_req = 36 },
1467 { .name = "tx1", .dma_req = 37 },
1468 { .name = "rx1", .dma_req = 38 },
1469 { .name = "tx2", .dma_req = 39 },
1470 { .name = "rx2", .dma_req = 40 },
1471 { .name = "tx3", .dma_req = 41 },
1472 { .name = "rx3", .dma_req = 42 },
1473};
1474
1475static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
1476 &omap34xx_l4_core__mcspi1,
1477};
1478
1479static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1480 .num_chipselect = 4,
1481};
1482
1483static struct omap_hwmod omap34xx_mcspi1 = {
1484 .name = "mcspi1",
1485 .mpu_irqs = omap34xx_mcspi1_mpu_irqs,
1486 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
1487 .sdma_reqs = omap34xx_mcspi1_sdma_reqs,
1488 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
1489 .main_clk = "mcspi1_fck",
1490 .prcm = {
1491 .omap2 = {
1492 .module_offs = CORE_MOD,
1493 .prcm_reg_id = 1,
1494 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1495 .idlest_reg_id = 1,
1496 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1497 },
1498 },
1499 .slaves = omap34xx_mcspi1_slaves,
1500 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
1501 .class = &omap34xx_mcspi_class,
1502 .dev_attr = &omap_mcspi1_dev_attr,
1503 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1504};
1505
1506/* mcspi2 */
1507static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
1508 { .name = "irq", .irq = 66 },
1509};
1510
1511static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
1512 { .name = "tx0", .dma_req = 43 },
1513 { .name = "rx0", .dma_req = 44 },
1514 { .name = "tx1", .dma_req = 45 },
1515 { .name = "rx1", .dma_req = 46 },
1516};
1517
1518static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
1519 &omap34xx_l4_core__mcspi2,
1520};
1521
1522static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1523 .num_chipselect = 2,
1524};
1525
1526static struct omap_hwmod omap34xx_mcspi2 = {
1527 .name = "mcspi2",
1528 .mpu_irqs = omap34xx_mcspi2_mpu_irqs,
1529 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
1530 .sdma_reqs = omap34xx_mcspi2_sdma_reqs,
1531 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
1532 .main_clk = "mcspi2_fck",
1533 .prcm = {
1534 .omap2 = {
1535 .module_offs = CORE_MOD,
1536 .prcm_reg_id = 1,
1537 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1538 .idlest_reg_id = 1,
1539 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1540 },
1541 },
1542 .slaves = omap34xx_mcspi2_slaves,
1543 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
1544 .class = &omap34xx_mcspi_class,
1545 .dev_attr = &omap_mcspi2_dev_attr,
1546 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1547};
1548
1549/* mcspi3 */
1550static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1551 { .name = "irq", .irq = 91 }, /* 91 */
1552};
1553
1554static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1555 { .name = "tx0", .dma_req = 15 },
1556 { .name = "rx0", .dma_req = 16 },
1557 { .name = "tx1", .dma_req = 23 },
1558 { .name = "rx1", .dma_req = 24 },
1559};
1560
1561static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
1562 &omap34xx_l4_core__mcspi3,
1563};
1564
1565static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1566 .num_chipselect = 2,
1567};
1568
1569static struct omap_hwmod omap34xx_mcspi3 = {
1570 .name = "mcspi3",
1571 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
1572 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
1573 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
1574 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
1575 .main_clk = "mcspi3_fck",
1576 .prcm = {
1577 .omap2 = {
1578 .module_offs = CORE_MOD,
1579 .prcm_reg_id = 1,
1580 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1581 .idlest_reg_id = 1,
1582 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1583 },
1584 },
1585 .slaves = omap34xx_mcspi3_slaves,
1586 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
1587 .class = &omap34xx_mcspi_class,
1588 .dev_attr = &omap_mcspi3_dev_attr,
1589 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1590};
1591
1592/* SPI4 */
1593static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1594 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
1595};
1596
1597static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1598 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1599 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1600};
1601
1602static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
1603 &omap34xx_l4_core__mcspi4,
1604};
1605
1606static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1607 .num_chipselect = 1,
1608};
1609
1610static struct omap_hwmod omap34xx_mcspi4 = {
1611 .name = "mcspi4",
1612 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
1613 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
1614 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
1615 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
1616 .main_clk = "mcspi4_fck",
1617 .prcm = {
1618 .omap2 = {
1619 .module_offs = CORE_MOD,
1620 .prcm_reg_id = 1,
1621 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1622 .idlest_reg_id = 1,
1623 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1624 },
1625 },
1626 .slaves = omap34xx_mcspi4_slaves,
1627 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
1628 .class = &omap34xx_mcspi_class,
1629 .dev_attr = &omap_mcspi4_dev_attr,
1630 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1631};
1632
1359static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { 1633static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
1360 &omap3xxx_l3_main_hwmod, 1634 &omap3xxx_l3_main_hwmod,
1361 &omap3xxx_l4_core_hwmod, 1635 &omap3xxx_l4_core_hwmod,
@@ -1387,6 +1661,12 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
1387 1661
1388 /* dma_system class*/ 1662 /* dma_system class*/
1389 &omap3xxx_dma_system_hwmod, 1663 &omap3xxx_dma_system_hwmod,
1664
1665 /* mcspi class */
1666 &omap34xx_mcspi1,
1667 &omap34xx_mcspi2,
1668 &omap34xx_mcspi3,
1669 &omap34xx_mcspi4,
1390 NULL, 1670 NULL,
1391}; 1671};
1392 1672