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authorWim Van Sebroeck <wim@iguana.be>2009-04-14 16:20:07 -0400
committerWim Van Sebroeck <wim@iguana.be>2009-06-18 03:30:22 -0400
commit0a7e658226d66a259097db5f4734589604b303fd (patch)
treede4f4b967ed286cbb5eb3f2203d21941016f38c4
parent1d89b30cc9be41af87881682ec82e2c107849dbe (diff)
[WATCHDOG] iTCO_wdt: Cleanup code
Clean-up the iTCO_wdt code so that checkpatch.pl get's happy... Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
-rw-r--r--drivers/watchdog/iTCO_vendor_support.c6
-rw-r--r--drivers/watchdog/iTCO_wdt.c24
2 files changed, 15 insertions, 15 deletions
diff --git a/drivers/watchdog/iTCO_vendor_support.c b/drivers/watchdog/iTCO_vendor_support.c
index d3c0f6de5523..843ef626bc50 100644
--- a/drivers/watchdog/iTCO_vendor_support.c
+++ b/drivers/watchdog/iTCO_vendor_support.c
@@ -35,9 +35,9 @@
35#include "iTCO_vendor.h" 35#include "iTCO_vendor.h"
36 36
37/* iTCO defines */ 37/* iTCO defines */
38#define SMI_EN acpibase + 0x30 /* SMI Control and Enable Register */ 38#define SMI_EN (acpibase + 0x30) /* SMI Control and Enable Register */
39#define TCOBASE acpibase + 0x60 /* TCO base address */ 39#define TCOBASE (acpibase + 0x60) /* TCO base address */
40#define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */ 40#define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */
41 41
42/* List of vendor support modes */ 42/* List of vendor support modes */
43/* SuperMicro Pentium 3 Era 370SSE+-OEM1/P3TSSE */ 43/* SuperMicro Pentium 3 Era 370SSE+-OEM1/P3TSSE */
diff --git a/drivers/watchdog/iTCO_wdt.c b/drivers/watchdog/iTCO_wdt.c
index 648250b998c4..6284961eff5b 100644
--- a/drivers/watchdog/iTCO_wdt.c
+++ b/drivers/watchdog/iTCO_wdt.c
@@ -236,19 +236,19 @@ MODULE_DEVICE_TABLE(pci, iTCO_wdt_pci_tbl);
236 236
237/* Address definitions for the TCO */ 237/* Address definitions for the TCO */
238/* TCO base address */ 238/* TCO base address */
239#define TCOBASE iTCO_wdt_private.ACPIBASE + 0x60 239#define TCOBASE (iTCO_wdt_private.ACPIBASE + 0x60)
240/* SMI Control and Enable Register */ 240/* SMI Control and Enable Register */
241#define SMI_EN iTCO_wdt_private.ACPIBASE + 0x30 241#define SMI_EN (iTCO_wdt_private.ACPIBASE + 0x30)
242 242
243#define TCO_RLD TCOBASE + 0x00 /* TCO Timer Reload and Curr. Value */ 243#define TCO_RLD (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */
244#define TCOv1_TMR TCOBASE + 0x01 /* TCOv1 Timer Initial Value */ 244#define TCOv1_TMR (TCOBASE + 0x01) /* TCOv1 Timer Initial Value */
245#define TCO_DAT_IN TCOBASE + 0x02 /* TCO Data In Register */ 245#define TCO_DAT_IN (TCOBASE + 0x02) /* TCO Data In Register */
246#define TCO_DAT_OUT TCOBASE + 0x03 /* TCO Data Out Register */ 246#define TCO_DAT_OUT (TCOBASE + 0x03) /* TCO Data Out Register */
247#define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */ 247#define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */
248#define TCO2_STS TCOBASE + 0x06 /* TCO2 Status Register */ 248#define TCO2_STS (TCOBASE + 0x06) /* TCO2 Status Register */
249#define TCO1_CNT TCOBASE + 0x08 /* TCO1 Control Register */ 249#define TCO1_CNT (TCOBASE + 0x08) /* TCO1 Control Register */
250#define TCO2_CNT TCOBASE + 0x0a /* TCO2 Control Register */ 250#define TCO2_CNT (TCOBASE + 0x0a) /* TCO2 Control Register */
251#define TCOv2_TMR TCOBASE + 0x12 /* TCOv2 Timer Initial Value */ 251#define TCOv2_TMR (TCOBASE + 0x12) /* TCOv2 Timer Initial Value */
252 252
253/* internal variables */ 253/* internal variables */
254static unsigned long is_active; 254static unsigned long is_active;