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authorRalf Baechle <ralf@linux-mips.org>2005-02-04 10:51:26 -0500
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:30:25 -0400
commitd1e344e500cc693139a69d29122db18190916448 (patch)
tree8501c79592d6ca06ce58a0ec34375cdb0c1ade34
parent28ecca4786bd8af209ae65689faa6aeea80adba2 (diff)
Use hardware mechanism to deal with cache aliases in the 24K.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/mm/c-r4k.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index c08fa366b189..1466c497beab 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1011,9 +1011,17 @@ static void __init probe_pcache(void)
1011 * normally they'd suffer from aliases but magic in the hardware deals 1011 * normally they'd suffer from aliases but magic in the hardware deals
1012 * with that for us so we don't need to take care ourselves. 1012 * with that for us so we don't need to take care ourselves.
1013 */ 1013 */
1014 if (c->cputype != CPU_R10000 && c->cputype != CPU_R12000) 1014 switch (c->cputype) {
1015 if (c->dcache.waysize > PAGE_SIZE) 1015 if (c->dcache.waysize > PAGE_SIZE)
1016 c->dcache.flags |= MIPS_CACHE_ALIASES; 1016
1017 case CPU_R10000:
1018 case CPU_R12000:
1019 break;
1020 case CPU_24K:
1021 if (!(read_c0_config7() & (1 << 16)))
1022 default:
1023 c->dcache.flags |= MIPS_CACHE_ALIASES;
1024 }
1017 1025
1018 switch (c->cputype) { 1026 switch (c->cputype) {
1019 case CPU_20KC: 1027 case CPU_20KC: