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authorKrzysztof Helt <krzysztof.h1@wp.pl>2007-10-16 04:29:06 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-10-16 12:43:18 -0400
commit69816699fa019145dd163949d65a07093af73b67 (patch)
tree62f882257742edc6edda05349cf75789fb6fabe9
parent9fa7bc016a688630386378c205f9ee0f7b2cc834 (diff)
s3c2410fb: adds pixclock to s3c2410fb_display
This patch adds pixelclock field to the s3c2410fb_display structure and make use of it in the driver. The Bast machine defined 9 modes but pixclock and margin values are defined only for the 640x480 modes so I removed other modes. This patch also fixes wrong display type constant for the SMDK2440 board. Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Signed-off-by: Antonino Daplas <adaplas@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat
-rw-r--r--arch/arm/mach-s3c2410/mach-amlm5900.c1
-rw-r--r--arch/arm/mach-s3c2410/mach-bast.c112
-rw-r--r--arch/arm/mach-s3c2410/mach-h1940.c1
-rw-r--r--arch/arm/mach-s3c2410/mach-qt2410.c3
-rw-r--r--arch/arm/mach-s3c2440/mach-rx3715.c1
-rw-r--r--arch/arm/mach-s3c2440/mach-smdk2440.c3
-rw-r--r--drivers/video/s3c2410fb.c42
-rw-r--r--include/asm-arm/arch-s3c2410/fb.h1
8 files changed, 28 insertions, 136 deletions
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index c4754226874d..a86d68d22a72 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -174,6 +174,7 @@ static struct s3c2410fb_display __initdata amlm5900_lcd_info = {
174 174
175 .type = S3C2410_LCDCON1_STN4, 175 .type = S3C2410_LCDCON1_STN4,
176 176
177 .pixclock = 680000, /* HCLK = 100MHz */
177 .xres = 160, 178 .xres = 160,
178 .yres = 160, 179 .yres = 160,
179 .bpp = 4, 180 .bpp = 4,
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 61d5b2a2874c..103fc5724735 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -473,25 +473,7 @@ static struct s3c2410fb_display __initdata bast_lcd_info[] = {
473 .width = 640, 473 .width = 640,
474 .height = 480, 474 .height = 480,
475 475
476 .xres = 320, 476 .pixclock = 33333,
477 .yres = 240,
478 .left_margin = 40,
479 .right_margin = 20,
480 .hsync_len = 88,
481 .upper_margin = 30,
482 .lower_margin = 32,
483 .vsync_len = 3,
484
485 .bpp = 4,
486
487 .lcdcon1 = 0x00000176,
488 .lcdcon5 = 0x00014b02,
489 },
490 {
491 .type = S3C2410_LCDCON1_TFT,
492 .width = 640,
493 .height = 480,
494
495 .xres = 640, 477 .xres = 640,
496 .yres = 480, 478 .yres = 480,
497 .bpp = 4, 479 .bpp = 4,
@@ -510,42 +492,7 @@ static struct s3c2410fb_display __initdata bast_lcd_info[] = {
510 .width = 640, 492 .width = 640,
511 .height = 480, 493 .height = 480,
512 494
513 .xres = 800, 495 .pixclock = 33333,
514 .yres = 600,
515 .bpp = 4,
516 .left_margin = 40,
517 .right_margin = 20,
518 .hsync_len = 88,
519 .upper_margin = 30,
520 .lower_margin = 32,
521 .vsync_len = 3,
522
523 .lcdcon1 = 0x00000176,
524 .lcdcon5 = 0x00014b02,
525 },
526 {
527 .type = S3C2410_LCDCON1_TFT,
528 .width = 640,
529 .height = 480,
530
531 .xres = 320,
532 .yres = 240,
533 .bpp = 8,
534 .left_margin = 40,
535 .right_margin = 20,
536 .hsync_len = 88,
537 .upper_margin = 30,
538 .lower_margin = 32,
539 .vsync_len = 3,
540
541 .lcdcon1 = 0x00000176,
542 .lcdcon5 = 0x00014b02,
543 },
544 {
545 .type = S3C2410_LCDCON1_TFT,
546 .width = 640,
547 .height = 480,
548
549 .xres = 640, 496 .xres = 640,
550 .yres = 480, 497 .yres = 480,
551 .bpp = 8, 498 .bpp = 8,
@@ -564,42 +511,7 @@ static struct s3c2410fb_display __initdata bast_lcd_info[] = {
564 .width = 640, 511 .width = 640,
565 .height = 480, 512 .height = 480,
566 513
567 .xres = 800, 514 .pixclock = 33333,
568 .yres = 600,
569 .bpp = 8,
570 .left_margin = 40,
571 .right_margin = 20,
572 .hsync_len = 88,
573 .upper_margin = 30,
574 .lower_margin = 32,
575 .vsync_len = 3,
576
577 .lcdcon1 = 0x00000176,
578 .lcdcon5 = 0x00014b02,
579 },
580 {
581 .type = S3C2410_LCDCON1_TFT,
582 .width = 640,
583 .height = 480,
584
585 .xres = 320,
586 .yres = 240,
587 .bpp = 16,
588 .left_margin = 40,
589 .right_margin = 20,
590 .hsync_len = 88,
591 .upper_margin = 30,
592 .lower_margin = 32,
593 .vsync_len = 3,
594
595 .lcdcon1 = 0x00000176,
596 .lcdcon5 = 0x00014b02,
597 },
598 {
599 .type = S3C2410_LCDCON1_TFT,
600 .width = 640,
601 .height = 480,
602
603 .xres = 640, 515 .xres = 640,
604 .yres = 480, 516 .yres = 480,
605 .bpp = 16, 517 .bpp = 16,
@@ -613,24 +525,6 @@ static struct s3c2410fb_display __initdata bast_lcd_info[] = {
613 .lcdcon1 = 0x00000176, 525 .lcdcon1 = 0x00000176,
614 .lcdcon5 = 0x00014b02, 526 .lcdcon5 = 0x00014b02,
615 }, 527 },
616 {
617 .type = S3C2410_LCDCON1_TFT,
618 .width = 640,
619 .height = 480,
620
621 .xres = 800,
622 .yres = 600,
623 .bpp = 16,
624 .left_margin = 40,
625 .right_margin = 20,
626 .hsync_len = 88,
627 .upper_margin = 30,
628 .lower_margin = 32,
629 .vsync_len = 3,
630
631 .lcdcon1 = 0x00000176,
632 .lcdcon5 = 0x00014b02,
633 },
634}; 528};
635 529
636/* LCD/VGA controller */ 530/* LCD/VGA controller */
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 78dfc7d4270f..8a508428a9e5 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -145,6 +145,7 @@ static struct s3c2410fb_display h1940_lcd __initdata = {
145 .type = S3C2410_LCDCON1_TFT, 145 .type = S3C2410_LCDCON1_TFT,
146 .width = 240, 146 .width = 240,
147 .height = 320, 147 .height = 320,
148 .pixclock = 260000,
148 .xres = 240, 149 .xres = 240,
149 .yres = 320, 150 .yres = 320,
150 .bpp = 16, 151 .bpp = 16,
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index ac94d561b6c9..612f62469525 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -112,6 +112,7 @@ static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
112 .width = 640, 112 .width = 640,
113 .height = 480, 113 .height = 480,
114 114
115 .pixclock = 40000, /* HCLK/4 */
115 .xres = 640, 116 .xres = 640,
116 .yres = 480, 117 .yres = 480,
117 .bpp = 16, 118 .bpp = 16,
@@ -137,6 +138,7 @@ static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
137 .type = S3C2410_LCDCON1_TFT, 138 .type = S3C2410_LCDCON1_TFT,
138 .width = 480, 139 .width = 480,
139 .height = 640, 140 .height = 640,
141 .pixclock = 40000, /* HCLK/4 */
140 .xres = 480, 142 .xres = 480,
141 .yres = 640, 143 .yres = 640,
142 .bpp = 16, 144 .bpp = 16,
@@ -162,6 +164,7 @@ static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
162 .type = S3C2410_LCDCON1_TFT, 164 .type = S3C2410_LCDCON1_TFT,
163 .width = 240, 165 .width = 240,
164 .height = 320, 166 .height = 320,
167 .pixclock = 100000, /* HCLK/10 */
165 .xres = 240, 168 .xres = 240,
166 .yres = 320, 169 .yres = 320,
167 .bpp = 16, 170 .bpp = 16,
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index f26adeaf1e74..408337f8bebf 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -123,6 +123,7 @@ static struct s3c2410fb_display rx3715_lcdcfg __initdata = {
123 .width = 240, 123 .width = 240,
124 .height = 320, 124 .height = 320,
125 125
126 .pixclock = 260000,
126 .xres = 240, 127 .xres = 240,
127 .yres = 320, 128 .yres = 320,
128 .bpp = 16, 129 .bpp = 16,
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c
index 840a480c40de..561e39147e67 100644
--- a/arch/arm/mach-s3c2440/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
@@ -115,11 +115,12 @@ static struct s3c2410fb_display smdk2440_lcd_cfg __initdata = {
115 S3C2410_LCDCON5_PWREN | 115 S3C2410_LCDCON5_PWREN |
116 S3C2410_LCDCON5_HWSWP, 116 S3C2410_LCDCON5_HWSWP,
117 117
118 .type = S3C2410_LCDCON1_TFT16BPP, 118 .type = S3C2410_LCDCON1_TFT,
119 119
120 .width = 240, 120 .width = 240,
121 .height = 320, 121 .height = 320,
122 122
123 .pixclock = 166667, /* HCLK 60 MHz, divisor 10 */
123 .xres = 240, 124 .xres = 240,
124 .yres = 320, 125 .yres = 320,
125 .bpp = 16, 126 .bpp = 16,
diff --git a/drivers/video/s3c2410fb.c b/drivers/video/s3c2410fb.c
index 09d19633d3bc..fd05231f0c08 100644
--- a/drivers/video/s3c2410fb.c
+++ b/drivers/video/s3c2410fb.c
@@ -199,6 +199,7 @@ static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
199 var->width = display->width; 199 var->width = display->width;
200 200
201 /* copy lcd settings */ 201 /* copy lcd settings */
202 var->pixclock = display->pixclock;
202 var->left_margin = display->left_margin; 203 var->left_margin = display->left_margin;
203 var->right_margin = display->right_margin; 204 var->right_margin = display->right_margin;
204 var->upper_margin = display->upper_margin; 205 var->upper_margin = display->upper_margin;
@@ -297,10 +298,6 @@ static void s3c2410fb_calculate_stn_lcd_regs(const struct fb_info *info,
297 unsigned wdly = (var->left_margin >> 4) - 1; 298 unsigned wdly = (var->left_margin >> 4) - 1;
298 unsigned wlh = (var->hsync_len >> 4) - 1; 299 unsigned wlh = (var->hsync_len >> 4) - 1;
299 300
300 dprintk("%s: var->xres = %d\n", __FUNCTION__, var->xres);
301 dprintk("%s: var->yres = %d\n", __FUNCTION__, var->yres);
302 dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
303
304 if (type != S3C2410_LCDCON1_STN4) 301 if (type != S3C2410_LCDCON1_STN4)
305 hs >>= 1; 302 hs >>= 1;
306 303
@@ -359,10 +356,6 @@ static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info *info,
359 const struct s3c2410fb_info *fbi = info->par; 356 const struct s3c2410fb_info *fbi = info->par;
360 const struct fb_var_screeninfo *var = &info->var; 357 const struct fb_var_screeninfo *var = &info->var;
361 358
362 dprintk("%s: var->xres = %d\n", __FUNCTION__, var->xres);
363 dprintk("%s: var->yres = %d\n", __FUNCTION__, var->yres);
364 dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
365
366 regs->lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK; 359 regs->lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
367 360
368 switch (var->bits_per_pixel) { 361 switch (var->bits_per_pixel) {
@@ -427,28 +420,25 @@ static void s3c2410fb_activate_var(struct fb_info *info)
427 void __iomem *regs = fbi->io; 420 void __iomem *regs = fbi->io;
428 int type = fbi->regs.lcdcon1 & S3C2410_LCDCON1_TFT; 421 int type = fbi->regs.lcdcon1 & S3C2410_LCDCON1_TFT;
429 struct fb_var_screeninfo *var = &info->var; 422 struct fb_var_screeninfo *var = &info->var;
423 int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock) / 2;
430 424
431 if (var->pixclock > 0) { 425 dprintk("%s: var->xres = %d\n", __FUNCTION__, var->xres);
432 int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock); 426 dprintk("%s: var->yres = %d\n", __FUNCTION__, var->yres);
433 427 dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
434 if (type == S3C2410_LCDCON1_TFT) {
435 clkdiv = (clkdiv / 2) - 1;
436 if (clkdiv < 0)
437 clkdiv = 0;
438 } else {
439 clkdiv = (clkdiv / 2);
440 if (clkdiv < 2)
441 clkdiv = 2;
442 }
443
444 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_CLKVAL(0x3ff);
445 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_CLKVAL(clkdiv);
446 }
447 428
448 if (type == S3C2410_LCDCON1_TFT) 429 if (type == S3C2410_LCDCON1_TFT) {
449 s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs); 430 s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs);
450 else 431 --clkdiv;
432 if (clkdiv < 0)
433 clkdiv = 0;
434 } else {
451 s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs); 435 s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs);
436 if (clkdiv < 2)
437 clkdiv = 2;
438 }
439
440 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_CLKVAL(0x3ff);
441 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_CLKVAL(clkdiv);
452 442
453 /* write new registers */ 443 /* write new registers */
454 444
diff --git a/include/asm-arm/arch-s3c2410/fb.h b/include/asm-arm/arch-s3c2410/fb.h
index 6f022bd3b2c0..9abe67b04dc8 100644
--- a/include/asm-arm/arch-s3c2410/fb.h
+++ b/include/asm-arm/arch-s3c2410/fb.h
@@ -36,6 +36,7 @@ struct s3c2410fb_display {
36 unsigned short yres; 36 unsigned short yres;
37 unsigned short bpp; 37 unsigned short bpp;
38 38
39 unsigned pixclock; /* pixclock in picoseconds */
39 unsigned short left_margin; /* value in pixels (TFT) or HCLKs (STN) */ 40 unsigned short left_margin; /* value in pixels (TFT) or HCLKs (STN) */
40 unsigned short right_margin; /* value in pixels (TFT) or HCLKs (STN) */ 41 unsigned short right_margin; /* value in pixels (TFT) or HCLKs (STN) */
41 unsigned short hsync_len; /* value in pixels (TFT) or HCLKs (STN) */ 42 unsigned short hsync_len; /* value in pixels (TFT) or HCLKs (STN) */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 03:42:34 -0500