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authorPaul Mundt <lethal@linux-sh.org>2009-06-01 06:50:08 -0400
committerPaul Mundt <lethal@linux-sh.org>2009-06-01 06:50:08 -0400
commit0bf8513ed0df64b38edce63411d4b7b368464f47 (patch)
treec15d7bb734f4daaba2fa01df9a83e4b79ea65726
parent7863d3f7aeae05099a38693a0a7eb7bdc7b2ab05 (diff)
sh: Tidy up SH-4A boot_cpu_data.flags probing.
This tidies up the boot_cpu_data.flags probing on SH-4A. All of them have a few things in common, which we can blindly set, rather than having each subtype have to set the same flags. We can also make assumptions about cache ways and the validity of PTEA, so this also kills off CPU_HAS_PTEA as a config option. There was also a bug in the FPU probing, which is now tidied up. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r--arch/sh/Kconfig1
-rw-r--r--arch/sh/Kconfig.cpu3
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c61
3 files changed, 15 insertions, 50 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index c815975b8d75..e9392aa8c561 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -174,7 +174,6 @@ config CPU_SH4
174 bool 174 bool
175 select CPU_HAS_INTEVT 175 select CPU_HAS_INTEVT
176 select CPU_HAS_SR_RB 176 select CPU_HAS_SR_RB
177 select CPU_HAS_PTEA if !CPU_SH4A || CPU_SHX2
178 select CPU_HAS_FPU if !CPU_SH4AL_DSP 177 select CPU_HAS_FPU if !CPU_SH4AL_DSP
179 select SYS_SUPPORTS_TMU 178 select SYS_SUPPORTS_TMU
180 179
diff --git a/arch/sh/Kconfig.cpu b/arch/sh/Kconfig.cpu
index 9eb1712372d8..cd6e3ea598d5 100644
--- a/arch/sh/Kconfig.cpu
+++ b/arch/sh/Kconfig.cpu
@@ -96,9 +96,6 @@ config CPU_HAS_SR_RB
96 See <file:Documentation/sh/register-banks.txt> for further 96 See <file:Documentation/sh/register-banks.txt> for further
97 information on SR.RB and register banking in the kernel in general. 97 information on SR.RB and register banking in the kernel in general.
98 98
99config CPU_HAS_PTEA
100 bool
101
102config CPU_HAS_PTEAEX 99config CPU_HAS_PTEAEX
103 bool 100 bool
104 101
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 28a2f0db01db..6c78d0a9c857 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -60,12 +60,18 @@ int __init detect_cpu_and_cache_system(void)
60 if ((cvr & 0x10000000) == 0) 60 if ((cvr & 0x10000000) == 0)
61 boot_cpu_data.flags |= CPU_HAS_DSP; 61 boot_cpu_data.flags |= CPU_HAS_DSP;
62 62
63 boot_cpu_data.flags |= CPU_HAS_LLSC; 63 boot_cpu_data.flags |= CPU_HAS_LLSC | CPU_HAS_PERF_COUNTER;
64 boot_cpu_data.cut_major = pvr & 0x7f; 64 boot_cpu_data.cut_major = pvr & 0x7f;
65
66 boot_cpu_data.icache.ways = 4;
67 boot_cpu_data.dcache.ways = 4;
68 } else {
69 /* And some SH-4 defaults.. */
70 boot_cpu_data.flags |= CPU_HAS_PTEA;
65 } 71 }
66 72
67 /* FPU detection works for everyone */ 73 /* FPU detection works for everyone */
68 if ((cvr & 0x20000000) == 1) 74 if ((cvr & 0x20000000))
69 boot_cpu_data.flags |= CPU_HAS_FPU; 75 boot_cpu_data.flags |= CPU_HAS_FPU;
70 76
71 /* Mask off the upper chip ID */ 77 /* Mask off the upper chip ID */
@@ -78,25 +84,20 @@ int __init detect_cpu_and_cache_system(void)
78 switch (pvr) { 84 switch (pvr) {
79 case 0x205: 85 case 0x205:
80 boot_cpu_data.type = CPU_SH7750; 86 boot_cpu_data.type = CPU_SH7750;
81 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | 87 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG |
82 CPU_HAS_PERF_COUNTER; 88 CPU_HAS_PERF_COUNTER;
83 break; 89 break;
84 case 0x206: 90 case 0x206:
85 boot_cpu_data.type = CPU_SH7750S; 91 boot_cpu_data.type = CPU_SH7750S;
86 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | 92 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG |
87 CPU_HAS_PERF_COUNTER; 93 CPU_HAS_PERF_COUNTER;
88 break; 94 break;
89 case 0x1100: 95 case 0x1100:
90 boot_cpu_data.type = CPU_SH7751; 96 boot_cpu_data.type = CPU_SH7751;
91 boot_cpu_data.flags |= CPU_HAS_FPU;
92 break; 97 break;
93 case 0x2001: 98 case 0x2001:
94 case 0x2004: 99 case 0x2004:
95 boot_cpu_data.type = CPU_SH7770; 100 boot_cpu_data.type = CPU_SH7770;
96 boot_cpu_data.icache.ways = 4;
97 boot_cpu_data.dcache.ways = 4;
98
99 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
100 break; 101 break;
101 case 0x2006: 102 case 0x2006:
102 case 0x200A: 103 case 0x200A:
@@ -107,45 +108,26 @@ int __init detect_cpu_and_cache_system(void)
107 else 108 else
108 boot_cpu_data.type = CPU_SH7780; 109 boot_cpu_data.type = CPU_SH7780;
109 110
110 boot_cpu_data.icache.ways = 4;
111 boot_cpu_data.dcache.ways = 4;
112
113 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
114 CPU_HAS_LLSC;
115 break; 111 break;
116 case 0x3000: 112 case 0x3000:
117 case 0x3003: 113 case 0x3003:
118 case 0x3009: 114 case 0x3009:
119 boot_cpu_data.type = CPU_SH7343; 115 boot_cpu_data.type = CPU_SH7343;
120 boot_cpu_data.icache.ways = 4;
121 boot_cpu_data.dcache.ways = 4;
122 boot_cpu_data.flags |= CPU_HAS_LLSC;
123 break; 116 break;
124 case 0x3004: 117 case 0x3004:
125 case 0x3007: 118 case 0x3007:
126 boot_cpu_data.type = CPU_SH7785; 119 boot_cpu_data.type = CPU_SH7785;
127 boot_cpu_data.icache.ways = 4;
128 boot_cpu_data.dcache.ways = 4;
129 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
130 CPU_HAS_LLSC;
131 break; 120 break;
132 case 0x4004: 121 case 0x4004:
133 boot_cpu_data.type = CPU_SH7786; 122 boot_cpu_data.type = CPU_SH7786;
134 boot_cpu_data.icache.ways = 4; 123 boot_cpu_data.flags |= CPU_HAS_PTEAEX | CPU_HAS_L2_CACHE;
135 boot_cpu_data.dcache.ways = 4;
136 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
137 CPU_HAS_LLSC | CPU_HAS_PTEAEX | CPU_HAS_L2_CACHE;
138 break; 124 break;
139 case 0x3008: 125 case 0x3008:
140 boot_cpu_data.icache.ways = 4;
141 boot_cpu_data.dcache.ways = 4;
142 boot_cpu_data.flags |= CPU_HAS_LLSC;
143
144 switch (prr) { 126 switch (prr) {
145 case 0x50: 127 case 0x50:
146 case 0x51: 128 case 0x51:
147 boot_cpu_data.type = CPU_SH7723; 129 boot_cpu_data.type = CPU_SH7723;
148 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_L2_CACHE; 130 boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
149 break; 131 break;
150 case 0x70: 132 case 0x70:
151 boot_cpu_data.type = CPU_SH7366; 133 boot_cpu_data.type = CPU_SH7366;
@@ -158,17 +140,11 @@ int __init detect_cpu_and_cache_system(void)
158 break; 140 break;
159 case 0x300b: 141 case 0x300b:
160 boot_cpu_data.type = CPU_SH7724; 142 boot_cpu_data.type = CPU_SH7724;
161 boot_cpu_data.icache.ways = 4; 143 boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
162 boot_cpu_data.dcache.ways = 4;
163 boot_cpu_data.flags |= CPU_HAS_LLSC | CPU_HAS_FPU | CPU_HAS_L2_CACHE;
164 break; 144 break;
165 case 0x4000: /* 1st cut */ 145 case 0x4000: /* 1st cut */
166 case 0x4001: /* 2nd cut */ 146 case 0x4001: /* 2nd cut */
167 boot_cpu_data.type = CPU_SHX3; 147 boot_cpu_data.type = CPU_SHX3;
168 boot_cpu_data.icache.ways = 4;
169 boot_cpu_data.dcache.ways = 4;
170 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
171 CPU_HAS_LLSC;
172 break; 148 break;
173 case 0x700: 149 case 0x700:
174 boot_cpu_data.type = CPU_SH4_501; 150 boot_cpu_data.type = CPU_SH4_501;
@@ -179,7 +155,6 @@ int __init detect_cpu_and_cache_system(void)
179 boot_cpu_data.type = CPU_SH4_202; 155 boot_cpu_data.type = CPU_SH4_202;
180 boot_cpu_data.icache.ways = 2; 156 boot_cpu_data.icache.ways = 2;
181 boot_cpu_data.dcache.ways = 2; 157 boot_cpu_data.dcache.ways = 2;
182 boot_cpu_data.flags |= CPU_HAS_FPU;
183 break; 158 break;
184 case 0x500 ... 0x501: 159 case 0x500 ... 0x501:
185 switch (prr) { 160 switch (prr) {
@@ -197,18 +172,12 @@ int __init detect_cpu_and_cache_system(void)
197 boot_cpu_data.icache.ways = 2; 172 boot_cpu_data.icache.ways = 2;
198 boot_cpu_data.dcache.ways = 2; 173 boot_cpu_data.dcache.ways = 2;
199 174
200 boot_cpu_data.flags |= CPU_HAS_FPU;
201
202 break; 175 break;
203 default: 176 default:
204 boot_cpu_data.type = CPU_SH_NONE; 177 boot_cpu_data.type = CPU_SH_NONE;
205 break; 178 break;
206 } 179 }
207 180
208#ifdef CONFIG_CPU_HAS_PTEA
209 boot_cpu_data.flags |= CPU_HAS_PTEA;
210#endif
211
212 /* 181 /*
213 * On anything that's not a direct-mapped cache, look to the CVR 182 * On anything that's not a direct-mapped cache, look to the CVR
214 * for I/D-cache specifics. 183 * for I/D-cache specifics.