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#ifndef _ASM_X86_SIGNAL_H
#define _ASM_X86_SIGNAL_H

#ifndef __ASSEMBLY__
#include <linux/types.h>
#include <linux/time.h>
#include <linux/compiler.h>

/* Avoid too many header ordering problems.  */
struct siginfo;

#ifdef __KERNEL__
#include <linux/linkage.h>

/* Most things should be clean enough to redefine this at will, if care
   is taken to make libc match.  */

#define _NSIG		64

#ifdef __i386__
# define _NSIG_BPW	32
#else
# define _NSIG_BPW	64
#endif

#define _NSIG_WORDS	(_NSIG / _NSIG_BPW)

typedef unsigned long old_sigset_t;		/* at least 32 bits */

typedef struct {
	unsigned long sig[_NSIG_WORDS];
} sigset_t;

#else
/* Here we must cater to libcs that poke about in kernel headers.  */

#define NSIG		32
typedef unsigned long sigset_t;

#endif /* __KERNEL__ */
#endif /* __ASSEMBLY__ */

#define SIGHUP		 1
#define SIGINT		 2
#define SIGQUIT		 3
#define SIGILL		 4
#define SIGTRAP		 5
#define SIGABRT		 6
#define SIGIOT		 6
#define SIGBUS		 7
#define SIGFPE		 8
#define SIGKILL		 9
#define SIGUSR1		10
#define SIGSEGV		11
#define SIGUSR2		12
#define SIGPIPE		13
#define SIGALRM		14
#define SIGTERM		15
#define SIGSTKFLT	16
#define SIGCHLD		17
#define SIGCONT		18
#define SIGSTOP		19
#define SIGTSTP		20
#define SIGTTIN		21
#define SIGTTOU		22
#define SIGURG		23
#define SIGXCPU		24
#define SIGXFSZ		25
#define SIGVTALRM	26
#define SIGPROF		27
#define SIGWINCH	28
#define SIGIO		29
#define SIGPOLL		SIGIO
/*
#define SIGLOST		29
*/
#define SIGPWR		30
#define SIGSYS		31
#define	SIGUNUSED	31

/* These should not be considered constants from userland.  */
#define SIGRTMIN	32
#define SIGRTMAX	_NSIG

/*
 * SA_FLAGS values:
 *
 * SA_ONSTACK indicates that a registered stack_t will be used.
 * SA_RESTART flag to get restarting signals (which were the default long ago)
 * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
 * SA_RESETHAND clears the handler when the signal is delivered.
 * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
 * SA_NODEFER prevents the current signal from being masked in the handler.
 *
 * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
 * Unix names RESETHAND and NODEFER respectively.
 */
#define SA_NOCLDSTOP	0x00000001u
#define SA_NOCLDWAIT	0x00000002u
#define SA_SIGINFO	0x00000004u
#define SA_ONSTACK	0x08000000u
#define SA_RESTART	0x10000000u
#define SA_NODEFER	0x40000000u
#define SA_RESETHAND	0x80000000u

#define SA_NOMASK	SA_NODEFER
#define SA_ONESHOT	SA_RESETHAND

#define SA_RESTORER	0x04000000

/*
 * sigaltstack controls
 */
#define SS_ONSTACK	1
#define SS_DISABLE	2

#define MINSIGSTKSZ	2048
#define SIGSTKSZ	8192

#include <asm-generic/signal.h>

#ifndef __ASSEMBLY__

#ifdef __i386__
# ifdef __KERNEL__
struct old_sigaction {
	__sighandler_t sa_handler;
	old_sigset_t sa_mask;
	unsigned long sa_flags;
	__sigrestore_t sa_restorer;
};

struct sigaction {
	__sighandler_t sa_handler;
	unsigned long sa_flags;
	__sigrestore_t sa_restorer;
	sigset_t sa_mask;		/* mask last for extensibility */
};

struct k_sigaction {
	struct sigaction sa;
};
# else /* __KERNEL__ */
/* Here we must cater to libcs that poke about in kernel headers.  */

struct sigaction {
	union {
	  __sighandler_t _sa_handler;
	  void (*_sa_sigaction)(int, struct siginfo *, void *);
	} _u;
	sigset_t sa_mask;
	unsigned long sa_flags;
	void (*sa_restorer)(void);
};

#define sa_handler	_u._sa_handler
#define sa_sigaction	_u._sa_sigaction

# endif /* ! __KERNEL__ */
#else /* __i386__ */

struct sigaction {
	__sighandler_t sa_handler;
	unsigned long sa_flags;
	__sigrestore_t sa_restorer;
	sigset_t sa_mask;		/* mask last for extensibility */
};

struct k_sigaction {
	struct sigaction sa;
};

#endif /* !__i386__ */

typedef struct sigaltstack {
	void __user *ss_sp;
	int ss_flags;
	size_t ss_size;
} stack_t;

#ifdef __KERNEL__
#include <asm/sigcontext.h>

#ifdef __i386__

#define __HAVE_ARCH_SIG_BITOPS

#define sigaddset(set,sig)		    \
	(__builtin_constant_p(sig)	    \
	 ? __const_sigaddset((set), (sig))  \
	 : __gen_sigaddset((set), (sig)))

static inline void __gen_sigaddset(sigset_t *set, int _sig)
{
	asm("btsl %1,%0" : "+m"(*set) : "Ir"(_sig - 1) : "cc");
}

static inline void __const_sigaddset(sigset_t *set, int _sig)
{
	unsigned long sig = _sig - 1;
	set->sig[sig / _NSIG_BPW] |= 1 << (sig % _NSIG_BPW);
}

#define sigdelset(set, sig)		    \
	(__builtin_constant_p(sig)	    \
	 ? __const_sigdelset((set), (sig))  \
	 : __gen_sigdelset((set), (sig)))


static inline void __gen_sigdelset(sigset_t *set, int _sig)
{
	asm("btrl %1,%0" : "+m"(*set) : "Ir"(_sig - 1) : "cc");
}

static inline void __const_sigdelset(sigset_t *set, int _sig)
{
	unsigned long sig = _sig - 1;
	set->sig[sig / _NSIG_BPW] &= ~(1 << (sig % _NSIG_BPW));
}

static inline int __const_sigismember(sigset_t *set, int _sig)
{
	unsigned long sig = _sig - 1;
	return 1 & (set->sig[sig / _NSIG_BPW] >> (sig % _NSIG_BPW));
}

static inline int __gen_sigismember(sigset_t *set, int _sig)
{
	int ret;
	asm("btl %2,%1\n\tsbbl %0,%0"
	    : "=r"(ret) : "m"(*set), "Ir"(_sig-1) : "cc");
	return ret;
}

#define sigismember(set, sig)			\
	(__builtin_constant_p(sig)		\
	 ? __const_sigismember((set), (sig))	\
	 : __gen_sigismember((set), (sig)))

static inline int sigfindinword(unsigned long word)
{
	asm("bsfl %1,%0" : "=r"(word) : "rm"(word) : "cc");
	return word;
}

struct pt_regs;

#else /* __i386__ */

#undef __HAVE_ARCH_SIG_BITOPS

#endif /* !__i386__ */

#define ptrace_signal_deliver(regs, cookie) do { } while (0)

#endif /* __KERNEL__ */
#endif /* __ASSEMBLY__ */

#endif
s="hl com">/* 03-00 0 OFFSET[03:00] Offset number from 0 to 15 */ /* */ /************************************************************************/ #define TRM_S1040_SCSI_SYNC 0x85 /* SCSI Synchronous Control (R/W) */ #define LVDS_SYNC 0x20 /* Enable LVDS synchronous */ #define WIDE_SYNC 0x10 /* Enable WIDE synchronous */ #define ALT_SYNC 0x08 /* Enable Fast-20 alternate synchronous */ /************************************************************************/ /* */ /* SYNCM 7 6 5 4 3 2 1 0 */ /* Name RSVD RSVD LVDS WIDE ALTPERD PERIOD2 PERIOD1 PERIOD0 */ /* Default 0 0 0 0 0 0 0 0 */ /* */ /* Bit Name Definition */ /* --------- ------------- --------------------------- */ /* 07-06 0 RSVD Reversed. Always read 0 */ /* 05 0 LVDS Reversed. Always read 0 */ /* 04 0 WIDE/WSCSI Enable wide (16-bits) SCSI */ /* transfer. */ /* 03 0 ALTPERD/ALTPD Alternate (Sync./Period) mode. */ /* */ /* @@ When this bit is set, */ /* the synchronous period bits 2:0 */ /* in the Synchronous Mode register */ /* are used to transfer data */ /* at the Fast-20 rate. */ /* @@ When this bit is unset, */ /* the synchronous period bits 2:0 */ /* in the Synchronous Mode Register */ /* are used to transfer data */ /* at the Fast-10 rate (or Fast-40 w/ LVDS). */ /* */ /* 02-00 0 PERIOD[2:0]/ Synchronous SCSI Transfer Rate. */ /* SXPD[02:00] These 3 bits specify */ /* the Synchronous SCSI Transfer */ /* Rate for Fast-20 and Fast-10. */ /* These bits are also reset */ /* by a SCSI Bus reset. */ /* */ /* For Fast-10 bit ALTPD = 0 and LVDS = 0 */ /* and bit2,bit1,bit0 is defined as follows : */ /* */ /* 000 100ns, 10.0 MHz */ /* 001 150ns, 6.6 MHz */ /* 010 200ns, 5.0 MHz */ /* 011 250ns, 4.0 MHz */ /* 100 300ns, 3.3 MHz */ /* 101 350ns, 2.8 MHz */ /* 110 400ns, 2.5 MHz */ /* 111 450ns, 2.2 MHz */ /* */ /* For Fast-20 bit ALTPD = 1 and LVDS = 0 */ /* and bit2,bit1,bit0 is defined as follows : */ /* */ /* 000 50ns, 20.0 MHz */ /* 001 75ns, 13.3 MHz */ /* 010 100ns, 10.0 MHz */ /* 011 125ns, 8.0 MHz */ /* 100 150ns, 6.6 MHz */ /* 101 175ns, 5.7 MHz */ /* 110 200ns, 5.0 MHz */ /* 111 250ns, 4.0 MHz KG: Maybe 225ns, 4.4 MHz */ /* */ /* For Fast-40 bit ALTPD = 0 and LVDS = 1 */ /* and bit2,bit1,bit0 is defined as follows : */ /* */ /* 000 25ns, 40.0 MHz */ /* 001 50ns, 20.0 MHz */ /* 010 75ns, 13.3 MHz */ /* 011 100ns, 10.0 MHz */ /* 100 125ns, 8.0 MHz */ /* 101 150ns, 6.6 MHz */ /* 110 175ns, 5.7 MHz */ /* 111 200ns, 5.0 MHz */ /* */ /************************************************************************/ #define TRM_S1040_SCSI_TARGETID 0x86 /* SCSI Target ID (R/W) */ #define TRM_S1040_SCSI_IDMSG 0x87 /* SCSI Identify Message (R) */ #define TRM_S1040_SCSI_HOSTID 0x87 /* SCSI Host ID (W) */ #define TRM_S1040_SCSI_COUNTER 0x88 /* SCSI Transfer Counter 24bits(R/W) */ #define TRM_S1040_SCSI_INTEN 0x8C /* SCSI Interrupt Enable (R/W) */ #define EN_SCAM 0x80 /* Enable SCAM selection interrupt */ #define EN_SELECT 0x40 /* Enable selection interrupt */ #define EN_SELTIMEOUT 0x20 /* Enable selection timeout interrupt */ #define EN_DISCONNECT 0x10 /* Enable bus disconnected interrupt */ #define EN_RESELECTED 0x08 /* Enable reselected interrupt */ #define EN_SCSIRESET 0x04 /* Enable SCSI reset detected interrupt */ #define EN_BUSSERVICE 0x02 /* Enable bus service interrupt */ #define EN_CMDDONE 0x01 /* Enable SCSI command done interrupt */ #define TRM_S1040_SCSI_CONFIG0 0x8D /* SCSI Configuration 0 (R/W) */ #define PHASELATCH 0x40 /* Enable phase latch */ #define INITIATOR 0x20 /* Enable initiator mode */ #define PARITYCHECK 0x10 /* Enable parity check */ #define BLOCKRST 0x01 /* Disable SCSI reset1 */ #define TRM_S1040_SCSI_CONFIG1 0x8E /* SCSI Configuration 1 (R/W) */ #define ACTIVE_NEGPLUS 0x10 /* Enhance active negation */ #define FILTER_DISABLE 0x08 /* Disable SCSI data filter */ #define FAST_FILTER 0x04 /* ? */ #define ACTIVE_NEG 0x02 /* Enable active negation */ #define TRM_S1040_SCSI_CONFIG2 0x8F /* SCSI Configuration 2 (R/W) */ #define CFG2_WIDEFIFO 0x02 /* */ #define TRM_S1040_SCSI_COMMAND 0x90 /* SCSI Command (R/W) */ #define SCMD_COMP 0x12 /* Command complete */ #define SCMD_SEL_ATN 0x60 /* Selection with ATN */ #define SCMD_SEL_ATN3 0x64 /* Selection with ATN3 */ #define SCMD_SEL_ATNSTOP 0xB8 /* Selection with ATN and Stop */ #define SCMD_FIFO_OUT 0xC0 /* SCSI FIFO transfer out */ #define SCMD_DMA_OUT 0xC1 /* SCSI DMA transfer out */ #define SCMD_FIFO_IN 0xC2 /* SCSI FIFO transfer in */ #define SCMD_DMA_IN 0xC3 /* SCSI DMA transfer in */ #define SCMD_MSGACCEPT 0xD8 /* Message accept */ /************************************************************************/ /* */ /* Code Command Description */ /* ---- ---------------------------------------- */ /* 02 Enable reselection with FIFO */ /* 40 Select without ATN with FIFO */ /* 60 Select with ATN with FIFO */ /* 64 Select with ATN3 with FIFO */ /* A0 Select with ATN and stop with FIFO */ /* C0 Transfer information out with FIFO */ /* C1 Transfer information out with DMA */ /* C2 Transfer information in with FIFO */ /* C3 Transfer information in with DMA */ /* 12 Initiator command complete with FIFO */ /* 50 Initiator transfer information out sequence without ATN */ /* with FIFO */ /* 70 Initiator transfer information out sequence with ATN */ /* with FIFO */ /* 74 Initiator transfer information out sequence with ATN3 */ /* with FIFO */ /* 52 Initiator transfer information in sequence without ATN */ /* with FIFO */ /* 72 Initiator transfer information in sequence with ATN */ /* with FIFO */ /* 76 Initiator transfer information in sequence with ATN3 */ /* with FIFO */ /* 90 Initiator transfer information out command complete */ /* with FIFO */ /* 92 Initiator transfer information in command complete */ /* with FIFO */ /* D2 Enable selection */ /* 08 Reselection */ /* 48 Disconnect command with FIFO */ /* 88 Terminate command with FIFO */ /* C8 Target command complete with FIFO */ /* 18 SCAM Arbitration/ Selection */ /* 5A Enable reselection */ /* 98 Select without ATN with FIFO */ /* B8 Select with ATN with FIFO */ /* D8 Message Accepted */ /* 58 NOP */ /* */ /************************************************************************/ #define TRM_S1040_SCSI_TIMEOUT 0x91 /* SCSI Time Out Value (R/W) */ #define TRM_S1040_SCSI_FIFO 0x98 /* SCSI FIFO (R/W) */ #define TRM_S1040_SCSI_TCR0 0x9C /* SCSI Target Control 0 (R/W) */ #define TCR0_WIDE_NEGO_DONE 0x8000 /* Wide nego done */ #define TCR0_SYNC_NEGO_DONE 0x4000 /* Synchronous nego done */ #define TCR0_ENABLE_LVDS 0x2000 /* Enable LVDS synchronous */ #define TCR0_ENABLE_WIDE 0x1000 /* Enable WIDE synchronous */ #define TCR0_ENABLE_ALT 0x0800 /* Enable alternate synchronous */ #define TCR0_PERIOD_MASK 0x0700 /* Transfer rate */ #define TCR0_DO_WIDE_NEGO 0x0080 /* Do wide NEGO */ #define TCR0_DO_SYNC_NEGO 0x0040 /* Do sync NEGO */ #define TCR0_DISCONNECT_EN 0x0020 /* Disconnection enable */ #define TCR0_OFFSET_MASK 0x001F /* Offset number */ #define TRM_S1040_SCSI_TCR1 0x9E /* SCSI Target Control 1 (R/W) */ #define MAXTAG_MASK 0x7F00 /* Maximum tags (127) */ #define NON_TAG_BUSY 0x0080 /* Non tag command active */ #define ACTTAG_MASK 0x007F /* Active tags */ /************************************************************************/ /* */ /* The DMA register offset for TRM_S1040 */ /* */ /************************************************************************/ #define TRM_S1040_DMA_COMMAND 0xA0 /* DMA Command (R/W) */ #define DMACMD_SG 0x02 /* Enable HW S/G support */ #define DMACMD_DIR 0x01 /* 1 = read from SCSI write to Host */ #define XFERDATAIN_SG 0x0103 /* Transfer data in w/ SG */ #define XFERDATAOUT_SG 0x0102 /* Transfer data out w/ SG */ #define XFERDATAIN 0x0101 /* Transfer data in w/o SG */ #define XFERDATAOUT 0x0100 /* Transfer data out w/o SG */ #define TRM_S1040_DMA_FIFOCNT 0xA1 /* DMA FIFO Counter (R) */ #define TRM_S1040_DMA_CONTROL 0xA1 /* DMA Control (W) */ #define DMARESETMODULE 0x10 /* Reset PCI/DMA module */ #define STOPDMAXFER 0x08 /* Stop DMA transfer */ #define ABORTXFER 0x04 /* Abort DMA transfer */ #define CLRXFIFO 0x02 /* Clear DMA transfer FIFO */ #define STARTDMAXFER 0x01 /* Start DMA transfer */ #define TRM_S1040_DMA_FIFOSTAT 0xA2 /* DMA FIFO Status (R) */ #define TRM_S1040_DMA_STATUS 0xA3 /* DMA Interrupt Status (R/W) */ #define XFERPENDING 0x80 /* Transfer pending */ #define SCSIBUSY 0x40 /* SCSI busy */ #define GLOBALINT 0x20 /* DMA_INTEN bit 0-4 set */ #define FORCEDMACOMP 0x10 /* Force DMA transfer complete */ #define DMAXFERERROR 0x08 /* DMA transfer error */ #define DMAXFERABORT 0x04 /* DMA transfer abort */ #define DMAXFERCOMP 0x02 /* Bus Master XFER Complete status */ #define SCSICOMP 0x01 /* SCSI complete interrupt */ #define TRM_S1040_DMA_INTEN 0xA4 /* DMA Interrupt Enable (R/W) */ #define EN_FORCEDMACOMP 0x10 /* Force DMA transfer complete */ #define EN_DMAXFERERROR 0x08 /* DMA transfer error */ #define EN_DMAXFERABORT 0x04 /* DMA transfer abort */ #define EN_DMAXFERCOMP 0x02 /* Bus Master XFER Complete status */ #define EN_SCSIINTR 0x01 /* Enable SCSI complete interrupt */ #define TRM_S1040_DMA_CONFIG 0xA6 /* DMA Configuration (R/W) */ #define DMA_ENHANCE 0x8000 /* Enable DMA enhance feature (SG?) */ #define DMA_PCI_DUAL_ADDR 0x4000 /* */ #define DMA_CFG_RES 0x2000 /* Always 1 */ #define DMA_AUTO_CLR_FIFO 0x1000 /* DISable DMA auto clear FIFO */ #define DMA_MEM_MULTI_READ 0x0800 /* */ #define DMA_MEM_WRITE_INVAL 0x0400 /* Memory write and invalidate */ #define DMA_FIFO_CTRL 0x0300 /* Control FIFO operation with DMA */ #define DMA_FIFO_HALF_HALF 0x0200 /* Keep half filled on both read/write */ #define TRM_S1040_DMA_XCNT 0xA8 /* DMA Transfer Counter (R/W), 24bits */ #define TRM_S1040_DMA_CXCNT 0xAC /* DMA Current Transfer Counter (R) */ #define TRM_S1040_DMA_XLOWADDR 0xB0 /* DMA Transfer Physical Low Address */ #define TRM_S1040_DMA_XHIGHADDR 0xB4 /* DMA Transfer Physical High Address */ /************************************************************************/ /* */ /* The general register offset for TRM_S1040 */ /* */ /************************************************************************/ #define TRM_S1040_GEN_CONTROL 0xD4 /* Global Control */ #define CTRL_LED 0x80 /* Control onboard LED */ #define EN_EEPROM 0x10 /* Enable EEPROM programming */ #define DIS_TERM 0x08 /* Disable onboard termination */ #define AUTOTERM 0x04 /* Enable Auto SCSI terminator */ #define LOW8TERM 0x02 /* Enable Lower 8 bit SCSI terminator */ #define UP8TERM 0x01 /* Enable Upper 8 bit SCSI terminator */ #define TRM_S1040_GEN_STATUS 0xD5 /* Global Status */ #define GTIMEOUT 0x80 /* Global timer reach 0 */ #define EXT68HIGH 0x40 /* Higher 8 bit connected externally */ #define INT68HIGH 0x20 /* Higher 8 bit connected internally */ #define CON5068 0x10 /* External 50/68 pin connected (low) */ #define CON68 0x08 /* Internal 68 pin connected (low) */ #define CON50 0x04 /* Internal 50 pin connected (low!) */ #define WIDESCSI 0x02 /* Wide SCSI card */ #define STATUS_LOAD_DEFAULT 0x01 /* */ #define TRM_S1040_GEN_NVRAM 0xD6 /* Serial NON-VOLATILE RAM port */ #define NVR_BITOUT 0x08 /* Serial data out */ #define NVR_BITIN 0x04 /* Serial data in */ #define NVR_CLOCK 0x02 /* Serial clock */ #define NVR_SELECT 0x01 /* Serial select */ #define TRM_S1040_GEN_EDATA 0xD7 /* Parallel EEPROM data port */ #define TRM_S1040_GEN_EADDRESS 0xD8 /* Parallel EEPROM address */ #define TRM_S1040_GEN_TIMER 0xDB /* Global timer */ /************************************************************************/ /* */ /* NvmTarCfg0: Target configuration byte 0 :..pDCB->DevMode */ /* */ /************************************************************************/ #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ #define NTC_DO_TAG_QUEUEING 0x10 /* Enable SCSI tag queuing */ #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */ #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ #define NTC_DO_PARITY_CHK 0x01 /* (it sould define at NAC) */ /* Parity check enable */ /************************************************************************/ /* */ /* Nvram Initiater bits definition */ /* */ /************************************************************************/ #if 0 #define MORE2_DRV BIT0 #define GREATER_1G BIT1 #define RST_SCSI_BUS BIT2 #define ACTIVE_NEGATION BIT3 #define NO_SEEK BIT4 #define LUN_CHECK BIT5 #endif /************************************************************************/ /* */ /* Nvram Adapter Cfg bits definition */ /* */ /************************************************************************/ #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */ #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ #define NAC_GREATER_1G 0x02 /* > 1G support enable */ #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */ /* #define NAC_DO_PARITY_CHK 0x08 */ /* Parity check enable */ #endif