/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
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* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
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* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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*/
#ifndef __MACH_CLK_H
#define __MACH_CLK_H
/* Magic rate value for use with PM QOS to request the board's maximum
* supported AXI rate. PM QOS will only pass positive s32 rate values
* through to the clock driver, so INT_MAX is used.
*/
#define MSM_AXI_MAX_FREQ LONG_MAX
enum clk_reset_action {
CLK_RESET_DEASSERT = 0,
CLK_RESET_ASSERT = 1
};
struct clk;
/* Rate is minimum clock rate in Hz */
int clk_set_min_rate(struct clk *clk, unsigned long rate);
/* Rate is maximum clock rate in Hz */
int clk_set_max_rate(struct clk *clk, unsigned long rate);
/* Assert/Deassert reset to a hardware block associated with a clock */
int clk_reset(struct clk *clk, enum clk_reset_action action);
/* Set clock-specific configuration parameters */
int clk_set_flags(struct clk *clk, unsigned long flags);
#endif
