path: root/arch/arm/boot/dts/socfpga_cyclone5.dts

/*
 *  Copyright (C) 2012 Altera Corporation <www.altera.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

/dts-v1/;
/include/ "socfpga.dtsi"

/ {
	model = "Altera SOCFPGA Cyclone V";
	compatible = "altr,socfpga-cyclone5", "altr,socfpga";

	chosen {
		bootargs = "console=ttyS0,57600";
	};

	memory {
		name = "memory";
		device_type = "memory";
		reg = <0x0 0x40000000>; /* 1GB */
	};

	aliases {
		/* this allow the ethaddr uboot environmnet variable contents
		 * to be added to the gmac1 device tree blob.
		 */
		ethernet0 = &gmac1;
	};

	soc {
		clkmgr@ffd04000 {
			clocks {
				osc1 {
					clock-frequency = <25000000>;
				};
			};
		};

		ethernet@ff702000 {
			phy-mode = "rgmii";
			phy-addr = <0xffffffff>; /* probe for phy addr */
			status = "okay";
		};

		timer0@ffc08000 {
			clock-frequency = <100000000>;
		};

		timer1@ffc09000 {
			clock-frequency = <100000000>;
		};

		timer2@ffd00000 {
			clock-frequency = <25000000>;
		};

		timer3@ffd01000 {
			clock-frequency = <25000000>;
		};

		serial0@ffc02000 {
			clock-frequency = <100000000>;
		};

		serial1@ffc03000 {
			clock-frequency = <100000000>;
		};

		sysmgr@ffd08000 {
			cpu1-start-addr = <0xffd080c4>;
		};
	};
};