litmus-rt.git/include/soc, branch master

pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.

2015-03-03T18:43:59+00:00

The DDRSDR controller fails miserably to put LPDDR1 memories in
self-refresh. Force the controller to think it has DDR2 memories
during the self-refresh period, as the DDR2 self-refresh spec is
equivalent to LPDDR1, and is correctly implemented in the
controller.

Assume that the second controller has the same fault, but that is
untested.

Signed-off-by: Peter Rosin 
Acked-by: Nicolas Ferre 
Signed-off-by: Nicolas Ferre

soc/tegra: Add Tegra132 support

2015-01-09T15:13:57+00:00

Add the chip ID for the NVIDIA Tegra132 SoC family.

Signed-off-by: Thierry Reding

soc/tegra: pmc: restrict compilation of suspend-related support to ARM

2015-01-09T12:41:19+00:00

Tegra SoCs with 64-bit ARM support don't currently support deep CPU
low-power states in mainline Linux.  When this support is added in the
future, it will probably look rather different from the existing
32-bit ARM support, since the ARM64 maintainers' strong preference is
to use PSCI to implement it.

So, for the time being, prevent the CPU suspend-related code and data
in the Tegra PMC driver from compiling on ARM64.

Signed-off-by: Paul Walmsley 
Signed-off-by: Paul Walmsley 
Cc: Thierry Reding 
Cc: Allen Martin 
Cc: Stephen Warren 
Cc: Alexandre Courbot 
Signed-off-by: Thierry Reding

Merge branch 'at91/cleanup5' into next/drivers

2014-12-08T17:29:20+00:00

The at91 cleanups changed a lot of files, this merges in the
latest cleanups to resolve the conflicts

Conflicts:
	arch/arm/mach-at91/at91sam9260.c
	arch/arm/mach-at91/at91sam9261.c
	arch/arm/mach-at91/at91sam9263.c
	arch/arm/mach-at91/clock.c
	arch/arm/mach-at91/clock.h
	drivers/rtc/Kconfig

Signed-off-by: Arnd Bergmann

memory: Add NVIDIA Tegra memory controller support

2014-12-04T15:11:47+00:00

The memory controller on NVIDIA Tegra exposes various knobs that can be
used to tune the behaviour of the clients attached to it.

Currently this driver sets up the latency allowance registers to the HW
defaults. Eventually an API should be exported by this driver (via a
custom API or a generic subsystem) to allow clients to register latency
requirements.

This driver also registers an IOMMU (SMMU) that's implemented by the
memory controller. It is supported on Tegra30, Tegra114 and Tegra124
currently. Tegra20 has a GART instead.

The Tegra SMMU operates on memory clients and SWGROUPs. A memory client
is a unidirectional, special-purpose DMA master. A SWGROUP represents a
set of memory clients that form a logical functional unit corresponding
to a single device. Typically a device has two clients: one client for
read transactions and one client for write transactions, but there are
also devices that have only read clients, but many of them (such as the
display controllers).

Because there is no 1:1 relationship between memory clients and devices
the driver keeps a table of memory clients and the SWGROUPs that they
belong to per SoC. Note that this is an exception and due to the fact
that the SMMU is tightly integrated with the rest of the Tegra SoC. The
use of these tables is discouraged in drivers for generic IOMMU devices
such as the ARM SMMU because the same IOMMU could be used in any number
of SoCs and keeping such tables for each SoC would not scale.

Acked-by: Joerg Roedel 
Signed-off-by: Thierry Reding

ARM: at91: move sdramc/ddrsdr header to include/soc/at91

2014-11-13T11:03:44+00:00

Move the (DDR) SDRAM controller headers to include/soc/at91 to remove the
dependency on mach/ headers from the at91-reset driver.

Signed-off-by: Alexandre Belloni 
Signed-off-by: Nicolas Ferre

ARM: tegra: Convert PMC to a driver

2014-07-17T12:58:43+00:00

This commit converts the PMC support code to a platform driver. Because
the boot process needs to call into this driver very early, also set up
a minimal environment via an early initcall.

Signed-off-by: Thierry Reding

soc/tegra: fuse: Set up in early initcall

2014-07-17T12:58:42+00:00

Rather than rely on explicit initialization order called from SoC setup
code, use a plain initcall and rely on initcall ordering to take care of
dependencies.

This driver exposes some functionality (querying the chip ID) needed at
very early stages of the boot process. An early initcall is good enough
provided that some of the dependencies are deferred to later stages. To
make sure any abuses are easily caught, output a warning message if the
chip ID is queried while it can't be read yet.

Signed-off-by: Thierry Reding

soc/tegra: Implement runtime check for Tegra SoCs

2014-07-17T12:58:41+00:00

Subsequent patches will move some of the initialization code from SoC
setup code to regular initcalls. To prevent breakage on other SoCs in
multi-platform builds, these initcalls need to check that they indeed
run on Tegra.

Signed-off-by: Thierry Reding

soc/tegra: fuse: move APB DMA into Tegra20 fuse driver

2014-07-17T12:37:12+00:00

The Tegra20 fuse driver is the only user of tegra_apb_readl_using_dma().
Therefore we can simply the code by incorporating the APB DMA handling into
the driver directly. tegra_apb_writel_using_dma() is dropped because there
are no users.

Signed-off-by: Peter De Schrijver 
Signed-off-by: Stephen Warren 
Signed-off-by: Thierry Reding