litmus-rt.git/include/asm-mips/mach-cobalt, branch master The LITMUS^RT kernel. MIPS: Move headfiles to new location below arch/mips/include 2008-10-11T15:18:52+00:00 Ralf Baechle ralf@linux-mips.org 2008-09-16T17:48:51+00:00 384740dc49ea651ba350704d13ff6be9976e37fe Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] remove unneeded button check for reset 2008-01-29T10:15:00+00:00 Yoichi Yuasa yoichi_yuasa@tripeaks.co.jp 2007-12-12T13:20:19+00:00 71466dd477c7a67d188d1d8310c7016a88531a04 Removed unneeded button check for reset. Because, the Cobalt has power switch. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Removed unneeded button check for reset.
Because, the Cobalt has power switch.

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Cobalt: Fix IRQ comment; the Cobalt kernel uses CP0 counter now. 2007-11-02T16:13:48+00:00 Yoichi Yuasa yoichi_yuasa@tripeaks.co.jp 2007-11-01T12:51:23+00:00 9aa4cc11b22ec447b42c5df03fdab5eb748971e2 Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Cobalt: Move reset port definition to arch/mips/cobalt/reset.c 2007-10-11T22:46:14+00:00 Yoichi Yuasa yoichi_yuasa@tripeaks.co.jp 2007-10-02T14:17:38+00:00 3282bd3cb0c7653e604c0d3666331281ae8f74c4 It's only used in arch/mips/cobalt/reset.c. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
It's only used in arch/mips/cobalt/reset.c.

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Cobalt: Move UART base definition to arch/mips/cobalt/console.c 2007-10-11T22:46:14+00:00 Yoichi Yuasa yoichi_yuasa@tripeaks.co.jp 2007-10-02T14:13:17+00:00 5a860424a1bcf21655d993a7c09b36662e34d2a9 They're only used in arch/mips/cobalt/console.c. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
They're only used in arch/mips/cobalt/console.c.

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Cobalt: Move PCI definitions to arch/mips/pci/fixup-cobalt.c. 2007-10-11T22:46:14+00:00 Yoichi Yuasa yoichi_yuasa@tripeaks.co.jp 2007-10-02T13:54:41+00:00 b4126e86301cfc6863cbc74bc4500a88b7c582df These PCI definitions are only used in arch/mips/pci/fixup-cobalt.c. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
These PCI definitions are only used in arch/mips/pci/fixup-cobalt.c.

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Split up war.h 2007-10-11T22:46:07+00:00 Ralf Baechle ralf@linux-mips.org 2007-10-11T22:46:07+00:00 baf22c1e7aedf264e264b15d2595e5e76564bd4e It was getting a little big, ugly and a primary source for merge conflicts. Also the old method was a bit too forgiving in that the workaround did default to off, so now there is an explicit #error forcing platform maintainers to think if they should enable a workaround for a particular platform. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
It was getting a little big, ugly and a primary source for merge conflicts.
Also the old method was a bit too forgiving in that the workaround did
default to off, so now there is an explicit #error forcing platform
maintainers to think if they should enable a workaround for a particular
platform.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code. 2007-10-11T22:46:05+00:00 Ralf Baechle ralf@linux-mips.org 2007-10-11T22:46:05+00:00 641e97f318870921d048154af6807e46e43c307a It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
It may not be perfect yet but the SB1 code is badly borken and has
horrible performance issues.

Downside: This seriously breaks support for pass 1 parts of the BCM1250
where indexed cacheops don't work quite reliable but I seem to be the
last one on the planet with a pass 1 part anyway.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Add GT641xx IRQ routines. 2007-10-11T22:46:04+00:00 Yoichi Yuasa yoichi_yuasa@tripeaks.co.jp 2007-09-13T14:51:26+00:00 d5ab1a6910fe850fa092888f210cf6c43136a7ab Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[MIPS] Disable UserLocal runtime detection on platforms which never have it. 2007-07-20T17:57:39+00:00 Ralf Baechle ralf@linux-mips.org 2007-07-13T17:58:25+00:00 ed203dadcd1373e80e95b04075e1eefc554a914b Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>