litmus-rt.git/drivers/spi/Makefile, branch linux-tip

spi: add spi_tegra driver

2010-10-22T01:15:05+00:00

v2 changes:
  from Thierry Reding:
    * add "select TEGRA_SYSTEM_DMA" to Kconfig
  from Grant Likely:
    * add oneline description to header
    * inline references to DRIVER_NAME
    * inline references to BUSY_TIMEOUT
    * open coded bytes_per_word()
    * spi_readl/writel -> spi_tegra_readl/writel
    * move transfer validation to spi_tegra_transfer
    * don't request_mem_region iomem as platform bus does that for us
    * __exit -> __devexit

v3 changes:
  from Russell King:
    * put request_mem_region back int
  from Grant Likely:
    * remove #undef DEBUG
    * add SLINK_ to register bit defines
    * remove unused bytes_per_word
    * make spi_tegra_readl/writel static linine
    * various refactoring for clarity
    * mark err if BSY bit is not cleared after 1000 retries
    * move spinlock to protect setting of RDY bit
    * subsys_initcall -> module_init

v3 changes:
  from Grant Likely:
    * update spi_tegra to use PTR_ERRless dma API

v4 changes:
  from Grant Likely:
    * remove empty spi_tegra_cleanup fucntion
    * allow device ids of -1

Signed-off-by: Erik Gilling 
Acked-by: Grant Likely 
Cc: Thierry Reding 
Cc: Russell King 

spi: tegra: cleanups from upstream review

Change-Id: Icecf7e64efcb39de072a15234ba1faa4bad40d25
Signed-off-by: Erik Gilling

spi/fsl_spi: add eSPI controller support

2010-10-13T03:38:12+00:00

Add eSPI controller support based on the library code spi_fsl_lib.c.

The eSPI controller is newer controller 85xx/Pxxx devices supported.
There're some differences comparing to the SPI controller:

1. Has different register map and different bit definition
   So leave the code operated the register to the driver code, not
   the common code.

2. Support 4 dedicated chip selects
   The software can't controll the chip selects directly, The SPCOM[CS]
   field is used to select which chip selects is used, and the
   SPCOM[TRANLEN] field is set to tell the controller how long the CS
   signal need to be asserted. So the driver doesn't need the chipselect
   related function when transfering data, just set corresponding register
   fields to controll the chipseclect.

3. Different Transmit/Receive FIFO access register behavior
   For SPI controller, the Tx/Rx FIFO access register can hold only
   one character regardless of the character length, but for eSPI
   controller, the register can hold 4 or 2 characters according to
   the character lengths. Access the Tx/Rx FIFO access register of the
   eSPI controller will shift out/in 4/2 characters one time. For SPI
   subsystem, the command and data are put into different transfers, so
   we need to combine all the transfers to one transfer in order to pass
   the transfer to eSPI controller.

4. The max transaction length limitation
   The max transaction length one time is limitted by the SPCOM[TRANSLEN]
   field which is 0xFFFF. When used mkfs.ext2 command to create ext2
   filesystem on the flash, the read length will exceed the max value of
   the SPCOM[TRANSLEN] field.

Signed-off-by: Mingkai Hu 
Signed-off-by: Grant Likely

spi/mpc8xxx: refactor the common code for SPI/eSPI controller

2010-10-13T03:38:12+00:00

Refactor the common code in file spi_fsl_spi.c to spi_fsl_lib.c used
by SPI/eSPI controller driver as a library, and leave the QE/CPM SPI
controller code in the SPI controller driver spi_fsl_spi.c.

Because the register map of the SPI controller and eSPI controller
is so different, also leave the code operated the register to the
driver code, not the common code.

Signed-off-by: Mingkai Hu 
Signed-off-by: Grant Likely

spi/mpc8xxx: rename spi_mpc8xxx.c to spi_fsl_spi.c

2010-10-13T03:38:12+00:00

This will pave the way to refactor out the common code which can be used
by the eSPI controller driver, and rename the SPI controller dirver to the
file spi_fsl_spi.c.

Signed-off-by: Mingkai Hu 
Signed-off-by: Grant Likely

spi: change to new flag variable

2010-10-13T03:37:37+00:00

Replace EXTRA_CFLAGS with ccflags-y.

Signed-off-by: matt mooney 
Signed-off-by: Grant Likely

spi/topcliff: Add topcliff platform controller hub (PCH) spi bus driver

2010-10-08T18:44:49+00:00

Topcliff PCH is the platform controller hub that is going to be used
in Intel's upcoming general embedded platform. All IO peripherals in
Topcliff PCH are actually devices sitting on AMBA bus.  This patch
adds a driver for the SPI bus integrated into the Topcliff device.

Signed-off-by: Masayuki Ohtake 
Signed-off-by: Grant Likely

spi/mpc5121: Add SPI master driver for MPC5121 PSC

2010-05-25T06:23:17+00:00

Signed-off-by: John Rigby 
Signed-off-by: Anatolij Gustschin 
Signed-off-by: Grant Likely

spi/ep93xx: implemented driver for Cirrus EP93xx SPI controller

2010-05-25T06:23:16+00:00

This patch adds an SPI master driver for the Cirrus EP93xx SPI controller found
in EP93xx chips.

Signed-off-by: Mika Westerberg 
Signed-off-by: H Hartley Sweeten 
Acked-by: H Hartley Sweeten 
Signed-off-by: Grant Likely

Memory-mapped dw_spi driver

2010-01-21T14:46:42+00:00

Adds a memory-mapped I/O dw_spi platform device.

Signed-off-by: Jean-Hugues Deschenes 
Signed-off-by: Grant Likely

spi: Add Freescale/Motorola Coldfire QSPI driver

2010-01-20T20:49:44+00:00

Add support for the QSPI controller found some on Freescale/Motorola
Coldfire MCUs.

Full duplex, active high cs, spi modes 0-3 and word sizes 8-16 bits are
supported.  The hardware drives the MISO, MOSI and SCLK lines, but the chip
selects are managed via GPIO and must be configured by the board code.

The QSPI controller has an 80 byte buffer which allows us to transfer up to 16
words at a time.  For transfers longer than 16 words, we split the buffer in
half so we can update in one half while the controller is operating on the
other half.  Interrupt latencies then ultimately limits our sustained thru-put
to something less than half the maximum speed supported by the part.

Signed-off-by: Steven King 
Signed-off-by: Grant Likely