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<title>litmus-rt.git/drivers/ntb, branch master</title>
<subtitle>The LITMUS^RT kernel.</subtitle>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt.git/'/>
<entry>
<title>ntb: initialize max_mw for Atom before using it</title>
<updated>2015-06-11T13:27:24+00:00</updated>
<author>
<name>Daniel Verkamp</name>
<email>daniel.verkamp@intel.com</email>
</author>
<published>2015-05-13T22:50:04+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt.git/commit/?id=ebaad1322d8080a1a8367ec631b345405d9879e2'/>
<id>ebaad1322d8080a1a8367ec631b345405d9879e2</id>
<content type='text'>
Commit ab760a0 (ntb: Adding split BAR support for Haswell platforms)
changed ntb_device's mw from a fixed-size array into a pointer that is
allocated based on limits.max_mw; however, on Atom platforms, max_mw
is not initialized until ntb_device_setup(), which happens after the
allocation.

Fill out max_mw in ntb_atom_detect() to match ntb_xeon_detect(); this
happens before the use of max_mw in the ndev-&gt;mw allocation.

Fixes a null pointer dereference on Atom platforms with ntb hardware.

v2: fix typo (mw_max should be max_mw)

Signed-off-by: Daniel Verkamp &lt;daniel.verkamp@intel.com&gt;
Acked-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</content>
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<pre>
Commit ab760a0 (ntb: Adding split BAR support for Haswell platforms)
changed ntb_device's mw from a fixed-size array into a pointer that is
allocated based on limits.max_mw; however, on Atom platforms, max_mw
is not initialized until ntb_device_setup(), which happens after the
allocation.

Fill out max_mw in ntb_atom_detect() to match ntb_xeon_detect(); this
happens before the use of max_mw in the ndev-&gt;mw allocation.

Fixes a null pointer dereference on Atom platforms with ntb hardware.

v2: fix typo (mw_max should be max_mw)

Signed-off-by: Daniel Verkamp &lt;daniel.verkamp@intel.com&gt;
Acked-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ntb: iounmap MW reg and vbase in error path</title>
<updated>2015-06-09T02:38:40+00:00</updated>
<author>
<name>Jon Mason</name>
<email>jdmason@kudzu.us</email>
</author>
<published>2015-04-05T18:57:22+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt.git/commit/?id=2f4eb6a80e57845ef6f3f7d1cdaaec7a6ab480a9'/>
<id>2f4eb6a80e57845ef6f3f7d1cdaaec7a6ab480a9</id>
<content type='text'>
The MW regbase and vbase(s) were not being freed if an error occurred
in the vbase allocation loop.  This is corrected by updating the error
path for the allocation loop to err4.

Reported-by: Julia Lawall &lt;julia.lawall@lip6.fr&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
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<pre>
The MW regbase and vbase(s) were not being freed if an error occurred
in the vbase allocation loop.  This is corrected by updating the error
path for the allocation loop to err4.

Reported-by: Julia Lawall &lt;julia.lawall@lip6.fr&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ntb: Adding split BAR support for Haswell platforms</title>
<updated>2014-10-17T11:08:51+00:00</updated>
<author>
<name>Dave Jiang</name>
<email>dave.jiang@intel.com</email>
</author>
<published>2014-08-28T20:53:23+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt.git/commit/?id=ab760a0c5667519b375ea9c5ab3a23501c4817ef'/>
<id>ab760a0c5667519b375ea9c5ab3a23501c4817ef</id>
<content type='text'>
On the Haswell platform, a split BAR option to allow creation of 2
32bit BARs (4 and 5) from the 64bit BAR 4. Adding support for this
new option.

Signed-off-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</content>
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<pre>
On the Haswell platform, a split BAR option to allow creation of 2
32bit BARs (4 and 5) from the 64bit BAR 4. Adding support for this
new option.

Signed-off-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ntb: use errata flag set via DID to implement workaround</title>
<updated>2014-10-17T11:08:51+00:00</updated>
<author>
<name>Dave Jiang</name>
<email>dave.jiang@intel.com</email>
</author>
<published>2014-08-28T20:53:18+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt.git/commit/?id=069684e888da73f175da0f10fe26da4f450d8c18'/>
<id>069684e888da73f175da0f10fe26da4f450d8c18</id>
<content type='text'>
Instead of using a module parameter, we should detect the errata via
PCI DID and then set an appropriate flag. This will be used for additional
errata later on.

Signed-off-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</content>
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<pre>
Instead of using a module parameter, we should detect the errata via
PCI DID and then set an appropriate flag. This will be used for additional
errata later on.

Signed-off-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ntb: conslidate reading of PPD to move platform detection earlier</title>
<updated>2014-10-17T11:08:50+00:00</updated>
<author>
<name>Dave Jiang</name>
<email>dave.jiang@intel.com</email>
</author>
<published>2014-08-28T20:53:13+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt.git/commit/?id=1db97f258966878317ece10868eaca99201d5884'/>
<id>1db97f258966878317ece10868eaca99201d5884</id>
<content type='text'>
To simplify some of the platform detection code. Move the platform detection
to a function to be called earlier.

Signed-off-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</content>
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<pre>
To simplify some of the platform detection code. Move the platform detection
to a function to be called earlier.

Signed-off-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ntb: move platform detection to separate function</title>
<updated>2014-10-17T11:08:50+00:00</updated>
<author>
<name>Dave Jiang</name>
<email>dave.jiang@intel.com</email>
</author>
<published>2014-08-28T20:53:07+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt.git/commit/?id=b775e85bdb0395077a23bc072c4a62986883e276'/>
<id>b775e85bdb0395077a23bc072c4a62986883e276</id>
<content type='text'>
Move the platform detection function to separate functions to allow
easier maintenence.

Signed-off-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Move the platform detection function to separate functions to allow
easier maintenence.

Signed-off-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>NTB: debugfs device entry</title>
<updated>2014-10-17T11:08:50+00:00</updated>
<author>
<name>Jon Mason</name>
<email>jon.mason@intel.com</email>
</author>
<published>2014-04-07T17:55:47+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt.git/commit/?id=6465d02ee15f7a45339b7e7859d0a0f22100ca87'/>
<id>6465d02ee15f7a45339b7e7859d0a0f22100ca87</id>
<content type='text'>
Create a debugfs entry for the NTB device to log the basic device info,
as well as display the error count on a number of registers.

Signed-off-by: Jon Mason &lt;jon.mason@intel.com&gt;
</content>
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<pre>
Create a debugfs entry for the NTB device to log the basic device info,
as well as display the error count on a number of registers.

Signed-off-by: Jon Mason &lt;jon.mason@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ntb: Add alignment check to meet hardware requirement</title>
<updated>2014-09-14T04:10:38+00:00</updated>
<author>
<name>Dave Jiang</name>
<email>dave.jiang@intel.com</email>
</author>
<published>2014-08-28T20:53:02+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt.git/commit/?id=3cc5ba1938eea0de372a41d1687c8030049c5e8f'/>
<id>3cc5ba1938eea0de372a41d1687c8030049c5e8f</id>
<content type='text'>
The NTB translate register must have the value to be BAR size aligned.
This alignment check make sure that the DMA memory allocated has the
proper alignment. Another requirement for NTB to function properly with
memory window BAR size greater or equal to 4M is to use the CMA feature
in 3.16 kernel with the appropriate CONFIG_CMA_ALIGNMENT and
CONFIG_CMA_SIZE_MBYTES set.

Signed-off-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</content>
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<pre>
The NTB translate register must have the value to be BAR size aligned.
This alignment check make sure that the DMA memory allocated has the
proper alignment. Another requirement for NTB to function properly with
memory window BAR size greater or equal to 4M is to use the CMA feature
in 3.16 kernel with the appropriate CONFIG_CMA_ALIGNMENT and
CONFIG_CMA_SIZE_MBYTES set.

Signed-off-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>NTB: correct the spread of queues over mw's</title>
<updated>2014-09-14T04:10:38+00:00</updated>
<author>
<name>Jon Mason</name>
<email>jon.mason@intel.com</email>
</author>
<published>2014-06-19T17:11:13+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt.git/commit/?id=a1413cfbcb9f56fca59043ef3c19369327e61b49'/>
<id>a1413cfbcb9f56fca59043ef3c19369327e61b49</id>
<content type='text'>
The detection of an uneven number of queues on the given memory windows
was not correct.  The mw_num is zero based and the mod should be
division to spread them evenly over the mw's.

Signed-off-by: Jon Mason &lt;jon.mason@intel.com&gt;
</content>
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<pre>
The detection of an uneven number of queues on the given memory windows
was not correct.  The mw_num is zero based and the mod should be
division to spread them evenly over the mw's.

Signed-off-by: Jon Mason &lt;jon.mason@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ntb: Use pci_enable_msix_range() instead of pci_enable_msix()</title>
<updated>2014-04-07T17:59:20+00:00</updated>
<author>
<name>Alexander Gordeev</name>
<email>agordeev@redhat.com</email>
</author>
<published>2014-03-11T16:00:35+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt.git/commit/?id=f220baad08963a75c78c80cdc1c9e9492ca0eb2a'/>
<id>f220baad08963a75c78c80cdc1c9e9492ca0eb2a</id>
<content type='text'>
As result of deprecation of MSI-X/MSI enablement functions
pci_enable_msix() and pci_enable_msi_block() all drivers
using these two interfaces need to be updated to use the
new pci_enable_msi_range()  or pci_enable_msi_exact()
and pci_enable_msix_range() or pci_enable_msix_exact()
interfaces.

Signed-off-by: Alexander Gordeev &lt;agordeev@redhat.com&gt;
Signed-off-by: Jon Mason &lt;jon.mason@intel.com&gt;
</content>
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<pre>
As result of deprecation of MSI-X/MSI enablement functions
pci_enable_msix() and pci_enable_msi_block() all drivers
using these two interfaces need to be updated to use the
new pci_enable_msi_range()  or pci_enable_msi_exact()
and pci_enable_msix_range() or pci_enable_msix_exact()
interfaces.

Signed-off-by: Alexander Gordeev &lt;agordeev@redhat.com&gt;
Signed-off-by: Jon Mason &lt;jon.mason@intel.com&gt;
</pre>
</div>
</content>
</entry>
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