<feed xmlns='http://www.w3.org/2005/Atom'>
<title>litmus-rt.git/drivers/cpufreq, branch test</title>
<subtitle>The LITMUS^RT kernel.</subtitle>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt.git/'/>
<entry>
<title>intel_pstate: set BYT MSR with wrmsrl_on_cpu()</title>
<updated>2015-07-10T16:49:34+00:00</updated>
<author>
<name>Joe Konno</name>
<email>joe.konno@intel.com</email>
</author>
<published>2015-05-12T14:59:42+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt.git/commit/?id=cd430d3e58e79d93597c26ee684730302940ae8c'/>
<id>cd430d3e58e79d93597c26ee684730302940ae8c</id>
<content type='text'>
commit 0dd23f94251f49da99a6cbfb22418b2d757d77d6 upstream.

Commit 007bea098b86 (intel_pstate: Add setting voltage value for
baytrail P states.) introduced byt_set_pstate() with the assumption that
it would always be run by the CPU whose MSR is to be written by it.  It
turns out, however, that is not always the case in practice, so modify
byt_set_pstate() to enforce the MSR write done by it to always happen on
the right CPU.

Fixes: 007bea098b86 (intel_pstate: Add setting voltage value for baytrail P states.)
Signed-off-by: Joe Konno &lt;joe.konno@intel.com&gt;
Acked-by: Kristen Carlson Accardi &lt;kristen@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
commit 0dd23f94251f49da99a6cbfb22418b2d757d77d6 upstream.

Commit 007bea098b86 (intel_pstate: Add setting voltage value for
baytrail P states.) introduced byt_set_pstate() with the assumption that
it would always be run by the CPU whose MSR is to be written by it.  It
turns out, however, that is not always the case in practice, so modify
byt_set_pstate() to enforce the MSR write done by it to always happen on
the right CPU.

Fixes: 007bea098b86 (intel_pstate: Add setting voltage value for baytrail P states.)
Signed-off-by: Joe Konno &lt;joe.konno@intel.com&gt;
Acked-by: Kristen Carlson Accardi &lt;kristen@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</pre>
</div>
</content>
</entry>
<entry>
<title>cpufreq: intel_pstate: Fix an annoying !CONFIG_SMP warning</title>
<updated>2015-04-15T21:02:24+00:00</updated>
<author>
<name>Borislav Petkov</name>
<email>bp@suse.de</email>
</author>
<published>2015-04-03T13:19:53+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt.git/commit/?id=64df1fdfccc054a4e5480c6bc965b67d3c83c3ae'/>
<id>64df1fdfccc054a4e5480c6bc965b67d3c83c3ae</id>
<content type='text'>
I keep seeing

  drivers/cpufreq/intel_pstate.c: In function ‘intel_pstate_init’:
  drivers/cpufreq/intel_pstate.c:1187:26: warning: initialization from incompatible pointer type
    struct cpuinfo_x86 *c = &amp;boot_cpu_data;

when doing randconfig builds.

This is caused by the fact that when !CONFIG_SMP, asm/processor.h
defines cpu_info to boot_cpu_data and the local variable

  struct cpu_defaults *cpu_info

overshadows it leading to this unfortunate assignment in the
preprocessed source:

 struct cpu_defaults *boot_cpu_data;
 struct cpuinfo_x86 *c = &amp;boot_cpu_data;

Rename the local variable and use static_cpu_has_safe() which alleviates
the need for defining a local cpuinfo_x86 pointer.

Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Acked-by: Kristen Carlson Accardi &lt;kristen@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
I keep seeing

  drivers/cpufreq/intel_pstate.c: In function ‘intel_pstate_init’:
  drivers/cpufreq/intel_pstate.c:1187:26: warning: initialization from incompatible pointer type
    struct cpuinfo_x86 *c = &amp;boot_cpu_data;

when doing randconfig builds.

This is caused by the fact that when !CONFIG_SMP, asm/processor.h
defines cpu_info to boot_cpu_data and the local variable

  struct cpu_defaults *cpu_info

overshadows it leading to this unfortunate assignment in the
preprocessed source:

 struct cpu_defaults *boot_cpu_data;
 struct cpuinfo_x86 *c = &amp;boot_cpu_data;

Rename the local variable and use static_cpu_has_safe() which alleviates
the need for defining a local cpuinfo_x86 pointer.

Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Acked-by: Kristen Carlson Accardi &lt;kristen@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>intel_pstate: Change the setpoint for Atom params</title>
<updated>2015-04-15T20:42:32+00:00</updated>
<author>
<name>Kristen Carlson Accardi</name>
<email>kristen@linux.intel.com</email>
</author>
<published>2015-04-10T18:06:43+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt.git/commit/?id=6a82ba6d4fda21e5f9fda0f4126add3b88522f02'/>
<id>6a82ba6d4fda21e5f9fda0f4126add3b88522f02</id>
<content type='text'>
Change the setpoint for the Baytrail and Cherrytrail CPUs.  This
will cause more aggressive pstate selection and improves
performance on a variety of workloads with little power penalty.

Signed-off-by: Kristen Carlson Accardi &lt;kristen@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Change the setpoint for the Baytrail and Cherrytrail CPUs.  This
will cause more aggressive pstate selection and improves
performance on a variety of workloads with little power penalty.

Signed-off-by: Kristen Carlson Accardi &lt;kristen@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>intel_pstate: Knights Landing support</title>
<updated>2015-04-11T00:13:29+00:00</updated>
<author>
<name>Dasaratharaman Chandramouli</name>
<email>dasaratharaman.chandramouli@intel.com</email>
</author>
<published>2015-04-10T17:22:18+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt.git/commit/?id=b34ef932d79ac2a36e1d7ba2742e5d4ba54efa3c'/>
<id>b34ef932d79ac2a36e1d7ba2742e5d4ba54efa3c</id>
<content type='text'>
 1. Add Knights Landing (KNL) CPUID to the list of CPUIDs supported by
    the intel_pstate driver.

 2. Add a new cpu_default structure for KNL since KNL has a slightly
    different mechanism to get turbo pstates from MSRs.

Signed-off-by: Dasaratharaman Chandramouli &lt;dasaratharaman.chandramouli@intel.com&gt;
Signed-off-by: Kristen Carlson Accardi &lt;kristen@linux.intel.com&gt;
[ rjw: Subject and changelog ]
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
 1. Add Knights Landing (KNL) CPUID to the list of CPUIDs supported by
    the intel_pstate driver.

 2. Add a new cpu_default structure for KNL since KNL has a slightly
    different mechanism to get turbo pstates from MSRs.

Signed-off-by: Dasaratharaman Chandramouli &lt;dasaratharaman.chandramouli@intel.com&gt;
Signed-off-by: Kristen Carlson Accardi &lt;kristen@linux.intel.com&gt;
[ rjw: Subject and changelog ]
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>intel_pstate: remove MSR test</title>
<updated>2015-04-11T00:13:28+00:00</updated>
<author>
<name>Kristen Carlson Accardi</name>
<email>kristen@linux.intel.com</email>
</author>
<published>2015-04-10T17:21:09+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt.git/commit/?id=5f97899d780787a8bbb42dee3be91ab5d8003b7f'/>
<id>5f97899d780787a8bbb42dee3be91ab5d8003b7f</id>
<content type='text'>
x86_match_cpu will not match our cpuid unless APERF/MPERF flag is
set, so there is no need to do the manual check for this MSR.

Signed-off-by: Kristen Carlson Accardi &lt;kristen@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
x86_match_cpu will not match our cpuid unless APERF/MPERF flag is
set, so there is no need to do the manual check for this MSR.

Signed-off-by: Kristen Carlson Accardi &lt;kristen@linux.intel.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpufreq: fix qoriq uniprocessor build</title>
<updated>2015-04-11T00:07:28+00:00</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2015-04-10T22:17:11+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt.git/commit/?id=4492d1a2e9566495858d25b35093e11509707407'/>
<id>4492d1a2e9566495858d25b35093e11509707407</id>
<content type='text'>
The qoriq-cpufreq driver contains a hack for powerpc to include
asm/smp.h on uniprocessor builds so it can get the hardware CPU
number. On ARM, it does not require this hack, but instead gets
a compile error:

In file included from drivers/cpufreq/qoriq-cpufreq.c:24:0:
arch/arm/include/asm/smp.h:18:3: error: #error "&lt;asm/smp.h&gt; included in non-SMP build"
arch/arm/include/asm/smp.h:21:0: warning: "raw_smp_processor_id" redefined

This adds an #ifdef to mirror the one in its get_cpu_physical_id()
function.

Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Fixes: 2f249358eedaf ("cpufreq: qoriq: rename the driver")
Cc: Tang Yuantian &lt;Yuantian.Tang@freescale.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The qoriq-cpufreq driver contains a hack for powerpc to include
asm/smp.h on uniprocessor builds so it can get the hardware CPU
number. On ARM, it does not require this hack, but instead gets
a compile error:

In file included from drivers/cpufreq/qoriq-cpufreq.c:24:0:
arch/arm/include/asm/smp.h:18:3: error: #error "&lt;asm/smp.h&gt; included in non-SMP build"
arch/arm/include/asm/smp.h:21:0: warning: "raw_smp_processor_id" redefined

This adds an #ifdef to mirror the one in its get_cpu_physical_id()
function.

Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Fixes: 2f249358eedaf ("cpufreq: qoriq: rename the driver")
Cc: Tang Yuantian &lt;Yuantian.Tang@freescale.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge back earlier cpufreq material for v4.1.</title>
<updated>2015-04-10T10:00:36+00:00</updated>
<author>
<name>Rafael J. Wysocki</name>
<email>rafael.j.wysocki@intel.com</email>
</author>
<published>2015-04-10T10:00:36+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt.git/commit/?id=38fc7839bae2db7a1321d9f6bfc7b5b3ccb59d2a'/>
<id>38fc7839bae2db7a1321d9f6bfc7b5b3ccb59d2a</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>cpufreq: Schedule work for the first-online CPU on resume</title>
<updated>2015-04-03T10:59:47+00:00</updated>
<author>
<name>Viresh Kumar</name>
<email>viresh.kumar@linaro.org</email>
</author>
<published>2015-04-02T04:51:33+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt.git/commit/?id=c75de0ac0756d4b442f460e10461720c7c2412c2'/>
<id>c75de0ac0756d4b442f460e10461720c7c2412c2</id>
<content type='text'>
All CPUs leaving the first-online CPU are hotplugged out on suspend and
and cpufreq core stops managing them.

On resume, we need to call cpufreq_update_policy() for this CPU's policy
to make sure its frequency is in sync with cpufreq's cached value, as it
might have got updated by hardware during suspend/resume.

The policies are always added to the top of the policy-list. So, in
normal circumstances, CPU 0's policy will be the last one in the list.
And so the code checks for the last policy.

But there are cases where it will fail. Consider quad-core system, with
policy-per core. If CPU0 is hotplugged out and added back again, the
last policy will be on CPU1 :(

To fix this in a proper way, always look for the policy of the first
online CPU. That way we will be sure that we are calling
cpufreq_update_policy() for the only CPU that wasn't hotplugged out.

Cc: 3.15+ &lt;stable@vger.kernel.org&gt; # 3.15+
Fixes: 2f0aea936360 ("cpufreq: suspend governors on system suspend/hibernate")
Reported-by: Saravana Kannan &lt;skannan@codeaurora.org&gt;
Signed-off-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Acked-by: Saravana Kannan &lt;skannan@codeaurora.org&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
All CPUs leaving the first-online CPU are hotplugged out on suspend and
and cpufreq core stops managing them.

On resume, we need to call cpufreq_update_policy() for this CPU's policy
to make sure its frequency is in sync with cpufreq's cached value, as it
might have got updated by hardware during suspend/resume.

The policies are always added to the top of the policy-list. So, in
normal circumstances, CPU 0's policy will be the last one in the list.
And so the code checks for the last policy.

But there are cases where it will fail. Consider quad-core system, with
policy-per core. If CPU0 is hotplugged out and added back again, the
last policy will be on CPU1 :(

To fix this in a proper way, always look for the policy of the first
online CPU. That way we will be sure that we are calling
cpufreq_update_policy() for the only CPU that wasn't hotplugged out.

Cc: 3.15+ &lt;stable@vger.kernel.org&gt; # 3.15+
Fixes: 2f0aea936360 ("cpufreq: suspend governors on system suspend/hibernate")
Reported-by: Saravana Kannan &lt;skannan@codeaurora.org&gt;
Signed-off-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Acked-by: Saravana Kannan &lt;skannan@codeaurora.org&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpufreq: hisilicon: add acpu driver</title>
<updated>2015-04-02T00:24:54+00:00</updated>
<author>
<name>Leo Yan</name>
<email>leo.yan@linaro.org</email>
</author>
<published>2015-03-30T05:26:37+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt.git/commit/?id=5acb972fed8bcfe6c38a4bdef4e74148eaad04b2'/>
<id>5acb972fed8bcfe6c38a4bdef4e74148eaad04b2</id>
<content type='text'>
Add acpu driver for hisilicon SoC, acpu is application processor
subsystem. Currently the acpu has the coupled clock domain for two
clusters, so this driver will directly use cpufreq-dt driver as
backend.

Signed-off-by: Leo Yan &lt;leo.yan@linaro.org&gt;
Acked-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add acpu driver for hisilicon SoC, acpu is application processor
subsystem. Currently the acpu has the coupled clock domain for two
clusters, so this driver will directly use cpufreq-dt driver as
backend.

Signed-off-by: Leo Yan &lt;leo.yan@linaro.org&gt;
Acked-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpufreq: powernv: Report cpu frequency throttling</title>
<updated>2015-04-01T21:02:24+00:00</updated>
<author>
<name>Shilpasri G Bhat</name>
<email>shilpa.bhat@linux.vnet.ibm.com</email>
</author>
<published>2015-04-01T09:46:34+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt.git/commit/?id=09a972d1620934142d30cfda455ffe429af751c4'/>
<id>09a972d1620934142d30cfda455ffe429af751c4</id>
<content type='text'>
The power and thermal safety of the system is taken care by an
On-Chip-Controller (OCC) which is real-time subsystem embedded within
the POWER8 processor. OCC continuously monitors the memory and core
temperature, the total system power, state of power supply and fan.

The cpu frequency can be throttled by OCC for the following reasons:
1)If a processor crosses its power and temperature limit then OCC will
  lower its Pmax to reduce the frequency and voltage.
2)If OCC crashes then the system is forced to Psafe frequency.
3)If OCC fails to recover then the kernel is not allowed to do any
  further frequency changes and the chip will remain in Psafe.

The user can see a drop in performance when frequency is throttled and
is unaware of throttling. So detect and report such a condition, so
the user can check the OCC status to reboot the system or check for
power supply or fan failures.

The current status of the core is read from Power Management Status
Register(PMSR) to check if any of the throttling condition is occurred
and the appropriate throttling message is reported.

Signed-off-by: Shilpasri G Bhat &lt;shilpa.bhat@linux.vnet.ibm.com&gt;
Reviewed-by: Preeti U Murthy &lt;preeti@linux.vnet.ibm.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The power and thermal safety of the system is taken care by an
On-Chip-Controller (OCC) which is real-time subsystem embedded within
the POWER8 processor. OCC continuously monitors the memory and core
temperature, the total system power, state of power supply and fan.

The cpu frequency can be throttled by OCC for the following reasons:
1)If a processor crosses its power and temperature limit then OCC will
  lower its Pmax to reduce the frequency and voltage.
2)If OCC crashes then the system is forced to Psafe frequency.
3)If OCC fails to recover then the kernel is not allowed to do any
  further frequency changes and the chip will remain in Psafe.

The user can see a drop in performance when frequency is throttled and
is unaware of throttling. So detect and report such a condition, so
the user can check the OCC status to reboot the system or check for
power supply or fan failures.

The current status of the core is read from Power Management Status
Register(PMSR) to check if any of the throttling condition is occurred
and the appropriate throttling message is reported.

Signed-off-by: Shilpasri G Bhat &lt;shilpa.bhat@linux.vnet.ibm.com&gt;
Reviewed-by: Preeti U Murthy &lt;preeti@linux.vnet.ibm.com&gt;
Signed-off-by: Rafael J. Wysocki &lt;rafael.j.wysocki@intel.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
