litmus-rt.git/arch/sparc/kernel, branch 2012.2

sparc: sun4m SMP: fix wrong shift instruction in IPI handler

2011-07-16T17:45:12+00:00

This shift instruction appears to be shifting in the wrong direction.
Without this change, my SparcStation-20MP hangs just after bringing up
the second CPU:

Entering SMP Mode...
Starting CPU 2 at f02b4e90
Brought up 2 CPUs
Total of 2 processors activated (99.52 BogoMIPS).
   *** stuck ***

Signed-off-by: Will Simoneau 
Signed-off-by: David S. Miller

sparc32, leon: bugfix in LEON SMP interrupt init

2011-06-09T23:12:34+00:00

During converting per-cpu ticker to genirq layer some
IRQ initialization code was removed by commit
2cf9530420e446bb61f665d02afeb81070106900 ("sparc32,leon:
per-cpu ticker use genirq per-cpu handler").

This patch reintroduces the code at the same place it was
removed from. IRQ12 - IRQ14 will crash on LEON SMP without
this patch because it will run the SUN4M IRQ trap handler.

Reported-by: Jan Andersson 
Signed-off-by: Daniel Hellstrom 
Signed-off-by: David S. Miller

sparc32, sun4m: bugfix in SMP IPI traphandler

2011-06-09T23:12:34+00:00

Three new IPIs were introduced by commit
ecbc42b70acbc6327adefe9635db93fcf62bf59d ("sparc32, sun4m:
Implemented SMP IPIs support for SUN4M machines"), the
old handler was already prepared for IPIs but handled only
IRQ14 and IRQ13, this patch adds support for the new IPI at
IRQ12.

The IPI trap handler looks at the mask rather than the
pending IRQ/IPI, this bug may have masked the problem
above, introduced by the same commit.

Signed-off-by: Daniel Hellstrom 
Signed-off-by: David S. Miller

sparc: Remove unnecessary semicolons

2011-06-07T23:06:34+00:00

Semicolons are not necessary after switch/while/for/if braces
so remove them.

Signed-off-by: Joe Perches 
Signed-off-by: David S. Miller

Add support for allocating irqs for bootbus devices

2011-06-07T23:06:33+00:00

Some devices that can generate interrupts are connected directly to the
CPU through the bootbus on sun4d. This patch allows IRQs to be allocated
for such devices. The information used for allocating interrupts for
sbus devices are present at the corresponding SBI node. For bootbus
devices this information is present in the bootbus node.

Signed-off-by: Kjetil Oftedal 
Signed-off-by: David S. Miller

Do not skip interrupt sources in sun4d interrupt handler and acknowledge interrupts correctly

2011-06-07T23:06:33+00:00

During the introduction of genirq on sparc32 bugs were introduced in
the interrupt handler for sun4d. The interrupts handler checks the status
of the various sbus interfaces in the system and generates a virtual
interrupt, based upon the location of the interrupt source. This lookup
was broken by restructuring the code in such a way that index and shift
operations were performed prior to comparing this against the values
read from the interrupt controllers.

This could cause the handler to loop eternally as the interrupt source
could be skipped before any check was performed. Additionally
sun4d_encode_irq performs shifting internally, so it should not be performed
twice.

In sun4d_unmask interrupts were not correctly acknowledged, as the
corresponding bit it the interrupt mask was not actually cleared.

Signed-off-by: Kjetil Oftedal 
Signed-off-by: David S. Miller

Restructure sun4d_build_device_irq so that timer interrupts can be allocated

2011-06-07T23:06:32+00:00

sun4d_build_device_irq was called without a valid platform_device when
the system timer was initialized on sun4d systems. This caused a NULL
pointer crash.

Josip Rodin suggested that the current sun4d_build_device_irq should be
split into two functions. So that the timer initialization could skip
the slot and sbus interface detection code in sun4d_build_device_irq, as
this does not make sence due to the timer interrupts not being generated
from a device located on sbus.

Signed-off-by: Kjetil Oftedal 
Signed-off-by: David S. Miller

sparc32,leon: add GRPCI2 PCI Host driver

2011-06-02T21:32:38+00:00

The DMA region must be accessible in order for PCI peripheral
drivers to work, the sparc32 has DMA in the normal memory
zone which requires the GRPCI2 to PCI target BARs so that all
kernel low mem (192MB) can be mapped 1:1 to PCI address
space. The GRPCI2 has resizeable target BARs, by default the
first is made 256MB and all other BARs are disabled.

I/O space are always located on 0x1000-0x10000, but accessed
through the GRPCI2 PCI I/O Window memory mapped to virtual
address space.

Configuration space is accessed through the 64KB GRPCI2 PCI
CFG Window using LDA bypassing the MMU.

The GRPCI2 has a single PCI Window for prefetchable and non-
prefetchable address space, it is up to the AHB master
requesting PCI data to determine access type. Memory space
is mapped 1:1.

The GRPCI2 core can be configured in 4 different IRQ modes,
where PCI Interrupt, Error Interrupt and DMA Interrupt are
shared on a single IRQ line or at most 5 IRQs are used. The
GRPCI2 can mask/unmask PCI interrupts, Err and DMA in the control
and check status bits which tells us which IRQ really happended.
The GENIRQ layer is used to unmask/mask each individual IRQ
source by creating virtual IRQs and implementing a IRQ chip.

The optional DMA functionality of the GRPCI2 is not supported
by this patch.

Signed-off-by: Daniel Hellstrom 
Signed-off-by: David S. Miller

sparc32,leon: added LEON-common low-level PCI routines

2011-06-02T21:32:37+00:00

The LEON architecture does not have a BIOS or bootloader that
initializes PCI for us, instead Linux generic PCI layer is used
to set up resources and IRQ.

Signed-off-by: Daniel Hellstrom 
Signed-off-by: David S. Miller

sparc32: added CONFIG_PCIC_PCI Kconfig setting

2011-06-02T21:32:37+00:00

Signed-off-by: Daniel Hellstrom 
Signed-off-by: David S. Miller