litmus-rt.git/Documentation/xtensa, branch test The LITMUS^RT kernel. xtensa: remap io area defined in device tree 2014-01-14T20:25:14+00:00 Baruch Siach baruch@tkos.co.il 2013-12-29T09:03:30+00:00 6cb971114f633a0bf240c20b681d989b45e3ec56 Use the simple-bus node to discover the io area, and remap the cached and bypass io ranges. The parent-bus-address value of the first triplet in the "ranges" property is used. This value is rounded down to the nearest 256MB boundary. The length of the io area is fixed at 256MB; the "ranges" property length value is ignored. Other limitations: (1) only the first simple-bus node is considered, and (2) only the first triplet of the "ranges" property is considered. See ePAPR 1.1 §6.5 for the simple-bus node description, and §2.3.8 for the "ranges" property description. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> 
Use the simple-bus node to discover the io area, and remap the cached and
bypass io ranges. The parent-bus-address value of the first triplet in the
"ranges" property is used. This value is rounded down to the nearest 256MB
boundary. The length of the io area is fixed at 256MB; the "ranges" property
length value is ignored.

Other limitations: (1) only the first simple-bus node is considered, and (2)
only the first triplet of the "ranges" property is considered.

See ePAPR 1.1 §6.5 for the simple-bus node description, and §2.3.8 for the
"ranges" property description.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: fix ATOMCTL register documentation 2014-01-14T20:21:23+00:00 Baruch Siach baruch@tkos.co.il 2013-11-11T15:15:17+00:00 5f42146e7599e120ee3f5b07d03ea45c633a955a Make the WT entry match table 4-52 of the Xtensa ISA RM (RD-2012.5). Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> 
Make the WT entry match table 4-52 of the Xtensa ISA RM (RD-2012.5).

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
xtensa: document MMUv3 setup sequence 2013-05-09T08:07:09+00:00 Max Filippov jcmvbkbc@gmail.com 2013-03-04T19:48:14+00:00 93e294ac99cc005044ab6357a26998eb962a10e8 Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net> 
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
xtensa: initialize atomctl SR 2012-12-19T05:10:22+00:00 Max Filippov jcmvbkbc@gmail.com 2012-11-19T03:00:41+00:00 c622b29d1f38021411965b7e0170ab055551b257 In order to use S32C1I instruction on cores with ATOMCTL SR the register must be properly initialized. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net> 
In order to use S32C1I instruction on cores with ATOMCTL SR the register
must be properly initialized.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>