litmus-rt.git/Documentation/devicetree/bindings/memory-controllers, branch master

dt-bindings: memory-controllers: Add binding for jz4780-nemc

2015-03-26T22:51:36+00:00

Add device tree bindings for the NAND/External Memory Controller (NEMC)
on Ingenic JZ4780

Signed-off-by: Alex Smith 
Signed-off-by: Zubair Lutfullah Kakakhel 
Signed-off-by: Greg Kroah-Hartman

ARM: shmobile: Add DT bindings for Renesas memory controllers

2015-01-14T23:53:50+00:00

Add DT bindings for Renesas R-Mobile and SH-Mobile memory controllers.
Currently memory controller device nodes are used only to reference PM
domains, and prevent these PM domains from being powered down, which
would crash the system.

Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman

Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

2014-12-09T22:48:22+00:00

Pull ARM SoC driver updates from Arnd Bergmann:
 "These are changes for drivers that are intimately tied to some SoC and
  for some reason could not get merged through the respective subsystem
  maintainer tree.

  The largest single change here this time around is the Tegra
  iommu/memory controller driver, which gets updated to the new iommu DT
  binding.  More drivers like this are likely to follow for the
  following merge window, but we should be able to do those through the
  iommu maintainer.

  Other notable changes are:
   - reset controller drivers from the reset maintainer (socfpga, sti,
     berlin)
   - fixes for the keystone navigator driver merged last time
   - at91 rtc driver changes related to the at91 cleanups
   - ARM perf driver changes from Will Deacon
   - updates for the brcmstb_gisb driver"

* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (53 commits)
  clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers
  clocksource: arch_timer: Fix code to use physical timers when requested
  memory: Add NVIDIA Tegra memory controller support
  bus: brcmstb_gisb: Add register offset tables for older chips
  bus: brcmstb_gisb: Look up register offsets in a table
  bus: brcmstb_gisb: Introduce wrapper functions for MMIO accesses
  bus: brcmstb_gisb: Make the driver buildable on MIPS
  of: Add NVIDIA Tegra memory controller binding
  ARM: tegra: Move AHB Kconfig to drivers/amba
  amba: Add Kconfig file
  clk: tegra: Implement memory-controller clock
  serial: samsung: Fix serial config dependencies for exynos7
  bus: brcmstb_gisb: resolve section mismatch
  ARM: common: edma: edma_pm_resume may be unused
  ARM: common: edma: add suspend resume hook
  powerpc/iommu: Rename iommu_[un]map_sg functions
  rtc: at91sam9: add DT bindings documentation
  rtc: at91sam9: use clk API instead of relying on AT91_SLOW_CLOCK
  ARM: at91: add clk_lookup entry for RTT devices
  rtc: at91sam9: rework the Kconfig description
  ...

of: Add NVIDIA Tegra memory controller binding

2014-11-26T08:43:25+00:00

The memory controller on NVIDIA Tegra exposes various knobs that can be
used to tune the behaviour of the clients attached to it.

In addition, the memory controller implements an SMMU (IOMMU) which can
translate I/O virtual addresses to physical addresses for clients. This
is useful for scatter-gather operation on devices that don't support it
natively and for virtualization or process separation.

Signed-off-by: Thierry Reding

Documentation: dt-bindings: minimal documentation for MVEBU SDRAM controller

2014-11-22T01:03:57+00:00

The suspend/resume code for Armada XP has to modify certain registers
of the SDRAM controller. Therefore, we need to define a Device Tree
binding for this hardware block.

Signed-off-by: Thomas Petazzoni 
Cc: devicetree@vger.kernel.org
Cc: Kumar Gala 
Cc: Ian Campbell 
Cc: Mark Rutland 
Cc: Rob Herring 
Reviewed-by: Gregory CLEMENT 
Link: https://lkml.kernel.org/r/1416585613-2113-2-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper

Documentation: devicetree: Add binding for Synopsys DDR controller

2014-09-16T10:55:05+00:00

Signed-off-by: Soren Brinkmann 
Signed-off-by: Michal Simek

memory: mvebu-devbus: add a devbus, keep-config property

2014-04-29T13:17:10+00:00

Currently, the mvebu-devbus Device Tree binding makes defining the
timing parameters mandatory.

However, in practice, when converting Orion5x platforms to the Device
Tree, we may not necessarily have easy access to the hardware
platforms to fetch those values which were not defined in old-style
board files: all these platforms rely on the bootloader setting the
timing parameters correctly.

In order to facilitate the migration to the Device Tree of this
platform, this commit relaxes the mvebu-devbus Device Tree binding by
introducing a 'devbus,keep-config' boolean property, which, if
defined, will ignore all timing parameters passed in the Device Tree,
and simply rely on the timing values already defined by the
bootloader.

Signed-off-by: Thomas Petazzoni 
Acked-by: Sebastian Hesselbarth 
Tested-by: Ezequiel Garcia 
Link: https://lkml.kernel.org/r/1398202002-28530-10-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper

memory: mvebu-devbus: add Orion5x support

2014-04-29T13:17:02+00:00

This commit adds support for the Orion5x family of Marvell processors
into the mvebu-devbus driver. It differs from the already supported
Armada 370/XP by:

 * Having a single register (instead of two) for doing all the timing
   configuration.

 * Having a few less timing configuration parameters.

For this reason, a separate compatible string "marvell,orion-devbus"
is introduced.

Signed-off-by: Thomas Petazzoni 
Acked-by: Sebastian Hesselbarth 
Tested-by: Ezequiel Garcia 
Link: https://lkml.kernel.org/r/1398202002-28530-9-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper

memory: ti-aemif: add bindings for AEMIF driver

2014-03-01T00:48:03+00:00

Add bindings for TI Async External Memory Interface (AEMIF) controller.

The Async External Memory Interface (EMIF16/AEMIF) controller is intended to
provide a glue-less interface to a variety of asynchronous memory devices like
ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories
can be accessed via 4 chip selects with 64M byte access per chip select.

We are not encoding CS number in reg property, it's memory partition number.
The CS number is encoded for Davinci NAND node using standalone property
"ti,davinci-chipselect" and we need to provide two memory ranges to it,
as result we can't encode CS number in "reg" for AEMIF child devices
(NAND/NOR/etc), as it will break bindings compatibility.

In this patch, NAND node is used just as an example of child node.

Acked-by: Santosh Shilimkar 
Signed-off-by: Ivan Khoronzhuk 
Signed-off-by: Greg Kroah-Hartman

driver/memory:Move Freescale IFC driver to a common driver

2014-02-18T20:20:45+00:00

 Freescale IFC controller has been used for mpc8xxx. It will be used
 for ARM-based SoC as well. This patch moves the driver to driver/memory
 and fix the header file includes.

  Also remove module_platform_driver() and  instead call
  platform_driver_register() from subsys_initcall() to make sure this module
  has been loaded before MTD partition parsing starts.

Signed-off-by: Prabhakar Kushwaha 
Acked-by: Arnd Bergmann 
Signed-off-by: Greg Kroah-Hartman