From e208f83a7aa4ebf6c0a68e814903e8aa33f9439a Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 25 Jul 2007 10:11:42 +0800 Subject: Blackfin arch: use HI/LO macros rather than masking the bit ranges ourselves Signed-off-by: Mike Frysinger Signed-off-by: Bryan Wu --- arch/blackfin/mach-bf533/head.S | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/blackfin/mach-bf533') diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S index 5aeffd06fe7..69da0e8b773 100644 --- a/arch/blackfin/mach-bf533/head.S +++ b/arch/blackfin/mach-bf533/head.S @@ -144,8 +144,8 @@ ENTRY(__start) ssync; /* Turn off the icache */ - p0.l = (IMEM_CONTROL & 0xFFFF); - p0.h = (IMEM_CONTROL >> 16); + p0.l = LO(IMEM_CONTROL); + p0.h = HI(IMEM_CONTROL); R1 = [p0]; R0 = ~ENICPLB; R0 = R0 & R1; @@ -162,8 +162,8 @@ ENTRY(__start) #endif /* Turn off the dcache */ - p0.l = (DMEM_CONTROL & 0xFFFF); - p0.h = (DMEM_CONTROL >> 16); + p0.l = LO(DMEM_CONTROL); + p0.h = HI(DMEM_CONTROL); R1 = [p0]; R0 = ~ENDCPLB; R0 = R0 & R1; @@ -417,8 +417,8 @@ ENTRY(_start_dma_code) w[p0] = r0.l; ssync; - p0.l = (EBIU_SDBCTL & 0xFFFF); - p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */ + p0.l = LO(EBIU_SDBCTL); + p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */ r0 = mem_SDBCTL; w[p0] = r0.l; ssync; -- cgit v1.2.2