| Commit message (Collapse) | Author | Age |
|---|
| |
|
|
|
|
|
|
| |
Tested with Malta; inflates malta_defconfig by 3932 bytes. Ideally there
should be additional configuration to allow getting rid of this overhead
but that would be too much complexity at this stage of the release cycle.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
| |
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Following a strict interpretation the empty definition of irq_enable_hazard
has always been a bug - but an intentional one because it didn't bite.
This has now changed, for uniprocessor kernels mm/slab.c:do_drain()
[...]
on_each_cpu(do_drain, cachep, 1, 1);
check_irq_on();
[...]
may be compiled into a mtc0 c0_status; mfc0 c0_status sequence resulting
in a back-to-back hazard.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
| |
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
| |
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
|
|
|
|
| |
Move FPU hazard handling to hazards.h and provide proper support for
MIPSR2 processors
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
| |
In the the sequence:
ei
..
mfc0 $x, $status
the mfc0 may not see the SR_IE bit set. This was a deliberate bug in the
kernel code because we knew this was a safe thing to do on all R2 silicon
so far but new silicon is changing this.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
|
|
|
| |
NEC VR4111 and VR4121 need one more nop with mtc0_tlbw_hazard().
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
| |
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
|
|
| |
Mostly based on patch by Chris Dearman and cleanups from Yoichi.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
| |
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
| |
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
|
| |
|
|
| |
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
|
|
|
| |
The SB1 core has a three cycle interrupt disable hazard but we were
wrongly treating it as fully interlocked.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
| |
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
|
|
|
|
|
|
|
| |
Gcc has a tradition of misscompiling the previous construct using the
address of a label as argument to inline assembler. Gas otoh has the
annoying difference between la and dla which are only usable for 32-bit
rsp. 64-bit code, so can't be used without conditional compilation.
The alterantive is switching the assembler to 64-bit code which happens
to work right even for 32-bit code ...
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
| |
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
| |
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
| |
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
| |
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
| |
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| |
|
|
|
|
| |
back mtc0 / mfc0 pairs from the same coprocessor register.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
|
|
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
|
