| Commit message (Collapse) | Author | Age | |
|---|---|---|---|
| * | SPI: add CSR SiRFprimaII SPI controller driver | Zhiwu Song | 2012-03-09 |
| CSR SiRFprimaII has two SPIs (SPI0 and SPI1). Features: * Master and slave modes * 8-/12-/16-/32-bit data unit * 256 bytes receive data FIFO and 256 bytes transmit data FIFO * Multi-unit frame * Configurable SPI_EN (chip select pin) active state * Configurable SPI_CLK polarity * Configurable SPI_CLK phase * Configurable MSB/LSB first Signed-off-by: Zhiwu Song <zhiwu.song@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca> | |||
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index : litmus-rt-tegra.git | |
| LITMUS^RT and MC^2 V0 support for the NVIDIA Tegra 3 SoC | Jonathan Herman |
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