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* Merge branch 'release' of ↵Linus Torvalds2009-04-01
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6 * 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6: (29 commits) [IA64] BUG to BUG_ON changes [IA64] Fix typo/thinko in arch/ia64/sn/kernel/sn2/sn2_smp.c ia64: remove some warnings. ia64/xen: fix the link error. ia64/pv_ops/bp/xen: implemented binary patchable pv_cpu_ops. ia64/pv_ops/binary patch: define paravirt_dv_serialize_data() and suppress false positive warning. ia64/pv_ops/bp/module: support binary patching for kernel module. ia64/pv_ops: implement binary patching optimization for native. ia64/pv_op/binarypatch: add helper functions to support binary patching for paravirt_ops. ia64/pv_ops/xen/gate.S: xen gate page paravirtualization ia64/pv_ops: paravirtualize gate.S. ia64/pv_ops: move down __kernel_syscall_via_epc. ia64/pv_ops/xen: define xen specific gate page. ia64/pv_ops: gate page paravirtualization. ia64/pv_ops/xen/pv_time_ops: implement sched_clock. ia64/pv_ops/pv_time_ops: add sched_clock hook. ia64/pv_ops/xen: paravirtualize read/write ar.itc and ar.itm ia64/pv_ops: paravirtualize mov = ar.itc. ia64/pv_ops/pvchecker: support mov = ar.itc paravirtualization ia64/pv_ops: paravirtualize fsys.S. ...
| * [IA64] BUG to BUG_ON changesStoyan Gaydarov2009-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | Replace: if (test) BUG(); with BUG_ON(test); Signed-off-by: Stoyan Gaydarov <stoyboyker@gmail.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * [IA64] Fix typo/thinko in arch/ia64/sn/kernel/sn2/sn2_smp.cRandy Dunlap2009-04-01
| | | | | | | | | | | | | | sn2_ptc_init() has what looks like a cut-n-paste error. Fix it. Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * Pull pvops into release branchTony Luck2009-03-31
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| | * ia64: remove some warnings.Isaku Yamahata2009-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the following warnings and related ones. Plus some cosmetics. arch/ia64/kernel/patch.c:112: warning: passing argument 1 of 'paravirt_fc' makes integer from pointer without a cast arch/ia64/kernel/patch.c:135: warning: passing argument 1 of 'paravirt_fc' makes integer from pointer without a cast arch/ia64/kernel/patch.c:166: warning: passing argument 1 of 'paravirt_fc' makes integer from pointer without a cast arch/ia64/kernel/patch.c:202: warning: passing argument 1 of 'paravirt_fc' makes integer from pointer without a cast arch/ia64/kernel/patch.c:220: warning: passing argument 1 of 'paravirt_fc' makes integer from pointer without a cast Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * ia64/xen: fix the link error.Isaku Yamahata2009-03-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the following link error with xen_domu_defconfig. Depending on compiler version, it doesn't link as follows. So remove const and use __initdata for xen_iosapic_ops. > arch/ia64/xen/xen_pv_ops.c:878: error: xen_iosapic_ops causes a section type conflict Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * ia64/pv_ops/bp/xen: implemented binary patchable pv_cpu_ops.Isaku Yamahata2009-03-26
| | | | | | | | | | | | | | | | | | | | | implemented xen binary patch for pv_cpu_ops. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * ia64/pv_ops/binary patch: define paravirt_dv_serialize_data() and suppress ↵Isaku Yamahata2009-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | false positive warning. define paravirt_dv_serialize_data() and insert it to suppress false positive warnings. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * ia64/pv_ops/bp/module: support binary patching for kernel module.Isaku Yamahata2009-03-26
| | | | | | | | | | | | | | | | | | | | | support binary patching for kernel module. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * ia64/pv_ops: implement binary patching optimization for native.Isaku Yamahata2009-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | implement binary patching optimization for pv_cpu_ops. With this optimization, indirect call for pv_cpu_ops methods can be converted into inline execution or direct call. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * ia64/pv_op/binarypatch: add helper functions to support binary patching for ↵Isaku Yamahata2009-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | paravirt_ops. add helper functions to support binary patching for paravirt_ops. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * ia64/pv_ops/xen/gate.S: xen gate page paravirtualizationIsaku Yamahata2009-03-26
| | | | | | | | | | | | | | | | | | | | | xen gate page paravirtualization Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * ia64/pv_ops: paravirtualize gate.S.Isaku Yamahata2009-03-26
| | | | | | | | | | | | | | | | | | | | | paravirtualize gate.S. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * ia64/pv_ops: move down __kernel_syscall_via_epc.Isaku Yamahata2009-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move down __kernel_syscall_via_epc to the end of the page. We want to paravirtualize only __kernel_syscall_via_epc because it includes privileged instructions. Its paravirtualization increases its symbols size. On the other hand, each paravirtualized gate must have e symbols of same value and size to native's because the page is mapped to GATE_ADDR and GATE_ADDR + PERCPU_PAGE_SIZE and vmlinux is linked to those symbols. Later to have the same symbol size, we pads NOPs at the end of __kernel_syscall_via_epc. Move it after other functions to keep symbols of other functions have same values and sizes. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * ia64/pv_ops/xen: define xen specific gate page.Isaku Yamahata2009-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | define xen specific gate page. At this phase bits in the gate page is same to native. At the next phase, it will be paravirtualized. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * ia64/pv_ops: gate page paravirtualization.Isaku Yamahata2009-03-26
| | | | | | | | | | | | | | | | | | | | | | | | paravirtualize gate page by allowing each pv_ops instances to define its own gate page. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * ia64/pv_ops/xen/pv_time_ops: implement sched_clock.Isaku Yamahata2009-03-26
| | | | | | | | | | | | | | | | | | | | | paravirtualize sched_clock. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * ia64/pv_ops/pv_time_ops: add sched_clock hook.Isaku Yamahata2009-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add sched_clock() hook to paravirtualize sched_clock(). ia64 sched_clock() is based on ar.itc which isn't stable on virtualized environment because vcpu may move around on pcpus. So it needs paravirtualization. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * ia64/pv_ops/xen: paravirtualize read/write ar.itc and ar.itmIsaku Yamahata2009-03-26
| | | | | | | | | | | | | | | | | | | | | paravirtualize ar.itc and ar.itm in order to support save/restore. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * ia64/pv_ops: paravirtualize mov = ar.itc.Isaku Yamahata2009-03-26
| | | | | | | | | | | | | | | | | | | | | paravirtualize mov reg = ar.itc. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * ia64/pv_ops/pvchecker: support mov = ar.itc paravirtualizationIsaku Yamahata2009-03-26
| | | | | | | | | | | | | | | | | | | | | add suport for mov = ar.itc to pvchecker. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * ia64/pv_ops: paravirtualize fsys.S.Isaku Yamahata2009-03-26
| | | | | | | | | | | | | | | | | | | | | paravirtualize fsys.S. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * ia64/pv_ops/xen: preliminary to paravirtualizing fsys.S for xen.Isaku Yamahata2009-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a preliminary patch to paravirtualizing fsys.S. compile fsys.S twice one for native and one for xen, and switch them at run tine. Later fsys.S will be paravirtualized. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * ia64/pv_ops: add hooks to paravirtualize fsyscall implementation.Isaku Yamahata2009-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add two hooks, paravirt_get_fsyscall_table() and paravirt_get_fsys_bubble_doen() to paravirtualize fsyscall implementation. This patch just add the hooks fsyscall and don't paravirtualize it. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * ia64/xen: short-circuit tests for dom0Isaku Yamahata2009-03-26
| | | | | | | | | | | | | | | | | | | | | This patch is ia64 counter part of clean up of the xen predicates. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
| | * ia64/pv_ops/xen: use __initconst instead of __initdata for const dataIsaku Yamahata2009-03-26
| | | | | | | | | | | | | | | | | | | | | | | | use __initconst instead of __initdata for const data like ec8148de85a73a3be397a59b6d8f4f32cf2dd254 Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
| * | Pull cpumask into release branchTony Luck2009-03-31
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| | * | cpumask: use mm_cpumask() wrapper: ia64Rusty Russell2009-03-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Makes code futureproof against the impending change to mm->cpu_vm_mask. It's also a chance to use the new cpumask_ ops which take a pointer (the older ones are deprecated, but there's no hurry for arch code). Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
| | * | cpumask: Use accessors code.: ia64Rusty Russell2009-03-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Impact: use new API Use the accessors rather than frobbing bits directly. Most of this is in arch code I haven't even compiled, but is straightforward. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Mike Travis <travis@sgi.com>
| | * | cpumask: prepare for iterators to only go to nr_cpu_ids/nr_cpumask_bits.: ia64Rusty Russell2009-03-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Impact: cleanup, futureproof In fact, all cpumask ops will only be valid (in general) for bit numbers < nr_cpu_ids. So use that instead of NR_CPUS in various places. This is always safe: no cpu number can be >= nr_cpu_ids, and nr_cpu_ids is initialized to NR_CPUS at boot. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Mike Travis <travis@sgi.com> Acked-by: Ingo Molnar <mingo@elte.hu>
| | * | cpumask: arch_send_call_function_ipi_mask: ia64Rusty Russell2009-03-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We're weaning the core code off handing cpumask's around on-stack. This introduces arch_send_call_function_ipi_mask(). We also take the chance to wean send_IPI_mask off the obsolescent for_each_cpu_mask(): making it take the pointer seemed the most natural way. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
| | * | cpumask: remove the now-obsoleted pcibus_to_cpumask(): ia64Rusty Russell2009-03-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Impact: reduce stack usage for large NR_CPUS cpumask_of_pcibus() is the new version. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
* | | | Merge branch 'x86-setup-for-linus' of ↵Linus Torvalds2009-04-01
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-setup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, setup: guard against pre-ACPI 3 e820 code not updating %ecx
| * | | | x86, setup: guard against pre-ACPI 3 e820 code not updating %ecxH. Peter Anvin2009-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Impact: BIOS bug safety For pre-ACPI 3 BIOSes, pre-initialize the end of the e820 buffer just in case the BIOS returns an unchanged %ecx but without actually touching the ACPI 3 extended flags field. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* | | | | Merge branch 'x86/setup' of ↵Linus Torvalds2009-04-01
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86/setup' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, setup: ACPI 3, BIOS workaround for E820-probing code x86, setup: preemptively save/restore edi and ebp around INT 15 E820 x86, setup: mark %esi as clobbered in E820 BIOS call
| * | | | x86, setup: ACPI 3, BIOS workaround for E820-probing codeH. Peter Anvin2009-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Impact: ACPI 3 spec compliance, BIOS bug workaround The ACPI 3 spec added another field to the E820 buffer -- which is backwards incompatible, since it contains a validity bit. Furthermore, there has been at least one report of a BIOS which assumes that the buffer it is pointed at is the same buffer as for the previous E820 call. Therefore, read the data into a temporary buffer and copy the standard part of it if and only if the valid bit is set. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
| * | | | x86, setup: preemptively save/restore edi and ebp around INT 15 E820H. Peter Anvin2009-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Impact: BIOS bugproofing Since there are BIOSes known to clobber %ebx and %esi for INT 15 E820, assume there is something out there clobbering %edi and/or %ebp too, and don't wait for it to fail. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
| * | | | x86, setup: mark %esi as clobbered in E820 BIOS callMichael K. Johnson2009-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Jordan Hargrave diagnosed a BIOS clobbering %esi in the E820 call. That particular BIOS has been fixed, but there is a possibility that this is responsible for other occasional reports of early boot failure, and it does not hurt to add %esi to the clobbers. -stable candidate patch. Cc: Justin Forbes <jmforbes@linuxtx.org> Signed-off-by: Michael K Johnson <johnsonm@rpath.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com> Cc: stable@kernel.org
* | | | | Merge branch 'linux-next' of ↵Linus Torvalds2009-04-01
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6 * 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (88 commits) PCI: fix HT MSI mapping fix PCI: don't enable too much HT MSI mapping x86/PCI: make pci=lastbus=255 work when acpi is on PCI: save and restore PCIe 2.0 registers PCI: update fakephp for bus_id removal PCI: fix kernel oops on bridge removal PCI: fix conflict between SR-IOV and config space sizing powerpc/PCI: include pci.h in powerpc MSI implementation PCI Hotplug: schedule fakephp for feature removal PCI Hotplug: rename legacy_fakephp to fakephp PCI Hotplug: restore fakephp interface with complete reimplementation PCI: Introduce /sys/bus/pci/devices/.../rescan PCI: Introduce /sys/bus/pci/devices/.../remove PCI: Introduce /sys/bus/pci/rescan PCI: Introduce pci_rescan_bus() PCI: do not enable bridges more than once PCI: do not initialize bridges more than once PCI: always scan child buses PCI: pci_scan_slot() returns newly found devices PCI: don't scan existing devices ... Fix trivial append-only conflict in Documentation/feature-removal-schedule.txt
| * | | | | x86/PCI: make pci=lastbus=255 work when acpi is onYinghai Lu2009-03-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Impact: scan more peer root buses even acpi is used Move pci_bios_fixup_peer_bridges out of pci_legacy_init and into pci_subsys_init. This allows pci_bios_fixup_peer_bridges to be called even pci_apci_init is driving PCI initialization. Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | | | | powerpc/PCI: include pci.h in powerpc MSI implementationJesse Barnes2009-03-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This file uses PCI MSI defines and so needs pci.h. Tested-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | | | | x86/PCI: host mmconfig detect clean upYinghai Lu2009-03-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix mmconfig detection to not assume a single mmconfig space in the northbridge, paving the way for AMD fam10h + mcp55 CPUs. On those, the MSR has some range, but the mcp55 pci config will have another one. Also helps the mcp55 + io55 case, where every one will have one range. If it is mcp55, exclude the range that is used by CPU MSR, in other words , if the CPU claims busses 0-255, the range in mcp55 is dropped, because CPU HW will not route those ranges to mcp55 mmconfig to handle it. Signed-off-by: Yinghai Lu <yinghai.lu@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | | | | x86/PCI: Detect mmconfig on nVidia MCP55Ed Swierk2009-03-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Detect and enable memory-mapped PCI configuration space on the nVidia MCP55 southbridge. Tested against 2.6.27.4 on an Arista Networks development board with one MCP55, Coreboot firmware, no ACPI. Signed-off-by: Ed Swierk <eswierk@aristanetworks.com> Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | | | | PCI/x86: detect host bridge config space size w/o using quirksYinghai Lu2009-03-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many host bridges support a 4k config space, so check them directy instead of using quirks to add them. We only need to do this extra check for host bridges at this point, because only host bridges are known to have extended address space without also having a PCI-X/PCI-E caps. Other devices with this property could be done with quirks (if there are any). As a bonus, we can remove the quirks for AMD host bridges with family 10h and 11h since they're not needed any more. With this patch, we can get correct pci cfg size of new Intel CPUs/IOHs with host bridges. Signed-off-by: Yinghai Lu <yinghai@kernel.org> Acked-by: H. Peter Anvin <hpa@zytor.com> Reviewed-by: Matthew Wilcox <willy@linux.intel.com> Cc: <stable@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | | | | PCI MSI: Add support for multiple MSIMatthew Wilcox2009-03-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the new API pci_enable_msi_block() to allow drivers to request multiple MSI and reimplement pci_enable_msi in terms of pci_enable_msi_block. Ensure that the architecture back ends don't have to know about multiple MSI. Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | | | | x86: use dev_printk in quirk messageBjorn Helgaas2009-03-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes a VIA PCI quirk to use dev_info() rather than printk(). Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgek.org>
| * | | | | PCI/alpha: pci sysfs resourcesIvan Kokshaysky2009-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This closes http://bugzilla.kernel.org/show_bug.cgi?id=10893 which is a showstopper for X development on alpha. The generic HAVE_PCI_MMAP code (drivers/pci-sysfs.c) is not very useful since we have to deal with three different types of MMIO address spaces: sparse and dense mappings for old ev4/ev5 machines and "normal" 1:1 MMIO space (bwx) for ev56 and later. Also "write combine" mappings are meaningless on alpha - roughly speaking, alpha does write combining, IO reordering and other optimizations by default, unless user splits IO accesses with memory barriers. I think the cleanest way to deal with resource files on alpha is to convert the default no-op pci_create_resource_files() and pci_remove_resource_files() for !HAVE_PCI_MMAP case into __weak functions and override them with alpha specific ones. Another alpha hook is needed for "legacy_" resource files to handle sparse addressing (pci_adjust_legacy_attr). With the "standard" resourceN files on ev56/ev6 libpciaccess works "out of the box". Handling of resourceN_sparse/resourceN_dense files on older machines obviously requires some userland work. Sparse/dense stuff has been tested on sx164 (pca56/pyxis, normally uses bwx IO) with the kernel hacked into "cia compatible" mode. Signed-off-by: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | | | | PCI/MSI: Use #ifdefs instead of weak functionsMichael Ellerman2009-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Weak functions aren't all they're cracked up to be. They lead to incorrect binaries with some toolchains, they require us to have empty functions we otherwise wouldn't, and the unused code is not elided (as of gcc 4.3.2 anyway). So replace the weak MSI arch hooks with the #define foo foo idiom. We no longer need empty versions of arch_setup/teardown_msi_irq(). This is less source (by 1 line!), and results in smaller binaries too: text data bss dec hex filename 9354300 1693916 678424 11726640 b2ef30 build/powerpc/vmlinux-before 9354052 1693852 678424 11726328 b2edf8 build/powerpc/vmlinux-after Also smaller on x86_64 and arm (iop13xx). Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | | | | PCI/x86: format early dump like other PCI outputBjorn Helgaas2009-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use %02x:%02x.%d rather than %02x:%02x:%02x so PCI addresses look the same as in other parts of the kernel. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | | | | PCI/x86: make early dump handle multi-function devicesBjorn Helgaas2009-03-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The early "dump PCI config space" code skips many multi-function devices. This patch fixes that, so it dumps all devices in PCI domain 0. We should not skip the rest of the functions if CLASS_REVISION is 0xffffffff. Often multi-function devices have gaps in the function ID space, e.g., 1c.0 and 1c.2 exist but 1c.1 doesn't. The CLASS_REVISION of the non-existent 1c.1 function will appear to be 0xffffffff. We should only look at the HEADER_TYPE of function zero. Often the "multi-function" is set in function zero, but not in other functions. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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