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* ARM: 5928/1: Change type of VMALLOC_END to unsigned long.Fenkart/Bostandzhyan2010-02-15
| | | | | | | | Makes it consistent with VMALLOC_START Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Andreas Fenkart <andreas.fenkart@streamunlimited.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5927/1: Make delimiters of DMA area globally visibly.Fenkart/Bostandzhyan2010-02-15
| | | | | | | | Adds DMA area to 'virtual memory map' startup message Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Andreas Fenkart <andreas.fenkart@streamunlimited.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5926/1: Add "Virtual kernel memory..." printout.Fenkart/Bostandzhyan2010-02-15
| | | | | | | | Code based on parisc and x86_32. Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Andreas Fenkart <andreas.fenkart@streamunlimited.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5919/1: ARM: L2 : Errata 588369: Clean & Invalidate do not invalidate ↵Santosh Shilimkar2010-02-15
| | | | | | | | | | | | | | | | | | clean lines This patch implements the work-around for the errata 588369.The secure API is used to alter L2 debug register because of trust-zone. This version updated with comments from Russell and Catalin and generated against 2.6.33-rc6 mainline kernel. Detail comments can be found: http://www.spinics.net/lists/linux-omap/msg23431.html Signed-off-by: Woodruff Richard <r-woodruff2@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5917/1: OMAP4: Add L2 Cache supportSantosh Shilimkar2010-02-15
| | | | | | | | | | This patch adds L2 Cache support for OMAP4. External L2 cache is used in OMAP4 CC: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5916/1: ARM: L2 : Add maintainace by line helper functionsSantosh Shilimkar2010-02-15
| | | | | | | | | This patch adds the cache maintainance by line helper functions. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5911/1: ARM: Select CPU_32v6K for CPU_V7 only if ARCH_OMAP2 is not selectedTony Lindgren2010-02-15
| | | | | | | | Otherwise the kernel built with both CPU_V6 and CPU_V7 will not boot on omap2. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5905/1: ARM: Global ASID allocation on SMPCatalin Marinas2010-02-15
| | | | | | | | | | | | | | | | The current ASID allocation algorithm doesn't ensure the notification of the other CPUs when the ASID rolls over. This may lead to two processes using the same ASID (but different generation) or multiple threads of the same process using different ASIDs. This patch adds the broadcasting of the ASID rollover event to the other CPUs. To avoid a race on multiple CPUs modifying "cpu_last_asid" during the handling of the broadcast, the ASID numbering now starts at "smp_processor_id() + 1". At rollover, the cpu_last_asid will be set to NR_CPUS. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5880/1: arm: use generic infrastructure for early paramsJeremy Kerr2010-02-15
| | | | | | | | | | | | | | | The ARM setup code includes its own parser for early params, there's also one in the generic init code. This patch removes __early_init (and related code) from arch/arm/kernel/setup.c, and changes users to the generic early_init macro instead. The generic macro takes a char * argument, rather than char **, so we need to update the parser functions a little. Signed-off-by: Jeremy Kerr <jeremy.kerr@canonical.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: Move creation of /proc/cpu out of alignment.cRussell King2010-02-15
| | | | | | | Always creating this directory avoids other users having to jump through silly hoops when they want to share this directory. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: Add caller information to ioremapRussell King2010-02-15
| | | | | | | | | This allows the procfs vmallocinfo file to show who created the ioremap regions. Note: __builtin_return_address(0) doesn't do what's expected if its used in an inline function, so we leave __arm_ioremap callers in such places alone. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2010-01-12
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master.kernel.org:/home/rmk/linux-2.6-arm: ARM: Ensure ARMv6/7 mm files are built using appropriate assembler options ARM: Fix wrong dmb ARM: 5874/1: serial21285: fix disable_irq-from-interrupt-handler deadlock ARM: 5873/1: ARM: Fix the reset logic for ARM RealView boards ARM: 5872/1: ARM: include needed linux/cpu.h in asm/cpu.h ARM: 5871/1: arch/arm: Fix build failure for lpd7a404_defconfig caused by missing includes ARM: 5870/1: arch/arm: Fix build failure for defconfigs without CONFIG_ISA_DMA_API set ARM: 5868/1: ARM: fix "BUG: using smp_processor_id() in preemptible code" ARM: 5867/1: Update U300 defconfig ARM: 5866/1: arm ptrace: use unsigned types for kernel pt_regs [ARM] pxa: fix strange characters in zaurus gpio .desc ARM: add missing recvmmsg syscall number [ARM] pxa: fix compiler warnings of unused variable 'id' in cpu_is_pxa9*() [ARM] pxa: update pwm_backlight->notify() to include missed 'struct device *' [ARM] pxa: enable L2 if present in XSC3 [ARM] pxa: do not enable L2 after MMU is enabled
| * ARM: Ensure ARMv6/7 mm files are built using appropriate assembler optionsRussell King2010-01-12
| | | | | | | | | | | | | | | | A kernel with both ARMv6 and ARMv7 selected results in build errors. Fix this by specifying the proper architectures for these assembly files. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * Merge branch 'fix' of ↵Russell King2010-01-08
| |\ | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6
| | * [ARM] pxa: enable L2 if present in XSC3Haojian Zhuang2010-01-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check whether L2 is present or not in XSC3. If it's present, enable L2 immediately. Disabling L2 after L2 is enabled that would result in unpredicatable behavior of XSC3 processor. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| | * [ARM] pxa: do not enable L2 after MMU is enabledHaojian Zhuang2010-01-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Outer cache checked whether L2 is enabled or not. If L2 isn't enabled in XSC3, it would enable L2. This operation is evil that would make system hang. In XSC3 core document, these words are mentioned in below. "Following reset, the L2 Unified Cache Enable bit is cleared. To enable the L2 Cache, software may set the bit to a '1' before or at the same time as enabling the MMU. Enabling the L2 Cache after the MMU has been enabled or disabling the L2 Cache after the L2 Cache has been enabled, may result in unpredictable behavior of the processor." When outer cache is initialized, the MMU is already enabled. We couldn't enable L2 after MMU enabled. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* | | mm: make totalhigh_pages unsigned longAndreas Fenkart2010-01-11
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Makes it consistent with the extern declaration, used when CONFIG_HIGHMEM is set Removes redundant casts in printout messages Signed-off-by: Andreas Fenkart <andreas.fenkart@streamunlimited.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: David Howells <dhowells@redhat.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Chen Liqin <liqin.chen@sunplusct.com> Cc: Lennox Wu <lennox.wu@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* / ARM: 5858/1: Remove unused vma_vm_flags macro from v7wbi_flush_user_tlb_rangeBahadir Balban2010-01-05
|/ | | | | Signed-off-by: Bahadir Balban <bbalban@b-labs.co.uk> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: fix PAGE_KERNELRussell King2009-12-24
| | | | | | | | PAGE_KERNEL should not be executable; any area marked executable can be prefetched into the instruction cache. We don't want vmalloc areas to be read in this way. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: Fix wrong shared bit for CPU write buffer bug testRussell King2009-12-23
| | | | | | | | It is unpredictable to have the same memory mapped using different shared bit settings for ARMv6 and ARMv7 CPUs. Fix this for the CPU write buffer bug test. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: Kill CONFIG_CPU_32Russell King2009-12-18
| | | | | | | | 26-bit ARM support was removed a long time ago, and this symbol has been defined to be 'y' ever since. As it's never disabled anymore, we can kill it without any side effects. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 5853/1: ARM: Fix build break on ARM v6 and v7Anand Gadiyar2009-12-18
| | | | | | | | | | | | | | | | | | Commit 2c9b9c849 added an argument to __cpuc_flush_dcache_page and renamed it. Update a caller of the old function to fix this build error: CC arch/arm/mm/copypage-v6.o arch/arm/mm/copypage-v6.c: In function 'v6_copy_user_highpage_nonaliasing': arch/arm/mm/copypage-v6.c:51: error: implicit declaration of function '__cpuc_flush_dcache_page' make[1]: *** [arch/arm/mm/copypage-v6.o] Error 1 make: *** [arch/arm/mm] Error 2 Reported-by: Jinsung Yang <jsgood.yang@samsung.com> Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'cache' (early part)Russell King2009-12-17
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| * Merge branch 'pending-l2x0' into cacheRussell King2009-12-14
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| | * ARM: cache-l2x0: make better use of background cache handlingRussell King2009-12-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's no point having the hardware support background operations if we issue a cache operation, and then wait for it to complete before calculating the address of the next operation. We gain no advantage in the cache controller stalling the bus until completion. What we should be doing is using the 'wait' time productively by calculating the address of the next operation, and only then waiting for the previous operation to complete. This means that cache operations can occur in parallel with the CPU calculating the next address. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
| | * ARM: cache-l2x0: avoid taking spinlock for every iterationRussell King2009-12-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | Taking the spinlock for every iteration is very expensive; instead, batch iterations up into 4K blocks, releasing and reacquiring the spinlock between each block. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
| * | ARM: add size argument to __cpuc_flush_dcache_pageRussell King2009-12-14
| | | | | | | | | | | | | | | | | | | | | ... and rename the function since it no longer operates on just pages. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 5848/1: kill flush_ioremap_region()Nicolas Pitre2009-12-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is not enough users to warrant its existence, and it is actually an obstacle to progress with the new DMA API which cannot cover this case properly. To keep backward compatibility, let's perform the necessary custom cache maintenance locally in the only driver affected. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | Merge branch 'for-rmk' of git://git.marvell.com/orionRussell King2009-12-16
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| * | | ARM: dove: fix the mm mmu flags of the pj4 procinfoSaeed Bishara2009-12-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ... to be the same as proc-v6 Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
* | | | fix broken aliasing checks for MAP_FIXED on sparc32, mips, arm and shAl Viro2009-12-11
| |/ / |/| | | | | | | | | | | | | | | | | | | | We want addr - (pgoff << PAGE_SHIFT) consistently coloured... Acked-by: Paul Mundt <lethal@linux-sh.org> Acked-by: Hugh Dickins <hugh.dickins@tiscali.co.uk> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* | | Merge branch 'devel-stable' into develRussell King2009-12-05
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| * \ \ Merge branch 'devel' of ↵Russell King2009-12-04
| |\ \ \ | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel-stable
| | * | | [ARM] pxa/treo: add Palm Centro 685 supportTomáš Čech2009-11-30
| | | |/ | | |/| | | | | | | | | | | | | Signed-off-by: Tomáš Čech <sleep_walker@suse.cz> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| * | | Merge branch 'for-rmk' of git://git.marvell.com/orion into devel-stableRussell King2009-12-01
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| | * | ARM: Add Tauros2 L2 cache controller supportLennert Buytenhek2009-11-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support for the Tauros2 L2 cache controller as used with the PJ1 and PJ4 CPUs. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
| | * | ARM: add base support for Marvell Dove SoCSaeed Bishara2009-11-27
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Marvell Dove (88AP510) is a high-performance, highly integrated, low power SoC with high-end ARM-compatible processor (known as PJ4), graphics processing unit, high-definition video decoding acceleration hardware, and a broad range of peripherals. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
| * | Merge branch 'next' of ↵Russell King2009-11-20
| |\ \ | | |/ | |/| | | | git://git.kernel.org/pub/scm/linux/kernel/git/djbw/xscaleiop into devel-stable
| | * iop: implement sched_clock()Mikael Pettersson2009-10-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a better sched_clock() to the IOP platform, implemented using its new clocksource support. Tested on n2100, compile-tested for all plat-iop machines. [dan.j.williams@intel.com: allow early cp6 access] Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* | | Merge branch 'pending-dma-coherent' into develRussell King2009-12-04
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| * | | ARM: dma-mapping: switch ARMv7 DMA mappings to retain 'memory' attributeRussell King2009-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On ARMv7, it is invalid to map the same physical address multiple times with different memory types. Since system RAM is already mapped as 'memory', subsequent remapping of it must retain this attribute. However, DMA memory maps it as "strongly ordered". Fix this by introducing 'pgprot_dmacoherent()' which provides the necessary page table bits for DMA mappings. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
| * | | ARM: dma-mapping: get rid of setting/clearing the reserved page bitRussell King2009-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's unnecessary; x86 doesn't do it, and ALSA doesn't require it anymore. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org>
| * | | ARM: dma-mapping: Factor out noMMU dma buffer allocation codeRussell King2009-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This entirely separates the DMA coherent buffer remapping code from the allocation code, and gets rid of the duplicate copy in the !MMU section. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org>
| * | | ARM: dma-mapping: clean up coherent arch dma allocationRussell King2009-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IXP23xx added support for dma_alloc_coherent() for DMA arches with an exception in dma_alloc_coherent(). This is a subset of what goes on in __dma_alloc(), and there is no reason why dma_alloc_writecombine() should not be given the same treatment (except, maybe, that IXP23xx doesn't use it.) We can better deal with this by moving the arch_is_coherent() test inside __dma_alloc() and killing the code duplication. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org>
| * | | ARM: dma-mapping: move consistent_init into CONFIG_MMU sectionRussell King2009-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No point wrapping the contents of this function with #ifdef CONFIG_MMU when we can place it and the core_initcall() entirely within the existing conditional block. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org>
| * | | ARM: dma-mapping: factor dma_free_coherent() common codeRussell King2009-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We effectively have three implementations of dma_free_coherent() mixed up in the code; the incoherent MMU, coherent MMU and noMMU versions. The coherent MMU and noMMU versions are actually functionally identical. The incoherent MMU version is almost the same, but with the additional step of unmapping the secondary mapping. Separate out this additional step into __dma_free_remap() and simplify the resulting dma_free_coherent() code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org>
| * | | ARM: dma-mapping: fix nommu dma_alloc_coherent()Russell King2009-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The nommu version of dma_alloc_coherent was using kmalloc/kfree to manage the memory. dma_alloc_coherent() is expected to work with a granularity of a page, so this is wrong. Fix it by using the helper functions now provided. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org>
| * | | ARM: dma-mapping: fix coherent arch dma_alloc_coherent()Russell King2009-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The coherent architecture dma_alloc_coherent was using kmalloc/kfree to manage the memory. dma_alloc_coherent() is expected to work with a granularity of a page, so this is wrong. Fix it by using the helper functions now provided. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org>
| * | | ARM: dma-mapping: functions to allocate/free a coherent bufferRussell King2009-11-24
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org>
| * | | ARM: dma-mapping: split out vmregion code from dma coherent mapping codeRussell King2009-11-24
| |/ / | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Greg Ungerer <gerg@uclinux.org>
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 11:28:47 -0400