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* Merge branch 'next/devel2' of ↵Linus Torvalds2011-07-26
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc * 'next/devel2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (47 commits) OMAP: Add debugfs node to show the summary of all clocks OMAP2+: hwmod: Follow the recommended PRCM module enable sequence OMAP2+: clock: allow per-SoC clock init code to prevent clockdomain calls from clock code OMAP2+: clockdomain: Add per clkdm lock to prevent concurrent state programming OMAP2+: PM: idle clkdms only if already in idle OMAP2+: clockdomain: add clkdm_in_hwsup() OMAP2+: clockdomain: Add 2 APIs to control clockdomain from hwmod framework OMAP: clockdomain: Remove redundant call to pwrdm_wait_transition() OMAP4: hwmod: Introduce the module control in hwmod control OMAP4: cm: Add two new APIs for modulemode control OMAP4: hwmod data: Add modulemode entry in omap_hwmod structure OMAP4: hwmod data: Add PRM context register offset OMAP4: prm: Remove deprecated functions OMAP4: prm: Replace warm reset API with the offset based version OMAP4: hwmod: Replace RSTCTRL absolute address with offset macros OMAP: hwmod: Wait the idle status to be disabled OMAP4: hwmod: Replace CLKCTRL absolute address with offset macros OMAP2+: hwmod: Init clkdm field at boot time OMAP4: hwmod data: Add clock domain attribute OMAP4: clock data: Add missing divider selection for auxclks ...
| *---. Merge branches 'omap4_clockdomain_hwmod_3.1', 'clock_debugfs_a_3.1', ↵Paul Walmsley2011-07-10
| |\ \ \ | | | | | | | | | | | | | | | 'omap4_clock_auxclk_3.1' and 'omap_device_a_3.1' into prcm-devel-3.1
| | | | * OMAP: omap_device: Create clkdev entry for hwmod main_clkBenoit Cousson2011-07-10
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend the existing function to create clkdev for every optional clocks to add a well one "fck" alias for the main_clk of the omap_hwmod. It will allow to remove these static clkdev entries from the clockXXX_data.c file. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@ti.com> Cc: Todd Poynor <toddpoynor@google.com> [paul@pwsan.com: remove all of the "fck" role clkdev aliases from the clock data files; fixed error message] Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * OMAP4: clock data: Add missing divider selection for auxclksRajendra Nayak2011-07-10
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On OMAP4 the auxclk nodes (part of SCRM) support both divider as well as parent selection. Supporting this requires splitting the existing nodes (which support only parent selection) into two nodes, one for parent and another for divider selection. The nodes for parent selection are named auxclk*_src_ck and the ones for divider selection as auxclk*_ck. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [b-cousson@ti.com: Rebase on top of clock cleanup and autogen alignement] Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * / OMAP2+: hwmod: Follow the recommended PRCM module enable sequenceRajendra Nayak2011-07-10
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On OMAP4, the PRCM recommended sequence for enabling a module after power-on-reset is: -1- Force clkdm to SW_WKUP -2- Enabling the clocks -3- Configure desired module mode to "enable" or "auto" -4- Wait for the desired module idle status to be FUNC -5- Program clkdm in HW_AUTO(if supported) This sequence applies to all older OMAPs' as well, however since they use autodeps, it makes sure that no clkdm is in IDLE, and hence not requiring a force SW_WKUP when a module is being enabled. OMAP4 does not need to support autodeps, because of the dyanamic dependency feature, wherein the HW takes care of waking up a clockdomain from idle and hence the module, whenever an interconnect access happens to the given module. Implementing the sequence for OMAP4 requires the clockdomain handling that is currently done in clock framework to be done as part of hwmod framework since the step -4- above to "Wait for the desired module idle status to be FUNC" is done as part of hwmod framework. Signed-off-by: Rajendra Nayak <rnayak@ti.com> [b-cousson@ti.com: Adapt it to the new clkdm hwmod attribute and API] Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> [paul@pwsan.com: dropped mach-omap2/clock.c changes; modified to only call the clockdomain code if oh->clkdm is set; disable clock->clockdomain interaction on OMAP4] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | Merge branch 'next/fixes2' of ↵Linus Torvalds2011-07-26
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc * 'next/fixes2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (24 commits) ASoC: omap: McBSP: fix build breakage on OMAP1 OMAP: hwmod: fix the i2c-reset timeout during bootup I2C: OMAP2+: add correct functionality flags to all omap2plus i2c dev_attr I2C: OMAP2+: Tag all OMAP2+ hwmod defintions with I2C IP revision I2C: OMAP1/OMAP2+: create omap I2C functionality flags for each cpu_... test I2C: OMAP2+: Introduce I2C IP versioning constants I2C: OMAP2+: increase omap_i2c_dev_attr flags from u8 to u32 I2C: OMAP2+: Set hwmod flags to only allow 16-bit accesses to i2c OMAP4: hwmod data: Change DSS main_clk scheme OMAP4: powerdomain data: Remove unsupported MPU powerdomain state OMAP4: clock data: Keep GPMC clocks always enabled and hardware managed OMAP4: powerdomain data: Fix core mem states and missing cefuse flag OMAP2+: PM: Initialise sleep_switch to a non-valid value OMAP4: hwmod data: Modify DSS opt clocks OMAP4: iommu: fix clock name omap: iovmm: s/sg_dma_len(sg)/sg->length/ omap: iommu: fix pte programming arm: omap3: cm-t35: fix slow path warning arm: omap3: cm-t35: minor comments fixes omap: ZOOM: QUART: Request reset GPIO ...
| *-. Merge branches 'powerdomain_fixes_3.1', 'hardware_workarounds_3.1', ↵Paul Walmsley2011-07-10
| |\ \ | | | | | | | | | | | | 'hwmod_dss_fix_3.1' and 'i2c_fixes_3.1' into prcm-fixes-3.1
| | | * OMAP4: hwmod data: Modify DSS opt clocksTomi Valkeinen2011-07-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing DSS optional clocks to HWMOD data for OMAP4xxx. Add HWMOD_CONTROL_OPT_CLKS_IN_RESET flag for dispc to fix dispc reset. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> [b-cousson@ti.com: Remove a comment and update the subject] Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> [paul@pwsan.com: removed DSS "fck" role and some clkdev aliases at Tomi's request] Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * | OMAP4: clock data: Keep GPMC clocks always enabled and hardware managedSantosh Shilimkar2011-07-09
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On OMAP4, CPU accesses on unmapped addresses are redirected to GPMC by L3 interconnect. Because of CPU speculative nature, such accesses are possible which can lead to indirect access to GPMC and if it's clock is not running, it can result in hang/abort on the platform. Above makes access to GPMC unpredictable during the execution, so it's module mode needs to be kept under hardware control instead of software control. Since the auto gating is supported for GPMC, there isn't any power impact because of this change. The issue was un-covered with security middleware running along with HLOS. In this case GPMC had a valid MMU descriptor on secure side where as HLOS didn't map the GMPC because it isn't being used. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [b-cousson@ti.com: Update subject and fix typos in the changelog] Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Kevin Hilman <khilman@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | | Merge branch 'next/soc' of ↵Linus Torvalds2011-07-26
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc * 'next/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: MAINTAINERS: add maintainer of CSR SiRFprimaII machine ARM: CSR: initializing L2 cache ARM: CSR: mapping early DEBUG_LL uart ARM: CSR: Adding CSR SiRFprimaII board support OMAP4: clocks: Update the clock tree with 4460 clock nodes OMAP4: PRCM: OMAP4460 specific PRM and CM register bitshifts OMAP4: ID: add omap_has_feature for max freq supported OMAP: ID: introduce chip detection for OMAP4460 ARM: Xilinx: merge board file into main platform code ARM: Xilinx: Adding Xilinx board support Fix up conflicts in arch/arm/mach-omap2/cm-regbits-44xx.h
| * | OMAP4: clocks: Update the clock tree with 4460 clock nodesRajendra Nayak2011-07-08
| |/ | | | | | | | | | | | | | | | | | | | | | | Add the new clock nodes (bandgap_ts_fclk, div_ts_ck) for omap4460. Handle these nodes using the clock flags (CK_*). Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | OMAP4: clock data: Remove UNIPRO clock nodesJon Hunter2011-07-09
| | | | | | | | | | | | | | | | | | | | | | | | UNIPRO was removed from OMAP4 devices from ES2.0 onwards. Since this IP was anyway non-functional and not supported, it is best to remove it completely. Signed-off-by: Jon Hunter <jon-hunter@ti.com> [b-cousson@ti.com: Update the changelog] Signed-off-by: Benoit Cousson <b-cousson@ti.com> [paul@pwsan.com: split PRCM header file changes into a separate patch] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | OMAP4: clock data: Remove McASP2, McASP3 and MMC6 clocksJon Hunter2011-07-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | McASP2, 3 and MMC6 modules are not present in the OMAP4 family. Remove the fclk and the clksel related to these nodes. Rename the references that were potentially re-used in order nodes. Remove related macros in prcm header files. Update TI copyright date. Signed-off-by: Jon Hunter <jon-hunter@ti.com> [b-cousson@ti.com: Update the patch according to autogen output] Signed-off-by: Benoit Cousson <b-cousson@ti.com> [paul@pwsan.com: split PRCM data changes into a separate patch] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | OMAP4: clock data: Fix max mult and div for USB DPLLBenoit Cousson2011-07-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DPLL USB can generate higher speed (x2) than the regular ones. The max multiplication value is then twice the previous value. Fix both max_mult and max_div with that correct values. Change the max_div variable type to u16 to allow storing up to 256. Replace as well the define with the value to avoid unneeded indirection and provide a better readability. Remove the defines that become useless. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | OMAP4: clock data: Re-order some clock nodes and structure fieldsBenoit Cousson2011-07-09
| | | | | | | | | | | | | | | | | | | | | | | | | | A couple of fieds were edited manually and thus do not stick to the template used by the generator and by other structures. Move them to the correct location. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> [paul@pwsan.com: dropped the UNIPRO changes since those will be removed in a later patch] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | OMAP4: clock data: Remove usb_host_fs clkdev with NULL devBenoit Cousson2011-07-09
| | | | | | | | | | | | | | | | | | | | | | usb_host_fs_fck does have a clkdev mapping with "usbhs-omap.0" and "fs_fck" alias used by the driver. The entry with NULL dev is thus not needed anymore. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Felipe Balbi <balbi@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | OMAP4: clock data: Add sddiv to USB DPLLBenoit Cousson2011-07-09
|/ | | | | | | | | | The USB DPLL is a J-Type DPLL with the sddiv extra parameter. Add it in USB DPLL. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> [paul@pwsan.com: dropped UNIPRO change since it is removed in a later patch] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP4: clock data: Change DSS clock aliasesTomi Valkeinen2011-04-20
| | | | | | | | | | | | | | | | | | | | | | DSS driver has used fck and ick clocks on OMAP2/3 to get DSS HW up and running, and also to get the pixel clock's source clock rate from the fck. On OMAP4 the clock data is set up in a different way, as there's no ick, dss_fck points to a fake clock which just affects DSS's MODULEMODE, and dss_dss_clk if the DSS_FCK. >From DSS driver's point of view the dss_fck sounds like an ick, and dss_dss_clk is the fck. While this is not entirely correct from HW point of view, especially for the ick, configuring the clock aliases that way makes DSS "just work" with OMAP4's clock setup. In the (hopefully near) future DSS driver will be reworked to use pm_runtime support which should clean up the clock code. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Benoît Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* Merge branch 'for-paul' of git://gitorious.org/linux-omap-dss2/linuxPaul Mundt2011-03-22
|\ | | | | | | | | | | | | Conflicts: arch/arm/mach-omap2/board-overo.c Signed-off-by: Paul Mundt <lethal@linux-sh.org>
| * OMAP4: DSS2: clocks: Add ick as dummy clockSumit Semwal2011-03-11
| | | | | | | | | | | | | | | | | | | | | | | | DSS code uses ick as one of the clocks in clk_get/clk_put. OMAP4 clock database doesn't have ick for DSS, so adding ick as dummy clock. This is needed for backward compatibility with OMAP2/3. Once pm_runtime* APIs get introduced in DSS, this will be revisited. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
| * OMAP2PLUS: clocks: Align DSS clock names and rolesSumit Semwal2011-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, clock database has <dev, clock-name> tuples for DSS2. Because of this, the clock names are different across different OMAP platforms. This patch aligns the DSS2 clock names and roles across OMAP 2420, 2430, 3xxx, 44xx platforms in the clock databases, hwmod databases for opt-clocks, and DSS clock handling. This ensures that clk_get/put/enable/disable APIs in DSS can use uniform role names. Signed-off-by: Sumit Semwal <sumit.semwal@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
* | Merge branch 'omap-for-linus' of ↵Linus Torvalds2011-03-17
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 * 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (258 commits) omap: zoom: host should not pull up wl1271's irq line arm: plat-omap: iommu: fix request_mem_region() error path OMAP2+: Common CPU DIE ID reading code reads wrong registers for OMAP4430 omap4: mux: Remove duplicate mux modes omap: iovmm: don't check 'da' to set IOVMF_DA_FIXED flag omap: iovmm: disallow mapping NULL address when IOVMF_DA_ANON is set omap2+: mux: Fix compile when CONFIG_OMAP_MUX is not selected omap4: board-omap4panda: Initialise the serial pads omap3: board-3430sdp: Initialise the serial pads omap4: board-4430sdp: Initialise the serial pads omap2+: mux: Add macro for configuring static with omap_hwmod_mux_init omap2+: mux: Remove the use of IDLE flag omap2+: Add separate list for dynamic pads to mux perf: add OMAP support for the new power events OMAP4: Add IVA OPP enteries. OMAP4: Update Voltage Rail Values for MPU, IVA and CORE OMAP4: Enable 800 MHz and 1 GHz MPU-OPP OMAP3+: OPP: Replace voltage values with Macros OMAP3: wdtimer: Fix CORE idle transition Watchdog: omap_wdt: add fine grain runtime-pm ... Fix up various conflicts in - arch/arm/mach-omap2/board-omap3evm.c - arch/arm/mach-omap2/clock3xxx_data.c - arch/arm/mach-omap2/usb-musb.c - arch/arm/plat-omap/include/plat/usb.h - drivers/usb/musb/musb_core.h
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| *-. | Merge remote branches 'remotes/origin/pwrdm_clkdm_b_2.6.39', ↵Paul Walmsley2011-03-11
| |\ \| | | | | | | | | | | | | 'remotes/origin/pwrdm_add_can_lose_context_fns_2.6.39', 'remotes/origin/omap_device_a_2.6.39', 'remotes/origin/mmc_a_2.6.39', 'remotes/origin/hwmod_b_2.6.39', 'remotes/origin/dmtimer_a_2.6.39', 'remotes/origin/pwrdm_clkdm_a_2.6.39', 'remotes/origin/clkdm_statdep_omap4_2.6.39', 'remotes/origin/clk_a_2.6.39', 'remotes/origin/clk_autoidle_a_2.6.39', 'remotes/origin/clk_autoidle_b_2.6.39', 'remotes/origin/clk_b_2.6.39', 'remotes/origin/clk_clkdm_a_2.6.39', 'remotes/origin/misc_a_2.6.39', 'remotes/origin/for_2.6.39/omap3_hwmod_data' and 'remotes/origin/wdtimer_a_2.6.39' into tmp-integration-2.6.39-20110310-024
| | | * OMAP: hsmmc: Rename the device and driverKishore Kadiyala2011-03-01
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | Modifying the device & driver name from "mmci-omap-hs" to "omap_hsmmc". Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com> Acked-by: Benoit Cousson<b-cousson@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * OMAP2+: clock: disable autoidle on all clocks during clock initPaul Walmsley2011-02-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disable autoidle on all clocks during clock framework initialization. (If CONFIG_PM is set, autoidle is re-enabled for all clocks later in the boot process.) The principle behind this patch, and some similar patches, is that the kernel should start with all power management features disabled. Later in the boot process, the PM code, if compiled in with CONFIG_PM, enables or re-enables power management features. Signed-off-by: Paul Walmsley <paul@pwsan.com> Tested-by: Rajendra Nayak <rnayak@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com>
| | * omap4: dpll: Enable auto gate control for all MX postdividersRajendra Nayak2011-02-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable hardware gate control for all dpll MX and X2 postdividers. This requires the allow_idle/deny_idle functions to be populated for all clock nodes (mx/x2 post dividers) in clkops. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | * OMAP3/4: DPLL: Add allow_idle/deny_idle support for all DPLL'sRajendra Nayak2011-02-25
| |/ | | | | | | | | | | | | | | | | All OMAP3/4 dpll's support hardware level autogating. Populate allow_idle/deny_idle function pointers for all DPLL's in clkops. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* / arm: omap: usb: clock entries for omap3 and omap4Keshava Munegowda2011-03-01
|/ | | | | | | | | | | The devices of clocks are set to usbhs, so that only usbhs common driver can invoke these clocks. The dummy per port clocks are added to omap3 clock data base. This helps to invoke common clock get APIs for omap3 and omap4. Signed-off-by: Keshava Munegowda <keshava_mgowda@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
* OMAP: PRCM: remove duplicated headersFelipe Balbi2011-01-18
| | | | | | | | | | | | | | | | | | | | | A few headers are included twice, remove them. Found the following errors using make includecheck: arch/arm/mach-omap2/clock44xx_data.c: prm44xx.h is included more than once. arch/arm/mach-omap2/clockdomains44xx_data.c: cm1_44xx.h is included more than once. arch/arm/mach-omap2/clockdomains44xx_data.c: cm2_44xx.h is included more than once. arch/arm/mach-omap2/powerdomain2xxx_3xxx.c: prm-regbits-34xx.h is included more than once. Cc: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Felipe Balbi <balbi@ti.com> [paul@pwsan.com: dropped lists from patch cc:s; tweaked subject line] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* Merge branch 'usb-next' of ↵Linus Torvalds2011-01-07
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6 * 'usb-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6: (144 commits) USB: add support for Dream Cheeky DL100B Webmail Notifier (1d34:0004) USB: serial: ftdi_sio: add support for TIOCSERGETLSR USB: ehci-mxc: Setup portsc register prior to accessing OTG viewport USB: atmel_usba_udc: fix freeing irq in usba_udc_remove() usb: ehci-omap: fix tll channel enable mask usb: ohci-omap3: fix trivial typo USB: gadget: ci13xxx: don't assume that PAGE_SIZE is 4096 USB: gadget: ci13xxx: fix complete() callback for no_interrupt rq's USB: gadget: update ci13xxx to work with g_ether USB: gadgets: ci13xxx: fix probing of compiled-in gadget drivers Revert "USB: musb: pm: don't rely fully on clock support" Revert "USB: musb: blackfin: pm: make it work" USB: uas: Use GFP_NOIO instead of GFP_KERNEL in I/O submission path USB: uas: Ensure we only bind to a UAS interface USB: uas: Rename sense pipe and sense urb to status pipe and status urb USB: uas: Use kzalloc instead of kmalloc USB: uas: Fix up the Sense IU usb: musb: core: kill unneeded #include's DA8xx: assign name to MUSB IRQ resource usb: gadget: g_ncm added ... Manually fix up trivial conflicts in USB Kconfig changes in: arch/arm/mach-omap2/Kconfig arch/sh/Kconfig drivers/usb/Kconfig drivers/usb/host/ehci-hcd.c and annoying chip clock data conflicts in: arch/arm/mach-omap2/clock3xxx_data.c arch/arm/mach-omap2/clock44xx_data.c
| * usb: musb: move clock handling to glue layerFelipe Balbi2010-12-10
| | | | | | | | | | | | | | | | | | musb core doesn't need to know about platform specific details. So start moving clock handling to platform glue layer and make musb core agnostic about that. Signed-off-by: Felipe Balbi <balbi@ti.com>
| * usb: musb: trivial search and replace patchFelipe Balbi2010-12-10
| | | | | | | | | | | | | | | | | | | | change all ocurrences of musb_hdrc to musb-hdrc. We will call glue layer drivers musb-<glue layer>, so in order to keep things somewhat standard, let's change the underscore into a dash. Signed-off-by: Felipe Balbi <balbi@ti.com>
| * omap: clock: add clkdev aliases for EHCI clocksAnand Gadiyar2010-11-30
| | | | | | | | | | | | | | | | | | | | | | | | Add clkdev aliases for the USBHOST and USBTLL clocks on OMAP3 and OMAP4, so that the driver can refer to the clocks using a common alias. This will disappear when the driver is converted to use the hwmod database, but until then this patch is needed. Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Acked-by: Tony Lindgren <tony@atomide.com>
* | OMAP4: clock data: Add missing fixed divisorsJon Hunter2010-12-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following OMAP4 clocks have the following fixed divisors that determine the frequency at which these clocks operate. These dividers are defined by the PRCM specification and without these dividers the rates of the below clocks are calculated incorrectly. This may cause internal peripherals using these clocks to operate at the wrong frequency. - abe_24m_fclk (freq = divided-by-8) - ddrphy_ck (freq = parent divided-by-2) - dll_clk_div_ck (freq = parent divided-by-2) - per_hs_clk_div_ck (freq = parent divided-by-2) - usb_hs_clk_div_ck (freq = parent divided-by-3) - func_12m_fclk (freq = parent divided-by-16) - func_24m_clk (freq = parent divided-by-4) - func_24mc_fclk (freq = parent divided-by-8) - func_48mc_fclk (freq = divided-by-4) - lp_clk_div_ck (freq = divided-by-16) - per_abe_24m_fclk (freq = divided-by-4) Signed-off-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Rajendra Nayak <rnayak@ti.com>
* | OMAP4: clock data: Keep L3INSTR clock domain modulemode under HW controlSantosh Shilimkar2010-12-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | L3INSTR clock domain is read only register and its reset value is HW_AUTO. The modules withing this clock domain needs to be kept under hardware control. MODULEMODE: - 0x0: Module is disable by software. Any INTRCONN access to module results in an error, except if resulting from a module wakeup (asynchronous wakeup). - 0x1: Module is managed automatically by hardware according to clock domain transition. A clock domain sleep transition put module into idle. A wakeup domain transition put it back into function. If CLKTRCTRL=3, any INTRCONN access to module is always granted. Module clocks may be gated according to the clock domain state. This patch keeps CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL and CM_L3INSTR_INTRCONN_WP1_CLKCTRL module mode under hardware control by using ENABLE_ON_INIT flag. Without this the OMAP4 device OFF mode SAR restore phase aborts during interconnect register restore phase. This can be also handled by doing explicit a clock enable and disable in the low power code since there is no direct module associated with it. But that seems not necessary since the clock domain is under HW control. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | OMAP4: clocks: add dummy clock for mailboxHari Kanigeri2010-12-21
| | | | | | | | | | | | | | | | | | | | In omap4, there is no explicit configuration register to enable mailbox clocks. Defining dummy clock for mailbox clock module to keep the mailbox driver backward compatible with previous omaps. Signed-off-by: Hari Kanigeri <h-kanigeri2@ti.com> Acked-by: Benoît Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | OMAP: clock: fix configuration of J-Type DPLLs to work for OMAP3 and OMAP4Jon Hunter2010-12-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | J-Type DPLLs have additional configuration parameters that need to be programmed when setting the multipler and divider for the DPLL. These parameters being the sigma delta divider (SD_DIV) for the DPLL and the digital controlled oscillator (DCO) to be used by the DPLL. The current code is implemented specifically to configure the OMAP3630 PER J-Type DPLL. The OMAP4430 USB DPLL is also a J-Type DPLL and so this code needs to be updated to work for both OMAP3 and OMAP4 devices and any other future devices that have J-TYPE DPLLs. For the OMAP3630 PER DPLL both the SD_DIV and DCO paramenters are used but for the OMAP4430 USB DPLL only the SD_DIV field is used. The current implementation will only program the SD_DIV and DCO fields if the DPLL has both and hence this does not work for OMAP4430. In order to make the code more generic add two new fields to the dpll_data structure for the SD_DIV field and DCO field bit-masks and only program these fields if the masks are defined for a specific DPLL. This simplifies the code and allows us to remove the flag DPLL_NO_DCO_SEL. Tested on OMAP36xx Zoom3 and OMAP4 Blaze. Signed-off-by: Jon Hunter <jon-hunter@ti.com> [paul@pwsan.com: removed explicit inlining and added '_' prefix on lookup_*() functions; added testing info to commit message; added 35xx comments back in] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | OMAP4: hwmod & clock data: Fix GPIO opt_clks and ocp_if iclkBenoit Cousson2010-12-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix opt clocks name in clock framework and hwmod. Add the missing iclk in the ocp_if structure. Add the HWMOD_CONTROL_OPT_CLKS_IN_RESET flag to ensure the the GPIO optional clock is enable during reset. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Tested-by: Charulatha V <charu@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com>
* | OMAP4: clock data: Export control to enable/disable CORE/PER M3 clocksRajendra Nayak2010-12-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CORE and PER M3 post dividers are different from the rest of the DPLL post dividers as in they go to SCRM, and are used there to export clocks for instance used by external sensor. There is no automatic HW dependency in PRCM to manage them. Hence these two clocks (dpll post dividers) should be managed by SW and explicitly enabled/disabled. Add control in clock framework to handle that. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | OMAP4: clock data: Add SCRM auxiliary clock nodesRajendra Nayak2010-12-21
| | | | | | | | | | | | | | | | Add support for auxiliary clocks nodes which are part of SCRM. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | OMAP4: clock data: Add missing fields in iva_hsd_byp_clk_mux_ckJonathan Bergsagel2010-12-21
| | | | | | | | | | | | | | | | | | | | Add register address, mask and link to the clksel structure that were missing in the IVA DPLL mux clock node. Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com>
* | OMAP4: clock data: Add missing DPLL x2 clock nodesThara Gopinath2010-12-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch extends the OMAP4 clock data to include various x2 clock nodes between DPLL and HS dividers as the clock framework skips a x2 while calculating the dpll locked frequency. The clock database extensions are autogenerated using the scripts maintained by Benoit Cousson. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Thara Gopinath <thara@ti.com> [paul@pwsan.com: fixed merge conflicts against v2.6.37-rc5; dropped dpll_mpu_x2_ck on advice from Benoît] Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com>
* | OMAP4: clock data: Add control for pad_clks_ck and slimbus_clkBenoit Cousson2010-12-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gating of pad_clks and slimbus_ck is controlled by the PRCM, but since the clock source is external, this is the SW responsability to gate / un-gate it when the mcpdm or slimbus module need to be used. There is no autogating possible with such external clock. Add SW control to enable / disable this SW gating in the pad_clks_ck and slimbus_clk clock node. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Sebastien Guiriec <s-guiriec@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com>
* | OMAP2/3: PRCM: split OMAP2/3-specific PRCM code into OMAP2/3-specific filesPaul Walmsley2010-12-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for adding OMAP4-specific PRCM accessor/mutator functions, split the existing OMAP2/3 PRCM code into OMAP2/3-specific files. Most of what was in mach-omap2/{cm,prm}.{c,h} has now been moved into mach-omap2/{cm,prm}2xxx_3xxx.{c,h}, since it was OMAP2xxx/3xxx-specific. This process also requires the #includes in each of these files to be changed to reference the new file name. As part of doing so, add some comments into plat-omap/sram.c and plat-omap/mcbsp.c, which use "sideways includes", to indicate that these users of the PRM/CM includes should not be doing so. Thanks to Felipe Contreras <felipe.contreras@gmail.com> for comments on this patch. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Jarkko Nikula <jhnikula@gmail.com> Cc: Peter Ujfalusi <peter.ujfalusi@nokia.com> Cc: Liam Girdwood <lrg@slimlogic.co.uk> Cc: Omar Ramirez Luna <omar.ramirez@ti.com> Acked-by: Omar Ramirez Luna <omar.ramirez@ti.com> Cc: Felipe Contreras <felipe.contreras@gmail.com> Acked-by: Felipe Contreras <felipe.contreras@gmail.com> Cc: Greg Kroah-Hartman <greg@kroah.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Reviewed-by: Kevin Hilman <khilman@deeprootsystems.com> Tested-by: Kevin Hilman <khilman@deeprootsystems.com> Tested-by: Rajendra Nayak <rnayak@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
* | OMAP4: PRCM: reorganize existing OMAP4 PRCM header filesPaul Walmsley2010-12-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split the existing cm44xx.h file into cm1_44xx.h and cm2_44xx.h files so they match their underlying OMAP hardware modules. Add clockdomain offset information. Add header files for the MPU local PRCM, prcm_mpu44xx.h, and for the SCRM, scrm44xx.h. SCRM register offsets still need to be added; TI should do this. Move the "_MOD" macros out of the prcm-common.h header file, into the header file of the hardware module that they belong to. For example, OMAP4430_PRM_*_MOD macros have been moved into the prm44xx.h header. Adjust #includes of all files that used the old PRCM header file names to point to the new filenames. The autogeneration scripts have been updated accordingly. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Reviewed-by: Kevin Hilman <khilman@deeprootsystems.com> Tested-by: Kevin Hilman <khilman@deeprootsystems.com> Tested-by: Rajendra Nayak <rnayak@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
* | I2C: i2c-omap: Change device name: i2c_omap -> omap_i2cBenoit Cousson2010-12-20
|/ | | | | | | | | | | | | | | | | The convention for omap device naming is omap_XXX. Rename the device and driver name in order to stick to this naming convention. Change device name in clock nodes as well. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Ben Dooks <ben-i2c@fluff.org> Acked-by: Paul Walmsley <paul@pwsan.com> Acked-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
* OMAP: control: move plat-omap/control.h to mach-omap2/control.hPaul Walmsley2010-10-08
| | | | | | | | | | | | | | | | | Only OMAP2+ platforms have the System Control Module (SCM) IP block. In the past, we've kept the SCM header file in plat-omap. This has led to abuse - device drivers including it; includes being added that create implicit dependencies on OMAP2+ builds; etc. In response, move the SCM headers into mach-omap2/. As part of this, remove the direct SCM access from the OMAP UDC driver. It was clearly broken. The UDC code needs an indepth review for use on OMAP2+ chips. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Cory Maccarrone <darkstar6262@gmail.com> Cc: Kyungmin Park <kyungmin.park@samsung.com>
* OMAP4: clocks: Fix ES2 clock issuesBenoit Cousson2010-09-27
| | | | | | | | | | | | | | | | | | Fix a few OMAP4430 clock tree problems after the recent manual merge of the various ES2 clock patches: - usim optional clock and its parent had the same name, rename the parent usim_fclk -> usim_ck - OPTFCLKEN_CLK32K is not handled anymore by the USBPHYOCP2SCP module in ES2 Create a new clock that belongs to CM_ALWON_USBPHY_CLKCTRL register This patch depends on some of the PRCM macro updates from Rajendra. Signed-off-by: Benoit Cousson <b-cousson@ti.com> [paul@pwsan.com: tweaked patch description] Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com>
* OMAP4: clock: Add optional clock nodesBenoit Cousson2010-09-27
| | | | | | | | | | | | | | | | | OMAP4 IP optional clocks require explicit enable in module CTRLCLK register. In order to allow that we have to create artificial clock nodes that represent this clock inputs in the IP. Notes: - Temporary use OMAP3 names for GPIO optional clocks until the GPIO hwmod convertion is done. It will enforce the usage of OMAP4 names as the reference. - Temporary use OMAP3 names for TIMER main clock (gptX_fck) until TIMER hwmod convertion is done. During that convertion, the new name will have to be used. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Rajendra Nayak <rnayak@ti.com>
* OMAP4: clock: Fix clock names and align with hwmod namesBenoit Cousson2010-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | The OMAP4 hwmod data introduced the new naming convention for TI IPs (See patch OMAP4: hwmod: Add partial hwmod support for OMAP4430 ES1.0) The leaf clock names are using the same IP name and thus must be modified to match the clock populated in the hwmod data. - Fix some leaf clocks nodes that were using a _iclk instead of the _fclk prefix. - Fix some wrong interface clock name for master IPs connected to interconnect. Please not that due to the fact that nodes are sorted by name, the name change will introduce a quite ugly diff a little bit hard to follow. Timers clock con_id is still using the old gptX_fck name until the gptimer driver is updated to omap_device framework. Timers entries in hwmods DB are still disabled until the migration if timer to platform_driver + omap_hwmod. Signed-off-by: Benoit Cousson <b-cousson@ti.com> [paul@pwsan.com: manually resolved conflicts with Rajendra's clock patch] Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com>
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