| Commit message (Collapse) | Author | Age |
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github.com:MISL-EBU-System-SW/mainline-public into mevbu-dt-additions
SMP support for Armada XP
The purpose of this series is to add the SMP support for the Armada XP
SoCs. Beside the SMP support itself brought by the last 3 commits,
this series also adds the support for the coherency fabric unit and
the power management service unit.
The coherency fabric is responsible for ensuring hardware coherency
between all CPUs and between CPUs and I/O masters. This unit is also
available for Armada 370 and will be used in an incoming patch set
for hardware I/O cache coherency.
The power management service unit is responsible for powering down and
waking up CPUs and other SOC units.
Conflicts:
arch/arm/mach-mvebu/armada-370-xp.c
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All the Device Tree files for Armada 370 and XP SoCs and boards use
the "armada-370-xp" common compatible string, except
armada-370-xp.dtsi which was specifying "armada_370_xp".
Fix this inconsistency by making armada-370-xp.dtsi declare a
compatible string of "armada-370-xp" like everyone else.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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git://github.com/MISL-EBU-System-SW/mainline-public into mvebu/everything
Marvell SATA and I2C enabling for OpenBlocks AX3-4
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This patch enables SATA support on the OpenBlocks AX3-4. It has one
internal SATA port, and an external eSATA port.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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The OpenBlocks AX3-4 has a Seiko Instruments S-35390A as the RTC
controller. This patch enables this RTC device in the OpenBlocks
AX3-4 Device Tree.
[Thomas Petazzoni: updated with other OpenBlocks changes, rephrased
commit log.]
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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The OpenBlocks AX3-4 board, based on the Armada XP SoC, has an I2C
bus. This patch enables this bus and sets the clock frequency of the
bus.
[Thomas Petazzoni: updated with other changes on OpenBlocks, rephrased
commit log.]
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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The Armada 370 and Armada XP have the same I2C controllers as previous
Marvell SoCs, so the existing mv64xxx-i2c driver works fine.
[Thomas Petazzoni: updated on top of other Armada 370/XP changes,
rephrased the commit log].
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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github.com:MISL-EBU-System-SW/mainline-public into test-the-merge
Marvell XOR driver DT changes for 3.8
Conflicts:
arch/arm/boot/dts/armada-xp.dtsi
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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github.com:MISL-EBU-System-SW/mainline-public into test-the-merge
Marvell Ethernet DT update for clk support
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github.com:MISL-EBU-System-SW/mainline-public into test-the-merge
Marvell boards changes related to Ethernet, for 3.8
Conflicts:
arch/arm/boot/dts/armada-370-xp.dtsi
arch/arm/boot/dts/armada-xp-db.dts
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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git://github.com/MISL-EBU-System-SW/mainline-public into mvebu/everything
Add hardware I/O coherency support for Armada 370/XP
The purpose of this patch set is to add hardware I/O Coherency support
for Armada 370 and Armada XP. Theses SoCs come with an unit called
coherency fabric. A beginning of the support for this unit have been
introduced with the SMP patch set. This series extend this support:
the coherency fabric unit allows to use the Armada XP and the Armada
370 as nearly coherent architectures.
The third patches enables this new feature and register our own set
of DMA ops, to benefit this hardware enhancement.
The first patches exports a dma operation function needed to register
our own set of dma ops.
The second patch introduces a new flag for the address decoding
configuration in order to be able to set the memory windows as
shared memory.
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Armada 370 and XP come with an unit called coherency fabric. This unit
allows to use the Armada 370/XP as a nearly coherent architecture. The
coherency mechanism uses snoop filters to ensure the coherency between
caches, DRAM and devices. This mechanism needs a synchronization
barrier which guarantees that all the memory writes initiated by the
devices have reached their target and do not reside in intermediate
write buffers. That's why the architecture is not totally coherent and
we need to provide our own functions for some DMA operations.
Beside the use of the coherency fabric, the device units will have to
set the attribute flag of the decoding address window to select the
accurate coherency process for the memory transaction. This is done
each device driver programs the DRAM address windows. The value of the
attribute set by the driver is retrieved through the
orion_addr_map_cfg struct filled during the early initialization of
the platform.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Yehuda Yitschak <yehuday@marvell.com>
Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>
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git://github.com/MISL-EBU-System-SW/mainline-public into mvebu/everything
SMP support for Armada XP
The purpose of this series is to add the SMP support for the Armada XP
SoCs. Beside the SMP support itself brought by the last 3 commits,
this series also adds the support for the coherency fabric unit and
the power management service unit.
The coherency fabric is responsible for ensuring hardware coherency
between all CPUs and between CPUs and I/O masters. This unit is also
available for Armada 370 and will be used in an incoming patch set
for hardware I/O cache coherency.
The power management service unit is responsible for powering down and
waking up CPUs and other SOC units.
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This patch enhances the IRQ controller driver to add support for
Inter-Processor-Interrupts that are needed to enable SMP support.
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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The Armada 370 and Armada XP SOCs have a power management service unit
which is responsible for powering down and waking up CPUs and other
SOC units. This patch adds support for this unit.
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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The Armada 370 and Armada XP SOCs have a coherency fabric unit which
is responsible for ensuring hardware coherency between all CPUs and
between CPUs and I/O masters. This patch provides the basic support
needed for SMP.
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
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git://github.com/MISL-EBU-System-SW/mainline-public into mvebu/everything
Marvell XOR driver DT changes for 3.8
Conflicts:
arch/arm/boot/dts/armada-xp.dtsi
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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With DT support for Marvell XOR DMA engine, make use of it on Dove.
Also remove the now redundant code in DT board init for xor engines.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Use DT to describe the two XOR DMA engines on Kirkwood. Remove the
C code initialization.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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nodes
The mvneta driver for the Marvell Armada 370/XP Ethernet devices has
gained proper clock framework integration, and the corresponding
Device Tree nodes now have a correct 'clocks' pointer.
The 'clock-frequency' properties in the various .dts files for Armada
370/XP boards have therefore become useless.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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The mvneta driver now understands a standard 'clocks' clock pointer
property in the Device Tree nodes for the Ethernet devices, so we add
the right clock reference for the different Ethernet ports of the
Armada 370/XP SoCs.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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github.com:MISL-EBU-System-SW/mainline-public into test-the-merge
Marvell boards changes related to Ethernet, for 3.8
Conflicts:
arch/arm/boot/dts/armada-370-xp.dtsi
arch/arm/boot/dts/armada-xp-db.dts
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The Globalscale Mirabox platform has two Ethernet interfaces,
connected to the SoC with a RGMII interface.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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The PlatHome OpenBlocks AX3-4 platform has 4 Ethernet ports, connected
to a single quad-port PHY through SGMII.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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This patch enables the two network interfaces of the Armada 370
official Marvell evaluation platform, and the four network interfaces
of the Armada XP official Marvell evaluation platform.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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The Armada 370 SoC has two network units, while the Armada XP has four
network units. The first two network units are common to both the
Armada XP and Armada 370, so they are added to armada-370-xp.dtsi,
while the other two network units are specific to the Armada XP and
therefore added to armada-xp.dtsi.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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This platform, available from Globalscale has an Armada 370. For now,
only the serial port is supported. Support for network, USB and other
peripherals will be added as drivers for them become available for
Armada 370 in mainline.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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This is 3.8 material.
Changes from original version posted by Gregory:
* Renamed .dts file to armada-370-mirabox.dts
* Change compatible string to 'globalscale,mirabox'
* Remove compatible string from armada-370-xp.c
* Removed references to MBX0001
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This platform, available in Japan from PlatHome, has a dual-core
Armada XP, the MV78260. For now, only the two serial ports and the
three front LEDs are supported. Support for SMP, network, SATA, USB
and other peripherals will be added as drivers for them become
available for Armada XP in mainline.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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This is 3.8 material.
Changes since v2:
* Renamed the .dts file to armada-xp-openblocks-ax3-4.dts
* Removed the compatible string from armada-370-xp.c (which now only
lists the common SoC compatible string)
Changes since v1:
* Renamed the board to OpenBlocks AX3-4, since there is a variant
called AX3-2 which has less RAM, and no mini PCIe port. Requested
by Andrew Lunn.
* Fix the amount of memory to 3 GB. In fact, the board has 1 GB
soldered, and 2 GB in a SODIMM slot (which is therefore
removable). But as the board is delivered as is, we'll assume it
has 3 GB of memory by default.
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Add the SATA device tree bindings for
- Armada XP evaluation board (DB-78460-BP)
- Armada 370 evaluation board (DB-88F6710-BP-DDR3)
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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With true DT clock providers available switch Kirkwood clock setup in
DT- enabled boards. While AUXDATA can be removed completely from bus
probing, some devices still don't know about DT. Therefore, some clkdev
aliases are created until these devices also move to DT.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
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With true DT clock providers available switch Dove clock setup in DT-
enabled boards. While AUXDATA can be removed completely from bus probing,
some devices still don't know about DT at all. Therefore, some clock
aliases are created until the devices also move to DT.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by Gregory CLEMENT <gregory.clement@free-electrons.com>
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Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by Gregory CLEMENT <gregory.clement@free-electrons.com>
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Pull ARM SoC device-tree updates, take 2, from Olof Johansson:
"This branch contains device-tree updates for the SPEAr platform. They
had dependencies on earlier branches from this merge window, which is
why they were broken out in a separate branch."
* tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: SPEAr3xx: Shirq: Move shirq controller out of plat/
ARM: SPEAr320: DT: Add SPEAr 320 HMI board support
ARM: SPEAr3xx: DT: add shirq node for interrupt multiplexor
ARM: SPEAr3xx: shirq: simplify and move the shared irq multiplexor to DT
ARM: SPEAr1310: Fix AUXDATA for compact flash controller
ARM: SPEAr13xx: Remove fields not required for ssp controller
ARM: SPEAr1310: Move 1310 specific misc register into machine specific files
ARM: SPEAr: DT: Update device nodes
ARM: SPEAr: DT: add uart state to fix warning
ARM: SPEAr: DT: Modify DT bindings for STMMAC
ARM: SPEAr: DT: Fix existing DT support
ARM: SPEAr: DT: Update partition info for MTD devices
ARM: SPEAr: DT: Update pinctrl list
ARM: SPEAr13xx: DT: Add spics gpio controller nodes
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This adds support for SPEAr320-HMI board.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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shirq layer has been adapted to DT, add corresponding nodes in all
SPEAr3xx variants.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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This patch adds multiple device nodes for SPEAr machines and boards.
Signed-off-by: Bhavna Yadav <bhavna.yadav@st.com>
Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Vijay Kumar Mishra <vijay.kumar@st.com>
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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amba-pl011 driver supports two pin state "default" and "sleep" and it
expect from dt to provide this pinctrl states and phandler otherwise it
gives a warning message.
To remove this warning message pass default state with null phandler to uart
pins in device node (In our case all the pins are configured in default states
so we pass null phandler to pins).
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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This patch modifies the DT bindings for the GMAC IP existings for the
SPEAr family. The DT bindings now additionally pass the phy mode as a
configuration parameter for the ethernet device.
Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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This patch fixes existing DT support for all SPEAr SoC's. This includes:
- Removing few nodes from board files
- Updating DT data of few nodes
- Updating ranges of few busses
- Moving devices to correct parent bus
Signed-off-by: Bhavna Yadav <bhavna.yadav@st.com>
Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Vijay Kumar Mishra <vijay.kumar@st.com>
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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This patch enhances partition information of MTD devices like fsmc-nand and
spear-smi.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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This patch updates pinctrl configuration for SPEAr SoC's.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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SPEAr platform provides a provision to control chipselects of ARM PL022 Prime
Cell spi controller through its system registers, which otherwise remains under
PL022 control which some protocols do not want.
This patch adds spics controller nodes in device tree for various SPEAr13xx
SoCs.
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Reviewed-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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This merges dependency branch pinctrl/devel for SPEAr DT updates.
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Pull ARM Soc updates, take 2, from Olof Johansson:
"This is the second batch of SoC updates for the 3.8 merge window,
containing parts that had dependencies on earlier branches such that
we couldn't include them with the first branch.
These are general updates for Samsung Exynos, Renesas/shmobile and a
topic branch that adds SMP support to Altera's socfpga platform."
Fix up conflicts mostly as per Olof.
* tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: EXYNOS: Clock settings for SATA and SATA PHY
ARM: EXYNOS: Add ARM down clock support
ARM: EXYNOS: Fix i2c suspend/resume for legacy controller
ARM: EXYNOS: Add aliases for i2c controller
ARM: EXYNOS: Setup legacy i2c controller interrupts
sh: clkfwk: fixup unsed variable warning
Revert "ARM: shmobile: r8a7779: Replace modify_scu_cpu_psr with scu_power_mode"
Revert "ARM: shmobile: sh73a0: Replace modify_scu_cpu_psr with scu_power_mode"
Revert "ARM: shmobile: emev2: Replace modify_scu_cpu_psr with scu_power_mode"
ARM: highbank: use common debug_ll_io_init
ARM: shmobile: sh7372: sh7372_fsiXck_clk become non-global
ARM: shmobile: sh7372: remove fsidivx clock
ARM: socfpga: mark secondary_trampoline as cpuinit
socfpga: map uart into virtual address space so that early_printk() works
ARM: socfpga: fix build break for allyesconfig
ARM: socfpga: Enable SMP for socfpga
ARM: EXYNOS: Add dp clock support for EXYNOS5
ARM: SAMSUNG: call clk_get_rate for debugfs rate files
ARM: SAMSUNG: add clock_tree debugfs file in clock
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Merging in the smp-on-socfpga branch into soc2 since the topics are similar
and it's a short branch in the first place.
* next/smp:
ARM: socfpga: mark secondary_trampoline as cpuinit
socfpga: map uart into virtual address space so that early_printk() works
ARM: socfpga: fix build break for allyesconfig
ARM: socfpga: Enable SMP for socfpga
Signed-off-by: Olof Johansson <olof@lixom.net>
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