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* Blackfin: boards: add example i2c resources for ad525x devicessteven miao2010-10-22
| | | | | Signed-off-by: steven miao <realmz6@gmail.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: SIC: fix off-by-one error in loopMichael Hennerich2010-10-22
| | | | | | | Make sure we include EMAC_SYSTAT when showing errors. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: bf537-stamp: tweak i2c address for ad5280 add-on tftlcd boardSonic Zhang2010-10-22
| | | | | | | | | The predefined i2c address 0x2c doesn't match the configuration of the ad5280 PINs AD0 and AD1 on the tftlcd add-on board. Both AD0 and AD1 are of voltage 3.3V, which means the i2c address should be 0x2F. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: bf51x: enable support for 0.2 siliconMike Frysinger2010-10-22
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: initial preempt support while returning from interruptBarry Song2010-10-22
| | | | | Signed-off-by: Barry Song <barry.song@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: workaround anomaly 05000481 (corruption with ITEST MMRs)Robin Getz2010-10-22
| | | | | | | | | | Nothing actually needs to use these MMRs (as direct cache manipulation is done with the DTEST MMRs), so simply hide the read funcs behind the anomaly define. They're generally unusable anyways when this anomaly is in effect. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: i2c-gpio boards: use GPIO_PF# definesMike Frysinger2010-10-22
| | | | | | Rather than use raw numbers for the GPIO pins, use proper GPIO defines. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: access_ok: permit L1 stackBarry Song2010-10-22
| | | | | | | | | When apps run with their stack in L1, some system calls might be made where a buffer is in the stack as an argument. So make sure the core Blackfin access code does not reject this memory location. Signed-off-by: Barry Song <barry.song@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: bf561-ezkit: add AD1836 codec resourcesBarry Song2010-10-22
| | | | | | | | This board has an AD1836 codec, so make sure we have the right resources declared for it. Signed-off-by: Barry Song <barry.song@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: ptrace: enable access to L1 stacksBarry Song2010-10-22
| | | | | | | | If an app is placing its stack in L1 scratchpad SRAM, make sure ptrace is granted access to it so that gdb can do its thing. Signed-off-by: Barry Song <barry.song@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: boards: fix num_chipselect values for on-chip SPI busesMike Frysinger2010-10-22
| | | | | | | | | The num_chipselect field for on-chip Blackfin SPI buses is supposed to be 1 larger than the number of actual CSs available. This is because the hardware starts counting at 1 and not 0. There is a field for "CS0", but it is marked as "reserved" everywhere. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: ad7160eval: new board portMichael Hennerich2010-10-22
| | | | | Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: bf537-stamp: re-use regulator framework with ad5398 partsSonic Zhang2010-10-22
| | | | | | | | We don't need our own header and structure to hook up the ad5398 part, so drop the custom resources for it. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: bf537-stamp: re-use the fixed regulator voltage driverSonic Zhang2010-10-22
| | | | | | | | Rather than write our own ADP switch driver, use the existing fixed regulator driver and rewrite the platform resources accordingly. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: SIC: BF537: change default data/error relative prioritiesMichael Hennerich2010-10-22
| | | | | | | | | | | | | | | | | | | | | | | | | Some peripherals might generate an error interrupt shortly after the data interrupt due to the fact that the peripheral isn't serviced fast enough. In most cases this isn't a problem and is expected behavior. This hasn't been a problem on most parts since you simply don't request the error interrupt (or you leave it disabled while there is an expected state) and do the peripheral status checking in the data interrupt. The Blackfin SIC allows people to prioritize data and error interrupts, and the Blackfin CEC allows interrupts of equal or higher priority to nest. The current default settings gives error interrupts a higher priority than data interrupts. So if an error occurs while processing the data interrupt, it will be serviced immediately. However, the error interrupt on the BF537 SIC cannot be enabled on a per-peripheral basis. Once the error interrupt is enabled for one peripheral, it is automatically enabled for all peripherals. Therefore lower the default multiplexed error interrupt priority so most people need not worry themselves with this issue. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: bf537-stamp: add example IIO resourcesMichael Hennerich2010-10-22
| | | | | | | Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Barry Song <barry.song@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: bf537-stamp: use correct spi mode with ad2s90 partsBarry Song2010-10-22
| | | | | Signed-off-by: Barry Song <barry.song@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: bf537-stamp: add example adau1373 i2c resourcesCliff Cai2010-10-22
| | | | | Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: bf537-stamp: add example adav801/3 resourcesYi Li2010-10-22
| | | | | Signed-off-by: Yi Li <yi.li@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: bf537-stamp: add example ad1937 i2c resourcesBarry Song2010-10-22
| | | | | Signed-off-by: Barry Song <barry.song@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: bf537-stamp: fix NAND resourcesMike Frysinger2010-10-22
| | | | | | | The NAND platform driver expects the registers to have a "mem" resource type rather than "io". Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: boards: use proper irq flags with isp1362-hcdMichael Hennerich2010-10-22
| | | | | | | | | | | | With the recent kernel update the isp1362-hcd driver evaluates the IORESOURCE_IRQ resource flags and requests the irq with the given polarity/edge settings. However the ISP1362 config requires low level/edge interrupts. Most of the Blackfin boards use some random flag or no flag at all. Make all boards use a know good flag IORESOURCE_IRQ_LOWEDGE. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: bf561-acvilon: fix NAND resourcesValentin Yakovenkov2010-10-22
| | | | | | | | The NAND platform driver expects the registers to have a "mem" resource type rather than "io". Signed-off-by: Valentin Yakovenkov <yakovenkov@gmail.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: cm-bf548: add support for Socket CANMichael Hennerich2010-10-22
| | | | | | | Add platform resources for the on-chip CAN peripheral so we can use it. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: boards: update AD183x resourcesBarry Song2010-10-22
| | | | | | | Make sure we use the right Kconfig names and platform strings. Signed-off-by: Barry Song <barry.song@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: bf537-stamp: update GPIO CS devicesBarry Song2010-10-22
| | | | | | | | Now that we've rewritten the GPIO CS handling in the Blackfin SPI peripheral, we need to update the platform resources accordingly. Signed-off-by: Barry Song <barry.song@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: punt short SPI MMR bit namesMike Frysinger2010-10-22
| | | | | | | Now that the common header defines everything and the SPI drivers are using it, we can drop these duplicated global namespace polluters. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Merge branch 'next' of ↵Linus Torvalds2010-10-22
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (71 commits) powerpc/44x: Update ppc44x_defconfig powerpc/watchdog: Make default timeout for Book-E watchdog a Kconfig option fsl_rio: Add comments for sRIO registers. powerpc/fsl-booke: Add e55xx (64-bit) smp defconfig powerpc/fsl-booke: Add p5020 DS board support powerpc/fsl-booke64: Use TLB CAMs to cover linear mapping on FSL 64-bit chips powerpc/fsl-booke: Add support for FSL Arch v1.0 MMU in setup_page_sizes powerpc/fsl-booke: Add support for FSL 64-bit e5500 core powerpc/85xx: add cache-sram support powerpc/85xx: add ngPIXIS FPGA device tree node to the P1022DS board powerpc: Fix compile error with paca code on ppc64e powerpc/fsl-booke: Add p3041 DS board support oprofile/fsl emb: Don't set MSR[PMM] until after clearing the interrupt. powerpc/fsl-booke: Add PCI device ids for P2040/P3041/P5010/P5020 QoirQ chips powerpc/mpc8xxx_gpio: Add support for 'qoriq-gpio' controllers powerpc/fsl_booke: Add support to boot from core other than 0 powerpc/p1022: Add probing for individual DMA channels powerpc/fsl_soc: Search all global-utilities nodes for rstccr powerpc: Fix invalid page flags in create TLB CAM path for PTE_64BIT powerpc/mpc83xx: Support for MPC8308 P1M board ... Fix up conflict with the generic irq_work changes in arch/powerpc/kernel/time.c
| * Merge remote branch 'jwb/next' into nextBenjamin Herrenschmidt2010-10-14
| |\
| | * powerpc/44x: Update ppc44x_defconfigJosh Boyer2010-10-14
| | | | | | | | | | | | | | | | | | | | | Make sure the new bluestone board is selected for the multiplatform defconfig. Also build logfs and squashfs as modules. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
| | * powerpc/44x: Add support for the AMCC APM821xx SoCTirumala Marri2010-10-13
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds CPU, device tree, defconfig and bluestone board support for APM821xx SoC. Signed-off-by: Tirumala R Marri <tmarri@apm.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
| * | powerpc/watchdog: Make default timeout for Book-E watchdog a Kconfig optionTimur Tabi2010-10-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PowerPC Book-E watchdog driver (booke_wdt.c) defines a default timeout value in the code based on whether it's a Freescale Book-E part of not. Instead of having hard-coded values in the driver, make it a Kconfig option. As newer chips gets faster, the current default values become less appropriate, since the timeout sometimes occurs before the kernel finishes booting. Making the value a Kconfig option allows BSPs to configure a new value without requiring the wdt_period command-line parameter to be set. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | fsl_rio: Add comments for sRIO registers.Shaohui Xie2010-10-14
| | | | | | | | | | | | | | | | | | | | | Add some comments to make sRIO registers map better readable. Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/fsl-booke: Add e55xx (64-bit) smp defconfigKumar Gala2010-10-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The p5020 SoC from Freescale is the first 64-bit Book-E processor and utilizes the two e5500 cores. Adding a defconfig that enables basic kernel for e5500 based processors. Also added the p5020 / e5500 support to the ppc64e defconfig. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/fsl-booke: Add p5020 DS board supportKumar Gala2010-10-14
| | | | | | | | | | | | | | | | | | | | | The P5020DS is in the same family of boards as the P4080 DS and thus shares the corenet_ds code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/fsl-booke64: Use TLB CAMs to cover linear mapping on FSL 64-bit chipsKumar Gala2010-10-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Freescale parts typically have TLB array for large mappings that we can bolt the linear mapping into. We utilize the code that already exists on PPC32 on the 64-bit side to setup the linear mapping to be cover by bolted TLB entries. We utilize a quarter of the variable size TLB array for this purpose. Additionally, we limit the amount of memory to what we can cover via bolted entries so we don't get secondary faults in the TLB miss handlers. We should fix this limitation in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/fsl-booke: Add support for FSL Arch v1.0 MMU in setup_page_sizesKumar Gala2010-10-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update setup_page_sizes() to support for a MMU v1.0 FSL style MMU implementation. In such a processor, we don't have TLB0PS or EPTCFG registers (and access to these registers may cause exceptions). We need to parse the older format of TLBnCFG for page size support. Additionaly, assume since we are an FSL implementation that we have 2 TLB arrays and the second array contains the variable size pages. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/fsl-booke: Add support for FSL 64-bit e5500 coreKumar Gala2010-10-14
| | | | | | | | | | | | | | | | | | | | | | | | The new e5500 core is similar to the e500mc core but adds 64-bit support. We support running it in 32-bit mode as it is identical to the e500mc. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: add cache-sram supportHarninder Rai2010-10-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It adds cache-sram support in P1/P2 QorIQ platforms as under: * A small abstraction over powerpc's remote heap allocator * Exports mpc85xx_cache_sram_alloc()/free() APIs * Supports only one contiguous SRAM window * Drivers can do the following in Kconfig to use these APIs "select FSL_85XX_CACHE_SRAM if MPC85xx" * Required SRAM size and the offset where SRAM should be mapped must be provided at kernel command line as : cache-sram-size=<value> cache-sram-offset=<offset> Signed-off-by: Harninder Rai <harninder.rai@freescale.com> Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/85xx: add ngPIXIS FPGA device tree node to the P1022DS boardTimur Tabi2010-10-14
| | | | | | | | | | | | | | | | | | | | | | | | The device tree for Freescale's P1022DS reference board is missing the node for the ngPIXIS FPGA. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc: Fix compile error with paca code on ppc64eKumar Gala2010-10-14
| | | | | | | | | | | | | | | | | | | | | | | | arch/powerpc/kernel/paca.c: In function 'allocate_lppacas': arch/powerpc/kernel/paca.c:111:1: error: parameter name omitted arch/powerpc/kernel/paca.c:111:1: error: parameter name omitted Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/fsl-booke: Add p3041 DS board supportKumar Gala2010-10-14
| | | | | | | | | | | | | | | | | | | | | The P3041DS is in the same family of boards as the P4080DS and thus shares the corenet_ds code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | oprofile/fsl emb: Don't set MSR[PMM] until after clearing the interrupt.Scott Wood2010-10-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On an arch 2.06 hypervisor, a pending perfmon interrupt will be delivered to the hypervisor at any point the guest is running, regardless of MSR[EE]. In order to reflect this interrupt, the hypervisor has to mask the interrupt in PMGC0 -- and set MSRP[PMMP] to intercept futher guest accesses to the PMRs to detect when to unmask (and prevent the guest from unmasking early, or seeing inconsistent state). This has the side effect of ignoring any changes the guest makes to MSR[PMM], so wait until after the interrupt is clear, and thus the hypervisor should have cleared MSRP[PMMP], before setting MSR[PMM]. The counters wil not actually run until PMGC0[FAC] is cleared in pmc_start_ctrs(), so this will not reduce the effectiveness of PMM. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/fsl-booke: Add PCI device ids for P2040/P3041/P5010/P5020 QoirQ chipsKumar Gala2010-10-14
| | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/mpc8xxx_gpio: Add support for 'qoriq-gpio' controllersKumar Gala2010-10-14
| | | | | | | | | | | | | | | | | | | | | | | | Add 'fsl,qoriq-gpio' compatiable to the list we search for to bind against for mpc8xxx_gpio. This compatiable will be used on P1-P5xxx QorIQ devices like P4080. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/fsl_booke: Add support to boot from core other than 0Matthew McClintock2010-10-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First we check to see if we are the first core booting up. This is accomplished by comparing the boot_cpuid with -1, if it is we assume this is the first core coming up. Secondly, we need to update the initial thread info structure to reflect the actual cpu we are running on otherwise smp_processor_id() and related functions will return the default initialization value of the struct or 0. Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/p1022: Add probing for individual DMA channelsTimur Tabi2010-10-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | Like the MPC8610 HPCD, the P1022DS ASoC DMA driver probes on individual DMA channel nodes, so the DMA controller nodes' compatible string must be listed in p1022_ds_ids[] to work. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/fsl_soc: Search all global-utilities nodes for rstccrMatthew McClintock2010-10-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | The first global-utilities node might not contain the rstcr property, so we should search all the nodes Signed-off-by: Matthew McClintock <msm@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc: Fix invalid page flags in create TLB CAM path for PTE_64BITPaul Gortmaker2010-10-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There exists a four line chunk of code, which when configured for 64 bit address space, can incorrectly set certain page flags during the TLB creation. It turns out that this is code which isn't used, but might still serve a purpose. Since it isn't obvious why it exists or why it causes problems, the below description covers both in detail. For powerpc bootstrap, the physical memory (at most 768M), is mapped into the kernel space via the following path: MMU_init() | + adjust_total_lowmem() | + map_mem_in_cams() | + settlbcam(i, virt, phys, cam_sz, PAGE_KERNEL_X, 0); On settlbcam(), the kernel will create TLB entries according to the flag, PAGE_KERNEL_X. settlbcam() { ... TLBCAM[index].MAS1 = MAS1_VALID | MAS1_IPROT | MAS1_TSIZE(tsize) | MAS1_TID(pid); ^ These entries cannot be invalidated by the kernel since MAS1_IPROT is set on TLB property. ... if (flags & _PAGE_USER) { TLBCAM[index].MAS3 |= MAS3_UX | MAS3_UR; TLBCAM[index].MAS3 |= ((flags & _PAGE_RW) ? MAS3_UW : 0); } For classic BookE (flags & _PAGE_USER) is 'zero' so it's fine. But on boards like the the Freescale P4080, we want to support 36-bit physical address on it. So the following options may be set: CONFIG_FSL_BOOKE=y CONFIG_PTE_64BIT=y CONFIG_PHYS_64BIT=y As a result, boards like the P4080 will introduce PTE format as Book3E. As per the file: arch/powerpc/include/asm/pgtable-ppc32.h * #elif defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT) * #include <asm/pte-book3e.h> So PAGE_KERNEL_X is __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) and the book3E version of _PAGE_KERNEL_RWX is defined with: (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY | _PAGE_BAP_SX) Note the _PAGE_BAP_SR, which is also defined in the book3E _PAGE_USER: #define _PAGE_USER (_PAGE_BAP_UR | _PAGE_BAP_SR) /* Can be read */ So the possibility exists to wrongly assign the user MAS3_U<RWX> bits to kernel (PAGE_KERNEL_X) address space via the following code fragment: if (flags & _PAGE_USER) { TLBCAM[index].MAS3 |= MAS3_UX | MAS3_UR; TLBCAM[index].MAS3 |= ((flags & _PAGE_RW) ? MAS3_UW : 0); } Here is a dump of the TLB info from Simics with the above code present: ------ L2 TLB1 GT SSS UUU V I Row Logical Physical SS TLPID TID WIMGE XWR XWR F P V ----- ----------------- ------------------- -- ----- ----- ----- --- --- - - - 0 c0000000-cfffffff 000000000-00fffffff 00 0 0 M XWR XWR 0 1 1 1 d0000000-dfffffff 010000000-01fffffff 00 0 0 M XWR XWR 0 1 1 2 e0000000-efffffff 020000000-02fffffff 00 0 0 M XWR XWR 0 1 1 Actually this conditional code was used for two legacy functions: 1: support KGDB to set break point. KGDB already dropped this; now uses its core write to set break point. 2: io_block_mapping() to create TLB in segmentation size (not PAGE_SIZE) for device IO space. This use case is also removed from the latest PowerPC kernel. However, there may still be a use case for it in the future, like large user pages, so we can't remove it entirely. As an alternative, we match on all bits of _PAGE_USER instead of just any bits, so the case where just _PAGE_BAP_SR is set can't sneak through. With this done, the TLB appears without U having XWR as below: ------- L2 TLB1 GT SSS UUU V I Row Logical Physical SS TLPID TID WIMGE XWR XWR F P V ----- ----------------- ------------------- -- ----- ----- ----- --- --- - - - 0 c0000000-cfffffff 000000000-00fffffff 00 0 0 M XWR 0 1 1 1 d0000000-dfffffff 010000000-01fffffff 00 0 0 M XWR 0 1 1 2 e0000000-efffffff 020000000-02fffffff 00 0 0 M XWR 0 1 1 Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | powerpc/mpc83xx: Support for MPC8308 P1M boardIlya Yanok2010-10-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for MPC8308 P1M board. Supported devices: DUART Dual Ethernet NOR flash Both I2C controllers USB in peripheral mode PCI Express Signed-off-by: Ilya Yanok <yanok@emcraft.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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