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-rw-r--r--sound/soc/codecs/wm8996.c3003
1 files changed, 3003 insertions, 0 deletions
diff --git a/sound/soc/codecs/wm8996.c b/sound/soc/codecs/wm8996.c
new file mode 100644
index 00000000000..5c40874811e
--- /dev/null
+++ b/sound/soc/codecs/wm8996.c
@@ -0,0 +1,3003 @@
1/*
2 * wm8996.c - WM8996 audio codec interface
3 *
4 * Copyright 2011 Wolfson Microelectronics PLC.
5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/completion.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/gcd.h>
20#include <linux/gpio.h>
21#include <linux/i2c.h>
22#include <linux/regulator/consumer.h>
23#include <linux/slab.h>
24#include <linux/workqueue.h>
25#include <sound/core.h>
26#include <sound/jack.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/initval.h>
31#include <sound/tlv.h>
32#include <trace/events/asoc.h>
33
34#include <sound/wm8996.h>
35#include "wm8996.h"
36
37#define WM8996_AIFS 2
38
39#define HPOUT1L 1
40#define HPOUT1R 2
41#define HPOUT2L 4
42#define HPOUT2R 8
43
44#define WM8996_NUM_SUPPLIES 4
45static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = {
46 "DBVDD",
47 "AVDD1",
48 "AVDD2",
49 "CPVDD",
50};
51
52struct wm8996_priv {
53 struct snd_soc_codec *codec;
54
55 int ldo1ena;
56
57 int sysclk;
58 int sysclk_src;
59
60 int fll_src;
61 int fll_fref;
62 int fll_fout;
63
64 struct completion fll_lock;
65
66 u16 dcs_pending;
67 struct completion dcs_done;
68
69 u16 hpout_ena;
70 u16 hpout_pending;
71
72 struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES];
73 struct notifier_block disable_nb[WM8996_NUM_SUPPLIES];
74
75 struct wm8996_pdata pdata;
76
77 int rx_rate[WM8996_AIFS];
78 int bclk_rate[WM8996_AIFS];
79
80 /* Platform dependant ReTune mobile configuration */
81 int num_retune_mobile_texts;
82 const char **retune_mobile_texts;
83 int retune_mobile_cfg[2];
84 struct soc_enum retune_mobile_enum;
85
86 struct snd_soc_jack *jack;
87 bool detecting;
88 bool jack_mic;
89 wm8996_polarity_fn polarity_cb;
90
91#ifdef CONFIG_GPIOLIB
92 struct gpio_chip gpio_chip;
93#endif
94};
95
96/* We can't use the same notifier block for more than one supply and
97 * there's no way I can see to get from a callback to the caller
98 * except container_of().
99 */
100#define WM8996_REGULATOR_EVENT(n) \
101static int wm8996_regulator_event_##n(struct notifier_block *nb, \
102 unsigned long event, void *data) \
103{ \
104 struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \
105 disable_nb[n]); \
106 if (event & REGULATOR_EVENT_DISABLE) { \
107 wm8996->codec->cache_sync = 1; \
108 } \
109 return 0; \
110}
111
112WM8996_REGULATOR_EVENT(0)
113WM8996_REGULATOR_EVENT(1)
114WM8996_REGULATOR_EVENT(2)
115WM8996_REGULATOR_EVENT(3)
116
117static const u16 wm8996_reg[WM8996_MAX_REGISTER] = {
118 [WM8996_SOFTWARE_RESET] = 0x8996,
119 [WM8996_POWER_MANAGEMENT_7] = 0x10,
120 [WM8996_DAC1_HPOUT1_VOLUME] = 0x88,
121 [WM8996_DAC2_HPOUT2_VOLUME] = 0x88,
122 [WM8996_DAC1_LEFT_VOLUME] = 0x2c0,
123 [WM8996_DAC1_RIGHT_VOLUME] = 0x2c0,
124 [WM8996_DAC2_LEFT_VOLUME] = 0x2c0,
125 [WM8996_DAC2_RIGHT_VOLUME] = 0x2c0,
126 [WM8996_OUTPUT1_LEFT_VOLUME] = 0x80,
127 [WM8996_OUTPUT1_RIGHT_VOLUME] = 0x80,
128 [WM8996_OUTPUT2_LEFT_VOLUME] = 0x80,
129 [WM8996_OUTPUT2_RIGHT_VOLUME] = 0x80,
130 [WM8996_MICBIAS_1] = 0x39,
131 [WM8996_MICBIAS_2] = 0x39,
132 [WM8996_LDO_1] = 0x3,
133 [WM8996_LDO_2] = 0x13,
134 [WM8996_ACCESSORY_DETECT_MODE_1] = 0x4,
135 [WM8996_HEADPHONE_DETECT_1] = 0x20,
136 [WM8996_MIC_DETECT_1] = 0x7600,
137 [WM8996_MIC_DETECT_2] = 0xbf,
138 [WM8996_CHARGE_PUMP_1] = 0x1f25,
139 [WM8996_CHARGE_PUMP_2] = 0xab19,
140 [WM8996_DC_SERVO_5] = 0x2a2a,
141 [WM8996_CONTROL_INTERFACE_1] = 0x8004,
142 [WM8996_CLOCKING_1] = 0x10,
143 [WM8996_AIF_RATE] = 0x83,
144 [WM8996_FLL_CONTROL_4] = 0x5dc0,
145 [WM8996_FLL_CONTROL_5] = 0xc84,
146 [WM8996_FLL_EFS_2] = 0x2,
147 [WM8996_AIF1_TX_LRCLK_1] = 0x80,
148 [WM8996_AIF1_TX_LRCLK_2] = 0x8,
149 [WM8996_AIF1_RX_LRCLK_1] = 0x80,
150 [WM8996_AIF1TX_DATA_CONFIGURATION_1] = 0x1818,
151 [WM8996_AIF1RX_DATA_CONFIGURATION] = 0x1818,
152 [WM8996_AIF1TX_TEST] = 0x7,
153 [WM8996_AIF2_TX_LRCLK_1] = 0x80,
154 [WM8996_AIF2_TX_LRCLK_2] = 0x8,
155 [WM8996_AIF2_RX_LRCLK_1] = 0x80,
156 [WM8996_AIF2TX_DATA_CONFIGURATION_1] = 0x1818,
157 [WM8996_AIF2RX_DATA_CONFIGURATION] = 0x1818,
158 [WM8996_AIF2TX_TEST] = 0x1,
159 [WM8996_DSP1_TX_LEFT_VOLUME] = 0xc0,
160 [WM8996_DSP1_TX_RIGHT_VOLUME] = 0xc0,
161 [WM8996_DSP1_RX_LEFT_VOLUME] = 0xc0,
162 [WM8996_DSP1_RX_RIGHT_VOLUME] = 0xc0,
163 [WM8996_DSP1_TX_FILTERS] = 0x2000,
164 [WM8996_DSP1_RX_FILTERS_1] = 0x200,
165 [WM8996_DSP1_RX_FILTERS_2] = 0x10,
166 [WM8996_DSP1_DRC_1] = 0x98,
167 [WM8996_DSP1_DRC_2] = 0x845,
168 [WM8996_DSP1_RX_EQ_GAINS_1] = 0x6318,
169 [WM8996_DSP1_RX_EQ_GAINS_2] = 0x6300,
170 [WM8996_DSP1_RX_EQ_BAND_1_A] = 0xfca,
171 [WM8996_DSP1_RX_EQ_BAND_1_B] = 0x400,
172 [WM8996_DSP1_RX_EQ_BAND_1_PG] = 0xd8,
173 [WM8996_DSP1_RX_EQ_BAND_2_A] = 0x1eb5,
174 [WM8996_DSP1_RX_EQ_BAND_2_B] = 0xf145,
175 [WM8996_DSP1_RX_EQ_BAND_2_C] = 0xb75,
176 [WM8996_DSP1_RX_EQ_BAND_2_PG] = 0x1c5,
177 [WM8996_DSP1_RX_EQ_BAND_3_A] = 0x1c58,
178 [WM8996_DSP1_RX_EQ_BAND_3_B] = 0xf373,
179 [WM8996_DSP1_RX_EQ_BAND_3_C] = 0xa54,
180 [WM8996_DSP1_RX_EQ_BAND_3_PG] = 0x558,
181 [WM8996_DSP1_RX_EQ_BAND_4_A] = 0x168e,
182 [WM8996_DSP1_RX_EQ_BAND_4_B] = 0xf829,
183 [WM8996_DSP1_RX_EQ_BAND_4_C] = 0x7ad,
184 [WM8996_DSP1_RX_EQ_BAND_4_PG] = 0x1103,
185 [WM8996_DSP1_RX_EQ_BAND_5_A] = 0x564,
186 [WM8996_DSP1_RX_EQ_BAND_5_B] = 0x559,
187 [WM8996_DSP1_RX_EQ_BAND_5_PG] = 0x4000,
188 [WM8996_DSP2_TX_LEFT_VOLUME] = 0xc0,
189 [WM8996_DSP2_TX_RIGHT_VOLUME] = 0xc0,
190 [WM8996_DSP2_RX_LEFT_VOLUME] = 0xc0,
191 [WM8996_DSP2_RX_RIGHT_VOLUME] = 0xc0,
192 [WM8996_DSP2_TX_FILTERS] = 0x2000,
193 [WM8996_DSP2_RX_FILTERS_1] = 0x200,
194 [WM8996_DSP2_RX_FILTERS_2] = 0x10,
195 [WM8996_DSP2_DRC_1] = 0x98,
196 [WM8996_DSP2_DRC_2] = 0x845,
197 [WM8996_DSP2_RX_EQ_GAINS_1] = 0x6318,
198 [WM8996_DSP2_RX_EQ_GAINS_2] = 0x6300,
199 [WM8996_DSP2_RX_EQ_BAND_1_A] = 0xfca,
200 [WM8996_DSP2_RX_EQ_BAND_1_B] = 0x400,
201 [WM8996_DSP2_RX_EQ_BAND_1_PG] = 0xd8,
202 [WM8996_DSP2_RX_EQ_BAND_2_A] = 0x1eb5,
203 [WM8996_DSP2_RX_EQ_BAND_2_B] = 0xf145,
204 [WM8996_DSP2_RX_EQ_BAND_2_C] = 0xb75,
205 [WM8996_DSP2_RX_EQ_BAND_2_PG] = 0x1c5,
206 [WM8996_DSP2_RX_EQ_BAND_3_A] = 0x1c58,
207 [WM8996_DSP2_RX_EQ_BAND_3_B] = 0xf373,
208 [WM8996_DSP2_RX_EQ_BAND_3_C] = 0xa54,
209 [WM8996_DSP2_RX_EQ_BAND_3_PG] = 0x558,
210 [WM8996_DSP2_RX_EQ_BAND_4_A] = 0x168e,
211 [WM8996_DSP2_RX_EQ_BAND_4_B] = 0xf829,
212 [WM8996_DSP2_RX_EQ_BAND_4_C] = 0x7ad,
213 [WM8996_DSP2_RX_EQ_BAND_4_PG] = 0x1103,
214 [WM8996_DSP2_RX_EQ_BAND_5_A] = 0x564,
215 [WM8996_DSP2_RX_EQ_BAND_5_B] = 0x559,
216 [WM8996_DSP2_RX_EQ_BAND_5_PG] = 0x4000,
217 [WM8996_OVERSAMPLING] = 0xd,
218 [WM8996_SIDETONE] = 0x1040,
219 [WM8996_GPIO_1] = 0xa101,
220 [WM8996_GPIO_2] = 0xa101,
221 [WM8996_GPIO_3] = 0xa101,
222 [WM8996_GPIO_4] = 0xa101,
223 [WM8996_GPIO_5] = 0xa101,
224 [WM8996_PULL_CONTROL_2] = 0x140,
225 [WM8996_INTERRUPT_STATUS_1_MASK] = 0x1f,
226 [WM8996_INTERRUPT_STATUS_2_MASK] = 0x1ecf,
227 [WM8996_RIGHT_PDM_SPEAKER] = 0x1,
228 [WM8996_PDM_SPEAKER_MUTE_SEQUENCE] = 0x69,
229 [WM8996_PDM_SPEAKER_VOLUME] = 0x66,
230 [WM8996_WRITE_SEQUENCER_0] = 0x1,
231 [WM8996_WRITE_SEQUENCER_1] = 0x1,
232 [WM8996_WRITE_SEQUENCER_3] = 0x6,
233 [WM8996_WRITE_SEQUENCER_4] = 0x40,
234 [WM8996_WRITE_SEQUENCER_5] = 0x1,
235 [WM8996_WRITE_SEQUENCER_6] = 0xf,
236 [WM8996_WRITE_SEQUENCER_7] = 0x6,
237 [WM8996_WRITE_SEQUENCER_8] = 0x1,
238 [WM8996_WRITE_SEQUENCER_9] = 0x3,
239 [WM8996_WRITE_SEQUENCER_10] = 0x104,
240 [WM8996_WRITE_SEQUENCER_12] = 0x60,
241 [WM8996_WRITE_SEQUENCER_13] = 0x11,
242 [WM8996_WRITE_SEQUENCER_14] = 0x401,
243 [WM8996_WRITE_SEQUENCER_16] = 0x50,
244 [WM8996_WRITE_SEQUENCER_17] = 0x3,
245 [WM8996_WRITE_SEQUENCER_18] = 0x100,
246 [WM8996_WRITE_SEQUENCER_20] = 0x51,
247 [WM8996_WRITE_SEQUENCER_21] = 0x3,
248 [WM8996_WRITE_SEQUENCER_22] = 0x104,
249 [WM8996_WRITE_SEQUENCER_23] = 0xa,
250 [WM8996_WRITE_SEQUENCER_24] = 0x60,
251 [WM8996_WRITE_SEQUENCER_25] = 0x3b,
252 [WM8996_WRITE_SEQUENCER_26] = 0x502,
253 [WM8996_WRITE_SEQUENCER_27] = 0x100,
254 [WM8996_WRITE_SEQUENCER_28] = 0x2fff,
255 [WM8996_WRITE_SEQUENCER_32] = 0x2fff,
256 [WM8996_WRITE_SEQUENCER_36] = 0x2fff,
257 [WM8996_WRITE_SEQUENCER_40] = 0x2fff,
258 [WM8996_WRITE_SEQUENCER_44] = 0x2fff,
259 [WM8996_WRITE_SEQUENCER_48] = 0x2fff,
260 [WM8996_WRITE_SEQUENCER_52] = 0x2fff,
261 [WM8996_WRITE_SEQUENCER_56] = 0x2fff,
262 [WM8996_WRITE_SEQUENCER_60] = 0x2fff,
263 [WM8996_WRITE_SEQUENCER_64] = 0x1,
264 [WM8996_WRITE_SEQUENCER_65] = 0x1,
265 [WM8996_WRITE_SEQUENCER_67] = 0x6,
266 [WM8996_WRITE_SEQUENCER_68] = 0x40,
267 [WM8996_WRITE_SEQUENCER_69] = 0x1,
268 [WM8996_WRITE_SEQUENCER_70] = 0xf,
269 [WM8996_WRITE_SEQUENCER_71] = 0x6,
270 [WM8996_WRITE_SEQUENCER_72] = 0x1,
271 [WM8996_WRITE_SEQUENCER_73] = 0x3,
272 [WM8996_WRITE_SEQUENCER_74] = 0x104,
273 [WM8996_WRITE_SEQUENCER_76] = 0x60,
274 [WM8996_WRITE_SEQUENCER_77] = 0x11,
275 [WM8996_WRITE_SEQUENCER_78] = 0x401,
276 [WM8996_WRITE_SEQUENCER_80] = 0x50,
277 [WM8996_WRITE_SEQUENCER_81] = 0x3,
278 [WM8996_WRITE_SEQUENCER_82] = 0x100,
279 [WM8996_WRITE_SEQUENCER_84] = 0x60,
280 [WM8996_WRITE_SEQUENCER_85] = 0x3b,
281 [WM8996_WRITE_SEQUENCER_86] = 0x502,
282 [WM8996_WRITE_SEQUENCER_87] = 0x100,
283 [WM8996_WRITE_SEQUENCER_88] = 0x2fff,
284 [WM8996_WRITE_SEQUENCER_92] = 0x2fff,
285 [WM8996_WRITE_SEQUENCER_96] = 0x2fff,
286 [WM8996_WRITE_SEQUENCER_100] = 0x2fff,
287 [WM8996_WRITE_SEQUENCER_104] = 0x2fff,
288 [WM8996_WRITE_SEQUENCER_108] = 0x2fff,
289 [WM8996_WRITE_SEQUENCER_112] = 0x2fff,
290 [WM8996_WRITE_SEQUENCER_116] = 0x2fff,
291 [WM8996_WRITE_SEQUENCER_120] = 0x2fff,
292 [WM8996_WRITE_SEQUENCER_124] = 0x2fff,
293 [WM8996_WRITE_SEQUENCER_128] = 0x1,
294 [WM8996_WRITE_SEQUENCER_129] = 0x1,
295 [WM8996_WRITE_SEQUENCER_131] = 0x6,
296 [WM8996_WRITE_SEQUENCER_132] = 0x40,
297 [WM8996_WRITE_SEQUENCER_133] = 0x1,
298 [WM8996_WRITE_SEQUENCER_134] = 0xf,
299 [WM8996_WRITE_SEQUENCER_135] = 0x6,
300 [WM8996_WRITE_SEQUENCER_136] = 0x1,
301 [WM8996_WRITE_SEQUENCER_137] = 0x3,
302 [WM8996_WRITE_SEQUENCER_138] = 0x106,
303 [WM8996_WRITE_SEQUENCER_140] = 0x61,
304 [WM8996_WRITE_SEQUENCER_141] = 0x11,
305 [WM8996_WRITE_SEQUENCER_142] = 0x401,
306 [WM8996_WRITE_SEQUENCER_144] = 0x50,
307 [WM8996_WRITE_SEQUENCER_145] = 0x3,
308 [WM8996_WRITE_SEQUENCER_146] = 0x102,
309 [WM8996_WRITE_SEQUENCER_148] = 0x51,
310 [WM8996_WRITE_SEQUENCER_149] = 0x3,
311 [WM8996_WRITE_SEQUENCER_150] = 0x106,
312 [WM8996_WRITE_SEQUENCER_151] = 0xa,
313 [WM8996_WRITE_SEQUENCER_152] = 0x61,
314 [WM8996_WRITE_SEQUENCER_153] = 0x3b,
315 [WM8996_WRITE_SEQUENCER_154] = 0x502,
316 [WM8996_WRITE_SEQUENCER_155] = 0x100,
317 [WM8996_WRITE_SEQUENCER_156] = 0x2fff,
318 [WM8996_WRITE_SEQUENCER_160] = 0x2fff,
319 [WM8996_WRITE_SEQUENCER_164] = 0x2fff,
320 [WM8996_WRITE_SEQUENCER_168] = 0x2fff,
321 [WM8996_WRITE_SEQUENCER_172] = 0x2fff,
322 [WM8996_WRITE_SEQUENCER_176] = 0x2fff,
323 [WM8996_WRITE_SEQUENCER_180] = 0x2fff,
324 [WM8996_WRITE_SEQUENCER_184] = 0x2fff,
325 [WM8996_WRITE_SEQUENCER_188] = 0x2fff,
326 [WM8996_WRITE_SEQUENCER_192] = 0x1,
327 [WM8996_WRITE_SEQUENCER_193] = 0x1,
328 [WM8996_WRITE_SEQUENCER_195] = 0x6,
329 [WM8996_WRITE_SEQUENCER_196] = 0x40,
330 [WM8996_WRITE_SEQUENCER_197] = 0x1,
331 [WM8996_WRITE_SEQUENCER_198] = 0xf,
332 [WM8996_WRITE_SEQUENCER_199] = 0x6,
333 [WM8996_WRITE_SEQUENCER_200] = 0x1,
334 [WM8996_WRITE_SEQUENCER_201] = 0x3,
335 [WM8996_WRITE_SEQUENCER_202] = 0x106,
336 [WM8996_WRITE_SEQUENCER_204] = 0x61,
337 [WM8996_WRITE_SEQUENCER_205] = 0x11,
338 [WM8996_WRITE_SEQUENCER_206] = 0x401,
339 [WM8996_WRITE_SEQUENCER_208] = 0x50,
340 [WM8996_WRITE_SEQUENCER_209] = 0x3,
341 [WM8996_WRITE_SEQUENCER_210] = 0x102,
342 [WM8996_WRITE_SEQUENCER_212] = 0x61,
343 [WM8996_WRITE_SEQUENCER_213] = 0x3b,
344 [WM8996_WRITE_SEQUENCER_214] = 0x502,
345 [WM8996_WRITE_SEQUENCER_215] = 0x100,
346 [WM8996_WRITE_SEQUENCER_216] = 0x2fff,
347 [WM8996_WRITE_SEQUENCER_220] = 0x2fff,
348 [WM8996_WRITE_SEQUENCER_224] = 0x2fff,
349 [WM8996_WRITE_SEQUENCER_228] = 0x2fff,
350 [WM8996_WRITE_SEQUENCER_232] = 0x2fff,
351 [WM8996_WRITE_SEQUENCER_236] = 0x2fff,
352 [WM8996_WRITE_SEQUENCER_240] = 0x2fff,
353 [WM8996_WRITE_SEQUENCER_244] = 0x2fff,
354 [WM8996_WRITE_SEQUENCER_248] = 0x2fff,
355 [WM8996_WRITE_SEQUENCER_252] = 0x2fff,
356 [WM8996_WRITE_SEQUENCER_256] = 0x60,
357 [WM8996_WRITE_SEQUENCER_258] = 0x601,
358 [WM8996_WRITE_SEQUENCER_260] = 0x50,
359 [WM8996_WRITE_SEQUENCER_262] = 0x100,
360 [WM8996_WRITE_SEQUENCER_264] = 0x1,
361 [WM8996_WRITE_SEQUENCER_266] = 0x104,
362 [WM8996_WRITE_SEQUENCER_267] = 0x100,
363 [WM8996_WRITE_SEQUENCER_268] = 0x2fff,
364 [WM8996_WRITE_SEQUENCER_272] = 0x2fff,
365 [WM8996_WRITE_SEQUENCER_276] = 0x2fff,
366 [WM8996_WRITE_SEQUENCER_280] = 0x2fff,
367 [WM8996_WRITE_SEQUENCER_284] = 0x2fff,
368 [WM8996_WRITE_SEQUENCER_288] = 0x2fff,
369 [WM8996_WRITE_SEQUENCER_292] = 0x2fff,
370 [WM8996_WRITE_SEQUENCER_296] = 0x2fff,
371 [WM8996_WRITE_SEQUENCER_300] = 0x2fff,
372 [WM8996_WRITE_SEQUENCER_304] = 0x2fff,
373 [WM8996_WRITE_SEQUENCER_308] = 0x2fff,
374 [WM8996_WRITE_SEQUENCER_312] = 0x2fff,
375 [WM8996_WRITE_SEQUENCER_316] = 0x2fff,
376 [WM8996_WRITE_SEQUENCER_320] = 0x61,
377 [WM8996_WRITE_SEQUENCER_322] = 0x601,
378 [WM8996_WRITE_SEQUENCER_324] = 0x50,
379 [WM8996_WRITE_SEQUENCER_326] = 0x102,
380 [WM8996_WRITE_SEQUENCER_328] = 0x1,
381 [WM8996_WRITE_SEQUENCER_330] = 0x106,
382 [WM8996_WRITE_SEQUENCER_331] = 0x100,
383 [WM8996_WRITE_SEQUENCER_332] = 0x2fff,
384 [WM8996_WRITE_SEQUENCER_336] = 0x2fff,
385 [WM8996_WRITE_SEQUENCER_340] = 0x2fff,
386 [WM8996_WRITE_SEQUENCER_344] = 0x2fff,
387 [WM8996_WRITE_SEQUENCER_348] = 0x2fff,
388 [WM8996_WRITE_SEQUENCER_352] = 0x2fff,
389 [WM8996_WRITE_SEQUENCER_356] = 0x2fff,
390 [WM8996_WRITE_SEQUENCER_360] = 0x2fff,
391 [WM8996_WRITE_SEQUENCER_364] = 0x2fff,
392 [WM8996_WRITE_SEQUENCER_368] = 0x2fff,
393 [WM8996_WRITE_SEQUENCER_372] = 0x2fff,
394 [WM8996_WRITE_SEQUENCER_376] = 0x2fff,
395 [WM8996_WRITE_SEQUENCER_380] = 0x2fff,
396 [WM8996_WRITE_SEQUENCER_384] = 0x60,
397 [WM8996_WRITE_SEQUENCER_386] = 0x601,
398 [WM8996_WRITE_SEQUENCER_388] = 0x61,
399 [WM8996_WRITE_SEQUENCER_390] = 0x601,
400 [WM8996_WRITE_SEQUENCER_392] = 0x50,
401 [WM8996_WRITE_SEQUENCER_394] = 0x300,
402 [WM8996_WRITE_SEQUENCER_396] = 0x1,
403 [WM8996_WRITE_SEQUENCER_398] = 0x304,
404 [WM8996_WRITE_SEQUENCER_400] = 0x40,
405 [WM8996_WRITE_SEQUENCER_402] = 0xf,
406 [WM8996_WRITE_SEQUENCER_404] = 0x1,
407 [WM8996_WRITE_SEQUENCER_407] = 0x100,
408};
409
410static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
411static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
412static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
413static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
414static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
415static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
416static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
417
418static const char *sidetone_hpf_text[] = {
419 "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
420};
421
422static const struct soc_enum sidetone_hpf =
423 SOC_ENUM_SINGLE(WM8996_SIDETONE, 7, 7, sidetone_hpf_text);
424
425static const char *hpf_mode_text[] = {
426 "HiFi", "Custom", "Voice"
427};
428
429static const struct soc_enum dsp1tx_hpf_mode =
430 SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 3, 3, hpf_mode_text);
431
432static const struct soc_enum dsp2tx_hpf_mode =
433 SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 3, 3, hpf_mode_text);
434
435static const char *hpf_cutoff_text[] = {
436 "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
437};
438
439static const struct soc_enum dsp1tx_hpf_cutoff =
440 SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text);
441
442static const struct soc_enum dsp2tx_hpf_cutoff =
443 SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text);
444
445static void wm8996_set_retune_mobile(struct snd_soc_codec *codec, int block)
446{
447 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
448 struct wm8996_pdata *pdata = &wm8996->pdata;
449 int base, best, best_val, save, i, cfg, iface;
450
451 if (!wm8996->num_retune_mobile_texts)
452 return;
453
454 switch (block) {
455 case 0:
456 base = WM8996_DSP1_RX_EQ_GAINS_1;
457 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
458 WM8996_DSP1RX_SRC)
459 iface = 1;
460 else
461 iface = 0;
462 break;
463 case 1:
464 base = WM8996_DSP1_RX_EQ_GAINS_2;
465 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
466 WM8996_DSP2RX_SRC)
467 iface = 1;
468 else
469 iface = 0;
470 break;
471 default:
472 return;
473 }
474
475 /* Find the version of the currently selected configuration
476 * with the nearest sample rate. */
477 cfg = wm8996->retune_mobile_cfg[block];
478 best = 0;
479 best_val = INT_MAX;
480 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
481 if (strcmp(pdata->retune_mobile_cfgs[i].name,
482 wm8996->retune_mobile_texts[cfg]) == 0 &&
483 abs(pdata->retune_mobile_cfgs[i].rate
484 - wm8996->rx_rate[iface]) < best_val) {
485 best = i;
486 best_val = abs(pdata->retune_mobile_cfgs[i].rate
487 - wm8996->rx_rate[iface]);
488 }
489 }
490
491 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
492 block,
493 pdata->retune_mobile_cfgs[best].name,
494 pdata->retune_mobile_cfgs[best].rate,
495 wm8996->rx_rate[iface]);
496
497 /* The EQ will be disabled while reconfiguring it, remember the
498 * current configuration.
499 */
500 save = snd_soc_read(codec, base);
501 save &= WM8996_DSP1RX_EQ_ENA;
502
503 for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
504 snd_soc_update_bits(codec, base + i, 0xffff,
505 pdata->retune_mobile_cfgs[best].regs[i]);
506
507 snd_soc_update_bits(codec, base, WM8996_DSP1RX_EQ_ENA, save);
508}
509
510/* Icky as hell but saves code duplication */
511static int wm8996_get_retune_mobile_block(const char *name)
512{
513 if (strcmp(name, "DSP1 EQ Mode") == 0)
514 return 0;
515 if (strcmp(name, "DSP2 EQ Mode") == 0)
516 return 1;
517 return -EINVAL;
518}
519
520static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
521 struct snd_ctl_elem_value *ucontrol)
522{
523 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
524 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
525 struct wm8996_pdata *pdata = &wm8996->pdata;
526 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
527 int value = ucontrol->value.integer.value[0];
528
529 if (block < 0)
530 return block;
531
532 if (value >= pdata->num_retune_mobile_cfgs)
533 return -EINVAL;
534
535 wm8996->retune_mobile_cfg[block] = value;
536
537 wm8996_set_retune_mobile(codec, block);
538
539 return 0;
540}
541
542static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
543 struct snd_ctl_elem_value *ucontrol)
544{
545 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
546 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
547 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
548
549 ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block];
550
551 return 0;
552}
553
554static const struct snd_kcontrol_new wm8996_snd_controls[] = {
555SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME,
556 WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
557SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME,
558 WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
559
560SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES,
561 0, 5, 24, 0, sidetone_tlv),
562SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES,
563 0, 5, 24, 0, sidetone_tlv),
564SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0),
565SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
566SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0),
567
568SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME,
569 WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
570SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME,
571 WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
572
573SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS,
574 13, 1, 0),
575SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0),
576SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
577SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
578
579SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS,
580 13, 1, 0),
581SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0),
582SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
583SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
584
585SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME,
586 WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
587SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1),
588
589SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME,
590 WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
591SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1),
592
593SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME,
594 WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
595SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME,
596 WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1),
597
598SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME,
599 WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
600SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME,
601 WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1),
602
603SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0),
604SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0),
605SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0),
606SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0),
607
608SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0),
609SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0),
610
611SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4,
612 8, 0, out_digital_tlv),
613SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4,
614 8, 0, out_digital_tlv),
615
616SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME,
617 WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
618SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUTPUT1_LEFT_VOLUME,
619 WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
620
621SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME,
622 WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
623SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUTPUT2_LEFT_VOLUME,
624 WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
625
626SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
627 spk_tlv),
628SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER,
629 WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1),
630SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER,
631 WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0),
632
633SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
634SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
635};
636
637static const struct snd_kcontrol_new wm8996_eq_controls[] = {
638SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
639 eq_tlv),
640SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
641 eq_tlv),
642SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
643 eq_tlv),
644SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
645 eq_tlv),
646SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
647 eq_tlv),
648
649SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
650 eq_tlv),
651SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
652 eq_tlv),
653SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
654 eq_tlv),
655SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
656 eq_tlv),
657SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
658 eq_tlv),
659};
660
661static int cp_event(struct snd_soc_dapm_widget *w,
662 struct snd_kcontrol *kcontrol, int event)
663{
664 switch (event) {
665 case SND_SOC_DAPM_POST_PMU:
666 msleep(5);
667 break;
668 default:
669 BUG();
670 return -EINVAL;
671 }
672
673 return 0;
674}
675
676static int rmv_short_event(struct snd_soc_dapm_widget *w,
677 struct snd_kcontrol *kcontrol, int event)
678{
679 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
680
681 /* Record which outputs we enabled */
682 switch (event) {
683 case SND_SOC_DAPM_PRE_PMD:
684 wm8996->hpout_pending &= ~w->shift;
685 break;
686 case SND_SOC_DAPM_PRE_PMU:
687 wm8996->hpout_pending |= w->shift;
688 break;
689 default:
690 BUG();
691 return -EINVAL;
692 }
693
694 return 0;
695}
696
697static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask)
698{
699 struct i2c_client *i2c = to_i2c_client(codec->dev);
700 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
701 int i, ret;
702 unsigned long timeout = 200;
703
704 snd_soc_write(codec, WM8996_DC_SERVO_2, mask);
705
706 /* Use the interrupt if possible */
707 do {
708 if (i2c->irq) {
709 timeout = wait_for_completion_timeout(&wm8996->dcs_done,
710 msecs_to_jiffies(200));
711 if (timeout == 0)
712 dev_err(codec->dev, "DC servo timed out\n");
713
714 } else {
715 msleep(1);
716 if (--i) {
717 timeout = 0;
718 break;
719 }
720 }
721
722 ret = snd_soc_read(codec, WM8996_DC_SERVO_2);
723 dev_dbg(codec->dev, "DC servo state: %x\n", ret);
724 } while (ret & mask);
725
726 if (timeout == 0)
727 dev_err(codec->dev, "DC servo timed out for %x\n", mask);
728 else
729 dev_dbg(codec->dev, "DC servo complete for %x\n", mask);
730}
731
732static void wm8996_seq_notifier(struct snd_soc_dapm_context *dapm,
733 enum snd_soc_dapm_type event, int subseq)
734{
735 struct snd_soc_codec *codec = container_of(dapm,
736 struct snd_soc_codec, dapm);
737 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
738 u16 val, mask;
739
740 /* Complete any pending DC servo starts */
741 if (wm8996->dcs_pending) {
742 dev_dbg(codec->dev, "Starting DC servo for %x\n",
743 wm8996->dcs_pending);
744
745 /* Trigger a startup sequence */
746 wait_for_dc_servo(codec, wm8996->dcs_pending
747 << WM8996_DCS_TRIG_STARTUP_0_SHIFT);
748
749 wm8996->dcs_pending = 0;
750 }
751
752 if (wm8996->hpout_pending != wm8996->hpout_ena) {
753 dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n",
754 wm8996->hpout_ena, wm8996->hpout_pending);
755
756 val = 0;
757 mask = 0;
758 if (wm8996->hpout_pending & HPOUT1L) {
759 val |= WM8996_HPOUT1L_RMV_SHORT;
760 mask |= WM8996_HPOUT1L_RMV_SHORT;
761 } else {
762 mask |= WM8996_HPOUT1L_RMV_SHORT |
763 WM8996_HPOUT1L_OUTP |
764 WM8996_HPOUT1L_DLY;
765 }
766
767 if (wm8996->hpout_pending & HPOUT1R) {
768 val |= WM8996_HPOUT1R_RMV_SHORT;
769 mask |= WM8996_HPOUT1R_RMV_SHORT;
770 } else {
771 mask |= WM8996_HPOUT1R_RMV_SHORT |
772 WM8996_HPOUT1R_OUTP |
773 WM8996_HPOUT1R_DLY;
774 }
775
776 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, mask, val);
777
778 val = 0;
779 mask = 0;
780 if (wm8996->hpout_pending & HPOUT2L) {
781 val |= WM8996_HPOUT2L_RMV_SHORT;
782 mask |= WM8996_HPOUT2L_RMV_SHORT;
783 } else {
784 mask |= WM8996_HPOUT2L_RMV_SHORT |
785 WM8996_HPOUT2L_OUTP |
786 WM8996_HPOUT2L_DLY;
787 }
788
789 if (wm8996->hpout_pending & HPOUT2R) {
790 val |= WM8996_HPOUT2R_RMV_SHORT;
791 mask |= WM8996_HPOUT2R_RMV_SHORT;
792 } else {
793 mask |= WM8996_HPOUT2R_RMV_SHORT |
794 WM8996_HPOUT2R_OUTP |
795 WM8996_HPOUT2R_DLY;
796 }
797
798 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_2, mask, val);
799
800 wm8996->hpout_ena = wm8996->hpout_pending;
801 }
802}
803
804static int dcs_start(struct snd_soc_dapm_widget *w,
805 struct snd_kcontrol *kcontrol, int event)
806{
807 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
808
809 switch (event) {
810 case SND_SOC_DAPM_POST_PMU:
811 wm8996->dcs_pending |= 1 << w->shift;
812 break;
813 default:
814 BUG();
815 return -EINVAL;
816 }
817
818 return 0;
819}
820
821static const char *sidetone_text[] = {
822 "IN1", "IN2",
823};
824
825static const struct soc_enum left_sidetone_enum =
826 SOC_ENUM_SINGLE(WM8996_SIDETONE, 0, 2, sidetone_text);
827
828static const struct snd_kcontrol_new left_sidetone =
829 SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
830
831static const struct soc_enum right_sidetone_enum =
832 SOC_ENUM_SINGLE(WM8996_SIDETONE, 1, 2, sidetone_text);
833
834static const struct snd_kcontrol_new right_sidetone =
835 SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
836
837static const char *spk_text[] = {
838 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
839};
840
841static const struct soc_enum spkl_enum =
842 SOC_ENUM_SINGLE(WM8996_LEFT_PDM_SPEAKER, 0, 4, spk_text);
843
844static const struct snd_kcontrol_new spkl_mux =
845 SOC_DAPM_ENUM("SPKL", spkl_enum);
846
847static const struct soc_enum spkr_enum =
848 SOC_ENUM_SINGLE(WM8996_RIGHT_PDM_SPEAKER, 0, 4, spk_text);
849
850static const struct snd_kcontrol_new spkr_mux =
851 SOC_DAPM_ENUM("SPKR", spkr_enum);
852
853static const char *dsp1rx_text[] = {
854 "AIF1", "AIF2"
855};
856
857static const struct soc_enum dsp1rx_enum =
858 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text);
859
860static const struct snd_kcontrol_new dsp1rx =
861 SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
862
863static const char *dsp2rx_text[] = {
864 "AIF2", "AIF1"
865};
866
867static const struct soc_enum dsp2rx_enum =
868 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text);
869
870static const struct snd_kcontrol_new dsp2rx =
871 SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
872
873static const char *aif2tx_text[] = {
874 "DSP2", "DSP1", "AIF1"
875};
876
877static const struct soc_enum aif2tx_enum =
878 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 6, 3, aif2tx_text);
879
880static const struct snd_kcontrol_new aif2tx =
881 SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
882
883static const char *inmux_text[] = {
884 "ADC", "DMIC1", "DMIC2"
885};
886
887static const struct soc_enum in1_enum =
888 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 0, 3, inmux_text);
889
890static const struct snd_kcontrol_new in1_mux =
891 SOC_DAPM_ENUM("IN1 Mux", in1_enum);
892
893static const struct soc_enum in2_enum =
894 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 4, 3, inmux_text);
895
896static const struct snd_kcontrol_new in2_mux =
897 SOC_DAPM_ENUM("IN2 Mux", in2_enum);
898
899static const struct snd_kcontrol_new dac2r_mix[] = {
900SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
901 5, 1, 0),
902SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
903 4, 1, 0),
904SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
905SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
906};
907
908static const struct snd_kcontrol_new dac2l_mix[] = {
909SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
910 5, 1, 0),
911SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
912 4, 1, 0),
913SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
914SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
915};
916
917static const struct snd_kcontrol_new dac1r_mix[] = {
918SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
919 5, 1, 0),
920SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
921 4, 1, 0),
922SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
923SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
924};
925
926static const struct snd_kcontrol_new dac1l_mix[] = {
927SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
928 5, 1, 0),
929SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
930 4, 1, 0),
931SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
932SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
933};
934
935static const struct snd_kcontrol_new dsp1txl[] = {
936SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
937 1, 1, 0),
938SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
939 0, 1, 0),
940};
941
942static const struct snd_kcontrol_new dsp1txr[] = {
943SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
944 1, 1, 0),
945SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
946 0, 1, 0),
947};
948
949static const struct snd_kcontrol_new dsp2txl[] = {
950SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
951 1, 1, 0),
952SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
953 0, 1, 0),
954};
955
956static const struct snd_kcontrol_new dsp2txr[] = {
957SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
958 1, 1, 0),
959SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
960 0, 1, 0),
961};
962
963
964static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = {
965SND_SOC_DAPM_INPUT("IN1LN"),
966SND_SOC_DAPM_INPUT("IN1LP"),
967SND_SOC_DAPM_INPUT("IN1RN"),
968SND_SOC_DAPM_INPUT("IN1RP"),
969
970SND_SOC_DAPM_INPUT("IN2LN"),
971SND_SOC_DAPM_INPUT("IN2LP"),
972SND_SOC_DAPM_INPUT("IN2RN"),
973SND_SOC_DAPM_INPUT("IN2RP"),
974
975SND_SOC_DAPM_INPUT("DMIC1DAT"),
976SND_SOC_DAPM_INPUT("DMIC2DAT"),
977
978SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0),
979SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0),
980SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0),
981SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event,
982 SND_SOC_DAPM_POST_PMU),
983
984SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
985SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0),
986SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0),
987
988SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
989SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
990
991SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANAGEMENT_7, 2, 0, &in1_mux),
992SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANAGEMENT_7, 3, 0, &in1_mux),
993SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANAGEMENT_7, 6, 0, &in2_mux),
994SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANAGEMENT_7, 7, 0, &in2_mux),
995
996SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
997SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
998
999SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0),
1000SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0),
1001SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0),
1002SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0),
1003
1004SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0),
1005SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0),
1006
1007SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
1008SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
1009
1010SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0),
1011SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0),
1012SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0),
1013SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0),
1014
1015SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0,
1016 dsp2txl, ARRAY_SIZE(dsp2txl)),
1017SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0,
1018 dsp2txr, ARRAY_SIZE(dsp2txr)),
1019SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0,
1020 dsp1txl, ARRAY_SIZE(dsp1txl)),
1021SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0,
1022 dsp1txr, ARRAY_SIZE(dsp1txr)),
1023
1024SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1025 dac2l_mix, ARRAY_SIZE(dac2l_mix)),
1026SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1027 dac2r_mix, ARRAY_SIZE(dac2r_mix)),
1028SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1029 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1030SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1031 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1032
1033SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0),
1034SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0),
1035SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0),
1036SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0),
1037
1038SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 1,
1039 WM8996_POWER_MANAGEMENT_4, 9, 0),
1040SND_SOC_DAPM_AIF_IN("AIF2RX0", "AIF2 Playback", 2,
1041 WM8996_POWER_MANAGEMENT_4, 8, 0),
1042
1043SND_SOC_DAPM_AIF_IN("AIF2TX1", "AIF2 Capture", 1,
1044 WM8996_POWER_MANAGEMENT_6, 9, 0),
1045SND_SOC_DAPM_AIF_IN("AIF2TX0", "AIF2 Capture", 2,
1046 WM8996_POWER_MANAGEMENT_6, 8, 0),
1047
1048SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 5,
1049 WM8996_POWER_MANAGEMENT_4, 5, 0),
1050SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 4,
1051 WM8996_POWER_MANAGEMENT_4, 4, 0),
1052SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 3,
1053 WM8996_POWER_MANAGEMENT_4, 3, 0),
1054SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 2,
1055 WM8996_POWER_MANAGEMENT_4, 2, 0),
1056SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 1,
1057 WM8996_POWER_MANAGEMENT_4, 1, 0),
1058SND_SOC_DAPM_AIF_IN("AIF1RX0", "AIF1 Playback", 0,
1059 WM8996_POWER_MANAGEMENT_4, 0, 0),
1060
1061SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 5,
1062 WM8996_POWER_MANAGEMENT_6, 5, 0),
1063SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 4,
1064 WM8996_POWER_MANAGEMENT_6, 4, 0),
1065SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 3,
1066 WM8996_POWER_MANAGEMENT_6, 3, 0),
1067SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 2,
1068 WM8996_POWER_MANAGEMENT_6, 2, 0),
1069SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 1,
1070 WM8996_POWER_MANAGEMENT_6, 1, 0),
1071SND_SOC_DAPM_AIF_OUT("AIF1TX0", "AIF1 Capture", 0,
1072 WM8996_POWER_MANAGEMENT_6, 0, 0),
1073
1074/* We route as stereo pairs so define some dummy widgets to squash
1075 * things down for now. RXA = 0,1, RXB = 2,3 and so on */
1076SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
1077SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
1078SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
1079SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
1080SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
1081
1082SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
1083SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
1084SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
1085
1086SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
1087SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
1088SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
1089SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
1090
1091SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
1092SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0),
1093SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start,
1094 SND_SOC_DAPM_POST_PMU),
1095SND_SOC_DAPM_PGA_S("HPOUT2L_OUTP", 3, WM8996_ANALOGUE_HP_2, 6, 0, NULL, 0),
1096SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
1097 rmv_short_event,
1098 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1099
1100SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
1101SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0),
1102SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start,
1103 SND_SOC_DAPM_POST_PMU),
1104SND_SOC_DAPM_PGA_S("HPOUT2R_OUTP", 3, WM8996_ANALOGUE_HP_2, 2, 0, NULL, 0),
1105SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
1106 rmv_short_event,
1107 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1108
1109SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
1110SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0),
1111SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start,
1112 SND_SOC_DAPM_POST_PMU),
1113SND_SOC_DAPM_PGA_S("HPOUT1L_OUTP", 3, WM8996_ANALOGUE_HP_1, 6, 0, NULL, 0),
1114SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
1115 rmv_short_event,
1116 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1117
1118SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
1119SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0),
1120SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start,
1121 SND_SOC_DAPM_POST_PMU),
1122SND_SOC_DAPM_PGA_S("HPOUT1R_OUTP", 3, WM8996_ANALOGUE_HP_1, 2, 0, NULL, 0),
1123SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
1124 rmv_short_event,
1125 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1126
1127SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1128SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1129SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1130SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1131SND_SOC_DAPM_OUTPUT("SPKDAT"),
1132};
1133
1134static const struct snd_soc_dapm_route wm8996_dapm_routes[] = {
1135 { "AIFCLK", NULL, "SYSCLK" },
1136 { "SYSDSPCLK", NULL, "SYSCLK" },
1137 { "Charge Pump", NULL, "SYSCLK" },
1138
1139 { "MICB1", NULL, "LDO2" },
1140 { "MICB2", NULL, "LDO2" },
1141
1142 { "IN1L PGA", NULL, "IN2LN" },
1143 { "IN1L PGA", NULL, "IN2LP" },
1144 { "IN1L PGA", NULL, "IN1LN" },
1145 { "IN1L PGA", NULL, "IN1LP" },
1146
1147 { "IN1R PGA", NULL, "IN2RN" },
1148 { "IN1R PGA", NULL, "IN2RP" },
1149 { "IN1R PGA", NULL, "IN1RN" },
1150 { "IN1R PGA", NULL, "IN1RP" },
1151
1152 { "ADCL", NULL, "IN1L PGA" },
1153
1154 { "ADCR", NULL, "IN1R PGA" },
1155
1156 { "DMIC1L", NULL, "DMIC1DAT" },
1157 { "DMIC1R", NULL, "DMIC1DAT" },
1158 { "DMIC2L", NULL, "DMIC2DAT" },
1159 { "DMIC2R", NULL, "DMIC2DAT" },
1160
1161 { "DMIC2L", NULL, "DMIC2" },
1162 { "DMIC2R", NULL, "DMIC2" },
1163 { "DMIC1L", NULL, "DMIC1" },
1164 { "DMIC1R", NULL, "DMIC1" },
1165
1166 { "IN1L Mux", "ADC", "ADCL" },
1167 { "IN1L Mux", "DMIC1", "DMIC1L" },
1168 { "IN1L Mux", "DMIC2", "DMIC2L" },
1169
1170 { "IN1R Mux", "ADC", "ADCR" },
1171 { "IN1R Mux", "DMIC1", "DMIC1R" },
1172 { "IN1R Mux", "DMIC2", "DMIC2R" },
1173
1174 { "IN2L Mux", "ADC", "ADCL" },
1175 { "IN2L Mux", "DMIC1", "DMIC1L" },
1176 { "IN2L Mux", "DMIC2", "DMIC2L" },
1177
1178 { "IN2R Mux", "ADC", "ADCR" },
1179 { "IN2R Mux", "DMIC1", "DMIC1R" },
1180 { "IN2R Mux", "DMIC2", "DMIC2R" },
1181
1182 { "Left Sidetone", "IN1", "IN1L Mux" },
1183 { "Left Sidetone", "IN2", "IN2L Mux" },
1184
1185 { "Right Sidetone", "IN1", "IN1R Mux" },
1186 { "Right Sidetone", "IN2", "IN2R Mux" },
1187
1188 { "DSP1TXL", "IN1 Switch", "IN1L Mux" },
1189 { "DSP1TXR", "IN1 Switch", "IN1R Mux" },
1190
1191 { "DSP2TXL", "IN1 Switch", "IN2L Mux" },
1192 { "DSP2TXR", "IN1 Switch", "IN2R Mux" },
1193
1194 { "AIF1TX0", NULL, "DSP1TXL" },
1195 { "AIF1TX1", NULL, "DSP1TXR" },
1196 { "AIF1TX2", NULL, "DSP2TXL" },
1197 { "AIF1TX3", NULL, "DSP2TXR" },
1198 { "AIF1TX4", NULL, "AIF2RX0" },
1199 { "AIF1TX5", NULL, "AIF2RX1" },
1200
1201 { "AIF1RX0", NULL, "AIFCLK" },
1202 { "AIF1RX1", NULL, "AIFCLK" },
1203 { "AIF1RX2", NULL, "AIFCLK" },
1204 { "AIF1RX3", NULL, "AIFCLK" },
1205 { "AIF1RX4", NULL, "AIFCLK" },
1206 { "AIF1RX5", NULL, "AIFCLK" },
1207
1208 { "AIF2RX0", NULL, "AIFCLK" },
1209 { "AIF2RX1", NULL, "AIFCLK" },
1210
1211 { "AIF1TX0", NULL, "AIFCLK" },
1212 { "AIF1TX1", NULL, "AIFCLK" },
1213 { "AIF1TX2", NULL, "AIFCLK" },
1214 { "AIF1TX3", NULL, "AIFCLK" },
1215 { "AIF1TX4", NULL, "AIFCLK" },
1216 { "AIF1TX5", NULL, "AIFCLK" },
1217
1218 { "AIF2TX0", NULL, "AIFCLK" },
1219 { "AIF2TX1", NULL, "AIFCLK" },
1220
1221 { "DSP1RXL", NULL, "SYSDSPCLK" },
1222 { "DSP1RXR", NULL, "SYSDSPCLK" },
1223 { "DSP2RXL", NULL, "SYSDSPCLK" },
1224 { "DSP2RXR", NULL, "SYSDSPCLK" },
1225 { "DSP1TXL", NULL, "SYSDSPCLK" },
1226 { "DSP1TXR", NULL, "SYSDSPCLK" },
1227 { "DSP2TXL", NULL, "SYSDSPCLK" },
1228 { "DSP2TXR", NULL, "SYSDSPCLK" },
1229
1230 { "AIF1RXA", NULL, "AIF1RX0" },
1231 { "AIF1RXA", NULL, "AIF1RX1" },
1232 { "AIF1RXB", NULL, "AIF1RX2" },
1233 { "AIF1RXB", NULL, "AIF1RX3" },
1234 { "AIF1RXC", NULL, "AIF1RX4" },
1235 { "AIF1RXC", NULL, "AIF1RX5" },
1236
1237 { "AIF2RX", NULL, "AIF2RX0" },
1238 { "AIF2RX", NULL, "AIF2RX1" },
1239
1240 { "AIF2TX", "DSP2", "DSP2TX" },
1241 { "AIF2TX", "DSP1", "DSP1RX" },
1242 { "AIF2TX", "AIF1", "AIF1RXC" },
1243
1244 { "DSP1RXL", NULL, "DSP1RX" },
1245 { "DSP1RXR", NULL, "DSP1RX" },
1246 { "DSP2RXL", NULL, "DSP2RX" },
1247 { "DSP2RXR", NULL, "DSP2RX" },
1248
1249 { "DSP2TX", NULL, "DSP2TXL" },
1250 { "DSP2TX", NULL, "DSP2TXR" },
1251
1252 { "DSP1RX", "AIF1", "AIF1RXA" },
1253 { "DSP1RX", "AIF2", "AIF2RX" },
1254
1255 { "DSP2RX", "AIF1", "AIF1RXB" },
1256 { "DSP2RX", "AIF2", "AIF2RX" },
1257
1258 { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
1259 { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
1260 { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1261 { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1262
1263 { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
1264 { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
1265 { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1266 { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1267
1268 { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
1269 { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
1270 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1271 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1272
1273 { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
1274 { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
1275 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1276 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1277
1278 { "DAC1L", NULL, "DAC1L Mixer" },
1279 { "DAC1R", NULL, "DAC1R Mixer" },
1280 { "DAC2L", NULL, "DAC2L Mixer" },
1281 { "DAC2R", NULL, "DAC2R Mixer" },
1282
1283 { "HPOUT2L PGA", NULL, "Charge Pump" },
1284 { "HPOUT2L PGA", NULL, "DAC2L" },
1285 { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
1286 { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
1287 { "HPOUT2L_OUTP", NULL, "HPOUT2L_DCS" },
1288 { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_OUTP" },
1289
1290 { "HPOUT2R PGA", NULL, "Charge Pump" },
1291 { "HPOUT2R PGA", NULL, "DAC2R" },
1292 { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
1293 { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
1294 { "HPOUT2R_OUTP", NULL, "HPOUT2R_DCS" },
1295 { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_OUTP" },
1296
1297 { "HPOUT1L PGA", NULL, "Charge Pump" },
1298 { "HPOUT1L PGA", NULL, "DAC1L" },
1299 { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
1300 { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
1301 { "HPOUT1L_OUTP", NULL, "HPOUT1L_DCS" },
1302 { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_OUTP" },
1303
1304 { "HPOUT1R PGA", NULL, "Charge Pump" },
1305 { "HPOUT1R PGA", NULL, "DAC1R" },
1306 { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
1307 { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
1308 { "HPOUT1R_OUTP", NULL, "HPOUT1R_DCS" },
1309 { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_OUTP" },
1310
1311 { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
1312 { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
1313 { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
1314 { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
1315
1316 { "SPKL", "DAC1L", "DAC1L" },
1317 { "SPKL", "DAC1R", "DAC1R" },
1318 { "SPKL", "DAC2L", "DAC2L" },
1319 { "SPKL", "DAC2R", "DAC2R" },
1320
1321 { "SPKR", "DAC1L", "DAC1L" },
1322 { "SPKR", "DAC1R", "DAC1R" },
1323 { "SPKR", "DAC2L", "DAC2L" },
1324 { "SPKR", "DAC2R", "DAC2R" },
1325
1326 { "SPKL PGA", NULL, "SPKL" },
1327 { "SPKR PGA", NULL, "SPKR" },
1328
1329 { "SPKDAT", NULL, "SPKL PGA" },
1330 { "SPKDAT", NULL, "SPKR PGA" },
1331};
1332
1333static int wm8996_readable_register(struct snd_soc_codec *codec,
1334 unsigned int reg)
1335{
1336 /* Due to the sparseness of the register map the compiler
1337 * output from an explicit switch statement ends up being much
1338 * more efficient than a table.
1339 */
1340 switch (reg) {
1341 case WM8996_SOFTWARE_RESET:
1342 case WM8996_POWER_MANAGEMENT_1:
1343 case WM8996_POWER_MANAGEMENT_2:
1344 case WM8996_POWER_MANAGEMENT_3:
1345 case WM8996_POWER_MANAGEMENT_4:
1346 case WM8996_POWER_MANAGEMENT_5:
1347 case WM8996_POWER_MANAGEMENT_6:
1348 case WM8996_POWER_MANAGEMENT_7:
1349 case WM8996_POWER_MANAGEMENT_8:
1350 case WM8996_LEFT_LINE_INPUT_VOLUME:
1351 case WM8996_RIGHT_LINE_INPUT_VOLUME:
1352 case WM8996_LINE_INPUT_CONTROL:
1353 case WM8996_DAC1_HPOUT1_VOLUME:
1354 case WM8996_DAC2_HPOUT2_VOLUME:
1355 case WM8996_DAC1_LEFT_VOLUME:
1356 case WM8996_DAC1_RIGHT_VOLUME:
1357 case WM8996_DAC2_LEFT_VOLUME:
1358 case WM8996_DAC2_RIGHT_VOLUME:
1359 case WM8996_OUTPUT1_LEFT_VOLUME:
1360 case WM8996_OUTPUT1_RIGHT_VOLUME:
1361 case WM8996_OUTPUT2_LEFT_VOLUME:
1362 case WM8996_OUTPUT2_RIGHT_VOLUME:
1363 case WM8996_MICBIAS_1:
1364 case WM8996_MICBIAS_2:
1365 case WM8996_LDO_1:
1366 case WM8996_LDO_2:
1367 case WM8996_ACCESSORY_DETECT_MODE_1:
1368 case WM8996_ACCESSORY_DETECT_MODE_2:
1369 case WM8996_HEADPHONE_DETECT_1:
1370 case WM8996_HEADPHONE_DETECT_2:
1371 case WM8996_MIC_DETECT_1:
1372 case WM8996_MIC_DETECT_2:
1373 case WM8996_MIC_DETECT_3:
1374 case WM8996_CHARGE_PUMP_1:
1375 case WM8996_CHARGE_PUMP_2:
1376 case WM8996_DC_SERVO_1:
1377 case WM8996_DC_SERVO_2:
1378 case WM8996_DC_SERVO_3:
1379 case WM8996_DC_SERVO_5:
1380 case WM8996_DC_SERVO_6:
1381 case WM8996_DC_SERVO_7:
1382 case WM8996_DC_SERVO_READBACK_0:
1383 case WM8996_ANALOGUE_HP_1:
1384 case WM8996_ANALOGUE_HP_2:
1385 case WM8996_CHIP_REVISION:
1386 case WM8996_CONTROL_INTERFACE_1:
1387 case WM8996_WRITE_SEQUENCER_CTRL_1:
1388 case WM8996_WRITE_SEQUENCER_CTRL_2:
1389 case WM8996_AIF_CLOCKING_1:
1390 case WM8996_AIF_CLOCKING_2:
1391 case WM8996_CLOCKING_1:
1392 case WM8996_CLOCKING_2:
1393 case WM8996_AIF_RATE:
1394 case WM8996_FLL_CONTROL_1:
1395 case WM8996_FLL_CONTROL_2:
1396 case WM8996_FLL_CONTROL_3:
1397 case WM8996_FLL_CONTROL_4:
1398 case WM8996_FLL_CONTROL_5:
1399 case WM8996_FLL_CONTROL_6:
1400 case WM8996_FLL_EFS_1:
1401 case WM8996_FLL_EFS_2:
1402 case WM8996_AIF1_CONTROL:
1403 case WM8996_AIF1_BCLK:
1404 case WM8996_AIF1_TX_LRCLK_1:
1405 case WM8996_AIF1_TX_LRCLK_2:
1406 case WM8996_AIF1_RX_LRCLK_1:
1407 case WM8996_AIF1_RX_LRCLK_2:
1408 case WM8996_AIF1TX_DATA_CONFIGURATION_1:
1409 case WM8996_AIF1TX_DATA_CONFIGURATION_2:
1410 case WM8996_AIF1RX_DATA_CONFIGURATION:
1411 case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION:
1412 case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION:
1413 case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION:
1414 case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION:
1415 case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION:
1416 case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION:
1417 case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION:
1418 case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION:
1419 case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION:
1420 case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION:
1421 case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION:
1422 case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION:
1423 case WM8996_AIF1RX_MONO_CONFIGURATION:
1424 case WM8996_AIF1TX_TEST:
1425 case WM8996_AIF2_CONTROL:
1426 case WM8996_AIF2_BCLK:
1427 case WM8996_AIF2_TX_LRCLK_1:
1428 case WM8996_AIF2_TX_LRCLK_2:
1429 case WM8996_AIF2_RX_LRCLK_1:
1430 case WM8996_AIF2_RX_LRCLK_2:
1431 case WM8996_AIF2TX_DATA_CONFIGURATION_1:
1432 case WM8996_AIF2TX_DATA_CONFIGURATION_2:
1433 case WM8996_AIF2RX_DATA_CONFIGURATION:
1434 case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION:
1435 case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION:
1436 case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION:
1437 case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION:
1438 case WM8996_AIF2RX_MONO_CONFIGURATION:
1439 case WM8996_AIF2TX_TEST:
1440 case WM8996_DSP1_TX_LEFT_VOLUME:
1441 case WM8996_DSP1_TX_RIGHT_VOLUME:
1442 case WM8996_DSP1_RX_LEFT_VOLUME:
1443 case WM8996_DSP1_RX_RIGHT_VOLUME:
1444 case WM8996_DSP1_TX_FILTERS:
1445 case WM8996_DSP1_RX_FILTERS_1:
1446 case WM8996_DSP1_RX_FILTERS_2:
1447 case WM8996_DSP1_DRC_1:
1448 case WM8996_DSP1_DRC_2:
1449 case WM8996_DSP1_DRC_3:
1450 case WM8996_DSP1_DRC_4:
1451 case WM8996_DSP1_DRC_5:
1452 case WM8996_DSP1_RX_EQ_GAINS_1:
1453 case WM8996_DSP1_RX_EQ_GAINS_2:
1454 case WM8996_DSP1_RX_EQ_BAND_1_A:
1455 case WM8996_DSP1_RX_EQ_BAND_1_B:
1456 case WM8996_DSP1_RX_EQ_BAND_1_PG:
1457 case WM8996_DSP1_RX_EQ_BAND_2_A:
1458 case WM8996_DSP1_RX_EQ_BAND_2_B:
1459 case WM8996_DSP1_RX_EQ_BAND_2_C:
1460 case WM8996_DSP1_RX_EQ_BAND_2_PG:
1461 case WM8996_DSP1_RX_EQ_BAND_3_A:
1462 case WM8996_DSP1_RX_EQ_BAND_3_B:
1463 case WM8996_DSP1_RX_EQ_BAND_3_C:
1464 case WM8996_DSP1_RX_EQ_BAND_3_PG:
1465 case WM8996_DSP1_RX_EQ_BAND_4_A:
1466 case WM8996_DSP1_RX_EQ_BAND_4_B:
1467 case WM8996_DSP1_RX_EQ_BAND_4_C:
1468 case WM8996_DSP1_RX_EQ_BAND_4_PG:
1469 case WM8996_DSP1_RX_EQ_BAND_5_A:
1470 case WM8996_DSP1_RX_EQ_BAND_5_B:
1471 case WM8996_DSP1_RX_EQ_BAND_5_PG:
1472 case WM8996_DSP2_TX_LEFT_VOLUME:
1473 case WM8996_DSP2_TX_RIGHT_VOLUME:
1474 case WM8996_DSP2_RX_LEFT_VOLUME:
1475 case WM8996_DSP2_RX_RIGHT_VOLUME:
1476 case WM8996_DSP2_TX_FILTERS:
1477 case WM8996_DSP2_RX_FILTERS_1:
1478 case WM8996_DSP2_RX_FILTERS_2:
1479 case WM8996_DSP2_DRC_1:
1480 case WM8996_DSP2_DRC_2:
1481 case WM8996_DSP2_DRC_3:
1482 case WM8996_DSP2_DRC_4:
1483 case WM8996_DSP2_DRC_5:
1484 case WM8996_DSP2_RX_EQ_GAINS_1:
1485 case WM8996_DSP2_RX_EQ_GAINS_2:
1486 case WM8996_DSP2_RX_EQ_BAND_1_A:
1487 case WM8996_DSP2_RX_EQ_BAND_1_B:
1488 case WM8996_DSP2_RX_EQ_BAND_1_PG:
1489 case WM8996_DSP2_RX_EQ_BAND_2_A:
1490 case WM8996_DSP2_RX_EQ_BAND_2_B:
1491 case WM8996_DSP2_RX_EQ_BAND_2_C:
1492 case WM8996_DSP2_RX_EQ_BAND_2_PG:
1493 case WM8996_DSP2_RX_EQ_BAND_3_A:
1494 case WM8996_DSP2_RX_EQ_BAND_3_B:
1495 case WM8996_DSP2_RX_EQ_BAND_3_C:
1496 case WM8996_DSP2_RX_EQ_BAND_3_PG:
1497 case WM8996_DSP2_RX_EQ_BAND_4_A:
1498 case WM8996_DSP2_RX_EQ_BAND_4_B:
1499 case WM8996_DSP2_RX_EQ_BAND_4_C:
1500 case WM8996_DSP2_RX_EQ_BAND_4_PG:
1501 case WM8996_DSP2_RX_EQ_BAND_5_A:
1502 case WM8996_DSP2_RX_EQ_BAND_5_B:
1503 case WM8996_DSP2_RX_EQ_BAND_5_PG:
1504 case WM8996_DAC1_MIXER_VOLUMES:
1505 case WM8996_DAC1_LEFT_MIXER_ROUTING:
1506 case WM8996_DAC1_RIGHT_MIXER_ROUTING:
1507 case WM8996_DAC2_MIXER_VOLUMES:
1508 case WM8996_DAC2_LEFT_MIXER_ROUTING:
1509 case WM8996_DAC2_RIGHT_MIXER_ROUTING:
1510 case WM8996_DSP1_TX_LEFT_MIXER_ROUTING:
1511 case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING:
1512 case WM8996_DSP2_TX_LEFT_MIXER_ROUTING:
1513 case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING:
1514 case WM8996_DSP_TX_MIXER_SELECT:
1515 case WM8996_DAC_SOFTMUTE:
1516 case WM8996_OVERSAMPLING:
1517 case WM8996_SIDETONE:
1518 case WM8996_GPIO_1:
1519 case WM8996_GPIO_2:
1520 case WM8996_GPIO_3:
1521 case WM8996_GPIO_4:
1522 case WM8996_GPIO_5:
1523 case WM8996_PULL_CONTROL_1:
1524 case WM8996_PULL_CONTROL_2:
1525 case WM8996_INTERRUPT_STATUS_1:
1526 case WM8996_INTERRUPT_STATUS_2:
1527 case WM8996_INTERRUPT_RAW_STATUS_2:
1528 case WM8996_INTERRUPT_STATUS_1_MASK:
1529 case WM8996_INTERRUPT_STATUS_2_MASK:
1530 case WM8996_INTERRUPT_CONTROL:
1531 case WM8996_LEFT_PDM_SPEAKER:
1532 case WM8996_RIGHT_PDM_SPEAKER:
1533 case WM8996_PDM_SPEAKER_MUTE_SEQUENCE:
1534 case WM8996_PDM_SPEAKER_VOLUME:
1535 return 1;
1536 default:
1537 return 0;
1538 }
1539}
1540
1541static int wm8996_volatile_register(struct snd_soc_codec *codec,
1542 unsigned int reg)
1543{
1544 switch (reg) {
1545 case WM8996_SOFTWARE_RESET:
1546 case WM8996_CHIP_REVISION:
1547 case WM8996_LDO_1:
1548 case WM8996_LDO_2:
1549 case WM8996_INTERRUPT_STATUS_1:
1550 case WM8996_INTERRUPT_STATUS_2:
1551 case WM8996_INTERRUPT_RAW_STATUS_2:
1552 case WM8996_DC_SERVO_READBACK_0:
1553 case WM8996_DC_SERVO_2:
1554 case WM8996_DC_SERVO_6:
1555 case WM8996_DC_SERVO_7:
1556 case WM8996_FLL_CONTROL_6:
1557 case WM8996_MIC_DETECT_3:
1558 case WM8996_HEADPHONE_DETECT_1:
1559 case WM8996_HEADPHONE_DETECT_2:
1560 return 1;
1561 default:
1562 return 0;
1563 }
1564}
1565
1566static int wm8996_reset(struct snd_soc_codec *codec)
1567{
1568 return snd_soc_write(codec, WM8996_SOFTWARE_RESET, 0x8915);
1569}
1570
1571static const int bclk_divs[] = {
1572 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
1573};
1574
1575static void wm8996_update_bclk(struct snd_soc_codec *codec)
1576{
1577 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1578 int aif, best, cur_val, bclk_rate, bclk_reg, i;
1579
1580 /* Don't bother if we're in a low frequency idle mode that
1581 * can't support audio.
1582 */
1583 if (wm8996->sysclk < 64000)
1584 return;
1585
1586 for (aif = 0; aif < WM8996_AIFS; aif++) {
1587 switch (aif) {
1588 case 0:
1589 bclk_reg = WM8996_AIF1_BCLK;
1590 break;
1591 case 1:
1592 bclk_reg = WM8996_AIF2_BCLK;
1593 break;
1594 }
1595
1596 bclk_rate = wm8996->bclk_rate[aif];
1597
1598 /* Pick a divisor for BCLK as close as we can get to ideal */
1599 best = 0;
1600 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1601 cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate;
1602 if (cur_val < 0) /* BCLK table is sorted */
1603 break;
1604 best = i;
1605 }
1606 bclk_rate = wm8996->sysclk / bclk_divs[best];
1607 dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1608 bclk_divs[best], bclk_rate);
1609
1610 snd_soc_update_bits(codec, bclk_reg,
1611 WM8996_AIF1_BCLK_DIV_MASK, best);
1612 }
1613}
1614
1615static int wm8996_set_bias_level(struct snd_soc_codec *codec,
1616 enum snd_soc_bias_level level)
1617{
1618 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1619 int ret;
1620
1621 switch (level) {
1622 case SND_SOC_BIAS_ON:
1623 break;
1624
1625 case SND_SOC_BIAS_PREPARE:
1626 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
1627 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
1628 WM8996_BG_ENA, WM8996_BG_ENA);
1629 msleep(2);
1630 }
1631 break;
1632
1633 case SND_SOC_BIAS_STANDBY:
1634 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1635 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
1636 wm8996->supplies);
1637 if (ret != 0) {
1638 dev_err(codec->dev,
1639 "Failed to enable supplies: %d\n",
1640 ret);
1641 return ret;
1642 }
1643
1644 if (wm8996->pdata.ldo_ena >= 0) {
1645 gpio_set_value_cansleep(wm8996->pdata.ldo_ena,
1646 1);
1647 msleep(5);
1648 }
1649
1650 codec->cache_only = false;
1651 snd_soc_cache_sync(codec);
1652 }
1653
1654 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
1655 WM8996_BG_ENA, 0);
1656 break;
1657
1658 case SND_SOC_BIAS_OFF:
1659 codec->cache_only = true;
1660 if (wm8996->pdata.ldo_ena >= 0)
1661 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
1662 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies),
1663 wm8996->supplies);
1664 break;
1665 }
1666
1667 codec->dapm.bias_level = level;
1668
1669 return 0;
1670}
1671
1672static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1673{
1674 struct snd_soc_codec *codec = dai->codec;
1675 int aifctrl = 0;
1676 int bclk = 0;
1677 int lrclk_tx = 0;
1678 int lrclk_rx = 0;
1679 int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
1680
1681 switch (dai->id) {
1682 case 0:
1683 aifctrl_reg = WM8996_AIF1_CONTROL;
1684 bclk_reg = WM8996_AIF1_BCLK;
1685 lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2;
1686 lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2;
1687 break;
1688 case 1:
1689 aifctrl_reg = WM8996_AIF2_CONTROL;
1690 bclk_reg = WM8996_AIF2_BCLK;
1691 lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2;
1692 lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2;
1693 break;
1694 default:
1695 BUG();
1696 return -EINVAL;
1697 }
1698
1699 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1700 case SND_SOC_DAIFMT_NB_NF:
1701 break;
1702 case SND_SOC_DAIFMT_IB_NF:
1703 bclk |= WM8996_AIF1_BCLK_INV;
1704 break;
1705 case SND_SOC_DAIFMT_NB_IF:
1706 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1707 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1708 break;
1709 case SND_SOC_DAIFMT_IB_IF:
1710 bclk |= WM8996_AIF1_BCLK_INV;
1711 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1712 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1713 break;
1714 }
1715
1716 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1717 case SND_SOC_DAIFMT_CBS_CFS:
1718 break;
1719 case SND_SOC_DAIFMT_CBS_CFM:
1720 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1721 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1722 break;
1723 case SND_SOC_DAIFMT_CBM_CFS:
1724 bclk |= WM8996_AIF1_BCLK_MSTR;
1725 break;
1726 case SND_SOC_DAIFMT_CBM_CFM:
1727 bclk |= WM8996_AIF1_BCLK_MSTR;
1728 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1729 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1730 break;
1731 default:
1732 return -EINVAL;
1733 }
1734
1735 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1736 case SND_SOC_DAIFMT_DSP_A:
1737 break;
1738 case SND_SOC_DAIFMT_DSP_B:
1739 aifctrl |= 1;
1740 break;
1741 case SND_SOC_DAIFMT_I2S:
1742 aifctrl |= 2;
1743 break;
1744 case SND_SOC_DAIFMT_LEFT_J:
1745 aifctrl |= 3;
1746 break;
1747 default:
1748 return -EINVAL;
1749 }
1750
1751 snd_soc_update_bits(codec, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl);
1752 snd_soc_update_bits(codec, bclk_reg,
1753 WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR,
1754 bclk);
1755 snd_soc_update_bits(codec, lrclk_tx_reg,
1756 WM8996_AIF1TX_LRCLK_INV |
1757 WM8996_AIF1TX_LRCLK_MSTR,
1758 lrclk_tx);
1759 snd_soc_update_bits(codec, lrclk_rx_reg,
1760 WM8996_AIF1RX_LRCLK_INV |
1761 WM8996_AIF1RX_LRCLK_MSTR,
1762 lrclk_rx);
1763
1764 return 0;
1765}
1766
1767static const int dsp_divs[] = {
1768 48000, 32000, 16000, 8000
1769};
1770
1771static int wm8996_hw_params(struct snd_pcm_substream *substream,
1772 struct snd_pcm_hw_params *params,
1773 struct snd_soc_dai *dai)
1774{
1775 struct snd_soc_codec *codec = dai->codec;
1776 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1777 int bits, i, bclk_rate;
1778 int aifdata = 0;
1779 int lrclk = 0;
1780 int dsp = 0;
1781 int aifdata_reg, lrclk_reg, dsp_shift;
1782
1783 switch (dai->id) {
1784 case 0:
1785 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1786 (snd_soc_read(codec, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) {
1787 aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION;
1788 lrclk_reg = WM8996_AIF1_RX_LRCLK_1;
1789 } else {
1790 aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1;
1791 lrclk_reg = WM8996_AIF1_TX_LRCLK_1;
1792 }
1793 dsp_shift = 0;
1794 break;
1795 case 1:
1796 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1797 (snd_soc_read(codec, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) {
1798 aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION;
1799 lrclk_reg = WM8996_AIF2_RX_LRCLK_1;
1800 } else {
1801 aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1;
1802 lrclk_reg = WM8996_AIF2_TX_LRCLK_1;
1803 }
1804 dsp_shift = WM8996_DSP2_DIV_SHIFT;
1805 break;
1806 default:
1807 BUG();
1808 return -EINVAL;
1809 }
1810
1811 bclk_rate = snd_soc_params_to_bclk(params);
1812 if (bclk_rate < 0) {
1813 dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
1814 return bclk_rate;
1815 }
1816
1817 wm8996->bclk_rate[dai->id] = bclk_rate;
1818 wm8996->rx_rate[dai->id] = params_rate(params);
1819
1820 /* Needs looking at for TDM */
1821 bits = snd_pcm_format_width(params_format(params));
1822 if (bits < 0)
1823 return bits;
1824 aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits;
1825
1826 for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
1827 if (dsp_divs[i] == params_rate(params))
1828 break;
1829 }
1830 if (i == ARRAY_SIZE(dsp_divs)) {
1831 dev_err(codec->dev, "Unsupported sample rate %dHz\n",
1832 params_rate(params));
1833 return -EINVAL;
1834 }
1835 dsp |= i << dsp_shift;
1836
1837 wm8996_update_bclk(codec);
1838
1839 lrclk = bclk_rate / params_rate(params);
1840 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1841 lrclk, bclk_rate / lrclk);
1842
1843 snd_soc_update_bits(codec, aifdata_reg,
1844 WM8996_AIF1TX_WL_MASK |
1845 WM8996_AIF1TX_SLOT_LEN_MASK,
1846 aifdata);
1847 snd_soc_update_bits(codec, lrclk_reg, WM8996_AIF1RX_RATE_MASK,
1848 lrclk);
1849 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_2,
1850 WM8996_DSP1_DIV_MASK << dsp_shift, dsp);
1851
1852 return 0;
1853}
1854
1855static int wm8996_set_sysclk(struct snd_soc_dai *dai,
1856 int clk_id, unsigned int freq, int dir)
1857{
1858 struct snd_soc_codec *codec = dai->codec;
1859 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1860 int lfclk = 0;
1861 int ratediv = 0;
1862 int src;
1863 int old;
1864
1865 if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src)
1866 return 0;
1867
1868 /* Disable SYSCLK while we reconfigure */
1869 old = snd_soc_read(codec, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA;
1870 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1871 WM8996_SYSCLK_ENA, 0);
1872
1873 switch (clk_id) {
1874 case WM8996_SYSCLK_MCLK1:
1875 wm8996->sysclk = freq;
1876 src = 0;
1877 break;
1878 case WM8996_SYSCLK_MCLK2:
1879 wm8996->sysclk = freq;
1880 src = 1;
1881 break;
1882 case WM8996_SYSCLK_FLL:
1883 wm8996->sysclk = freq;
1884 src = 2;
1885 break;
1886 default:
1887 dev_err(codec->dev, "Unsupported clock source %d\n", clk_id);
1888 return -EINVAL;
1889 }
1890
1891 switch (wm8996->sysclk) {
1892 case 6144000:
1893 snd_soc_update_bits(codec, WM8996_AIF_RATE,
1894 WM8996_SYSCLK_RATE, 0);
1895 break;
1896 case 24576000:
1897 ratediv = WM8996_SYSCLK_DIV;
1898 wm8996->sysclk /= 2;
1899 case 12288000:
1900 snd_soc_update_bits(codec, WM8996_AIF_RATE,
1901 WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);
1902 break;
1903 case 32000:
1904 case 32768:
1905 lfclk = WM8996_LFCLK_ENA;
1906 break;
1907 default:
1908 dev_warn(codec->dev, "Unsupported clock rate %dHz\n",
1909 wm8996->sysclk);
1910 return -EINVAL;
1911 }
1912
1913 wm8996_update_bclk(codec);
1914
1915 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1916 WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK,
1917 src << WM8996_SYSCLK_SRC_SHIFT | ratediv);
1918 snd_soc_update_bits(codec, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk);
1919 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
1920 WM8996_SYSCLK_ENA, old);
1921
1922 wm8996->sysclk_src = clk_id;
1923
1924 return 0;
1925}
1926
1927struct _fll_div {
1928 u16 fll_fratio;
1929 u16 fll_outdiv;
1930 u16 fll_refclk_div;
1931 u16 fll_loop_gain;
1932 u16 fll_ref_freq;
1933 u16 n;
1934 u16 theta;
1935 u16 lambda;
1936};
1937
1938static struct {
1939 unsigned int min;
1940 unsigned int max;
1941 u16 fll_fratio;
1942 int ratio;
1943} fll_fratios[] = {
1944 { 0, 64000, 4, 16 },
1945 { 64000, 128000, 3, 8 },
1946 { 128000, 256000, 2, 4 },
1947 { 256000, 1000000, 1, 2 },
1948 { 1000000, 13500000, 0, 1 },
1949};
1950
1951static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1952 unsigned int Fout)
1953{
1954 unsigned int target;
1955 unsigned int div;
1956 unsigned int fratio, gcd_fll;
1957 int i;
1958
1959 /* Fref must be <=13.5MHz */
1960 div = 1;
1961 fll_div->fll_refclk_div = 0;
1962 while ((Fref / div) > 13500000) {
1963 div *= 2;
1964 fll_div->fll_refclk_div++;
1965
1966 if (div > 8) {
1967 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1968 Fref);
1969 return -EINVAL;
1970 }
1971 }
1972
1973 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1974
1975 /* Apply the division for our remaining calculations */
1976 Fref /= div;
1977
1978 if (Fref >= 3000000)
1979 fll_div->fll_loop_gain = 5;
1980 else
1981 fll_div->fll_loop_gain = 0;
1982
1983 if (Fref >= 48000)
1984 fll_div->fll_ref_freq = 0;
1985 else
1986 fll_div->fll_ref_freq = 1;
1987
1988 /* Fvco should be 90-100MHz; don't check the upper bound */
1989 div = 2;
1990 while (Fout * div < 90000000) {
1991 div++;
1992 if (div > 64) {
1993 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1994 Fout);
1995 return -EINVAL;
1996 }
1997 }
1998 target = Fout * div;
1999 fll_div->fll_outdiv = div - 1;
2000
2001 pr_debug("FLL Fvco=%dHz\n", target);
2002
2003 /* Find an appropraite FLL_FRATIO and factor it out of the target */
2004 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2005 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2006 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2007 fratio = fll_fratios[i].ratio;
2008 break;
2009 }
2010 }
2011 if (i == ARRAY_SIZE(fll_fratios)) {
2012 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2013 return -EINVAL;
2014 }
2015
2016 fll_div->n = target / (fratio * Fref);
2017
2018 if (target % Fref == 0) {
2019 fll_div->theta = 0;
2020 fll_div->lambda = 0;
2021 } else {
2022 gcd_fll = gcd(target, fratio * Fref);
2023
2024 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2025 / gcd_fll;
2026 fll_div->lambda = (fratio * Fref) / gcd_fll;
2027 }
2028
2029 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2030 fll_div->n, fll_div->theta, fll_div->lambda);
2031 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2032 fll_div->fll_fratio, fll_div->fll_outdiv,
2033 fll_div->fll_refclk_div);
2034
2035 return 0;
2036}
2037
2038static int wm8996_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2039 unsigned int Fref, unsigned int Fout)
2040{
2041 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2042 struct i2c_client *i2c = to_i2c_client(codec->dev);
2043 struct _fll_div fll_div;
2044 unsigned long timeout;
2045 int ret, reg;
2046
2047 /* Any change? */
2048 if (source == wm8996->fll_src && Fref == wm8996->fll_fref &&
2049 Fout == wm8996->fll_fout)
2050 return 0;
2051
2052 if (Fout == 0) {
2053 dev_dbg(codec->dev, "FLL disabled\n");
2054
2055 wm8996->fll_fref = 0;
2056 wm8996->fll_fout = 0;
2057
2058 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2059 WM8996_FLL_ENA, 0);
2060
2061 return 0;
2062 }
2063
2064 ret = fll_factors(&fll_div, Fref, Fout);
2065 if (ret != 0)
2066 return ret;
2067
2068 switch (source) {
2069 case WM8996_FLL_MCLK1:
2070 reg = 0;
2071 break;
2072 case WM8996_FLL_MCLK2:
2073 reg = 1;
2074 break;
2075 case WM8996_FLL_DACLRCLK1:
2076 reg = 2;
2077 break;
2078 case WM8996_FLL_BCLK1:
2079 reg = 3;
2080 break;
2081 default:
2082 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2083 return -EINVAL;
2084 }
2085
2086 reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT;
2087 reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT;
2088
2089 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_5,
2090 WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ |
2091 WM8996_FLL_REFCLK_SRC_MASK, reg);
2092
2093 reg = 0;
2094 if (fll_div.theta || fll_div.lambda)
2095 reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT);
2096 else
2097 reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT;
2098 snd_soc_write(codec, WM8996_FLL_EFS_2, reg);
2099
2100 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_2,
2101 WM8996_FLL_OUTDIV_MASK |
2102 WM8996_FLL_FRATIO_MASK,
2103 (fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) |
2104 (fll_div.fll_fratio));
2105
2106 snd_soc_write(codec, WM8996_FLL_CONTROL_3, fll_div.theta);
2107
2108 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_4,
2109 WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK,
2110 (fll_div.n << WM8996_FLL_N_SHIFT) |
2111 fll_div.fll_loop_gain);
2112
2113 snd_soc_write(codec, WM8996_FLL_EFS_1, fll_div.lambda);
2114
2115 /* Clear any pending completions (eg, from failed startups) */
2116 try_wait_for_completion(&wm8996->fll_lock);
2117
2118 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2119 WM8996_FLL_ENA, WM8996_FLL_ENA);
2120
2121 /* The FLL supports live reconfiguration - kick that in case we were
2122 * already enabled.
2123 */
2124 snd_soc_write(codec, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK);
2125
2126 /* Wait for the FLL to lock, using the interrupt if possible */
2127 if (Fref > 1000000)
2128 timeout = usecs_to_jiffies(300);
2129 else
2130 timeout = msecs_to_jiffies(2);
2131
2132 /* Allow substantially longer if we've actually got the IRQ */
2133 if (i2c->irq)
2134 timeout *= 1000;
2135
2136 ret = wait_for_completion_timeout(&wm8996->fll_lock, timeout);
2137
2138 if (ret == 0 && i2c->irq) {
2139 dev_err(codec->dev, "Timed out waiting for FLL\n");
2140 ret = -ETIMEDOUT;
2141 } else {
2142 ret = 0;
2143 }
2144
2145 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2146
2147 wm8996->fll_fref = Fref;
2148 wm8996->fll_fout = Fout;
2149 wm8996->fll_src = source;
2150
2151 return ret;
2152}
2153
2154#ifdef CONFIG_GPIOLIB
2155static inline struct wm8996_priv *gpio_to_wm8996(struct gpio_chip *chip)
2156{
2157 return container_of(chip, struct wm8996_priv, gpio_chip);
2158}
2159
2160static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2161{
2162 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2163 struct snd_soc_codec *codec = wm8996->codec;
2164
2165 snd_soc_update_bits(codec, WM8996_GPIO_1 + offset,
2166 WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT);
2167}
2168
2169static int wm8996_gpio_direction_out(struct gpio_chip *chip,
2170 unsigned offset, int value)
2171{
2172 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2173 struct snd_soc_codec *codec = wm8996->codec;
2174 int val;
2175
2176 val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT);
2177
2178 return snd_soc_update_bits(codec, WM8996_GPIO_1 + offset,
2179 WM8996_GP1_FN_MASK | WM8996_GP1_DIR |
2180 WM8996_GP1_LVL, val);
2181}
2182
2183static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset)
2184{
2185 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2186 struct snd_soc_codec *codec = wm8996->codec;
2187 int ret;
2188
2189 ret = snd_soc_read(codec, WM8996_GPIO_1 + offset);
2190 if (ret < 0)
2191 return ret;
2192
2193 return (ret & WM8996_GP1_LVL) != 0;
2194}
2195
2196static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2197{
2198 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2199 struct snd_soc_codec *codec = wm8996->codec;
2200
2201 return snd_soc_update_bits(codec, WM8996_GPIO_1 + offset,
2202 WM8996_GP1_FN_MASK | WM8996_GP1_DIR,
2203 (1 << WM8996_GP1_FN_SHIFT) |
2204 (1 << WM8996_GP1_DIR_SHIFT));
2205}
2206
2207static struct gpio_chip wm8996_template_chip = {
2208 .label = "wm8996",
2209 .owner = THIS_MODULE,
2210 .direction_output = wm8996_gpio_direction_out,
2211 .set = wm8996_gpio_set,
2212 .direction_input = wm8996_gpio_direction_in,
2213 .get = wm8996_gpio_get,
2214 .can_sleep = 1,
2215};
2216
2217static void wm8996_init_gpio(struct snd_soc_codec *codec)
2218{
2219 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2220 int ret;
2221
2222 wm8996->gpio_chip = wm8996_template_chip;
2223 wm8996->gpio_chip.ngpio = 5;
2224 wm8996->gpio_chip.dev = codec->dev;
2225
2226 if (wm8996->pdata.gpio_base)
2227 wm8996->gpio_chip.base = wm8996->pdata.gpio_base;
2228 else
2229 wm8996->gpio_chip.base = -1;
2230
2231 ret = gpiochip_add(&wm8996->gpio_chip);
2232 if (ret != 0)
2233 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
2234}
2235
2236static void wm8996_free_gpio(struct snd_soc_codec *codec)
2237{
2238 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2239 int ret;
2240
2241 ret = gpiochip_remove(&wm8996->gpio_chip);
2242 if (ret != 0)
2243 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
2244}
2245#else
2246static void wm8996_init_gpio(struct snd_soc_codec *codec)
2247{
2248}
2249
2250static void wm8996_free_gpio(struct snd_soc_codec *codec)
2251{
2252}
2253#endif
2254
2255/**
2256 * wm8996_detect - Enable default WM8996 jack detection
2257 *
2258 * The WM8996 has advanced accessory detection support for headsets.
2259 * This function provides a default implementation which integrates
2260 * the majority of this functionality with minimal user configuration.
2261 *
2262 * This will detect headset, headphone and short circuit button and
2263 * will also detect inverted microphone ground connections and update
2264 * the polarity of the connections.
2265 */
2266int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2267 wm8996_polarity_fn polarity_cb)
2268{
2269 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2270
2271 wm8996->jack = jack;
2272 wm8996->detecting = true;
2273 wm8996->polarity_cb = polarity_cb;
2274
2275 if (wm8996->polarity_cb)
2276 wm8996->polarity_cb(codec, 0);
2277
2278 /* Clear discarge to avoid noise during detection */
2279 snd_soc_update_bits(codec, WM8996_MICBIAS_1,
2280 WM8996_MICB1_DISCH, 0);
2281 snd_soc_update_bits(codec, WM8996_MICBIAS_2,
2282 WM8996_MICB2_DISCH, 0);
2283
2284 /* LDO2 powers the microphones, SYSCLK clocks detection */
2285 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2286 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2287
2288 /* We start off just enabling microphone detection - even a
2289 * plain headphone will trigger detection.
2290 */
2291 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2292 WM8996_MICD_ENA, WM8996_MICD_ENA);
2293
2294 /* Slowest detection rate, gives debounce for initial detection */
2295 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2296 WM8996_MICD_RATE_MASK,
2297 WM8996_MICD_RATE_MASK);
2298
2299 /* Enable interrupts and we're off */
2300 snd_soc_update_bits(codec, WM8996_INTERRUPT_STATUS_2_MASK,
2301 WM8996_IM_MICD_EINT, 0);
2302
2303 return 0;
2304}
2305EXPORT_SYMBOL_GPL(wm8996_detect);
2306
2307static void wm8996_micd(struct snd_soc_codec *codec)
2308{
2309 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2310 int val, reg;
2311
2312 val = snd_soc_read(codec, WM8996_MIC_DETECT_3);
2313
2314 dev_dbg(codec->dev, "Microphone event: %x\n", val);
2315
2316 if (!(val & WM8996_MICD_VALID)) {
2317 dev_warn(codec->dev, "Microphone detection state invalid\n");
2318 return;
2319 }
2320
2321 /* No accessory, reset everything and report removal */
2322 if (!(val & WM8996_MICD_STS)) {
2323 dev_dbg(codec->dev, "Jack removal detected\n");
2324 wm8996->jack_mic = false;
2325 wm8996->detecting = true;
2326 snd_soc_jack_report(wm8996->jack, 0,
2327 SND_JACK_HEADSET | SND_JACK_BTN_0);
2328 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2329 WM8996_MICD_RATE_MASK,
2330 WM8996_MICD_RATE_MASK);
2331 return;
2332 }
2333
2334 /* If the measurement is very high we've got a microphone but
2335 * do a little debounce to account for mechanical issues.
2336 */
2337 if (val & 0x400) {
2338 dev_dbg(codec->dev, "Microphone detected\n");
2339 snd_soc_jack_report(wm8996->jack, SND_JACK_HEADSET,
2340 SND_JACK_HEADSET | SND_JACK_BTN_0);
2341 wm8996->jack_mic = true;
2342 wm8996->detecting = false;
2343
2344 /* Increase poll rate to give better responsiveness
2345 * for buttons */
2346 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2347 WM8996_MICD_RATE_MASK,
2348 5 << WM8996_MICD_RATE_SHIFT);
2349 }
2350
2351 /* If we detected a lower impedence during initial startup
2352 * then we probably have the wrong polarity, flip it. Don't
2353 * do this for the lowest impedences to speed up detection of
2354 * plain headphones.
2355 */
2356 if (wm8996->detecting && (val & 0x3f0)) {
2357 reg = snd_soc_read(codec, WM8996_ACCESSORY_DETECT_MODE_2);
2358 reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2359 WM8996_MICD_BIAS_SRC;
2360 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2361 WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2362 WM8996_MICD_BIAS_SRC, reg);
2363
2364 if (wm8996->polarity_cb)
2365 wm8996->polarity_cb(codec,
2366 (reg & WM8996_MICD_SRC) != 0);
2367
2368 dev_dbg(codec->dev, "Set microphone polarity to %d\n",
2369 (reg & WM8996_MICD_SRC) != 0);
2370
2371 return;
2372 }
2373
2374 /* Don't distinguish between buttons, just report any low
2375 * impedence as BTN_0.
2376 */
2377 if (val & 0x3fc) {
2378 if (wm8996->jack_mic) {
2379 dev_dbg(codec->dev, "Mic button detected\n");
2380 snd_soc_jack_report(wm8996->jack,
2381 SND_JACK_HEADSET | SND_JACK_BTN_0,
2382 SND_JACK_HEADSET | SND_JACK_BTN_0);
2383 } else {
2384 dev_dbg(codec->dev, "Headphone detected\n");
2385 snd_soc_jack_report(wm8996->jack,
2386 SND_JACK_HEADPHONE,
2387 SND_JACK_HEADSET |
2388 SND_JACK_BTN_0);
2389
2390 /* Increase the detection rate a bit for
2391 * responsiveness.
2392 */
2393 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2394 WM8996_MICD_RATE_MASK,
2395 7 << WM8996_MICD_RATE_SHIFT);
2396
2397 wm8996->detecting = false;
2398 }
2399 }
2400}
2401
2402static irqreturn_t wm8996_irq(int irq, void *data)
2403{
2404 struct snd_soc_codec *codec = data;
2405 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2406 int irq_val;
2407
2408 irq_val = snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2);
2409 if (irq_val < 0) {
2410 dev_err(codec->dev, "Failed to read IRQ status: %d\n",
2411 irq_val);
2412 return IRQ_NONE;
2413 }
2414 irq_val &= ~snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2_MASK);
2415
2416 snd_soc_write(codec, WM8996_INTERRUPT_STATUS_2, irq_val);
2417
2418 if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) {
2419 dev_dbg(codec->dev, "DC servo IRQ\n");
2420 complete(&wm8996->dcs_done);
2421 }
2422
2423 if (irq_val & WM8996_FIFOS_ERR_EINT)
2424 dev_err(codec->dev, "Digital core FIFO error\n");
2425
2426 if (irq_val & WM8996_FLL_LOCK_EINT) {
2427 dev_dbg(codec->dev, "FLL locked\n");
2428 complete(&wm8996->fll_lock);
2429 }
2430
2431 if (irq_val & WM8996_MICD_EINT)
2432 wm8996_micd(codec);
2433
2434 if (irq_val)
2435 return IRQ_HANDLED;
2436 else
2437 return IRQ_NONE;
2438}
2439
2440static irqreturn_t wm8996_edge_irq(int irq, void *data)
2441{
2442 irqreturn_t ret = IRQ_NONE;
2443 irqreturn_t val;
2444
2445 do {
2446 val = wm8996_irq(irq, data);
2447 if (val != IRQ_NONE)
2448 ret = val;
2449 } while (val != IRQ_NONE);
2450
2451 return ret;
2452}
2453
2454static void wm8996_retune_mobile_pdata(struct snd_soc_codec *codec)
2455{
2456 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2457 struct wm8996_pdata *pdata = &wm8996->pdata;
2458
2459 struct snd_kcontrol_new controls[] = {
2460 SOC_ENUM_EXT("DSP1 EQ Mode",
2461 wm8996->retune_mobile_enum,
2462 wm8996_get_retune_mobile_enum,
2463 wm8996_put_retune_mobile_enum),
2464 SOC_ENUM_EXT("DSP2 EQ Mode",
2465 wm8996->retune_mobile_enum,
2466 wm8996_get_retune_mobile_enum,
2467 wm8996_put_retune_mobile_enum),
2468 };
2469 int ret, i, j;
2470 const char **t;
2471
2472 /* We need an array of texts for the enum API but the number
2473 * of texts is likely to be less than the number of
2474 * configurations due to the sample rate dependency of the
2475 * configurations. */
2476 wm8996->num_retune_mobile_texts = 0;
2477 wm8996->retune_mobile_texts = NULL;
2478 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2479 for (j = 0; j < wm8996->num_retune_mobile_texts; j++) {
2480 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2481 wm8996->retune_mobile_texts[j]) == 0)
2482 break;
2483 }
2484
2485 if (j != wm8996->num_retune_mobile_texts)
2486 continue;
2487
2488 /* Expand the array... */
2489 t = krealloc(wm8996->retune_mobile_texts,
2490 sizeof(char *) *
2491 (wm8996->num_retune_mobile_texts + 1),
2492 GFP_KERNEL);
2493 if (t == NULL)
2494 continue;
2495
2496 /* ...store the new entry... */
2497 t[wm8996->num_retune_mobile_texts] =
2498 pdata->retune_mobile_cfgs[i].name;
2499
2500 /* ...and remember the new version. */
2501 wm8996->num_retune_mobile_texts++;
2502 wm8996->retune_mobile_texts = t;
2503 }
2504
2505 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2506 wm8996->num_retune_mobile_texts);
2507
2508 wm8996->retune_mobile_enum.max = wm8996->num_retune_mobile_texts;
2509 wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts;
2510
2511 ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls));
2512 if (ret != 0)
2513 dev_err(codec->dev,
2514 "Failed to add ReTune Mobile controls: %d\n", ret);
2515}
2516
2517static int wm8996_probe(struct snd_soc_codec *codec)
2518{
2519 int ret;
2520 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2521 struct i2c_client *i2c = to_i2c_client(codec->dev);
2522 struct snd_soc_dapm_context *dapm = &codec->dapm;
2523 int i, irq_flags;
2524
2525 wm8996->codec = codec;
2526
2527 init_completion(&wm8996->dcs_done);
2528 init_completion(&wm8996->fll_lock);
2529
2530 dapm->idle_bias_off = true;
2531 dapm->bias_level = SND_SOC_BIAS_OFF;
2532
2533 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
2534 if (ret != 0) {
2535 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2536 goto err;
2537 }
2538
2539 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
2540 wm8996->supplies[i].supply = wm8996_supply_names[i];
2541
2542 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8996->supplies),
2543 wm8996->supplies);
2544 if (ret != 0) {
2545 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
2546 goto err;
2547 }
2548
2549 wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0;
2550 wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1;
2551 wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2;
2552 wm8996->disable_nb[3].notifier_call = wm8996_regulator_event_3;
2553
2554 /* This should really be moved into the regulator core */
2555 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) {
2556 ret = regulator_register_notifier(wm8996->supplies[i].consumer,
2557 &wm8996->disable_nb[i]);
2558 if (ret != 0) {
2559 dev_err(codec->dev,
2560 "Failed to register regulator notifier: %d\n",
2561 ret);
2562 }
2563 }
2564
2565 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
2566 wm8996->supplies);
2567 if (ret != 0) {
2568 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
2569 goto err_get;
2570 }
2571
2572 if (wm8996->pdata.ldo_ena >= 0) {
2573 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1);
2574 msleep(5);
2575 }
2576
2577 ret = snd_soc_read(codec, WM8996_SOFTWARE_RESET);
2578 if (ret < 0) {
2579 dev_err(codec->dev, "Failed to read ID register: %d\n", ret);
2580 goto err_enable;
2581 }
2582 if (ret != 0x8915) {
2583 dev_err(codec->dev, "Device is not a WM8996, ID %x\n", ret);
2584 ret = -EINVAL;
2585 goto err_enable;
2586 }
2587
2588 ret = snd_soc_read(codec, WM8996_CHIP_REVISION);
2589 if (ret < 0) {
2590 dev_err(codec->dev, "Failed to read device revision: %d\n",
2591 ret);
2592 goto err_enable;
2593 }
2594
2595 dev_info(codec->dev, "revision %c\n",
2596 (ret & WM8996_CHIP_REV_MASK) + 'A');
2597
2598 if (wm8996->pdata.ldo_ena >= 0) {
2599 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
2600 } else {
2601 ret = wm8996_reset(codec);
2602 if (ret < 0) {
2603 dev_err(codec->dev, "Failed to issue reset\n");
2604 goto err_enable;
2605 }
2606 }
2607
2608 codec->cache_only = true;
2609
2610 /* Apply platform data settings */
2611 snd_soc_update_bits(codec, WM8996_LINE_INPUT_CONTROL,
2612 WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK,
2613 wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT |
2614 wm8996->pdata.inr_mode);
2615
2616 for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) {
2617 if (!wm8996->pdata.gpio_default[i])
2618 continue;
2619
2620 snd_soc_write(codec, WM8996_GPIO_1 + i,
2621 wm8996->pdata.gpio_default[i] & 0xffff);
2622 }
2623
2624 if (wm8996->pdata.spkmute_seq)
2625 snd_soc_update_bits(codec, WM8996_PDM_SPEAKER_MUTE_SEQUENCE,
2626 WM8996_SPK_MUTE_ENDIAN |
2627 WM8996_SPK_MUTE_SEQ1_MASK,
2628 wm8996->pdata.spkmute_seq);
2629
2630 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2631 WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC |
2632 WM8996_MICD_SRC, wm8996->pdata.micdet_def);
2633
2634 /* Latch volume update bits */
2635 snd_soc_update_bits(codec, WM8996_LEFT_LINE_INPUT_VOLUME,
2636 WM8996_IN1_VU, WM8996_IN1_VU);
2637 snd_soc_update_bits(codec, WM8996_RIGHT_LINE_INPUT_VOLUME,
2638 WM8996_IN1_VU, WM8996_IN1_VU);
2639
2640 snd_soc_update_bits(codec, WM8996_DAC1_LEFT_VOLUME,
2641 WM8996_DAC1_VU, WM8996_DAC1_VU);
2642 snd_soc_update_bits(codec, WM8996_DAC1_RIGHT_VOLUME,
2643 WM8996_DAC1_VU, WM8996_DAC1_VU);
2644 snd_soc_update_bits(codec, WM8996_DAC2_LEFT_VOLUME,
2645 WM8996_DAC2_VU, WM8996_DAC2_VU);
2646 snd_soc_update_bits(codec, WM8996_DAC2_RIGHT_VOLUME,
2647 WM8996_DAC2_VU, WM8996_DAC2_VU);
2648
2649 snd_soc_update_bits(codec, WM8996_OUTPUT1_LEFT_VOLUME,
2650 WM8996_DAC1_VU, WM8996_DAC1_VU);
2651 snd_soc_update_bits(codec, WM8996_OUTPUT1_RIGHT_VOLUME,
2652 WM8996_DAC1_VU, WM8996_DAC1_VU);
2653 snd_soc_update_bits(codec, WM8996_OUTPUT2_LEFT_VOLUME,
2654 WM8996_DAC2_VU, WM8996_DAC2_VU);
2655 snd_soc_update_bits(codec, WM8996_OUTPUT2_RIGHT_VOLUME,
2656 WM8996_DAC2_VU, WM8996_DAC2_VU);
2657
2658 snd_soc_update_bits(codec, WM8996_DSP1_TX_LEFT_VOLUME,
2659 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2660 snd_soc_update_bits(codec, WM8996_DSP1_TX_RIGHT_VOLUME,
2661 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2662 snd_soc_update_bits(codec, WM8996_DSP2_TX_LEFT_VOLUME,
2663 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2664 snd_soc_update_bits(codec, WM8996_DSP2_TX_RIGHT_VOLUME,
2665 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2666
2667 snd_soc_update_bits(codec, WM8996_DSP1_RX_LEFT_VOLUME,
2668 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2669 snd_soc_update_bits(codec, WM8996_DSP1_RX_RIGHT_VOLUME,
2670 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2671 snd_soc_update_bits(codec, WM8996_DSP2_RX_LEFT_VOLUME,
2672 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2673 snd_soc_update_bits(codec, WM8996_DSP2_RX_RIGHT_VOLUME,
2674 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2675
2676 /* No support currently for the underclocked TDM modes and
2677 * pick a default TDM layout with each channel pair working with
2678 * slots 0 and 1. */
2679 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_0_CONFIGURATION,
2680 WM8996_AIF1RX_CHAN0_SLOTS_MASK |
2681 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2682 1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
2683 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_1_CONFIGURATION,
2684 WM8996_AIF1RX_CHAN1_SLOTS_MASK |
2685 WM8996_AIF1RX_CHAN1_START_SLOT_MASK,
2686 1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
2687 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_2_CONFIGURATION,
2688 WM8996_AIF1RX_CHAN2_SLOTS_MASK |
2689 WM8996_AIF1RX_CHAN2_START_SLOT_MASK,
2690 1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
2691 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_3_CONFIGURATION,
2692 WM8996_AIF1RX_CHAN3_SLOTS_MASK |
2693 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2694 1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
2695 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_4_CONFIGURATION,
2696 WM8996_AIF1RX_CHAN4_SLOTS_MASK |
2697 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2698 1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
2699 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_5_CONFIGURATION,
2700 WM8996_AIF1RX_CHAN5_SLOTS_MASK |
2701 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2702 1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
2703
2704 snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_0_CONFIGURATION,
2705 WM8996_AIF2RX_CHAN0_SLOTS_MASK |
2706 WM8996_AIF2RX_CHAN0_START_SLOT_MASK,
2707 1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
2708 snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_1_CONFIGURATION,
2709 WM8996_AIF2RX_CHAN1_SLOTS_MASK |
2710 WM8996_AIF2RX_CHAN1_START_SLOT_MASK,
2711 1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
2712
2713 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_0_CONFIGURATION,
2714 WM8996_AIF1TX_CHAN0_SLOTS_MASK |
2715 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2716 1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
2717 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2718 WM8996_AIF1TX_CHAN1_SLOTS_MASK |
2719 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2720 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2721 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_2_CONFIGURATION,
2722 WM8996_AIF1TX_CHAN2_SLOTS_MASK |
2723 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2724 1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
2725 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_3_CONFIGURATION,
2726 WM8996_AIF1TX_CHAN3_SLOTS_MASK |
2727 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2728 1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
2729 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_4_CONFIGURATION,
2730 WM8996_AIF1TX_CHAN4_SLOTS_MASK |
2731 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2732 1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
2733 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_5_CONFIGURATION,
2734 WM8996_AIF1TX_CHAN5_SLOTS_MASK |
2735 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2736 1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
2737
2738 snd_soc_update_bits(codec, WM8996_AIF2TX_CHANNEL_0_CONFIGURATION,
2739 WM8996_AIF2TX_CHAN0_SLOTS_MASK |
2740 WM8996_AIF2TX_CHAN0_START_SLOT_MASK,
2741 1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
2742 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2743 WM8996_AIF2TX_CHAN1_SLOTS_MASK |
2744 WM8996_AIF2TX_CHAN1_START_SLOT_MASK,
2745 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2746
2747 if (wm8996->pdata.num_retune_mobile_cfgs)
2748 wm8996_retune_mobile_pdata(codec);
2749 else
2750 snd_soc_add_controls(codec, wm8996_eq_controls,
2751 ARRAY_SIZE(wm8996_eq_controls));
2752
2753 /* If the TX LRCLK pins are not in LRCLK mode configure the
2754 * AIFs to source their clocks from the RX LRCLKs.
2755 */
2756 if ((snd_soc_read(codec, WM8996_GPIO_1)))
2757 snd_soc_update_bits(codec, WM8996_AIF1_TX_LRCLK_2,
2758 WM8996_AIF1TX_LRCLK_MODE,
2759 WM8996_AIF1TX_LRCLK_MODE);
2760
2761 if ((snd_soc_read(codec, WM8996_GPIO_2)))
2762 snd_soc_update_bits(codec, WM8996_AIF2_TX_LRCLK_2,
2763 WM8996_AIF2TX_LRCLK_MODE,
2764 WM8996_AIF2TX_LRCLK_MODE);
2765
2766 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
2767
2768 wm8996_init_gpio(codec);
2769
2770 if (i2c->irq) {
2771 if (wm8996->pdata.irq_flags)
2772 irq_flags = wm8996->pdata.irq_flags;
2773 else
2774 irq_flags = IRQF_TRIGGER_LOW;
2775
2776 irq_flags |= IRQF_ONESHOT;
2777
2778 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2779 ret = request_threaded_irq(i2c->irq, NULL,
2780 wm8996_edge_irq,
2781 irq_flags, "wm8996", codec);
2782 else
2783 ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq,
2784 irq_flags, "wm8996", codec);
2785
2786 if (ret == 0) {
2787 /* Unmask the interrupt */
2788 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
2789 WM8996_IM_IRQ, 0);
2790
2791 /* Enable error reporting and DC servo status */
2792 snd_soc_update_bits(codec,
2793 WM8996_INTERRUPT_STATUS_2_MASK,
2794 WM8996_IM_DCS_DONE_23_EINT |
2795 WM8996_IM_DCS_DONE_01_EINT |
2796 WM8996_IM_FLL_LOCK_EINT |
2797 WM8996_IM_FIFOS_ERR_EINT,
2798 0);
2799 } else {
2800 dev_err(codec->dev, "Failed to request IRQ: %d\n",
2801 ret);
2802 }
2803 }
2804
2805 return 0;
2806
2807err_enable:
2808 if (wm8996->pdata.ldo_ena >= 0)
2809 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
2810
2811 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
2812err_get:
2813 regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
2814err:
2815 return ret;
2816}
2817
2818static int wm8996_remove(struct snd_soc_codec *codec)
2819{
2820 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2821 struct i2c_client *i2c = to_i2c_client(codec->dev);
2822 int i;
2823
2824 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
2825 WM8996_IM_IRQ, WM8996_IM_IRQ);
2826
2827 if (i2c->irq)
2828 free_irq(i2c->irq, codec);
2829
2830 wm8996_free_gpio(codec);
2831
2832 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
2833 regulator_unregister_notifier(wm8996->supplies[i].consumer,
2834 &wm8996->disable_nb[i]);
2835 regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
2836
2837 return 0;
2838}
2839
2840static struct snd_soc_codec_driver soc_codec_dev_wm8996 = {
2841 .probe = wm8996_probe,
2842 .remove = wm8996_remove,
2843 .set_bias_level = wm8996_set_bias_level,
2844 .seq_notifier = wm8996_seq_notifier,
2845 .reg_cache_size = WM8996_MAX_REGISTER + 1,
2846 .reg_word_size = sizeof(u16),
2847 .reg_cache_default = wm8996_reg,
2848 .volatile_register = wm8996_volatile_register,
2849 .readable_register = wm8996_readable_register,
2850 .compress_type = SND_SOC_RBTREE_COMPRESSION,
2851 .controls = wm8996_snd_controls,
2852 .num_controls = ARRAY_SIZE(wm8996_snd_controls),
2853 .dapm_widgets = wm8996_dapm_widgets,
2854 .num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets),
2855 .dapm_routes = wm8996_dapm_routes,
2856 .num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes),
2857 .set_pll = wm8996_set_fll,
2858};
2859
2860#define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
2861 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
2862#define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
2863 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
2864 SNDRV_PCM_FMTBIT_S32_LE)
2865
2866static struct snd_soc_dai_ops wm8996_dai_ops = {
2867 .set_fmt = wm8996_set_fmt,
2868 .hw_params = wm8996_hw_params,
2869 .set_sysclk = wm8996_set_sysclk,
2870};
2871
2872static struct snd_soc_dai_driver wm8996_dai[] = {
2873 {
2874 .name = "wm8996-aif1",
2875 .playback = {
2876 .stream_name = "AIF1 Playback",
2877 .channels_min = 1,
2878 .channels_max = 6,
2879 .rates = WM8996_RATES,
2880 .formats = WM8996_FORMATS,
2881 },
2882 .capture = {
2883 .stream_name = "AIF1 Capture",
2884 .channels_min = 1,
2885 .channels_max = 6,
2886 .rates = WM8996_RATES,
2887 .formats = WM8996_FORMATS,
2888 },
2889 .ops = &wm8996_dai_ops,
2890 },
2891 {
2892 .name = "wm8996-aif2",
2893 .playback = {
2894 .stream_name = "AIF2 Playback",
2895 .channels_min = 1,
2896 .channels_max = 2,
2897 .rates = WM8996_RATES,
2898 .formats = WM8996_FORMATS,
2899 },
2900 .capture = {
2901 .stream_name = "AIF2 Capture",
2902 .channels_min = 1,
2903 .channels_max = 2,
2904 .rates = WM8996_RATES,
2905 .formats = WM8996_FORMATS,
2906 },
2907 .ops = &wm8996_dai_ops,
2908 },
2909};
2910
2911static __devinit int wm8996_i2c_probe(struct i2c_client *i2c,
2912 const struct i2c_device_id *id)
2913{
2914 struct wm8996_priv *wm8996;
2915 int ret;
2916
2917 wm8996 = kzalloc(sizeof(struct wm8996_priv), GFP_KERNEL);
2918 if (wm8996 == NULL)
2919 return -ENOMEM;
2920
2921 i2c_set_clientdata(i2c, wm8996);
2922
2923 if (dev_get_platdata(&i2c->dev))
2924 memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev),
2925 sizeof(wm8996->pdata));
2926
2927 if (wm8996->pdata.ldo_ena > 0) {
2928 ret = gpio_request_one(wm8996->pdata.ldo_ena,
2929 GPIOF_OUT_INIT_LOW, "WM8996 ENA");
2930 if (ret < 0) {
2931 dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
2932 wm8996->pdata.ldo_ena, ret);
2933 goto err;
2934 }
2935 }
2936
2937 ret = snd_soc_register_codec(&i2c->dev,
2938 &soc_codec_dev_wm8996, wm8996_dai,
2939 ARRAY_SIZE(wm8996_dai));
2940 if (ret < 0)
2941 goto err_gpio;
2942
2943 return ret;
2944
2945err_gpio:
2946 if (wm8996->pdata.ldo_ena > 0)
2947 gpio_free(wm8996->pdata.ldo_ena);
2948err:
2949 kfree(wm8996);
2950
2951 return ret;
2952}
2953
2954static __devexit int wm8996_i2c_remove(struct i2c_client *client)
2955{
2956 struct wm8996_priv *wm8996 = i2c_get_clientdata(client);
2957
2958 snd_soc_unregister_codec(&client->dev);
2959 if (wm8996->pdata.ldo_ena > 0)
2960 gpio_free(wm8996->pdata.ldo_ena);
2961 kfree(i2c_get_clientdata(client));
2962 return 0;
2963}
2964
2965static const struct i2c_device_id wm8996_i2c_id[] = {
2966 { "wm8996", 0 },
2967 { }
2968};
2969MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id);
2970
2971static struct i2c_driver wm8996_i2c_driver = {
2972 .driver = {
2973 .name = "wm8996",
2974 .owner = THIS_MODULE,
2975 },
2976 .probe = wm8996_i2c_probe,
2977 .remove = __devexit_p(wm8996_i2c_remove),
2978 .id_table = wm8996_i2c_id,
2979};
2980
2981static int __init wm8996_modinit(void)
2982{
2983 int ret;
2984
2985 ret = i2c_add_driver(&wm8996_i2c_driver);
2986 if (ret != 0) {
2987 printk(KERN_ERR "Failed to register WM8996 I2C driver: %d\n",
2988 ret);
2989 }
2990
2991 return ret;
2992}
2993module_init(wm8996_modinit);
2994
2995static void __exit wm8996_exit(void)
2996{
2997 i2c_del_driver(&wm8996_i2c_driver);
2998}
2999module_exit(wm8996_exit);
3000
3001MODULE_DESCRIPTION("ASoC WM8996 driver");
3002MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3003MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-22 05:38:18 -0400