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-rw-r--r--sound/pci/Kconfig27
-rw-r--r--sound/pci/Makefile2
-rw-r--r--sound/pci/ac97/ac97_codec.c2
-rw-r--r--sound/pci/ac97/ac97_patch.c7
-rw-r--r--sound/pci/atiixp.c6
-rw-r--r--sound/pci/au88x0/au88x0_core.c10
-rw-r--r--sound/pci/bt87x.c8
-rw-r--r--sound/pci/ca0106/ca0106_main.c1
-rw-r--r--sound/pci/ca0106/ca0106_mixer.c12
-rw-r--r--sound/pci/cmipci.c2
-rw-r--r--sound/pci/ctxfi/Makefile5
-rw-r--r--sound/pci/ctxfi/ct20k1reg.h636
-rw-r--r--sound/pci/ctxfi/ct20k2reg.h85
-rw-r--r--sound/pci/ctxfi/ctamixer.c488
-rw-r--r--sound/pci/ctxfi/ctamixer.h96
-rw-r--r--sound/pci/ctxfi/ctatc.c1619
-rw-r--r--sound/pci/ctxfi/ctatc.h147
-rw-r--r--sound/pci/ctxfi/ctdaio.c769
-rw-r--r--sound/pci/ctxfi/ctdaio.h122
-rw-r--r--sound/pci/ctxfi/cthardware.c91
-rw-r--r--sound/pci/ctxfi/cthardware.h196
-rw-r--r--sound/pci/ctxfi/cthw20k1.c2248
-rw-r--r--sound/pci/ctxfi/cthw20k1.h26
-rw-r--r--sound/pci/ctxfi/cthw20k2.c2137
-rw-r--r--sound/pci/ctxfi/cthw20k2.h26
-rw-r--r--sound/pci/ctxfi/ctimap.c112
-rw-r--r--sound/pci/ctxfi/ctimap.h40
-rw-r--r--sound/pci/ctxfi/ctmixer.c1123
-rw-r--r--sound/pci/ctxfi/ctmixer.h67
-rw-r--r--sound/pci/ctxfi/ctpcm.c426
-rw-r--r--sound/pci/ctxfi/ctpcm.h27
-rw-r--r--sound/pci/ctxfi/ctresource.c301
-rw-r--r--sound/pci/ctxfi/ctresource.h72
-rw-r--r--sound/pci/ctxfi/ctsrc.c886
-rw-r--r--sound/pci/ctxfi/ctsrc.h149
-rw-r--r--sound/pci/ctxfi/cttimer.c441
-rw-r--r--sound/pci/ctxfi/cttimer.h29
-rw-r--r--sound/pci/ctxfi/ctvmem.c250
-rw-r--r--sound/pci/ctxfi/ctvmem.h61
-rw-r--r--sound/pci/ctxfi/xfi.c142
-rw-r--r--sound/pci/echoaudio/indigodjx.c1
-rw-r--r--sound/pci/echoaudio/indigoiox.c1
-rw-r--r--sound/pci/emu10k1/Makefile10
-rw-r--r--sound/pci/emu10k1/emu10k1x.c1
-rw-r--r--sound/pci/emu10k1/emupcm.c2
-rw-r--r--sound/pci/emu10k1/io.c2
-rw-r--r--sound/pci/ice1712/Makefile2
-rw-r--r--sound/pci/ice1712/ice1712.h12
-rw-r--r--sound/pci/ice1712/ice1724.c96
-rw-r--r--sound/pci/ice1712/maya44.c779
-rw-r--r--sound/pci/ice1712/maya44.h10
-rw-r--r--sound/pci/intel8x0.c18
-rw-r--r--sound/pci/korg1212/korg1212.c6
-rw-r--r--sound/pci/lx6464es/Makefile2
-rw-r--r--sound/pci/lx6464es/lx6464es.c1152
-rw-r--r--sound/pci/lx6464es/lx6464es.h114
-rw-r--r--sound/pci/lx6464es/lx_core.c1444
-rw-r--r--sound/pci/lx6464es/lx_core.h242
-rw-r--r--sound/pci/lx6464es/lx_defs.h376
-rw-r--r--sound/pci/oxygen/oxygen_pcm.c6
-rw-r--r--sound/pci/oxygen/virtuoso.c64
-rw-r--r--sound/pci/riptide/riptide.c357
-rw-r--r--sound/pci/rme9652/hdsp.c11
-rw-r--r--sound/pci/rme9652/hdspm.c4
-rw-r--r--sound/pci/via82xx.c2
65 files changed, 17310 insertions, 298 deletions
diff --git a/sound/pci/Kconfig b/sound/pci/Kconfig
index 93422e3a3f0..748f6b7d90b 100644
--- a/sound/pci/Kconfig
+++ b/sound/pci/Kconfig
@@ -275,6 +275,16 @@ config SND_CS5535AUDIO
275 To compile this driver as a module, choose M here: the module 275 To compile this driver as a module, choose M here: the module
276 will be called snd-cs5535audio. 276 will be called snd-cs5535audio.
277 277
278config SND_CTXFI
279 tristate "Creative Sound Blaster X-Fi"
280 select SND_PCM
281 help
282 If you want to use soundcards based on Creative Sound Blastr X-Fi
283 boards with 20k1 or 20k2 chips, say Y here.
284
285 To compile this driver as a module, choose M here: the module
286 will be called snd-ctxfi.
287
278config SND_DARLA20 288config SND_DARLA20
279 tristate "(Echoaudio) Darla20" 289 tristate "(Echoaudio) Darla20"
280 select FW_LOADER 290 select FW_LOADER
@@ -532,6 +542,9 @@ config SND_HDSP
532 To compile this driver as a module, choose M here: the module 542 To compile this driver as a module, choose M here: the module
533 will be called snd-hdsp. 543 will be called snd-hdsp.
534 544
545comment "Don't forget to add built-in firmwares for HDSP driver"
546 depends on SND_HDSP=y
547
535config SND_HDSPM 548config SND_HDSPM
536 tristate "RME Hammerfall DSP MADI" 549 tristate "RME Hammerfall DSP MADI"
537 select SND_HWDEP 550 select SND_HWDEP
@@ -622,6 +635,16 @@ config SND_KORG1212
622 To compile this driver as a module, choose M here: the module 635 To compile this driver as a module, choose M here: the module
623 will be called snd-korg1212. 636 will be called snd-korg1212.
624 637
638config SND_LX6464ES
639 tristate "Digigram LX6464ES"
640 select SND_PCM
641 help
642 Say Y here to include support for Digigram LX6464ES boards.
643
644 To compile this driver as a module, choose M here: the module
645 will be called snd-lx6464es.
646
647
625config SND_MAESTRO3 648config SND_MAESTRO3
626 tristate "ESS Allegro/Maestro3" 649 tristate "ESS Allegro/Maestro3"
627 select SND_AC97_CODEC 650 select SND_AC97_CODEC
@@ -764,8 +787,8 @@ config SND_VIRTUOSO
764 select SND_OXYGEN_LIB 787 select SND_OXYGEN_LIB
765 help 788 help
766 Say Y here to include support for sound cards based on the 789 Say Y here to include support for sound cards based on the
767 Asus AV100/AV200 chips, i.e., Xonar D1, DX, D2, D2X, and 790 Asus AV100/AV200 chips, i.e., Xonar D1, DX, D2, D2X,
768 Essence STX. 791 Essence ST (Deluxe), and Essence STX.
769 Support for the HDAV1.3 (Deluxe) is very experimental. 792 Support for the HDAV1.3 (Deluxe) is very experimental.
770 793
771 To compile this driver as a module, choose M here: the module 794 To compile this driver as a module, choose M here: the module
diff --git a/sound/pci/Makefile b/sound/pci/Makefile
index 65b25d221cd..ecfc609d2b9 100644
--- a/sound/pci/Makefile
+++ b/sound/pci/Makefile
@@ -59,9 +59,11 @@ obj-$(CONFIG_SND) += \
59 ali5451/ \ 59 ali5451/ \
60 au88x0/ \ 60 au88x0/ \
61 aw2/ \ 61 aw2/ \
62 ctxfi/ \
62 ca0106/ \ 63 ca0106/ \
63 cs46xx/ \ 64 cs46xx/ \
64 cs5535audio/ \ 65 cs5535audio/ \
66 lx6464es/ \
65 echoaudio/ \ 67 echoaudio/ \
66 emu10k1/ \ 68 emu10k1/ \
67 hda/ \ 69 hda/ \
diff --git a/sound/pci/ac97/ac97_codec.c b/sound/pci/ac97/ac97_codec.c
index 97ee127ac33..78288dbfc17 100644
--- a/sound/pci/ac97/ac97_codec.c
+++ b/sound/pci/ac97/ac97_codec.c
@@ -2122,7 +2122,7 @@ int snd_ac97_mixer(struct snd_ac97_bus *bus, struct snd_ac97_template *template,
2122 } 2122 }
2123 /* nothing should be in powerdown mode */ 2123 /* nothing should be in powerdown mode */
2124 snd_ac97_write_cache(ac97, AC97_GENERAL_PURPOSE, 0); 2124 snd_ac97_write_cache(ac97, AC97_GENERAL_PURPOSE, 0);
2125 end_time = jiffies + msecs_to_jiffies(100); 2125 end_time = jiffies + msecs_to_jiffies(120);
2126 do { 2126 do {
2127 if ((snd_ac97_read(ac97, AC97_POWERDOWN) & 0x0f) == 0x0f) 2127 if ((snd_ac97_read(ac97, AC97_POWERDOWN) & 0x0f) == 0x0f)
2128 goto __ready_ok; 2128 goto __ready_ok;
diff --git a/sound/pci/ac97/ac97_patch.c b/sound/pci/ac97/ac97_patch.c
index 81bc93e5f1e..7337abdbe4e 100644
--- a/sound/pci/ac97/ac97_patch.c
+++ b/sound/pci/ac97/ac97_patch.c
@@ -958,10 +958,13 @@ static int patch_sigmatel_stac9708_3d(struct snd_ac97 * ac97)
958} 958}
959 959
960static const struct snd_kcontrol_new snd_ac97_sigmatel_4speaker = 960static const struct snd_kcontrol_new snd_ac97_sigmatel_4speaker =
961AC97_SINGLE("Sigmatel 4-Speaker Stereo Playback Switch", AC97_SIGMATEL_DAC2INVERT, 2, 1, 0); 961AC97_SINGLE("Sigmatel 4-Speaker Stereo Playback Switch",
962 AC97_SIGMATEL_DAC2INVERT, 2, 1, 0);
962 963
964/* "Sigmatel " removed due to excessive name length: */
963static const struct snd_kcontrol_new snd_ac97_sigmatel_phaseinvert = 965static const struct snd_kcontrol_new snd_ac97_sigmatel_phaseinvert =
964AC97_SINGLE("Sigmatel Surround Phase Inversion Playback Switch", AC97_SIGMATEL_DAC2INVERT, 3, 1, 0); 966AC97_SINGLE("Surround Phase Inversion Playback Switch",
967 AC97_SIGMATEL_DAC2INVERT, 3, 1, 0);
965 968
966static const struct snd_kcontrol_new snd_ac97_sigmatel_controls[] = { 969static const struct snd_kcontrol_new snd_ac97_sigmatel_controls[] = {
967AC97_SINGLE("Sigmatel DAC 6dB Attenuate", AC97_SIGMATEL_ANALOG, 1, 1, 0), 970AC97_SINGLE("Sigmatel DAC 6dB Attenuate", AC97_SIGMATEL_ANALOG, 1, 1, 0),
diff --git a/sound/pci/atiixp.c b/sound/pci/atiixp.c
index 9ce8548c03e..71515ddb459 100644
--- a/sound/pci/atiixp.c
+++ b/sound/pci/atiixp.c
@@ -1393,6 +1393,12 @@ static struct ac97_quirk ac97_quirks[] __devinitdata = {
1393 .name = "HP nx6125", 1393 .name = "HP nx6125",
1394 .type = AC97_TUNE_MUTE_LED 1394 .type = AC97_TUNE_MUTE_LED
1395 }, 1395 },
1396 {
1397 .subvendor = 0x103c,
1398 .subdevice = 0x3091,
1399 .name = "unknown HP",
1400 .type = AC97_TUNE_MUTE_LED
1401 },
1396 { } /* terminator */ 1402 { } /* terminator */
1397}; 1403};
1398 1404
diff --git a/sound/pci/au88x0/au88x0_core.c b/sound/pci/au88x0/au88x0_core.c
index 3906f5afe27..23f49f356e0 100644
--- a/sound/pci/au88x0/au88x0_core.c
+++ b/sound/pci/au88x0/au88x0_core.c
@@ -1255,8 +1255,8 @@ static int inline vortex_adbdma_getlinearpos(vortex_t * vortex, int adbdma)
1255 int temp; 1255 int temp;
1256 1256
1257 temp = hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2)); 1257 temp = hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2));
1258 temp = (dma->period_virt * dma->period_bytes) + (temp & POS_MASK); 1258 temp = (dma->period_virt * dma->period_bytes) + (temp & (dma->period_bytes - 1));
1259 return (temp); 1259 return temp;
1260} 1260}
1261 1261
1262static void vortex_adbdma_startfifo(vortex_t * vortex, int adbdma) 1262static void vortex_adbdma_startfifo(vortex_t * vortex, int adbdma)
@@ -1504,8 +1504,7 @@ static int inline vortex_wtdma_getlinearpos(vortex_t * vortex, int wtdma)
1504 int temp; 1504 int temp;
1505 1505
1506 temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)); 1506 temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2));
1507 //temp = (temp & POS_MASK) + (((temp>>WT_SUBBUF_SHIFT) & WT_SUBBUF_MASK)*(dma->cfg0&POS_MASK)); 1507 temp = (dma->period_virt * dma->period_bytes) + (temp & (dma->period_bytes - 1));
1508 temp = (temp & POS_MASK) + ((dma->period_virt) * (dma->period_bytes));
1509 return temp; 1508 return temp;
1510} 1509}
1511 1510
@@ -2441,7 +2440,8 @@ static irqreturn_t vortex_interrupt(int irq, void *dev_id)
2441 spin_lock(&vortex->lock); 2440 spin_lock(&vortex->lock);
2442 for (i = 0; i < NR_ADB; i++) { 2441 for (i = 0; i < NR_ADB; i++) {
2443 if (vortex->dma_adb[i].fifo_status == FIFO_START) { 2442 if (vortex->dma_adb[i].fifo_status == FIFO_START) {
2444 if (vortex_adbdma_bufshift(vortex, i)) ; 2443 if (!vortex_adbdma_bufshift(vortex, i))
2444 continue;
2445 spin_unlock(&vortex->lock); 2445 spin_unlock(&vortex->lock);
2446 snd_pcm_period_elapsed(vortex->dma_adb[i]. 2446 snd_pcm_period_elapsed(vortex->dma_adb[i].
2447 substream); 2447 substream);
diff --git a/sound/pci/bt87x.c b/sound/pci/bt87x.c
index a299340519d..24585c6c6d0 100644
--- a/sound/pci/bt87x.c
+++ b/sound/pci/bt87x.c
@@ -349,7 +349,8 @@ static struct snd_pcm_hardware snd_bt87x_digital_hw = {
349 .info = SNDRV_PCM_INFO_MMAP | 349 .info = SNDRV_PCM_INFO_MMAP |
350 SNDRV_PCM_INFO_INTERLEAVED | 350 SNDRV_PCM_INFO_INTERLEAVED |
351 SNDRV_PCM_INFO_BLOCK_TRANSFER | 351 SNDRV_PCM_INFO_BLOCK_TRANSFER |
352 SNDRV_PCM_INFO_MMAP_VALID, 352 SNDRV_PCM_INFO_MMAP_VALID |
353 SNDRV_PCM_INFO_BATCH,
353 .formats = SNDRV_PCM_FMTBIT_S16_LE, 354 .formats = SNDRV_PCM_FMTBIT_S16_LE,
354 .rates = 0, /* set at runtime */ 355 .rates = 0, /* set at runtime */
355 .channels_min = 2, 356 .channels_min = 2,
@@ -365,7 +366,8 @@ static struct snd_pcm_hardware snd_bt87x_analog_hw = {
365 .info = SNDRV_PCM_INFO_MMAP | 366 .info = SNDRV_PCM_INFO_MMAP |
366 SNDRV_PCM_INFO_INTERLEAVED | 367 SNDRV_PCM_INFO_INTERLEAVED |
367 SNDRV_PCM_INFO_BLOCK_TRANSFER | 368 SNDRV_PCM_INFO_BLOCK_TRANSFER |
368 SNDRV_PCM_INFO_MMAP_VALID, 369 SNDRV_PCM_INFO_MMAP_VALID |
370 SNDRV_PCM_INFO_BATCH,
369 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8, 371 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
370 .rates = SNDRV_PCM_RATE_KNOT, 372 .rates = SNDRV_PCM_RATE_KNOT,
371 .rate_min = ANALOG_CLOCK / CLOCK_DIV_MAX, 373 .rate_min = ANALOG_CLOCK / CLOCK_DIV_MAX,
@@ -808,6 +810,8 @@ static struct pci_device_id snd_bt87x_ids[] = {
808 BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x107d, 0x6606, GENERIC), 810 BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x107d, 0x6606, GENERIC),
809 /* Voodoo TV 200 */ 811 /* Voodoo TV 200 */
810 BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x121a, 0x3000, GENERIC), 812 BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x121a, 0x3000, GENERIC),
813 /* Askey Computer Corp. MagicTView'99 */
814 BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x144f, 0x3000, GENERIC),
811 /* AVerMedia Studio No. 103, 203, ...? */ 815 /* AVerMedia Studio No. 103, 203, ...? */
812 BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x1461, 0x0003, AVPHONE98), 816 BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x1461, 0x0003, AVPHONE98),
813 /* Prolink PixelView PV-M4900 */ 817 /* Prolink PixelView PV-M4900 */
diff --git a/sound/pci/ca0106/ca0106_main.c b/sound/pci/ca0106/ca0106_main.c
index bfac30f7929..57b992a5c05 100644
--- a/sound/pci/ca0106/ca0106_main.c
+++ b/sound/pci/ca0106/ca0106_main.c
@@ -1319,7 +1319,6 @@ static int __devinit snd_ca0106_pcm(struct snd_ca0106 *emu, int device)
1319 } 1319 }
1320 1320
1321 pcm->info_flags = 0; 1321 pcm->info_flags = 0;
1322 pcm->dev_subclass = SNDRV_PCM_SUBCLASS_GENERIC_MIX;
1323 strcpy(pcm->name, "CA0106"); 1322 strcpy(pcm->name, "CA0106");
1324 1323
1325 for(substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream; 1324 for(substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
diff --git a/sound/pci/ca0106/ca0106_mixer.c b/sound/pci/ca0106/ca0106_mixer.c
index ad2888705d2..c8c6f437f5b 100644
--- a/sound/pci/ca0106/ca0106_mixer.c
+++ b/sound/pci/ca0106/ca0106_mixer.c
@@ -739,7 +739,7 @@ static int __devinit rename_ctl(struct snd_card *card, const char *src, const ch
739 } while (0) 739 } while (0)
740 740
741static __devinitdata 741static __devinitdata
742DECLARE_TLV_DB_SCALE(snd_ca0106_master_db_scale, -6375, 50, 1); 742DECLARE_TLV_DB_SCALE(snd_ca0106_master_db_scale, -6375, 25, 1);
743 743
744static char *slave_vols[] __devinitdata = { 744static char *slave_vols[] __devinitdata = {
745 "Analog Front Playback Volume", 745 "Analog Front Playback Volume",
@@ -800,7 +800,7 @@ int __devinit snd_ca0106_mixer(struct snd_ca0106 *emu)
800 "Capture Volume", 800 "Capture Volume",
801 "External Amplifier", 801 "External Amplifier",
802 "Sigmatel 4-Speaker Stereo Playback Switch", 802 "Sigmatel 4-Speaker Stereo Playback Switch",
803 "Sigmatel Surround Phase Inversion Playback ", 803 "Surround Phase Inversion Playback Switch",
804 NULL 804 NULL
805 }; 805 };
806 static char *ca0106_rename_ctls[] = { 806 static char *ca0106_rename_ctls[] = {
@@ -841,6 +841,9 @@ int __devinit snd_ca0106_mixer(struct snd_ca0106 *emu)
841 snd_ca0106_master_db_scale); 841 snd_ca0106_master_db_scale);
842 if (!vmaster) 842 if (!vmaster)
843 return -ENOMEM; 843 return -ENOMEM;
844 err = snd_ctl_add(card, vmaster);
845 if (err < 0)
846 return err;
844 add_slaves(card, vmaster, slave_vols); 847 add_slaves(card, vmaster, slave_vols);
845 848
846 if (emu->details->spi_dac == 1) { 849 if (emu->details->spi_dac == 1) {
@@ -848,8 +851,13 @@ int __devinit snd_ca0106_mixer(struct snd_ca0106 *emu)
848 NULL); 851 NULL);
849 if (!vmaster) 852 if (!vmaster)
850 return -ENOMEM; 853 return -ENOMEM;
854 err = snd_ctl_add(card, vmaster);
855 if (err < 0)
856 return err;
851 add_slaves(card, vmaster, slave_sws); 857 add_slaves(card, vmaster, slave_sws);
852 } 858 }
859
860 strcpy(card->mixername, "CA0106");
853 return 0; 861 return 0;
854} 862}
855 863
diff --git a/sound/pci/cmipci.c b/sound/pci/cmipci.c
index c7899c32aba..449fe02f666 100644
--- a/sound/pci/cmipci.c
+++ b/sound/pci/cmipci.c
@@ -3014,7 +3014,7 @@ static int __devinit snd_cmipci_create(struct snd_card *card, struct pci_dev *pc
3014 .dev_free = snd_cmipci_dev_free, 3014 .dev_free = snd_cmipci_dev_free,
3015 }; 3015 };
3016 unsigned int val; 3016 unsigned int val;
3017 long iomidi; 3017 long iomidi = 0;
3018 int integrated_midi = 0; 3018 int integrated_midi = 0;
3019 char modelstr[16]; 3019 char modelstr[16];
3020 int pcm_index, pcm_spdif_index; 3020 int pcm_index, pcm_spdif_index;
diff --git a/sound/pci/ctxfi/Makefile b/sound/pci/ctxfi/Makefile
new file mode 100644
index 00000000000..15075f89e98
--- /dev/null
+++ b/sound/pci/ctxfi/Makefile
@@ -0,0 +1,5 @@
1snd-ctxfi-objs := xfi.o ctatc.o ctvmem.o ctpcm.o ctmixer.o ctresource.o \
2 ctsrc.o ctamixer.o ctdaio.o ctimap.o cthardware.o cttimer.o \
3 cthw20k2.o cthw20k1.o
4
5obj-$(CONFIG_SND_CTXFI) += snd-ctxfi.o
diff --git a/sound/pci/ctxfi/ct20k1reg.h b/sound/pci/ctxfi/ct20k1reg.h
new file mode 100644
index 00000000000..f2e34e3f27e
--- /dev/null
+++ b/sound/pci/ctxfi/ct20k1reg.h
@@ -0,0 +1,636 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 */
8
9#ifndef CT20K1REG_H
10#define CT20k1REG_H
11
12/* 20k1 registers */
13#define DSPXRAM_START 0x000000
14#define DSPXRAM_END 0x013FFC
15#define DSPAXRAM_START 0x020000
16#define DSPAXRAM_END 0x023FFC
17#define DSPYRAM_START 0x040000
18#define DSPYRAM_END 0x04FFFC
19#define DSPAYRAM_START 0x020000
20#define DSPAYRAM_END 0x063FFC
21#define DSPMICRO_START 0x080000
22#define DSPMICRO_END 0x0B3FFC
23#define DSP0IO_START 0x100000
24#define DSP0IO_END 0x101FFC
25#define AUDIORINGIPDSP0_START 0x100000
26#define AUDIORINGIPDSP0_END 0x1003FC
27#define AUDIORINGOPDSP0_START 0x100400
28#define AUDIORINGOPDSP0_END 0x1007FC
29#define AUDPARARINGIODSP0_START 0x100800
30#define AUDPARARINGIODSP0_END 0x100BFC
31#define DSP0LOCALHWREG_START 0x100C00
32#define DSP0LOCALHWREG_END 0x100C3C
33#define DSP0XYRAMAGINDEX_START 0x100C40
34#define DSP0XYRAMAGINDEX_END 0x100C5C
35#define DSP0XYRAMAGMDFR_START 0x100C60
36#define DSP0XYRAMAGMDFR_END 0x100C7C
37#define DSP0INTCONTLVEC_START 0x100C80
38#define DSP0INTCONTLVEC_END 0x100CD8
39#define INTCONTLGLOBALREG_START 0x100D1C
40#define INTCONTLGLOBALREG_END 0x100D3C
41#define HOSTINTFPORTADDRCONTDSP0 0x100D40
42#define HOSTINTFPORTDATADSP0 0x100D44
43#define TIME0PERENBDSP0 0x100D60
44#define TIME0COUNTERDSP0 0x100D64
45#define TIME1PERENBDSP0 0x100D68
46#define TIME1COUNTERDSP0 0x100D6C
47#define TIME2PERENBDSP0 0x100D70
48#define TIME2COUNTERDSP0 0x100D74
49#define TIME3PERENBDSP0 0x100D78
50#define TIME3COUNTERDSP0 0x100D7C
51#define XRAMINDOPERREFNOUP_STARTDSP0 0x100D80
52#define XRAMINDOPERREFNOUP_ENDDSP0 0x100D9C
53#define XRAMINDOPERREFUP_STARTDSP0 0x100DA0
54#define XRAMINDOPERREFUP_ENDDSP0 0x100DBC
55#define YRAMINDOPERREFNOUP_STARTDSP0 0x100DC0
56#define YRAMINDOPERREFNOUP_ENDDSP0 0x100DDC
57#define YRAMINDOPERREFUP_STARTDSP0 0x100DE0
58#define YRAMINDOPERREFUP_ENDDSP0 0x100DFC
59#define DSP0CONDCODE 0x100E00
60#define DSP0STACKFLAG 0x100E04
61#define DSP0PROGCOUNTSTACKPTREG 0x100E08
62#define DSP0PROGCOUNTSTACKDATAREG 0x100E0C
63#define DSP0CURLOOPADDRREG 0x100E10
64#define DSP0CURLOOPCOUNT 0x100E14
65#define DSP0TOPLOOPCOUNTSTACK 0x100E18
66#define DSP0TOPLOOPADDRSTACK 0x100E1C
67#define DSP0LOOPSTACKPTR 0x100E20
68#define DSP0STASSTACKDATAREG 0x100E24
69#define DSP0STASSTACKPTR 0x100E28
70#define DSP0PROGCOUNT 0x100E2C
71#define GLOBDSPDEBGREG 0x100E30
72#define GLOBDSPBREPTRREG 0x100E30
73#define DSP0XYRAMBASE_START 0x100EA0
74#define DSP0XYRAMBASE_END 0x100EBC
75#define DSP0XYRAMLENG_START 0x100EC0
76#define DSP0XYRAMLENG_END 0x100EDC
77#define SEMAPHOREREGDSP0 0x100EE0
78#define DSP0INTCONTMASKREG 0x100EE4
79#define DSP0INTCONTPENDREG 0x100EE8
80#define DSP0INTCONTSERVINT 0x100EEC
81#define DSPINTCONTEXTINTMODREG 0x100EEC
82#define GPIODSP0 0x100EFC
83#define DMADSPBASEADDRREG_STARTDSP0 0x100F00
84#define DMADSPBASEADDRREG_ENDDSP0 0x100F1C
85#define DMAHOSTBASEADDRREG_STARTDSP0 0x100F20
86#define DMAHOSTBASEADDRREG_ENDDSP0 0x100F3C
87#define DMADSPCURADDRREG_STARTDSP0 0x100F40
88#define DMADSPCURADDRREG_ENDDSP0 0x100F5C
89#define DMAHOSTCURADDRREG_STARTDSP0 0x100F60
90#define DMAHOSTCURADDRREG_ENDDSP0 0x100F7C
91#define DMATANXCOUNTREG_STARTDSP0 0x100F80
92#define DMATANXCOUNTREG_ENDDSP0 0x100F9C
93#define DMATIMEBUGREG_STARTDSP0 0x100FA0
94#define DMATIMEBUGREG_ENDDSP0 0x100FAC
95#define DMACNTLMODFREG_STARTDSP0 0x100FA0
96#define DMACNTLMODFREG_ENDDSP0 0x100FAC
97
98#define DMAGLOBSTATSREGDSP0 0x100FEC
99#define DSP0XGPRAM_START 0x101000
100#define DSP0XGPRAM_END 0x1017FC
101#define DSP0YGPRAM_START 0x101800
102#define DSP0YGPRAM_END 0x101FFC
103
104
105
106
107#define AUDIORINGIPDSP1_START 0x102000
108#define AUDIORINGIPDSP1_END 0x1023FC
109#define AUDIORINGOPDSP1_START 0x102400
110#define AUDIORINGOPDSP1_END 0x1027FC
111#define AUDPARARINGIODSP1_START 0x102800
112#define AUDPARARINGIODSP1_END 0x102BFC
113#define DSP1LOCALHWREG_START 0x102C00
114#define DSP1LOCALHWREG_END 0x102C3C
115#define DSP1XYRAMAGINDEX_START 0x102C40
116#define DSP1XYRAMAGINDEX_END 0x102C5C
117#define DSP1XYRAMAGMDFR_START 0x102C60
118#define DSP1XYRAMAGMDFR_END 0x102C7C
119#define DSP1INTCONTLVEC_START 0x102C80
120#define DSP1INTCONTLVEC_END 0x102CD8
121#define HOSTINTFPORTADDRCONTDSP1 0x102D40
122#define HOSTINTFPORTDATADSP1 0x102D44
123#define TIME0PERENBDSP1 0x102D60
124#define TIME0COUNTERDSP1 0x102D64
125#define TIME1PERENBDSP1 0x102D68
126#define TIME1COUNTERDSP1 0x102D6C
127#define TIME2PERENBDSP1 0x102D70
128#define TIME2COUNTERDSP1 0x102D74
129#define TIME3PERENBDSP1 0x102D78
130#define TIME3COUNTERDSP1 0x102D7C
131#define XRAMINDOPERREFNOUP_STARTDSP1 0x102D80
132#define XRAMINDOPERREFNOUP_ENDDSP1 0x102D9C
133#define XRAMINDOPERREFUP_STARTDSP1 0x102DA0
134#define XRAMINDOPERREFUP_ENDDSP1 0x102DBC
135#define YRAMINDOPERREFNOUP_STARTDSP1 0x102DC0
136#define YRAMINDOPERREFNOUP_ENDDSP1 0x102DDC
137#define YRAMINDOPERREFUP_STARTDSP1 0x102DE0
138#define YRAMINDOPERREFUP_ENDDSP1 0x102DFC
139
140#define DSP1CONDCODE 0x102E00
141#define DSP1STACKFLAG 0x102E04
142#define DSP1PROGCOUNTSTACKPTREG 0x102E08
143#define DSP1PROGCOUNTSTACKDATAREG 0x102E0C
144#define DSP1CURLOOPADDRREG 0x102E10
145#define DSP1CURLOOPCOUNT 0x102E14
146#define DSP1TOPLOOPCOUNTSTACK 0x102E18
147#define DSP1TOPLOOPADDRSTACK 0x102E1C
148#define DSP1LOOPSTACKPTR 0x102E20
149#define DSP1STASSTACKDATAREG 0x102E24
150#define DSP1STASSTACKPTR 0x102E28
151#define DSP1PROGCOUNT 0x102E2C
152#define DSP1XYRAMBASE_START 0x102EA0
153#define DSP1XYRAMBASE_END 0x102EBC
154#define DSP1XYRAMLENG_START 0x102EC0
155#define DSP1XYRAMLENG_END 0x102EDC
156#define SEMAPHOREREGDSP1 0x102EE0
157#define DSP1INTCONTMASKREG 0x102EE4
158#define DSP1INTCONTPENDREG 0x102EE8
159#define DSP1INTCONTSERVINT 0x102EEC
160#define GPIODSP1 0x102EFC
161#define DMADSPBASEADDRREG_STARTDSP1 0x102F00
162#define DMADSPBASEADDRREG_ENDDSP1 0x102F1C
163#define DMAHOSTBASEADDRREG_STARTDSP1 0x102F20
164#define DMAHOSTBASEADDRREG_ENDDSP1 0x102F3C
165#define DMADSPCURADDRREG_STARTDSP1 0x102F40
166#define DMADSPCURADDRREG_ENDDSP1 0x102F5C
167#define DMAHOSTCURADDRREG_STARTDSP1 0x102F60
168#define DMAHOSTCURADDRREG_ENDDSP1 0x102F7C
169#define DMATANXCOUNTREG_STARTDSP1 0x102F80
170#define DMATANXCOUNTREG_ENDDSP1 0x102F9C
171#define DMATIMEBUGREG_STARTDSP1 0x102FA0
172#define DMATIMEBUGREG_ENDDSP1 0x102FAC
173#define DMACNTLMODFREG_STARTDSP1 0x102FA0
174#define DMACNTLMODFREG_ENDDSP1 0x102FAC
175
176#define DMAGLOBSTATSREGDSP1 0x102FEC
177#define DSP1XGPRAM_START 0x103000
178#define DSP1XGPRAM_END 0x1033FC
179#define DSP1YGPRAM_START 0x103400
180#define DSP1YGPRAM_END 0x1037FC
181
182
183
184#define AUDIORINGIPDSP2_START 0x104000
185#define AUDIORINGIPDSP2_END 0x1043FC
186#define AUDIORINGOPDSP2_START 0x104400
187#define AUDIORINGOPDSP2_END 0x1047FC
188#define AUDPARARINGIODSP2_START 0x104800
189#define AUDPARARINGIODSP2_END 0x104BFC
190#define DSP2LOCALHWREG_START 0x104C00
191#define DSP2LOCALHWREG_END 0x104C3C
192#define DSP2XYRAMAGINDEX_START 0x104C40
193#define DSP2XYRAMAGINDEX_END 0x104C5C
194#define DSP2XYRAMAGMDFR_START 0x104C60
195#define DSP2XYRAMAGMDFR_END 0x104C7C
196#define DSP2INTCONTLVEC_START 0x104C80
197#define DSP2INTCONTLVEC_END 0x104CD8
198#define HOSTINTFPORTADDRCONTDSP2 0x104D40
199#define HOSTINTFPORTDATADSP2 0x104D44
200#define TIME0PERENBDSP2 0x104D60
201#define TIME0COUNTERDSP2 0x104D64
202#define TIME1PERENBDSP2 0x104D68
203#define TIME1COUNTERDSP2 0x104D6C
204#define TIME2PERENBDSP2 0x104D70
205#define TIME2COUNTERDSP2 0x104D74
206#define TIME3PERENBDSP2 0x104D78
207#define TIME3COUNTERDSP2 0x104D7C
208#define XRAMINDOPERREFNOUP_STARTDSP2 0x104D80
209#define XRAMINDOPERREFNOUP_ENDDSP2 0x104D9C
210#define XRAMINDOPERREFUP_STARTDSP2 0x104DA0
211#define XRAMINDOPERREFUP_ENDDSP2 0x104DBC
212#define YRAMINDOPERREFNOUP_STARTDSP2 0x104DC0
213#define YRAMINDOPERREFNOUP_ENDDSP2 0x104DDC
214#define YRAMINDOPERREFUP_STARTDSP2 0x104DE0
215#define YRAMINDOPERREFUP_ENDDSP2 0x104DFC
216#define DSP2CONDCODE 0x104E00
217#define DSP2STACKFLAG 0x104E04
218#define DSP2PROGCOUNTSTACKPTREG 0x104E08
219#define DSP2PROGCOUNTSTACKDATAREG 0x104E0C
220#define DSP2CURLOOPADDRREG 0x104E10
221#define DSP2CURLOOPCOUNT 0x104E14
222#define DSP2TOPLOOPCOUNTSTACK 0x104E18
223#define DSP2TOPLOOPADDRSTACK 0x104E1C
224#define DSP2LOOPSTACKPTR 0x104E20
225#define DSP2STASSTACKDATAREG 0x104E24
226#define DSP2STASSTACKPTR 0x104E28
227#define DSP2PROGCOUNT 0x104E2C
228#define DSP2XYRAMBASE_START 0x104EA0
229#define DSP2XYRAMBASE_END 0x104EBC
230#define DSP2XYRAMLENG_START 0x104EC0
231#define DSP2XYRAMLENG_END 0x104EDC
232#define SEMAPHOREREGDSP2 0x104EE0
233#define DSP2INTCONTMASKREG 0x104EE4
234#define DSP2INTCONTPENDREG 0x104EE8
235#define DSP2INTCONTSERVINT 0x104EEC
236#define GPIODSP2 0x104EFC
237#define DMADSPBASEADDRREG_STARTDSP2 0x104F00
238#define DMADSPBASEADDRREG_ENDDSP2 0x104F1C
239#define DMAHOSTBASEADDRREG_STARTDSP2 0x104F20
240#define DMAHOSTBASEADDRREG_ENDDSP2 0x104F3C
241#define DMADSPCURADDRREG_STARTDSP2 0x104F40
242#define DMADSPCURADDRREG_ENDDSP2 0x104F5C
243#define DMAHOSTCURADDRREG_STARTDSP2 0x104F60
244#define DMAHOSTCURADDRREG_ENDDSP2 0x104F7C
245#define DMATANXCOUNTREG_STARTDSP2 0x104F80
246#define DMATANXCOUNTREG_ENDDSP2 0x104F9C
247#define DMATIMEBUGREG_STARTDSP2 0x104FA0
248#define DMATIMEBUGREG_ENDDSP2 0x104FAC
249#define DMACNTLMODFREG_STARTDSP2 0x104FA0
250#define DMACNTLMODFREG_ENDDSP2 0x104FAC
251
252#define DMAGLOBSTATSREGDSP2 0x104FEC
253#define DSP2XGPRAM_START 0x105000
254#define DSP2XGPRAM_END 0x1051FC
255#define DSP2YGPRAM_START 0x105800
256#define DSP2YGPRAM_END 0x1059FC
257
258
259
260#define AUDIORINGIPDSP3_START 0x106000
261#define AUDIORINGIPDSP3_END 0x1063FC
262#define AUDIORINGOPDSP3_START 0x106400
263#define AUDIORINGOPDSP3_END 0x1067FC
264#define AUDPARARINGIODSP3_START 0x106800
265#define AUDPARARINGIODSP3_END 0x106BFC
266#define DSP3LOCALHWREG_START 0x106C00
267#define DSP3LOCALHWREG_END 0x106C3C
268#define DSP3XYRAMAGINDEX_START 0x106C40
269#define DSP3XYRAMAGINDEX_END 0x106C5C
270#define DSP3XYRAMAGMDFR_START 0x106C60
271#define DSP3XYRAMAGMDFR_END 0x106C7C
272#define DSP3INTCONTLVEC_START 0x106C80
273#define DSP3INTCONTLVEC_END 0x106CD8
274#define HOSTINTFPORTADDRCONTDSP3 0x106D40
275#define HOSTINTFPORTDATADSP3 0x106D44
276#define TIME0PERENBDSP3 0x106D60
277#define TIME0COUNTERDSP3 0x106D64
278#define TIME1PERENBDSP3 0x106D68
279#define TIME1COUNTERDSP3 0x106D6C
280#define TIME2PERENBDSP3 0x106D70
281#define TIME2COUNTERDSP3 0x106D74
282#define TIME3PERENBDSP3 0x106D78
283#define TIME3COUNTERDSP3 0x106D7C
284#define XRAMINDOPERREFNOUP_STARTDSP3 0x106D80
285#define XRAMINDOPERREFNOUP_ENDDSP3 0x106D9C
286#define XRAMINDOPERREFUP_STARTDSP3 0x106DA0
287#define XRAMINDOPERREFUP_ENDDSP3 0x106DBC
288#define YRAMINDOPERREFNOUP_STARTDSP3 0x106DC0
289#define YRAMINDOPERREFNOUP_ENDDSP3 0x106DDC
290#define YRAMINDOPERREFUP_STARTDSP3 0x106DE0
291#define YRAMINDOPERREFUP_ENDDSP3 0x100DFC
292
293#define DSP3CONDCODE 0x106E00
294#define DSP3STACKFLAG 0x106E04
295#define DSP3PROGCOUNTSTACKPTREG 0x106E08
296#define DSP3PROGCOUNTSTACKDATAREG 0x106E0C
297#define DSP3CURLOOPADDRREG 0x106E10
298#define DSP3CURLOOPCOUNT 0x106E14
299#define DSP3TOPLOOPCOUNTSTACK 0x106E18
300#define DSP3TOPLOOPADDRSTACK 0x106E1C
301#define DSP3LOOPSTACKPTR 0x106E20
302#define DSP3STASSTACKDATAREG 0x106E24
303#define DSP3STASSTACKPTR 0x106E28
304#define DSP3PROGCOUNT 0x106E2C
305#define DSP3XYRAMBASE_START 0x106EA0
306#define DSP3XYRAMBASE_END 0x106EBC
307#define DSP3XYRAMLENG_START 0x106EC0
308#define DSP3XYRAMLENG_END 0x106EDC
309#define SEMAPHOREREGDSP3 0x106EE0
310#define DSP3INTCONTMASKREG 0x106EE4
311#define DSP3INTCONTPENDREG 0x106EE8
312#define DSP3INTCONTSERVINT 0x106EEC
313#define GPIODSP3 0x106EFC
314#define DMADSPBASEADDRREG_STARTDSP3 0x106F00
315#define DMADSPBASEADDRREG_ENDDSP3 0x106F1C
316#define DMAHOSTBASEADDRREG_STARTDSP3 0x106F20
317#define DMAHOSTBASEADDRREG_ENDDSP3 0x106F3C
318#define DMADSPCURADDRREG_STARTDSP3 0x106F40
319#define DMADSPCURADDRREG_ENDDSP3 0x106F5C
320#define DMAHOSTCURADDRREG_STARTDSP3 0x106F60
321#define DMAHOSTCURADDRREG_ENDDSP3 0x106F7C
322#define DMATANXCOUNTREG_STARTDSP3 0x106F80
323#define DMATANXCOUNTREG_ENDDSP3 0x106F9C
324#define DMATIMEBUGREG_STARTDSP3 0x106FA0
325#define DMATIMEBUGREG_ENDDSP3 0x106FAC
326#define DMACNTLMODFREG_STARTDSP3 0x106FA0
327#define DMACNTLMODFREG_ENDDSP3 0x106FAC
328
329#define DMAGLOBSTATSREGDSP3 0x106FEC
330#define DSP3XGPRAM_START 0x107000
331#define DSP3XGPRAM_END 0x1071FC
332#define DSP3YGPRAM_START 0x107800
333#define DSP3YGPRAM_END 0x1079FC
334
335/* end of DSP reg definitions */
336
337#define DSPAIMAP_START 0x108000
338#define DSPAIMAP_END 0x1083FC
339#define DSPPIMAP_START 0x108400
340#define DSPPIMAP_END 0x1087FC
341#define DSPPOMAP_START 0x108800
342#define DSPPOMAP_END 0x108BFC
343#define DSPPOCTL 0x108C00
344#define TKCTL_START 0x110000
345#define TKCTL_END 0x110FFC
346#define TKCC_START 0x111000
347#define TKCC_END 0x111FFC
348#define TKIMAP_START 0x112000
349#define TKIMAP_END 0x112FFC
350#define TKDCTR16 0x113000
351#define TKPB16 0x113004
352#define TKBS16 0x113008
353#define TKDCTR32 0x11300C
354#define TKPB32 0x113010
355#define TKBS32 0x113014
356#define ICDCTR16 0x113018
357#define ITBS16 0x11301C
358#define ICDCTR32 0x113020
359#define ITBS32 0x113024
360#define ITSTART 0x113028
361#define TKSQ 0x11302C
362
363#define TKSCCTL_START 0x114000
364#define TKSCCTL_END 0x11403C
365#define TKSCADR_START 0x114100
366#define TKSCADR_END 0x11413C
367#define TKSCDATAX_START 0x114800
368#define TKSCDATAX_END 0x1149FC
369#define TKPCDATAX_START 0x120000
370#define TKPCDATAX_END 0x12FFFC
371
372#define MALSA 0x130000
373#define MAPPHA 0x130004
374#define MAPPLA 0x130008
375#define MALSB 0x130010
376#define MAPPHB 0x130014
377#define MAPPLB 0x130018
378
379#define TANSPORTMAPABREGS_START 0x130020
380#define TANSPORTMAPABREGS_END 0x13A2FC
381
382#define PTPAHX 0x13B000
383#define PTPALX 0x13B004
384
385#define TANSPPAGETABLEPHYADDR015_START 0x13B008
386#define TANSPPAGETABLEPHYADDR015_END 0x13B07C
387#define TRNQADRX_START 0x13B100
388#define TRNQADRX_END 0x13B13C
389#define TRNQTIMX_START 0x13B200
390#define TRNQTIMX_END 0x13B23C
391#define TRNQAPARMX_START 0x13B300
392#define TRNQAPARMX_END 0x13B33C
393
394#define TRNQCNT 0x13B400
395#define TRNCTL 0x13B404
396#define TRNIS 0x13B408
397#define TRNCURTS 0x13B40C
398
399#define AMOP_START 0x140000
400#define AMOPLO 0x140000
401#define AMOPHI 0x140004
402#define AMOP_END 0x147FFC
403#define PMOP_START 0x148000
404#define PMOPLO 0x148000
405#define PMOPHI 0x148004
406#define PMOP_END 0x14FFFC
407#define PCURR_START 0x150000
408#define PCURR_END 0x153FFC
409#define PTRAG_START 0x154000
410#define PTRAG_END 0x157FFC
411#define PSR_START 0x158000
412#define PSR_END 0x15BFFC
413
414#define PFSTAT4SEG_START 0x160000
415#define PFSTAT4SEG_END 0x160BFC
416#define PFSTAT2SEG_START 0x160C00
417#define PFSTAT2SEG_END 0x1617FC
418#define PFTARG4SEG_START 0x164000
419#define PFTARG4SEG_END 0x164BFC
420#define PFTARG2SEG_START 0x164C00
421#define PFTARG2SEG_END 0x1657FC
422#define PFSR4SEG_START 0x168000
423#define PFSR4SEG_END 0x168BFC
424#define PFSR2SEG_START 0x168C00
425#define PFSR2SEG_END 0x1697FC
426#define PCURRMS4SEG_START 0x16C000
427#define PCURRMS4SEG_END 0x16CCFC
428#define PCURRMS2SEG_START 0x16CC00
429#define PCURRMS2SEG_END 0x16D7FC
430#define PTARGMS4SEG_START 0x170000
431#define PTARGMS4SEG_END 0x172FFC
432#define PTARGMS2SEG_START 0x173000
433#define PTARGMS2SEG_END 0x1747FC
434#define PSRMS4SEG_START 0x170000
435#define PSRMS4SEG_END 0x172FFC
436#define PSRMS2SEG_START 0x173000
437#define PSRMS2SEG_END 0x1747FC
438
439#define PRING_LO_START 0x190000
440#define PRING_LO_END 0x193FFC
441#define PRING_HI_START 0x194000
442#define PRING_HI_END 0x197FFC
443#define PRING_LO_HI_START 0x198000
444#define PRING_LO_HI 0x198000
445#define PRING_LO_HI_END 0x19BFFC
446
447#define PINTFIFO 0x1A0000
448#define SRCCTL 0x1B0000
449#define SRCCCR 0x1B0004
450#define SRCIMAP 0x1B0008
451#define SRCODDC 0x1B000C
452#define SRCCA 0x1B0010
453#define SRCCF 0x1B0014
454#define SRCSA 0x1B0018
455#define SRCLA 0x1B001C
456#define SRCCTLSWR 0x1B0020
457
458/* SRC HERE */
459#define SRCALBA 0x1B002C
460#define SRCMCTL 0x1B012C
461#define SRCCERR 0x1B022C
462#define SRCITB 0x1B032C
463#define SRCIPM 0x1B082C
464#define SRCIP 0x1B102C
465#define SRCENBSTAT 0x1B202C
466#define SRCENBLO 0x1B212C
467#define SRCENBHI 0x1B222C
468#define SRCENBS 0x1B232C
469#define SRCENB 0x1B282C
470#define SRCENB07 0x1B282C
471#define SRCENBS07 0x1B302C
472
473#define SRCDN0Z 0x1B0030
474#define SRCDN0Z0 0x1B0030
475#define SRCDN0Z1 0x1B0034
476#define SRCDN0Z2 0x1B0038
477#define SRCDN0Z3 0x1B003C
478#define SRCDN1Z 0x1B0040
479#define SRCDN1Z0 0x1B0040
480#define SRCDN1Z1 0x1B0044
481#define SRCDN1Z2 0x1B0048
482#define SRCDN1Z3 0x1B004C
483#define SRCDN1Z4 0x1B0050
484#define SRCDN1Z5 0x1B0054
485#define SRCDN1Z6 0x1B0058
486#define SRCDN1Z7 0x1B005C
487#define SRCUPZ 0x1B0060
488#define SRCUPZ0 0x1B0060
489#define SRCUPZ1 0x1B0064
490#define SRCUPZ2 0x1B0068
491#define SRCUPZ3 0x1B006C
492#define SRCUPZ4 0x1B0070
493#define SRCUPZ5 0x1B0074
494#define SRCUPZ6 0x1B0078
495#define SRCUPZ7 0x1B007C
496#define SRCCD0 0x1B0080
497#define SRCCD1 0x1B0084
498#define SRCCD2 0x1B0088
499#define SRCCD3 0x1B008C
500#define SRCCD4 0x1B0090
501#define SRCCD5 0x1B0094
502#define SRCCD6 0x1B0098
503#define SRCCD7 0x1B009C
504#define SRCCD8 0x1B00A0
505#define SRCCD9 0x1B00A4
506#define SRCCDA 0x1B00A8
507#define SRCCDB 0x1B00AC
508#define SRCCDC 0x1B00B0
509#define SRCCDD 0x1B00B4
510#define SRCCDE 0x1B00B8
511#define SRCCDF 0x1B00BC
512#define SRCCD10 0x1B00C0
513#define SRCCD11 0x1B00C4
514#define SRCCD12 0x1B00C8
515#define SRCCD13 0x1B00CC
516#define SRCCD14 0x1B00D0
517#define SRCCD15 0x1B00D4
518#define SRCCD16 0x1B00D8
519#define SRCCD17 0x1B00DC
520#define SRCCD18 0x1B00E0
521#define SRCCD19 0x1B00E4
522#define SRCCD1A 0x1B00E8
523#define SRCCD1B 0x1B00EC
524#define SRCCD1C 0x1B00F0
525#define SRCCD1D 0x1B00F4
526#define SRCCD1E 0x1B00F8
527#define SRCCD1F 0x1B00FC
528
529#define SRCCONTRBLOCK_START 0x1B0100
530#define SRCCONTRBLOCK_END 0x1BFFFC
531#define FILTOP_START 0x1C0000
532#define FILTOP_END 0x1C05FC
533#define FILTIMAP_START 0x1C0800
534#define FILTIMAP_END 0x1C0DFC
535#define FILTZ1_START 0x1C1000
536#define FILTZ1_END 0x1C15FC
537#define FILTZ2_START 0x1C1800
538#define FILTZ2_END 0x1C1DFC
539#define DAOIMAP_START 0x1C5000
540#define DAOIMAP 0x1C5000
541#define DAOIMAP_END 0x1C5124
542
543#define AC97D 0x1C5400
544#define AC97A 0x1C5404
545#define AC97CTL 0x1C5408
546#define I2SCTL 0x1C5420
547
548#define SPOS 0x1C5440
549#define SPOSA 0x1C5440
550#define SPOSB 0x1C5444
551#define SPOSC 0x1C5448
552#define SPOSD 0x1C544C
553
554#define SPISA 0x1C5450
555#define SPISB 0x1C5454
556#define SPISC 0x1C5458
557#define SPISD 0x1C545C
558
559#define SPFSCTL 0x1C5460
560
561#define SPFS0 0x1C5468
562#define SPFS1 0x1C546C
563#define SPFS2 0x1C5470
564#define SPFS3 0x1C5474
565#define SPFS4 0x1C5478
566#define SPFS5 0x1C547C
567
568#define SPOCTL 0x1C5480
569#define SPICTL 0x1C5484
570#define SPISTS 0x1C5488
571#define SPINTP 0x1C548C
572#define SPINTE 0x1C5490
573#define SPUTCTLAB 0x1C5494
574#define SPUTCTLCD 0x1C5498
575
576#define SRTSPA 0x1C54C0
577#define SRTSPB 0x1C54C4
578#define SRTSPC 0x1C54C8
579#define SRTSPD 0x1C54CC
580
581#define SRTSCTL 0x1C54D0
582#define SRTSCTLA 0x1C54D0
583#define SRTSCTLB 0x1C54D4
584#define SRTSCTLC 0x1C54D8
585#define SRTSCTLD 0x1C54DC
586
587#define SRTI2S 0x1C54E0
588#define SRTICTL 0x1C54F0
589
590#define WC 0x1C6000
591#define TIMR 0x1C6004
592# define TIMR_IE (1<<15)
593# define TIMR_IP (1<<14)
594
595#define GIP 0x1C6010
596#define GIE 0x1C6014
597#define DIE 0x1C6018
598#define DIC 0x1C601C
599#define GPIO 0x1C6020
600#define GPIOCTL 0x1C6024
601#define GPIP 0x1C6028
602#define GPIE 0x1C602C
603#define DSPINT0 0x1C6030
604#define DSPEIOC 0x1C6034
605#define MUADAT 0x1C6040
606#define MUACMD 0x1C6044
607#define MUASTAT 0x1C6044
608#define MUBDAT 0x1C6048
609#define MUBCMD 0x1C604C
610#define MUBSTAT 0x1C604C
611#define UARTCMA 0x1C6050
612#define UARTCMB 0x1C6054
613#define UARTIP 0x1C6058
614#define UARTIE 0x1C605C
615#define PLLCTL 0x1C6060
616#define PLLDCD 0x1C6064
617#define GCTL 0x1C6070
618#define ID0 0x1C6080
619#define ID1 0x1C6084
620#define ID2 0x1C6088
621#define ID3 0x1C608C
622#define SDRCTL 0x1C7000
623
624
625#define I2SA_L 0x0L
626#define I2SA_R 0x1L
627#define I2SB_L 0x8L
628#define I2SB_R 0x9L
629#define I2SC_L 0x10L
630#define I2SC_R 0x11L
631#define I2SD_L 0x18L
632#define I2SD_R 0x19L
633
634#endif /* CT20K1REG_H */
635
636
diff --git a/sound/pci/ctxfi/ct20k2reg.h b/sound/pci/ctxfi/ct20k2reg.h
new file mode 100644
index 00000000000..2d07986f57c
--- /dev/null
+++ b/sound/pci/ctxfi/ct20k2reg.h
@@ -0,0 +1,85 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 */
8
9#ifndef _20K2REGISTERS_H_
10#define _20K2REGISTERS_H_
11
12
13/* Timer Registers */
14#define TIMER_TIMR 0x1B7004
15#define INTERRUPT_GIP 0x1B7010
16#define INTERRUPT_GIE 0x1B7014
17
18/* I2C Registers */
19#define I2C_IF_ADDRESS 0x1B9000
20#define I2C_IF_WDATA 0x1B9004
21#define I2C_IF_RDATA 0x1B9008
22#define I2C_IF_STATUS 0x1B900C
23#define I2C_IF_WLOCK 0x1B9010
24
25/* Global Control Registers */
26#define GLOBAL_CNTL_GCTL 0x1B7090
27
28/* PLL Registers */
29#define PLL_CTL 0x1B7080
30#define PLL_STAT 0x1B7084
31#define PLL_ENB 0x1B7088
32
33/* SRC Registers */
34#define SRC_CTL 0x1A0000 /* 0x1A0000 + (256 * Chn) */
35#define SRC_CCR 0x1A0004 /* 0x1A0004 + (256 * Chn) */
36#define SRC_IMAP 0x1A0008 /* 0x1A0008 + (256 * Chn) */
37#define SRC_CA 0x1A0010 /* 0x1A0010 + (256 * Chn) */
38#define SRC_CF 0x1A0014 /* 0x1A0014 + (256 * Chn) */
39#define SRC_SA 0x1A0018 /* 0x1A0018 + (256 * Chn) */
40#define SRC_LA 0x1A001C /* 0x1A001C + (256 * Chn) */
41#define SRC_CTLSWR 0x1A0020 /* 0x1A0020 + (256 * Chn) */
42#define SRC_CD 0x1A0080 /* 0x1A0080 + (256 * Chn) + (4 * Regn) */
43#define SRC_MCTL 0x1A012C
44#define SRC_IP 0x1A102C /* 0x1A102C + (256 * Regn) */
45#define SRC_ENB 0x1A282C /* 0x1A282C + (256 * Regn) */
46#define SRC_ENBSTAT 0x1A202C
47#define SRC_ENBSA 0x1A232C
48#define SRC_DN0Z 0x1A0030
49#define SRC_DN1Z 0x1A0040
50#define SRC_UPZ 0x1A0060
51
52/* GPIO Registers */
53#define GPIO_DATA 0x1B7020
54#define GPIO_CTRL 0x1B7024
55
56/* Virtual memory registers */
57#define VMEM_PTPAL 0x1C6300 /* 0x1C6300 + (16 * Chn) */
58#define VMEM_PTPAH 0x1C6304 /* 0x1C6304 + (16 * Chn) */
59#define VMEM_CTL 0x1C7000
60
61/* Transport Registers */
62#define TRANSPORT_ENB 0x1B6000
63#define TRANSPORT_CTL 0x1B6004
64#define TRANSPORT_INT 0x1B6008
65
66/* Audio IO */
67#define AUDIO_IO_AIM 0x1B5000 /* 0x1B5000 + (0x04 * Chn) */
68#define AUDIO_IO_TX_CTL 0x1B5400 /* 0x1B5400 + (0x40 * Chn) */
69#define AUDIO_IO_TX_CSTAT_L 0x1B5408 /* 0x1B5408 + (0x40 * Chn) */
70#define AUDIO_IO_TX_CSTAT_H 0x1B540C /* 0x1B540C + (0x40 * Chn) */
71#define AUDIO_IO_RX_CTL 0x1B5410 /* 0x1B5410 + (0x40 * Chn) */
72#define AUDIO_IO_RX_SRT_CTL 0x1B5420 /* 0x1B5420 + (0x40 * Chn) */
73#define AUDIO_IO_MCLK 0x1B5600
74#define AUDIO_IO_TX_BLRCLK 0x1B5604
75#define AUDIO_IO_RX_BLRCLK 0x1B5608
76
77/* Mixer */
78#define MIXER_AMOPLO 0x130000 /* 0x130000 + (8 * Chn) [4095 : 0] */
79#define MIXER_AMOPHI 0x130004 /* 0x130004 + (8 * Chn) [4095 : 0] */
80#define MIXER_PRING_LO_HI 0x188000 /* 0x188000 + (4 * Chn) [4095 : 0] */
81#define MIXER_PMOPLO 0x138000 /* 0x138000 + (8 * Chn) [4095 : 0] */
82#define MIXER_PMOPHI 0x138004 /* 0x138004 + (8 * Chn) [4095 : 0] */
83#define MIXER_AR_ENABLE 0x19000C
84
85#endif
diff --git a/sound/pci/ctxfi/ctamixer.c b/sound/pci/ctxfi/ctamixer.c
new file mode 100644
index 00000000000..a1db51b3ead
--- /dev/null
+++ b/sound/pci/ctxfi/ctamixer.c
@@ -0,0 +1,488 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File ctamixer.c
9 *
10 * @Brief
11 * This file contains the implementation of the Audio Mixer
12 * resource management object.
13 *
14 * @Author Liu Chun
15 * @Date May 21 2008
16 *
17 */
18
19#include "ctamixer.h"
20#include "cthardware.h"
21#include <linux/slab.h>
22
23#define AMIXER_RESOURCE_NUM 256
24#define SUM_RESOURCE_NUM 256
25
26#define AMIXER_Y_IMMEDIATE 1
27
28#define BLANK_SLOT 4094
29
30static int amixer_master(struct rsc *rsc)
31{
32 rsc->conj = 0;
33 return rsc->idx = container_of(rsc, struct amixer, rsc)->idx[0];
34}
35
36static int amixer_next_conj(struct rsc *rsc)
37{
38 rsc->conj++;
39 return container_of(rsc, struct amixer, rsc)->idx[rsc->conj];
40}
41
42static int amixer_index(const struct rsc *rsc)
43{
44 return container_of(rsc, struct amixer, rsc)->idx[rsc->conj];
45}
46
47static int amixer_output_slot(const struct rsc *rsc)
48{
49 return (amixer_index(rsc) << 4) + 0x4;
50}
51
52static struct rsc_ops amixer_basic_rsc_ops = {
53 .master = amixer_master,
54 .next_conj = amixer_next_conj,
55 .index = amixer_index,
56 .output_slot = amixer_output_slot,
57};
58
59static int amixer_set_input(struct amixer *amixer, struct rsc *rsc)
60{
61 struct hw *hw;
62
63 hw = amixer->rsc.hw;
64 hw->amixer_set_mode(amixer->rsc.ctrl_blk, AMIXER_Y_IMMEDIATE);
65 amixer->input = rsc;
66 if (NULL == rsc)
67 hw->amixer_set_x(amixer->rsc.ctrl_blk, BLANK_SLOT);
68 else
69 hw->amixer_set_x(amixer->rsc.ctrl_blk,
70 rsc->ops->output_slot(rsc));
71
72 return 0;
73}
74
75/* y is a 14-bit immediate constant */
76static int amixer_set_y(struct amixer *amixer, unsigned int y)
77{
78 struct hw *hw;
79
80 hw = amixer->rsc.hw;
81 hw->amixer_set_y(amixer->rsc.ctrl_blk, y);
82
83 return 0;
84}
85
86static int amixer_set_invalid_squash(struct amixer *amixer, unsigned int iv)
87{
88 struct hw *hw;
89
90 hw = amixer->rsc.hw;
91 hw->amixer_set_iv(amixer->rsc.ctrl_blk, iv);
92
93 return 0;
94}
95
96static int amixer_set_sum(struct amixer *amixer, struct sum *sum)
97{
98 struct hw *hw;
99
100 hw = amixer->rsc.hw;
101 amixer->sum = sum;
102 if (NULL == sum) {
103 hw->amixer_set_se(amixer->rsc.ctrl_blk, 0);
104 } else {
105 hw->amixer_set_se(amixer->rsc.ctrl_blk, 1);
106 hw->amixer_set_sadr(amixer->rsc.ctrl_blk,
107 sum->rsc.ops->index(&sum->rsc));
108 }
109
110 return 0;
111}
112
113static int amixer_commit_write(struct amixer *amixer)
114{
115 struct hw *hw;
116 unsigned int index;
117 int i;
118 struct rsc *input;
119 struct sum *sum;
120
121 hw = amixer->rsc.hw;
122 input = amixer->input;
123 sum = amixer->sum;
124
125 /* Program master and conjugate resources */
126 amixer->rsc.ops->master(&amixer->rsc);
127 if (NULL != input)
128 input->ops->master(input);
129
130 if (NULL != sum)
131 sum->rsc.ops->master(&sum->rsc);
132
133 for (i = 0; i < amixer->rsc.msr; i++) {
134 hw->amixer_set_dirty_all(amixer->rsc.ctrl_blk);
135 if (NULL != input) {
136 hw->amixer_set_x(amixer->rsc.ctrl_blk,
137 input->ops->output_slot(input));
138 input->ops->next_conj(input);
139 }
140 if (NULL != sum) {
141 hw->amixer_set_sadr(amixer->rsc.ctrl_blk,
142 sum->rsc.ops->index(&sum->rsc));
143 sum->rsc.ops->next_conj(&sum->rsc);
144 }
145 index = amixer->rsc.ops->output_slot(&amixer->rsc);
146 hw->amixer_commit_write(hw, index, amixer->rsc.ctrl_blk);
147 amixer->rsc.ops->next_conj(&amixer->rsc);
148 }
149 amixer->rsc.ops->master(&amixer->rsc);
150 if (NULL != input)
151 input->ops->master(input);
152
153 if (NULL != sum)
154 sum->rsc.ops->master(&sum->rsc);
155
156 return 0;
157}
158
159static int amixer_commit_raw_write(struct amixer *amixer)
160{
161 struct hw *hw;
162 unsigned int index;
163
164 hw = amixer->rsc.hw;
165 index = amixer->rsc.ops->output_slot(&amixer->rsc);
166 hw->amixer_commit_write(hw, index, amixer->rsc.ctrl_blk);
167
168 return 0;
169}
170
171static int amixer_get_y(struct amixer *amixer)
172{
173 struct hw *hw;
174
175 hw = amixer->rsc.hw;
176 return hw->amixer_get_y(amixer->rsc.ctrl_blk);
177}
178
179static int amixer_setup(struct amixer *amixer, struct rsc *input,
180 unsigned int scale, struct sum *sum)
181{
182 amixer_set_input(amixer, input);
183 amixer_set_y(amixer, scale);
184 amixer_set_sum(amixer, sum);
185 amixer_commit_write(amixer);
186 return 0;
187}
188
189static struct amixer_rsc_ops amixer_ops = {
190 .set_input = amixer_set_input,
191 .set_invalid_squash = amixer_set_invalid_squash,
192 .set_scale = amixer_set_y,
193 .set_sum = amixer_set_sum,
194 .commit_write = amixer_commit_write,
195 .commit_raw_write = amixer_commit_raw_write,
196 .setup = amixer_setup,
197 .get_scale = amixer_get_y,
198};
199
200static int amixer_rsc_init(struct amixer *amixer,
201 const struct amixer_desc *desc,
202 struct amixer_mgr *mgr)
203{
204 int err;
205
206 err = rsc_init(&amixer->rsc, amixer->idx[0],
207 AMIXER, desc->msr, mgr->mgr.hw);
208 if (err)
209 return err;
210
211 /* Set amixer specific operations */
212 amixer->rsc.ops = &amixer_basic_rsc_ops;
213 amixer->ops = &amixer_ops;
214 amixer->input = NULL;
215 amixer->sum = NULL;
216
217 amixer_setup(amixer, NULL, 0, NULL);
218
219 return 0;
220}
221
222static int amixer_rsc_uninit(struct amixer *amixer)
223{
224 amixer_setup(amixer, NULL, 0, NULL);
225 rsc_uninit(&amixer->rsc);
226 amixer->ops = NULL;
227 amixer->input = NULL;
228 amixer->sum = NULL;
229 return 0;
230}
231
232static int get_amixer_rsc(struct amixer_mgr *mgr,
233 const struct amixer_desc *desc,
234 struct amixer **ramixer)
235{
236 int err, i;
237 unsigned int idx;
238 struct amixer *amixer;
239 unsigned long flags;
240
241 *ramixer = NULL;
242
243 /* Allocate mem for amixer resource */
244 amixer = kzalloc(sizeof(*amixer), GFP_KERNEL);
245 if (NULL == amixer) {
246 err = -ENOMEM;
247 return err;
248 }
249
250 /* Check whether there are sufficient
251 * amixer resources to meet request. */
252 spin_lock_irqsave(&mgr->mgr_lock, flags);
253 for (i = 0; i < desc->msr; i++) {
254 err = mgr_get_resource(&mgr->mgr, 1, &idx);
255 if (err)
256 break;
257
258 amixer->idx[i] = idx;
259 }
260 spin_unlock_irqrestore(&mgr->mgr_lock, flags);
261 if (err) {
262 printk(KERN_ERR "ctxfi: Can't meet AMIXER resource request!\n");
263 goto error;
264 }
265
266 err = amixer_rsc_init(amixer, desc, mgr);
267 if (err)
268 goto error;
269
270 *ramixer = amixer;
271
272 return 0;
273
274error:
275 spin_lock_irqsave(&mgr->mgr_lock, flags);
276 for (i--; i >= 0; i--)
277 mgr_put_resource(&mgr->mgr, 1, amixer->idx[i]);
278
279 spin_unlock_irqrestore(&mgr->mgr_lock, flags);
280 kfree(amixer);
281 return err;
282}
283
284static int put_amixer_rsc(struct amixer_mgr *mgr, struct amixer *amixer)
285{
286 unsigned long flags;
287 int i;
288
289 spin_lock_irqsave(&mgr->mgr_lock, flags);
290 for (i = 0; i < amixer->rsc.msr; i++)
291 mgr_put_resource(&mgr->mgr, 1, amixer->idx[i]);
292
293 spin_unlock_irqrestore(&mgr->mgr_lock, flags);
294 amixer_rsc_uninit(amixer);
295 kfree(amixer);
296
297 return 0;
298}
299
300int amixer_mgr_create(void *hw, struct amixer_mgr **ramixer_mgr)
301{
302 int err;
303 struct amixer_mgr *amixer_mgr;
304
305 *ramixer_mgr = NULL;
306 amixer_mgr = kzalloc(sizeof(*amixer_mgr), GFP_KERNEL);
307 if (NULL == amixer_mgr)
308 return -ENOMEM;
309
310 err = rsc_mgr_init(&amixer_mgr->mgr, AMIXER, AMIXER_RESOURCE_NUM, hw);
311 if (err)
312 goto error;
313
314 spin_lock_init(&amixer_mgr->mgr_lock);
315
316 amixer_mgr->get_amixer = get_amixer_rsc;
317 amixer_mgr->put_amixer = put_amixer_rsc;
318
319 *ramixer_mgr = amixer_mgr;
320
321 return 0;
322
323error:
324 kfree(amixer_mgr);
325 return err;
326}
327
328int amixer_mgr_destroy(struct amixer_mgr *amixer_mgr)
329{
330 rsc_mgr_uninit(&amixer_mgr->mgr);
331 kfree(amixer_mgr);
332 return 0;
333}
334
335/* SUM resource management */
336
337static int sum_master(struct rsc *rsc)
338{
339 rsc->conj = 0;
340 return rsc->idx = container_of(rsc, struct sum, rsc)->idx[0];
341}
342
343static int sum_next_conj(struct rsc *rsc)
344{
345 rsc->conj++;
346 return container_of(rsc, struct sum, rsc)->idx[rsc->conj];
347}
348
349static int sum_index(const struct rsc *rsc)
350{
351 return container_of(rsc, struct sum, rsc)->idx[rsc->conj];
352}
353
354static int sum_output_slot(const struct rsc *rsc)
355{
356 return (sum_index(rsc) << 4) + 0xc;
357}
358
359static struct rsc_ops sum_basic_rsc_ops = {
360 .master = sum_master,
361 .next_conj = sum_next_conj,
362 .index = sum_index,
363 .output_slot = sum_output_slot,
364};
365
366static int sum_rsc_init(struct sum *sum,
367 const struct sum_desc *desc,
368 struct sum_mgr *mgr)
369{
370 int err;
371
372 err = rsc_init(&sum->rsc, sum->idx[0], SUM, desc->msr, mgr->mgr.hw);
373 if (err)
374 return err;
375
376 sum->rsc.ops = &sum_basic_rsc_ops;
377
378 return 0;
379}
380
381static int sum_rsc_uninit(struct sum *sum)
382{
383 rsc_uninit(&sum->rsc);
384 return 0;
385}
386
387static int get_sum_rsc(struct sum_mgr *mgr,
388 const struct sum_desc *desc,
389 struct sum **rsum)
390{
391 int err, i;
392 unsigned int idx;
393 struct sum *sum;
394 unsigned long flags;
395
396 *rsum = NULL;
397
398 /* Allocate mem for sum resource */
399 sum = kzalloc(sizeof(*sum), GFP_KERNEL);
400 if (NULL == sum) {
401 err = -ENOMEM;
402 return err;
403 }
404
405 /* Check whether there are sufficient sum resources to meet request. */
406 spin_lock_irqsave(&mgr->mgr_lock, flags);
407 for (i = 0; i < desc->msr; i++) {
408 err = mgr_get_resource(&mgr->mgr, 1, &idx);
409 if (err)
410 break;
411
412 sum->idx[i] = idx;
413 }
414 spin_unlock_irqrestore(&mgr->mgr_lock, flags);
415 if (err) {
416 printk(KERN_ERR "ctxfi: Can't meet SUM resource request!\n");
417 goto error;
418 }
419
420 err = sum_rsc_init(sum, desc, mgr);
421 if (err)
422 goto error;
423
424 *rsum = sum;
425
426 return 0;
427
428error:
429 spin_lock_irqsave(&mgr->mgr_lock, flags);
430 for (i--; i >= 0; i--)
431 mgr_put_resource(&mgr->mgr, 1, sum->idx[i]);
432
433 spin_unlock_irqrestore(&mgr->mgr_lock, flags);
434 kfree(sum);
435 return err;
436}
437
438static int put_sum_rsc(struct sum_mgr *mgr, struct sum *sum)
439{
440 unsigned long flags;
441 int i;
442
443 spin_lock_irqsave(&mgr->mgr_lock, flags);
444 for (i = 0; i < sum->rsc.msr; i++)
445 mgr_put_resource(&mgr->mgr, 1, sum->idx[i]);
446
447 spin_unlock_irqrestore(&mgr->mgr_lock, flags);
448 sum_rsc_uninit(sum);
449 kfree(sum);
450
451 return 0;
452}
453
454int sum_mgr_create(void *hw, struct sum_mgr **rsum_mgr)
455{
456 int err;
457 struct sum_mgr *sum_mgr;
458
459 *rsum_mgr = NULL;
460 sum_mgr = kzalloc(sizeof(*sum_mgr), GFP_KERNEL);
461 if (NULL == sum_mgr)
462 return -ENOMEM;
463
464 err = rsc_mgr_init(&sum_mgr->mgr, SUM, SUM_RESOURCE_NUM, hw);
465 if (err)
466 goto error;
467
468 spin_lock_init(&sum_mgr->mgr_lock);
469
470 sum_mgr->get_sum = get_sum_rsc;
471 sum_mgr->put_sum = put_sum_rsc;
472
473 *rsum_mgr = sum_mgr;
474
475 return 0;
476
477error:
478 kfree(sum_mgr);
479 return err;
480}
481
482int sum_mgr_destroy(struct sum_mgr *sum_mgr)
483{
484 rsc_mgr_uninit(&sum_mgr->mgr);
485 kfree(sum_mgr);
486 return 0;
487}
488
diff --git a/sound/pci/ctxfi/ctamixer.h b/sound/pci/ctxfi/ctamixer.h
new file mode 100644
index 00000000000..cc49e5ab475
--- /dev/null
+++ b/sound/pci/ctxfi/ctamixer.h
@@ -0,0 +1,96 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File ctamixer.h
9 *
10 * @Brief
11 * This file contains the definition of the Audio Mixer
12 * resource management object.
13 *
14 * @Author Liu Chun
15 * @Date May 21 2008
16 *
17 */
18
19#ifndef CTAMIXER_H
20#define CTAMIXER_H
21
22#include "ctresource.h"
23#include <linux/spinlock.h>
24
25/* Define the descriptor of a summation node resource */
26struct sum {
27 struct rsc rsc; /* Basic resource info */
28 unsigned char idx[8];
29};
30
31/* Define sum resource request description info */
32struct sum_desc {
33 unsigned int msr;
34};
35
36struct sum_mgr {
37 struct rsc_mgr mgr; /* Basic resource manager info */
38 spinlock_t mgr_lock;
39
40 /* request one sum resource */
41 int (*get_sum)(struct sum_mgr *mgr,
42 const struct sum_desc *desc, struct sum **rsum);
43 /* return one sum resource */
44 int (*put_sum)(struct sum_mgr *mgr, struct sum *sum);
45};
46
47/* Constructor and destructor of daio resource manager */
48int sum_mgr_create(void *hw, struct sum_mgr **rsum_mgr);
49int sum_mgr_destroy(struct sum_mgr *sum_mgr);
50
51/* Define the descriptor of a amixer resource */
52struct amixer_rsc_ops;
53
54struct amixer {
55 struct rsc rsc; /* Basic resource info */
56 unsigned char idx[8];
57 struct rsc *input; /* pointer to a resource acting as source */
58 struct sum *sum; /* Put amixer output to this summation node */
59 struct amixer_rsc_ops *ops; /* AMixer specific operations */
60};
61
62struct amixer_rsc_ops {
63 int (*set_input)(struct amixer *amixer, struct rsc *rsc);
64 int (*set_scale)(struct amixer *amixer, unsigned int scale);
65 int (*set_invalid_squash)(struct amixer *amixer, unsigned int iv);
66 int (*set_sum)(struct amixer *amixer, struct sum *sum);
67 int (*commit_write)(struct amixer *amixer);
68 /* Only for interleaved recording */
69 int (*commit_raw_write)(struct amixer *amixer);
70 int (*setup)(struct amixer *amixer, struct rsc *input,
71 unsigned int scale, struct sum *sum);
72 int (*get_scale)(struct amixer *amixer);
73};
74
75/* Define amixer resource request description info */
76struct amixer_desc {
77 unsigned int msr;
78};
79
80struct amixer_mgr {
81 struct rsc_mgr mgr; /* Basic resource manager info */
82 spinlock_t mgr_lock;
83
84 /* request one amixer resource */
85 int (*get_amixer)(struct amixer_mgr *mgr,
86 const struct amixer_desc *desc,
87 struct amixer **ramixer);
88 /* return one amixer resource */
89 int (*put_amixer)(struct amixer_mgr *mgr, struct amixer *amixer);
90};
91
92/* Constructor and destructor of amixer resource manager */
93int amixer_mgr_create(void *hw, struct amixer_mgr **ramixer_mgr);
94int amixer_mgr_destroy(struct amixer_mgr *amixer_mgr);
95
96#endif /* CTAMIXER_H */
diff --git a/sound/pci/ctxfi/ctatc.c b/sound/pci/ctxfi/ctatc.c
new file mode 100644
index 00000000000..80fb2baed7a
--- /dev/null
+++ b/sound/pci/ctxfi/ctatc.c
@@ -0,0 +1,1619 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File ctatc.c
9 *
10 * @Brief
11 * This file contains the implementation of the device resource management
12 * object.
13 *
14 * @Author Liu Chun
15 * @Date Mar 28 2008
16 */
17
18#include "ctatc.h"
19#include "ctpcm.h"
20#include "ctmixer.h"
21#include "cthardware.h"
22#include "ctsrc.h"
23#include "ctamixer.h"
24#include "ctdaio.h"
25#include "cttimer.h"
26#include <linux/delay.h>
27#include <sound/pcm.h>
28#include <sound/control.h>
29#include <sound/asoundef.h>
30
31#define MONO_SUM_SCALE 0x19a8 /* 2^(-0.5) in 14-bit floating format */
32#define DAIONUM 7
33#define MAX_MULTI_CHN 8
34
35#define IEC958_DEFAULT_CON ((IEC958_AES0_NONAUDIO \
36 | IEC958_AES0_CON_NOT_COPYRIGHT) \
37 | ((IEC958_AES1_CON_MIXER \
38 | IEC958_AES1_CON_ORIGINAL) << 8) \
39 | (0x10 << 16) \
40 | ((IEC958_AES3_CON_FS_48000) << 24))
41
42static struct snd_pci_quirk __devinitdata subsys_20k1_list[] = {
43 SND_PCI_QUIRK(PCI_VENDOR_ID_CREATIVE, 0x0022, "SB055x", CTSB055X),
44 SND_PCI_QUIRK(PCI_VENDOR_ID_CREATIVE, 0x002f, "SB055x", CTSB055X),
45 SND_PCI_QUIRK(PCI_VENDOR_ID_CREATIVE, 0x0029, "SB073x", CTSB073X),
46 SND_PCI_QUIRK(PCI_VENDOR_ID_CREATIVE, 0x0031, "SB073x", CTSB073X),
47 SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_CREATIVE, 0xf000, 0x6000,
48 "UAA", CTUAA),
49 SND_PCI_QUIRK_VENDOR(PCI_VENDOR_ID_CREATIVE,
50 "Unknown", CT20K1_UNKNOWN),
51 { } /* terminator */
52};
53
54static struct snd_pci_quirk __devinitdata subsys_20k2_list[] = {
55 SND_PCI_QUIRK(PCI_VENDOR_ID_CREATIVE, PCI_SUBDEVICE_ID_CREATIVE_SB0760,
56 "SB0760", CTSB0760),
57 SND_PCI_QUIRK(PCI_VENDOR_ID_CREATIVE, PCI_SUBDEVICE_ID_CREATIVE_SB08801,
58 "SB0880", CTSB0880),
59 SND_PCI_QUIRK(PCI_VENDOR_ID_CREATIVE, PCI_SUBDEVICE_ID_CREATIVE_SB08802,
60 "SB0880", CTSB0880),
61 SND_PCI_QUIRK(PCI_VENDOR_ID_CREATIVE, PCI_SUBDEVICE_ID_CREATIVE_SB08803,
62 "SB0880", CTSB0880),
63 SND_PCI_QUIRK_MASK(PCI_VENDOR_ID_CREATIVE, 0xf000,
64 PCI_SUBDEVICE_ID_CREATIVE_HENDRIX, "HENDRIX",
65 CTHENDRIX),
66 { } /* terminator */
67};
68
69static const char *ct_subsys_name[NUM_CTCARDS] = {
70 [CTSB055X] = "SB055x",
71 [CTSB073X] = "SB073x",
72 [CTSB0760] = "SB076x",
73 [CTUAA] = "UAA",
74 [CT20K1_UNKNOWN] = "Unknown",
75 [CTHENDRIX] = "Hendrix",
76 [CTSB0880] = "SB0880",
77};
78
79static struct {
80 int (*create)(struct ct_atc *atc,
81 enum CTALSADEVS device, const char *device_name);
82 int (*destroy)(void *alsa_dev);
83 const char *public_name;
84} alsa_dev_funcs[NUM_CTALSADEVS] = {
85 [FRONT] = { .create = ct_alsa_pcm_create,
86 .destroy = NULL,
87 .public_name = "Front/WaveIn"},
88 [SURROUND] = { .create = ct_alsa_pcm_create,
89 .destroy = NULL,
90 .public_name = "Surround"},
91 [CLFE] = { .create = ct_alsa_pcm_create,
92 .destroy = NULL,
93 .public_name = "Center/LFE"},
94 [SIDE] = { .create = ct_alsa_pcm_create,
95 .destroy = NULL,
96 .public_name = "Side"},
97 [IEC958] = { .create = ct_alsa_pcm_create,
98 .destroy = NULL,
99 .public_name = "IEC958 Non-audio"},
100
101 [MIXER] = { .create = ct_alsa_mix_create,
102 .destroy = NULL,
103 .public_name = "Mixer"}
104};
105
106typedef int (*create_t)(void *, void **);
107typedef int (*destroy_t)(void *);
108
109static struct {
110 int (*create)(void *hw, void **rmgr);
111 int (*destroy)(void *mgr);
112} rsc_mgr_funcs[NUM_RSCTYP] = {
113 [SRC] = { .create = (create_t)src_mgr_create,
114 .destroy = (destroy_t)src_mgr_destroy },
115 [SRCIMP] = { .create = (create_t)srcimp_mgr_create,
116 .destroy = (destroy_t)srcimp_mgr_destroy },
117 [AMIXER] = { .create = (create_t)amixer_mgr_create,
118 .destroy = (destroy_t)amixer_mgr_destroy },
119 [SUM] = { .create = (create_t)sum_mgr_create,
120 .destroy = (destroy_t)sum_mgr_destroy },
121 [DAIO] = { .create = (create_t)daio_mgr_create,
122 .destroy = (destroy_t)daio_mgr_destroy }
123};
124
125static int
126atc_pcm_release_resources(struct ct_atc *atc, struct ct_atc_pcm *apcm);
127
128/* *
129 * Only mono and interleaved modes are supported now.
130 * Always allocates a contiguous channel block.
131 * */
132
133static int ct_map_audio_buffer(struct ct_atc *atc, struct ct_atc_pcm *apcm)
134{
135 struct snd_pcm_runtime *runtime;
136 struct ct_vm *vm;
137
138 if (NULL == apcm->substream)
139 return 0;
140
141 runtime = apcm->substream->runtime;
142 vm = atc->vm;
143
144 apcm->vm_block = vm->map(vm, apcm->substream, runtime->dma_bytes);
145
146 if (NULL == apcm->vm_block)
147 return -ENOENT;
148
149 return 0;
150}
151
152static void ct_unmap_audio_buffer(struct ct_atc *atc, struct ct_atc_pcm *apcm)
153{
154 struct ct_vm *vm;
155
156 if (NULL == apcm->vm_block)
157 return;
158
159 vm = atc->vm;
160
161 vm->unmap(vm, apcm->vm_block);
162
163 apcm->vm_block = NULL;
164}
165
166static unsigned long atc_get_ptp_phys(struct ct_atc *atc, int index)
167{
168 struct ct_vm *vm;
169 void *kvirt_addr;
170 unsigned long phys_addr;
171
172 vm = atc->vm;
173 kvirt_addr = vm->get_ptp_virt(vm, index);
174 if (kvirt_addr == NULL)
175 phys_addr = (~0UL);
176 else
177 phys_addr = virt_to_phys(kvirt_addr);
178
179 return phys_addr;
180}
181
182static unsigned int convert_format(snd_pcm_format_t snd_format)
183{
184 switch (snd_format) {
185 case SNDRV_PCM_FORMAT_U8:
186 return SRC_SF_U8;
187 case SNDRV_PCM_FORMAT_S16_LE:
188 return SRC_SF_S16;
189 case SNDRV_PCM_FORMAT_S24_3LE:
190 return SRC_SF_S24;
191 case SNDRV_PCM_FORMAT_S32_LE:
192 return SRC_SF_S32;
193 case SNDRV_PCM_FORMAT_FLOAT_LE:
194 return SRC_SF_F32;
195 default:
196 printk(KERN_ERR "ctxfi: not recognized snd format is %d \n",
197 snd_format);
198 return SRC_SF_S16;
199 }
200}
201
202static unsigned int
203atc_get_pitch(unsigned int input_rate, unsigned int output_rate)
204{
205 unsigned int pitch;
206 int b;
207
208 /* get pitch and convert to fixed-point 8.24 format. */
209 pitch = (input_rate / output_rate) << 24;
210 input_rate %= output_rate;
211 input_rate /= 100;
212 output_rate /= 100;
213 for (b = 31; ((b >= 0) && !(input_rate >> b)); )
214 b--;
215
216 if (b >= 0) {
217 input_rate <<= (31 - b);
218 input_rate /= output_rate;
219 b = 24 - (31 - b);
220 if (b >= 0)
221 input_rate <<= b;
222 else
223 input_rate >>= -b;
224
225 pitch |= input_rate;
226 }
227
228 return pitch;
229}
230
231static int select_rom(unsigned int pitch)
232{
233 if ((pitch > 0x00428f5c) && (pitch < 0x01b851ec)) {
234 /* 0.26 <= pitch <= 1.72 */
235 return 1;
236 } else if ((0x01d66666 == pitch) || (0x01d66667 == pitch)) {
237 /* pitch == 1.8375 */
238 return 2;
239 } else if (0x02000000 == pitch) {
240 /* pitch == 2 */
241 return 3;
242 } else if ((pitch >= 0x0) && (pitch <= 0x08000000)) {
243 /* 0 <= pitch <= 8 */
244 return 0;
245 } else {
246 return -ENOENT;
247 }
248}
249
250static int atc_pcm_playback_prepare(struct ct_atc *atc, struct ct_atc_pcm *apcm)
251{
252 struct src_mgr *src_mgr = atc->rsc_mgrs[SRC];
253 struct amixer_mgr *amixer_mgr = atc->rsc_mgrs[AMIXER];
254 struct src_desc desc = {0};
255 struct amixer_desc mix_dsc = {0};
256 struct src *src;
257 struct amixer *amixer;
258 int err;
259 int n_amixer = apcm->substream->runtime->channels, i = 0;
260 int device = apcm->substream->pcm->device;
261 unsigned int pitch;
262 unsigned long flags;
263
264 if (NULL != apcm->src) {
265 /* Prepared pcm playback */
266 return 0;
267 }
268
269 /* first release old resources */
270 atc->pcm_release_resources(atc, apcm);
271
272 /* Get SRC resource */
273 desc.multi = apcm->substream->runtime->channels;
274 desc.msr = atc->msr;
275 desc.mode = MEMRD;
276 err = src_mgr->get_src(src_mgr, &desc, (struct src **)&apcm->src);
277 if (err)
278 goto error1;
279
280 pitch = atc_get_pitch(apcm->substream->runtime->rate,
281 (atc->rsr * atc->msr));
282 src = apcm->src;
283 src->ops->set_pitch(src, pitch);
284 src->ops->set_rom(src, select_rom(pitch));
285 src->ops->set_sf(src, convert_format(apcm->substream->runtime->format));
286 src->ops->set_pm(src, (src->ops->next_interleave(src) != NULL));
287
288 /* Get AMIXER resource */
289 n_amixer = (n_amixer < 2) ? 2 : n_amixer;
290 apcm->amixers = kzalloc(sizeof(void *)*n_amixer, GFP_KERNEL);
291 if (NULL == apcm->amixers) {
292 err = -ENOMEM;
293 goto error1;
294 }
295 mix_dsc.msr = atc->msr;
296 for (i = 0, apcm->n_amixer = 0; i < n_amixer; i++) {
297 err = amixer_mgr->get_amixer(amixer_mgr, &mix_dsc,
298 (struct amixer **)&apcm->amixers[i]);
299 if (err)
300 goto error1;
301
302 apcm->n_amixer++;
303 }
304
305 /* Set up device virtual mem map */
306 err = ct_map_audio_buffer(atc, apcm);
307 if (err < 0)
308 goto error1;
309
310 /* Connect resources */
311 src = apcm->src;
312 for (i = 0; i < n_amixer; i++) {
313 amixer = apcm->amixers[i];
314 spin_lock_irqsave(&atc->atc_lock, flags);
315 amixer->ops->setup(amixer, &src->rsc,
316 INIT_VOL, atc->pcm[i+device*2]);
317 spin_unlock_irqrestore(&atc->atc_lock, flags);
318 src = src->ops->next_interleave(src);
319 if (NULL == src)
320 src = apcm->src;
321 }
322
323 ct_timer_prepare(apcm->timer);
324
325 return 0;
326
327error1:
328 atc_pcm_release_resources(atc, apcm);
329 return err;
330}
331
332static int
333atc_pcm_release_resources(struct ct_atc *atc, struct ct_atc_pcm *apcm)
334{
335 struct src_mgr *src_mgr = atc->rsc_mgrs[SRC];
336 struct srcimp_mgr *srcimp_mgr = atc->rsc_mgrs[SRCIMP];
337 struct amixer_mgr *amixer_mgr = atc->rsc_mgrs[AMIXER];
338 struct sum_mgr *sum_mgr = atc->rsc_mgrs[SUM];
339 struct srcimp *srcimp;
340 int i;
341
342 if (NULL != apcm->srcimps) {
343 for (i = 0; i < apcm->n_srcimp; i++) {
344 srcimp = apcm->srcimps[i];
345 srcimp->ops->unmap(srcimp);
346 srcimp_mgr->put_srcimp(srcimp_mgr, srcimp);
347 apcm->srcimps[i] = NULL;
348 }
349 kfree(apcm->srcimps);
350 apcm->srcimps = NULL;
351 }
352
353 if (NULL != apcm->srccs) {
354 for (i = 0; i < apcm->n_srcc; i++) {
355 src_mgr->put_src(src_mgr, apcm->srccs[i]);
356 apcm->srccs[i] = NULL;
357 }
358 kfree(apcm->srccs);
359 apcm->srccs = NULL;
360 }
361
362 if (NULL != apcm->amixers) {
363 for (i = 0; i < apcm->n_amixer; i++) {
364 amixer_mgr->put_amixer(amixer_mgr, apcm->amixers[i]);
365 apcm->amixers[i] = NULL;
366 }
367 kfree(apcm->amixers);
368 apcm->amixers = NULL;
369 }
370
371 if (NULL != apcm->mono) {
372 sum_mgr->put_sum(sum_mgr, apcm->mono);
373 apcm->mono = NULL;
374 }
375
376 if (NULL != apcm->src) {
377 src_mgr->put_src(src_mgr, apcm->src);
378 apcm->src = NULL;
379 }
380
381 if (NULL != apcm->vm_block) {
382 /* Undo device virtual mem map */
383 ct_unmap_audio_buffer(atc, apcm);
384 apcm->vm_block = NULL;
385 }
386
387 return 0;
388}
389
390static int atc_pcm_playback_start(struct ct_atc *atc, struct ct_atc_pcm *apcm)
391{
392 unsigned int max_cisz;
393 struct src *src = apcm->src;
394
395 if (apcm->started)
396 return 0;
397 apcm->started = 1;
398
399 max_cisz = src->multi * src->rsc.msr;
400 max_cisz = 0x80 * (max_cisz < 8 ? max_cisz : 8);
401
402 src->ops->set_sa(src, apcm->vm_block->addr);
403 src->ops->set_la(src, apcm->vm_block->addr + apcm->vm_block->size);
404 src->ops->set_ca(src, apcm->vm_block->addr + max_cisz);
405 src->ops->set_cisz(src, max_cisz);
406
407 src->ops->set_bm(src, 1);
408 src->ops->set_state(src, SRC_STATE_INIT);
409 src->ops->commit_write(src);
410
411 ct_timer_start(apcm->timer);
412 return 0;
413}
414
415static int atc_pcm_stop(struct ct_atc *atc, struct ct_atc_pcm *apcm)
416{
417 struct src *src;
418 int i;
419
420 ct_timer_stop(apcm->timer);
421
422 src = apcm->src;
423 src->ops->set_bm(src, 0);
424 src->ops->set_state(src, SRC_STATE_OFF);
425 src->ops->commit_write(src);
426
427 if (NULL != apcm->srccs) {
428 for (i = 0; i < apcm->n_srcc; i++) {
429 src = apcm->srccs[i];
430 src->ops->set_bm(src, 0);
431 src->ops->set_state(src, SRC_STATE_OFF);
432 src->ops->commit_write(src);
433 }
434 }
435
436 apcm->started = 0;
437
438 return 0;
439}
440
441static int
442atc_pcm_playback_position(struct ct_atc *atc, struct ct_atc_pcm *apcm)
443{
444 struct src *src = apcm->src;
445 u32 size, max_cisz;
446 int position;
447
448 if (!src)
449 return 0;
450 position = src->ops->get_ca(src);
451
452 size = apcm->vm_block->size;
453 max_cisz = src->multi * src->rsc.msr;
454 max_cisz = 128 * (max_cisz < 8 ? max_cisz : 8);
455
456 return (position + size - max_cisz - apcm->vm_block->addr) % size;
457}
458
459struct src_node_conf_t {
460 unsigned int pitch;
461 unsigned int msr:8;
462 unsigned int mix_msr:8;
463 unsigned int imp_msr:8;
464 unsigned int vo:1;
465};
466
467static void setup_src_node_conf(struct ct_atc *atc, struct ct_atc_pcm *apcm,
468 struct src_node_conf_t *conf, int *n_srcc)
469{
470 unsigned int pitch;
471
472 /* get pitch and convert to fixed-point 8.24 format. */
473 pitch = atc_get_pitch((atc->rsr * atc->msr),
474 apcm->substream->runtime->rate);
475 *n_srcc = 0;
476
477 if (1 == atc->msr) {
478 *n_srcc = apcm->substream->runtime->channels;
479 conf[0].pitch = pitch;
480 conf[0].mix_msr = conf[0].imp_msr = conf[0].msr = 1;
481 conf[0].vo = 1;
482 } else if (2 == atc->msr) {
483 if (0x8000000 < pitch) {
484 /* Need two-stage SRCs, SRCIMPs and
485 * AMIXERs for converting format */
486 conf[0].pitch = (atc->msr << 24);
487 conf[0].msr = conf[0].mix_msr = 1;
488 conf[0].imp_msr = atc->msr;
489 conf[0].vo = 0;
490 conf[1].pitch = atc_get_pitch(atc->rsr,
491 apcm->substream->runtime->rate);
492 conf[1].msr = conf[1].mix_msr = conf[1].imp_msr = 1;
493 conf[1].vo = 1;
494 *n_srcc = apcm->substream->runtime->channels * 2;
495 } else if (0x1000000 < pitch) {
496 /* Need one-stage SRCs, SRCIMPs and
497 * AMIXERs for converting format */
498 conf[0].pitch = pitch;
499 conf[0].msr = conf[0].mix_msr
500 = conf[0].imp_msr = atc->msr;
501 conf[0].vo = 1;
502 *n_srcc = apcm->substream->runtime->channels;
503 }
504 }
505}
506
507static int
508atc_pcm_capture_get_resources(struct ct_atc *atc, struct ct_atc_pcm *apcm)
509{
510 struct src_mgr *src_mgr = atc->rsc_mgrs[SRC];
511 struct srcimp_mgr *srcimp_mgr = atc->rsc_mgrs[SRCIMP];
512 struct amixer_mgr *amixer_mgr = atc->rsc_mgrs[AMIXER];
513 struct sum_mgr *sum_mgr = atc->rsc_mgrs[SUM];
514 struct src_desc src_dsc = {0};
515 struct src *src;
516 struct srcimp_desc srcimp_dsc = {0};
517 struct srcimp *srcimp;
518 struct amixer_desc mix_dsc = {0};
519 struct sum_desc sum_dsc = {0};
520 unsigned int pitch;
521 int multi, err, i;
522 int n_srcimp, n_amixer, n_srcc, n_sum;
523 struct src_node_conf_t src_node_conf[2] = {{0} };
524
525 /* first release old resources */
526 atc_pcm_release_resources(atc, apcm);
527
528 /* The numbers of converting SRCs and SRCIMPs should be determined
529 * by pitch value. */
530
531 multi = apcm->substream->runtime->channels;
532
533 /* get pitch and convert to fixed-point 8.24 format. */
534 pitch = atc_get_pitch((atc->rsr * atc->msr),
535 apcm->substream->runtime->rate);
536
537 setup_src_node_conf(atc, apcm, src_node_conf, &n_srcc);
538 n_sum = (1 == multi) ? 1 : 0;
539 n_amixer = n_sum * 2 + n_srcc;
540 n_srcimp = n_srcc;
541 if ((multi > 1) && (0x8000000 >= pitch)) {
542 /* Need extra AMIXERs and SRCIMPs for special treatment
543 * of interleaved recording of conjugate channels */
544 n_amixer += multi * atc->msr;
545 n_srcimp += multi * atc->msr;
546 } else {
547 n_srcimp += multi;
548 }
549
550 if (n_srcc) {
551 apcm->srccs = kzalloc(sizeof(void *)*n_srcc, GFP_KERNEL);
552 if (NULL == apcm->srccs)
553 return -ENOMEM;
554 }
555 if (n_amixer) {
556 apcm->amixers = kzalloc(sizeof(void *)*n_amixer, GFP_KERNEL);
557 if (NULL == apcm->amixers) {
558 err = -ENOMEM;
559 goto error1;
560 }
561 }
562 apcm->srcimps = kzalloc(sizeof(void *)*n_srcimp, GFP_KERNEL);
563 if (NULL == apcm->srcimps) {
564 err = -ENOMEM;
565 goto error1;
566 }
567
568 /* Allocate SRCs for sample rate conversion if needed */
569 src_dsc.multi = 1;
570 src_dsc.mode = ARCRW;
571 for (i = 0, apcm->n_srcc = 0; i < n_srcc; i++) {
572 src_dsc.msr = src_node_conf[i/multi].msr;
573 err = src_mgr->get_src(src_mgr, &src_dsc,
574 (struct src **)&apcm->srccs[i]);
575 if (err)
576 goto error1;
577
578 src = apcm->srccs[i];
579 pitch = src_node_conf[i/multi].pitch;
580 src->ops->set_pitch(src, pitch);
581 src->ops->set_rom(src, select_rom(pitch));
582 src->ops->set_vo(src, src_node_conf[i/multi].vo);
583
584 apcm->n_srcc++;
585 }
586
587 /* Allocate AMIXERs for routing SRCs of conversion if needed */
588 for (i = 0, apcm->n_amixer = 0; i < n_amixer; i++) {
589 if (i < (n_sum*2))
590 mix_dsc.msr = atc->msr;
591 else if (i < (n_sum*2+n_srcc))
592 mix_dsc.msr = src_node_conf[(i-n_sum*2)/multi].mix_msr;
593 else
594 mix_dsc.msr = 1;
595
596 err = amixer_mgr->get_amixer(amixer_mgr, &mix_dsc,
597 (struct amixer **)&apcm->amixers[i]);
598 if (err)
599 goto error1;
600
601 apcm->n_amixer++;
602 }
603
604 /* Allocate a SUM resource to mix all input channels together */
605 sum_dsc.msr = atc->msr;
606 err = sum_mgr->get_sum(sum_mgr, &sum_dsc, (struct sum **)&apcm->mono);
607 if (err)
608 goto error1;
609
610 pitch = atc_get_pitch((atc->rsr * atc->msr),
611 apcm->substream->runtime->rate);
612 /* Allocate SRCIMP resources */
613 for (i = 0, apcm->n_srcimp = 0; i < n_srcimp; i++) {
614 if (i < (n_srcc))
615 srcimp_dsc.msr = src_node_conf[i/multi].imp_msr;
616 else if (1 == multi)
617 srcimp_dsc.msr = (pitch <= 0x8000000) ? atc->msr : 1;
618 else
619 srcimp_dsc.msr = 1;
620
621 err = srcimp_mgr->get_srcimp(srcimp_mgr, &srcimp_dsc, &srcimp);
622 if (err)
623 goto error1;
624
625 apcm->srcimps[i] = srcimp;
626 apcm->n_srcimp++;
627 }
628
629 /* Allocate a SRC for writing data to host memory */
630 src_dsc.multi = apcm->substream->runtime->channels;
631 src_dsc.msr = 1;
632 src_dsc.mode = MEMWR;
633 err = src_mgr->get_src(src_mgr, &src_dsc, (struct src **)&apcm->src);
634 if (err)
635 goto error1;
636
637 src = apcm->src;
638 src->ops->set_pitch(src, pitch);
639
640 /* Set up device virtual mem map */
641 err = ct_map_audio_buffer(atc, apcm);
642 if (err < 0)
643 goto error1;
644
645 return 0;
646
647error1:
648 atc_pcm_release_resources(atc, apcm);
649 return err;
650}
651
652static int atc_pcm_capture_prepare(struct ct_atc *atc, struct ct_atc_pcm *apcm)
653{
654 struct src *src;
655 struct amixer *amixer;
656 struct srcimp *srcimp;
657 struct ct_mixer *mixer = atc->mixer;
658 struct sum *mono;
659 struct rsc *out_ports[8] = {NULL};
660 int err, i, j, n_sum, multi;
661 unsigned int pitch;
662 int mix_base = 0, imp_base = 0;
663
664 if (NULL != apcm->src) {
665 /* Prepared pcm capture */
666 return 0;
667 }
668
669 /* Get needed resources. */
670 err = atc_pcm_capture_get_resources(atc, apcm);
671 if (err)
672 return err;
673
674 /* Connect resources */
675 mixer->get_output_ports(mixer, MIX_PCMO_FRONT,
676 &out_ports[0], &out_ports[1]);
677
678 multi = apcm->substream->runtime->channels;
679 if (1 == multi) {
680 mono = apcm->mono;
681 for (i = 0; i < 2; i++) {
682 amixer = apcm->amixers[i];
683 amixer->ops->setup(amixer, out_ports[i],
684 MONO_SUM_SCALE, mono);
685 }
686 out_ports[0] = &mono->rsc;
687 n_sum = 1;
688 mix_base = n_sum * 2;
689 }
690
691 for (i = 0; i < apcm->n_srcc; i++) {
692 src = apcm->srccs[i];
693 srcimp = apcm->srcimps[imp_base+i];
694 amixer = apcm->amixers[mix_base+i];
695 srcimp->ops->map(srcimp, src, out_ports[i%multi]);
696 amixer->ops->setup(amixer, &src->rsc, INIT_VOL, NULL);
697 out_ports[i%multi] = &amixer->rsc;
698 }
699
700 pitch = atc_get_pitch((atc->rsr * atc->msr),
701 apcm->substream->runtime->rate);
702
703 if ((multi > 1) && (pitch <= 0x8000000)) {
704 /* Special connection for interleaved
705 * recording with conjugate channels */
706 for (i = 0; i < multi; i++) {
707 out_ports[i]->ops->master(out_ports[i]);
708 for (j = 0; j < atc->msr; j++) {
709 amixer = apcm->amixers[apcm->n_srcc+j*multi+i];
710 amixer->ops->set_input(amixer, out_ports[i]);
711 amixer->ops->set_scale(amixer, INIT_VOL);
712 amixer->ops->set_sum(amixer, NULL);
713 amixer->ops->commit_raw_write(amixer);
714 out_ports[i]->ops->next_conj(out_ports[i]);
715
716 srcimp = apcm->srcimps[apcm->n_srcc+j*multi+i];
717 srcimp->ops->map(srcimp, apcm->src,
718 &amixer->rsc);
719 }
720 }
721 } else {
722 for (i = 0; i < multi; i++) {
723 srcimp = apcm->srcimps[apcm->n_srcc+i];
724 srcimp->ops->map(srcimp, apcm->src, out_ports[i]);
725 }
726 }
727
728 ct_timer_prepare(apcm->timer);
729
730 return 0;
731}
732
733static int atc_pcm_capture_start(struct ct_atc *atc, struct ct_atc_pcm *apcm)
734{
735 struct src *src;
736 struct src_mgr *src_mgr = atc->rsc_mgrs[SRC];
737 int i, multi;
738
739 if (apcm->started)
740 return 0;
741
742 apcm->started = 1;
743 multi = apcm->substream->runtime->channels;
744 /* Set up converting SRCs */
745 for (i = 0; i < apcm->n_srcc; i++) {
746 src = apcm->srccs[i];
747 src->ops->set_pm(src, ((i%multi) != (multi-1)));
748 src_mgr->src_disable(src_mgr, src);
749 }
750
751 /* Set up recording SRC */
752 src = apcm->src;
753 src->ops->set_sf(src, convert_format(apcm->substream->runtime->format));
754 src->ops->set_sa(src, apcm->vm_block->addr);
755 src->ops->set_la(src, apcm->vm_block->addr + apcm->vm_block->size);
756 src->ops->set_ca(src, apcm->vm_block->addr);
757 src_mgr->src_disable(src_mgr, src);
758
759 /* Disable relevant SRCs firstly */
760 src_mgr->commit_write(src_mgr);
761
762 /* Enable SRCs respectively */
763 for (i = 0; i < apcm->n_srcc; i++) {
764 src = apcm->srccs[i];
765 src->ops->set_state(src, SRC_STATE_RUN);
766 src->ops->commit_write(src);
767 src_mgr->src_enable_s(src_mgr, src);
768 }
769 src = apcm->src;
770 src->ops->set_bm(src, 1);
771 src->ops->set_state(src, SRC_STATE_RUN);
772 src->ops->commit_write(src);
773 src_mgr->src_enable_s(src_mgr, src);
774
775 /* Enable relevant SRCs synchronously */
776 src_mgr->commit_write(src_mgr);
777
778 ct_timer_start(apcm->timer);
779 return 0;
780}
781
782static int
783atc_pcm_capture_position(struct ct_atc *atc, struct ct_atc_pcm *apcm)
784{
785 struct src *src = apcm->src;
786
787 if (!src)
788 return 0;
789 return src->ops->get_ca(src) - apcm->vm_block->addr;
790}
791
792static int spdif_passthru_playback_get_resources(struct ct_atc *atc,
793 struct ct_atc_pcm *apcm)
794{
795 struct src_mgr *src_mgr = atc->rsc_mgrs[SRC];
796 struct amixer_mgr *amixer_mgr = atc->rsc_mgrs[AMIXER];
797 struct src_desc desc = {0};
798 struct amixer_desc mix_dsc = {0};
799 struct src *src;
800 int err;
801 int n_amixer = apcm->substream->runtime->channels, i;
802 unsigned int pitch, rsr = atc->pll_rate;
803
804 /* first release old resources */
805 atc_pcm_release_resources(atc, apcm);
806
807 /* Get SRC resource */
808 desc.multi = apcm->substream->runtime->channels;
809 desc.msr = 1;
810 while (apcm->substream->runtime->rate > (rsr * desc.msr))
811 desc.msr <<= 1;
812
813 desc.mode = MEMRD;
814 err = src_mgr->get_src(src_mgr, &desc, (struct src **)&apcm->src);
815 if (err)
816 goto error1;
817
818 pitch = atc_get_pitch(apcm->substream->runtime->rate, (rsr * desc.msr));
819 src = apcm->src;
820 src->ops->set_pitch(src, pitch);
821 src->ops->set_rom(src, select_rom(pitch));
822 src->ops->set_sf(src, convert_format(apcm->substream->runtime->format));
823 src->ops->set_pm(src, (src->ops->next_interleave(src) != NULL));
824 src->ops->set_bp(src, 1);
825
826 /* Get AMIXER resource */
827 n_amixer = (n_amixer < 2) ? 2 : n_amixer;
828 apcm->amixers = kzalloc(sizeof(void *)*n_amixer, GFP_KERNEL);
829 if (NULL == apcm->amixers) {
830 err = -ENOMEM;
831 goto error1;
832 }
833 mix_dsc.msr = desc.msr;
834 for (i = 0, apcm->n_amixer = 0; i < n_amixer; i++) {
835 err = amixer_mgr->get_amixer(amixer_mgr, &mix_dsc,
836 (struct amixer **)&apcm->amixers[i]);
837 if (err)
838 goto error1;
839
840 apcm->n_amixer++;
841 }
842
843 /* Set up device virtual mem map */
844 err = ct_map_audio_buffer(atc, apcm);
845 if (err < 0)
846 goto error1;
847
848 return 0;
849
850error1:
851 atc_pcm_release_resources(atc, apcm);
852 return err;
853}
854
855static int atc_pll_init(struct ct_atc *atc, int rate)
856{
857 struct hw *hw = atc->hw;
858 int err;
859 err = hw->pll_init(hw, rate);
860 atc->pll_rate = err ? 0 : rate;
861 return err;
862}
863
864static int
865spdif_passthru_playback_setup(struct ct_atc *atc, struct ct_atc_pcm *apcm)
866{
867 struct dao *dao = container_of(atc->daios[SPDIFOO], struct dao, daio);
868 unsigned long flags;
869 unsigned int rate = apcm->substream->runtime->rate;
870 unsigned int status;
871 int err;
872 unsigned char iec958_con_fs;
873
874 switch (rate) {
875 case 48000:
876 iec958_con_fs = IEC958_AES3_CON_FS_48000;
877 break;
878 case 44100:
879 iec958_con_fs = IEC958_AES3_CON_FS_44100;
880 break;
881 case 32000:
882 iec958_con_fs = IEC958_AES3_CON_FS_32000;
883 break;
884 default:
885 return -ENOENT;
886 }
887
888 spin_lock_irqsave(&atc->atc_lock, flags);
889 dao->ops->get_spos(dao, &status);
890 if (((status >> 24) & IEC958_AES3_CON_FS) != iec958_con_fs) {
891 status &= ((~IEC958_AES3_CON_FS) << 24);
892 status |= (iec958_con_fs << 24);
893 dao->ops->set_spos(dao, status);
894 dao->ops->commit_write(dao);
895 }
896 if ((rate != atc->pll_rate) && (32000 != rate))
897 err = atc_pll_init(atc, rate);
898 spin_unlock_irqrestore(&atc->atc_lock, flags);
899
900 return err;
901}
902
903static int
904spdif_passthru_playback_prepare(struct ct_atc *atc, struct ct_atc_pcm *apcm)
905{
906 struct src *src;
907 struct amixer *amixer;
908 struct dao *dao;
909 int err;
910 int i;
911 unsigned long flags;
912
913 if (NULL != apcm->src)
914 return 0;
915
916 /* Configure SPDIFOO and PLL to passthrough mode;
917 * determine pll_rate. */
918 err = spdif_passthru_playback_setup(atc, apcm);
919 if (err)
920 return err;
921
922 /* Get needed resources. */
923 err = spdif_passthru_playback_get_resources(atc, apcm);
924 if (err)
925 return err;
926
927 /* Connect resources */
928 src = apcm->src;
929 for (i = 0; i < apcm->n_amixer; i++) {
930 amixer = apcm->amixers[i];
931 amixer->ops->setup(amixer, &src->rsc, INIT_VOL, NULL);
932 src = src->ops->next_interleave(src);
933 if (NULL == src)
934 src = apcm->src;
935 }
936 /* Connect to SPDIFOO */
937 spin_lock_irqsave(&atc->atc_lock, flags);
938 dao = container_of(atc->daios[SPDIFOO], struct dao, daio);
939 amixer = apcm->amixers[0];
940 dao->ops->set_left_input(dao, &amixer->rsc);
941 amixer = apcm->amixers[1];
942 dao->ops->set_right_input(dao, &amixer->rsc);
943 spin_unlock_irqrestore(&atc->atc_lock, flags);
944
945 ct_timer_prepare(apcm->timer);
946
947 return 0;
948}
949
950static int atc_select_line_in(struct ct_atc *atc)
951{
952 struct hw *hw = atc->hw;
953 struct ct_mixer *mixer = atc->mixer;
954 struct src *src;
955
956 if (hw->is_adc_source_selected(hw, ADC_LINEIN))
957 return 0;
958
959 mixer->set_input_left(mixer, MIX_MIC_IN, NULL);
960 mixer->set_input_right(mixer, MIX_MIC_IN, NULL);
961
962 hw->select_adc_source(hw, ADC_LINEIN);
963
964 src = atc->srcs[2];
965 mixer->set_input_left(mixer, MIX_LINE_IN, &src->rsc);
966 src = atc->srcs[3];
967 mixer->set_input_right(mixer, MIX_LINE_IN, &src->rsc);
968
969 return 0;
970}
971
972static int atc_select_mic_in(struct ct_atc *atc)
973{
974 struct hw *hw = atc->hw;
975 struct ct_mixer *mixer = atc->mixer;
976 struct src *src;
977
978 if (hw->is_adc_source_selected(hw, ADC_MICIN))
979 return 0;
980
981 mixer->set_input_left(mixer, MIX_LINE_IN, NULL);
982 mixer->set_input_right(mixer, MIX_LINE_IN, NULL);
983
984 hw->select_adc_source(hw, ADC_MICIN);
985
986 src = atc->srcs[2];
987 mixer->set_input_left(mixer, MIX_MIC_IN, &src->rsc);
988 src = atc->srcs[3];
989 mixer->set_input_right(mixer, MIX_MIC_IN, &src->rsc);
990
991 return 0;
992}
993
994static int atc_have_digit_io_switch(struct ct_atc *atc)
995{
996 struct hw *hw = atc->hw;
997
998 return hw->have_digit_io_switch(hw);
999}
1000
1001static int atc_select_digit_io(struct ct_atc *atc)
1002{
1003 struct hw *hw = atc->hw;
1004
1005 if (hw->is_adc_source_selected(hw, ADC_NONE))
1006 return 0;
1007
1008 hw->select_adc_source(hw, ADC_NONE);
1009
1010 return 0;
1011}
1012
1013static int atc_daio_unmute(struct ct_atc *atc, unsigned char state, int type)
1014{
1015 struct daio_mgr *daio_mgr = atc->rsc_mgrs[DAIO];
1016
1017 if (state)
1018 daio_mgr->daio_enable(daio_mgr, atc->daios[type]);
1019 else
1020 daio_mgr->daio_disable(daio_mgr, atc->daios[type]);
1021
1022 daio_mgr->commit_write(daio_mgr);
1023
1024 return 0;
1025}
1026
1027static int
1028atc_dao_get_status(struct ct_atc *atc, unsigned int *status, int type)
1029{
1030 struct dao *dao = container_of(atc->daios[type], struct dao, daio);
1031 return dao->ops->get_spos(dao, status);
1032}
1033
1034static int
1035atc_dao_set_status(struct ct_atc *atc, unsigned int status, int type)
1036{
1037 struct dao *dao = container_of(atc->daios[type], struct dao, daio);
1038
1039 dao->ops->set_spos(dao, status);
1040 dao->ops->commit_write(dao);
1041 return 0;
1042}
1043
1044static int atc_line_front_unmute(struct ct_atc *atc, unsigned char state)
1045{
1046 return atc_daio_unmute(atc, state, LINEO1);
1047}
1048
1049static int atc_line_surround_unmute(struct ct_atc *atc, unsigned char state)
1050{
1051 return atc_daio_unmute(atc, state, LINEO4);
1052}
1053
1054static int atc_line_clfe_unmute(struct ct_atc *atc, unsigned char state)
1055{
1056 return atc_daio_unmute(atc, state, LINEO3);
1057}
1058
1059static int atc_line_rear_unmute(struct ct_atc *atc, unsigned char state)
1060{
1061 return atc_daio_unmute(atc, state, LINEO2);
1062}
1063
1064static int atc_line_in_unmute(struct ct_atc *atc, unsigned char state)
1065{
1066 return atc_daio_unmute(atc, state, LINEIM);
1067}
1068
1069static int atc_spdif_out_unmute(struct ct_atc *atc, unsigned char state)
1070{
1071 return atc_daio_unmute(atc, state, SPDIFOO);
1072}
1073
1074static int atc_spdif_in_unmute(struct ct_atc *atc, unsigned char state)
1075{
1076 return atc_daio_unmute(atc, state, SPDIFIO);
1077}
1078
1079static int atc_spdif_out_get_status(struct ct_atc *atc, unsigned int *status)
1080{
1081 return atc_dao_get_status(atc, status, SPDIFOO);
1082}
1083
1084static int atc_spdif_out_set_status(struct ct_atc *atc, unsigned int status)
1085{
1086 return atc_dao_set_status(atc, status, SPDIFOO);
1087}
1088
1089static int atc_spdif_out_passthru(struct ct_atc *atc, unsigned char state)
1090{
1091 unsigned long flags;
1092 struct dao_desc da_dsc = {0};
1093 struct dao *dao;
1094 int err;
1095 struct ct_mixer *mixer = atc->mixer;
1096 struct rsc *rscs[2] = {NULL};
1097 unsigned int spos = 0;
1098
1099 spin_lock_irqsave(&atc->atc_lock, flags);
1100 dao = container_of(atc->daios[SPDIFOO], struct dao, daio);
1101 da_dsc.msr = state ? 1 : atc->msr;
1102 da_dsc.passthru = state ? 1 : 0;
1103 err = dao->ops->reinit(dao, &da_dsc);
1104 if (state) {
1105 spos = IEC958_DEFAULT_CON;
1106 } else {
1107 mixer->get_output_ports(mixer, MIX_SPDIF_OUT,
1108 &rscs[0], &rscs[1]);
1109 dao->ops->set_left_input(dao, rscs[0]);
1110 dao->ops->set_right_input(dao, rscs[1]);
1111 /* Restore PLL to atc->rsr if needed. */
1112 if (atc->pll_rate != atc->rsr)
1113 err = atc_pll_init(atc, atc->rsr);
1114 }
1115 dao->ops->set_spos(dao, spos);
1116 dao->ops->commit_write(dao);
1117 spin_unlock_irqrestore(&atc->atc_lock, flags);
1118
1119 return err;
1120}
1121
1122static int ct_atc_destroy(struct ct_atc *atc)
1123{
1124 struct daio_mgr *daio_mgr;
1125 struct dao *dao;
1126 struct dai *dai;
1127 struct daio *daio;
1128 struct sum_mgr *sum_mgr;
1129 struct src_mgr *src_mgr;
1130 struct srcimp_mgr *srcimp_mgr;
1131 struct srcimp *srcimp;
1132 struct ct_mixer *mixer;
1133 int i = 0;
1134
1135 if (NULL == atc)
1136 return 0;
1137
1138 if (atc->timer) {
1139 ct_timer_free(atc->timer);
1140 atc->timer = NULL;
1141 }
1142
1143 /* Stop hardware and disable all interrupts */
1144 if (NULL != atc->hw)
1145 ((struct hw *)atc->hw)->card_stop(atc->hw);
1146
1147 /* Destroy internal mixer objects */
1148 if (NULL != atc->mixer) {
1149 mixer = atc->mixer;
1150 mixer->set_input_left(mixer, MIX_LINE_IN, NULL);
1151 mixer->set_input_right(mixer, MIX_LINE_IN, NULL);
1152 mixer->set_input_left(mixer, MIX_MIC_IN, NULL);
1153 mixer->set_input_right(mixer, MIX_MIC_IN, NULL);
1154 mixer->set_input_left(mixer, MIX_SPDIF_IN, NULL);
1155 mixer->set_input_right(mixer, MIX_SPDIF_IN, NULL);
1156 ct_mixer_destroy(atc->mixer);
1157 }
1158
1159 if (NULL != atc->daios) {
1160 daio_mgr = (struct daio_mgr *)atc->rsc_mgrs[DAIO];
1161 for (i = 0; i < atc->n_daio; i++) {
1162 daio = atc->daios[i];
1163 if (daio->type < LINEIM) {
1164 dao = container_of(daio, struct dao, daio);
1165 dao->ops->clear_left_input(dao);
1166 dao->ops->clear_right_input(dao);
1167 } else {
1168 dai = container_of(daio, struct dai, daio);
1169 /* some thing to do for dai ... */
1170 }
1171 daio_mgr->put_daio(daio_mgr, daio);
1172 }
1173 kfree(atc->daios);
1174 }
1175
1176 if (NULL != atc->pcm) {
1177 sum_mgr = atc->rsc_mgrs[SUM];
1178 for (i = 0; i < atc->n_pcm; i++)
1179 sum_mgr->put_sum(sum_mgr, atc->pcm[i]);
1180
1181 kfree(atc->pcm);
1182 }
1183
1184 if (NULL != atc->srcs) {
1185 src_mgr = atc->rsc_mgrs[SRC];
1186 for (i = 0; i < atc->n_src; i++)
1187 src_mgr->put_src(src_mgr, atc->srcs[i]);
1188
1189 kfree(atc->srcs);
1190 }
1191
1192 if (NULL != atc->srcimps) {
1193 srcimp_mgr = atc->rsc_mgrs[SRCIMP];
1194 for (i = 0; i < atc->n_srcimp; i++) {
1195 srcimp = atc->srcimps[i];
1196 srcimp->ops->unmap(srcimp);
1197 srcimp_mgr->put_srcimp(srcimp_mgr, atc->srcimps[i]);
1198 }
1199 kfree(atc->srcimps);
1200 }
1201
1202 for (i = 0; i < NUM_RSCTYP; i++) {
1203 if ((NULL != rsc_mgr_funcs[i].destroy) &&
1204 (NULL != atc->rsc_mgrs[i]))
1205 rsc_mgr_funcs[i].destroy(atc->rsc_mgrs[i]);
1206
1207 }
1208
1209 if (NULL != atc->hw)
1210 destroy_hw_obj((struct hw *)atc->hw);
1211
1212 /* Destroy device virtual memory manager object */
1213 if (NULL != atc->vm) {
1214 ct_vm_destroy(atc->vm);
1215 atc->vm = NULL;
1216 }
1217
1218 kfree(atc);
1219
1220 return 0;
1221}
1222
1223static int atc_dev_free(struct snd_device *dev)
1224{
1225 struct ct_atc *atc = dev->device_data;
1226 return ct_atc_destroy(atc);
1227}
1228
1229static int __devinit atc_identify_card(struct ct_atc *atc)
1230{
1231 const struct snd_pci_quirk *p;
1232 const struct snd_pci_quirk *list;
1233
1234 switch (atc->chip_type) {
1235 case ATC20K1:
1236 atc->chip_name = "20K1";
1237 list = subsys_20k1_list;
1238 break;
1239 case ATC20K2:
1240 atc->chip_name = "20K2";
1241 list = subsys_20k2_list;
1242 break;
1243 default:
1244 return -ENOENT;
1245 }
1246 p = snd_pci_quirk_lookup(atc->pci, list);
1247 if (!p)
1248 return -ENOENT;
1249 atc->model = p->value;
1250 atc->model_name = ct_subsys_name[atc->model];
1251 snd_printd("ctxfi: chip %s model %s (%04x:%04x) is found\n",
1252 atc->chip_name, atc->model_name,
1253 atc->pci->subsystem_vendor,
1254 atc->pci->subsystem_device);
1255 return 0;
1256}
1257
1258int __devinit ct_atc_create_alsa_devs(struct ct_atc *atc)
1259{
1260 enum CTALSADEVS i;
1261 int err;
1262
1263 alsa_dev_funcs[MIXER].public_name = atc->chip_name;
1264
1265 for (i = 0; i < NUM_CTALSADEVS; i++) {
1266 if (NULL == alsa_dev_funcs[i].create)
1267 continue;
1268
1269 err = alsa_dev_funcs[i].create(atc, i,
1270 alsa_dev_funcs[i].public_name);
1271 if (err) {
1272 printk(KERN_ERR "ctxfi: "
1273 "Creating alsa device %d failed!\n", i);
1274 return err;
1275 }
1276 }
1277
1278 return 0;
1279}
1280
1281static int __devinit atc_create_hw_devs(struct ct_atc *atc)
1282{
1283 struct hw *hw;
1284 struct card_conf info = {0};
1285 int i, err;
1286
1287 err = create_hw_obj(atc->pci, atc->chip_type, atc->model, &hw);
1288 if (err) {
1289 printk(KERN_ERR "Failed to create hw obj!!!\n");
1290 return err;
1291 }
1292 atc->hw = hw;
1293
1294 /* Initialize card hardware. */
1295 info.rsr = atc->rsr;
1296 info.msr = atc->msr;
1297 info.vm_pgt_phys = atc_get_ptp_phys(atc, 0);
1298 err = hw->card_init(hw, &info);
1299 if (err < 0)
1300 return err;
1301
1302 for (i = 0; i < NUM_RSCTYP; i++) {
1303 if (NULL == rsc_mgr_funcs[i].create)
1304 continue;
1305
1306 err = rsc_mgr_funcs[i].create(atc->hw, &atc->rsc_mgrs[i]);
1307 if (err) {
1308 printk(KERN_ERR "ctxfi: "
1309 "Failed to create rsc_mgr %d!!!\n", i);
1310 return err;
1311 }
1312 }
1313
1314 return 0;
1315}
1316
1317static int __devinit atc_get_resources(struct ct_atc *atc)
1318{
1319 struct daio_desc da_desc = {0};
1320 struct daio_mgr *daio_mgr;
1321 struct src_desc src_dsc = {0};
1322 struct src_mgr *src_mgr;
1323 struct srcimp_desc srcimp_dsc = {0};
1324 struct srcimp_mgr *srcimp_mgr;
1325 struct sum_desc sum_dsc = {0};
1326 struct sum_mgr *sum_mgr;
1327 int err, i;
1328
1329 atc->daios = kzalloc(sizeof(void *)*(DAIONUM), GFP_KERNEL);
1330 if (NULL == atc->daios)
1331 return -ENOMEM;
1332
1333 atc->srcs = kzalloc(sizeof(void *)*(2*2), GFP_KERNEL);
1334 if (NULL == atc->srcs)
1335 return -ENOMEM;
1336
1337 atc->srcimps = kzalloc(sizeof(void *)*(2*2), GFP_KERNEL);
1338 if (NULL == atc->srcimps)
1339 return -ENOMEM;
1340
1341 atc->pcm = kzalloc(sizeof(void *)*(2*4), GFP_KERNEL);
1342 if (NULL == atc->pcm)
1343 return -ENOMEM;
1344
1345 daio_mgr = (struct daio_mgr *)atc->rsc_mgrs[DAIO];
1346 da_desc.msr = atc->msr;
1347 for (i = 0, atc->n_daio = 0; i < DAIONUM-1; i++) {
1348 da_desc.type = i;
1349 err = daio_mgr->get_daio(daio_mgr, &da_desc,
1350 (struct daio **)&atc->daios[i]);
1351 if (err) {
1352 printk(KERN_ERR "ctxfi: Failed to get DAIO "
1353 "resource %d!!!\n", i);
1354 return err;
1355 }
1356 atc->n_daio++;
1357 }
1358 if (atc->model == CTSB073X)
1359 da_desc.type = SPDIFI1;
1360 else
1361 da_desc.type = SPDIFIO;
1362 err = daio_mgr->get_daio(daio_mgr, &da_desc,
1363 (struct daio **)&atc->daios[i]);
1364 if (err) {
1365 printk(KERN_ERR "ctxfi: Failed to get S/PDIF-in resource!!!\n");
1366 return err;
1367 }
1368 atc->n_daio++;
1369
1370 src_mgr = atc->rsc_mgrs[SRC];
1371 src_dsc.multi = 1;
1372 src_dsc.msr = atc->msr;
1373 src_dsc.mode = ARCRW;
1374 for (i = 0, atc->n_src = 0; i < (2*2); i++) {
1375 err = src_mgr->get_src(src_mgr, &src_dsc,
1376 (struct src **)&atc->srcs[i]);
1377 if (err)
1378 return err;
1379
1380 atc->n_src++;
1381 }
1382
1383 srcimp_mgr = atc->rsc_mgrs[SRCIMP];
1384 srcimp_dsc.msr = 8; /* SRCIMPs for S/PDIFIn SRT */
1385 for (i = 0, atc->n_srcimp = 0; i < (2*1); i++) {
1386 err = srcimp_mgr->get_srcimp(srcimp_mgr, &srcimp_dsc,
1387 (struct srcimp **)&atc->srcimps[i]);
1388 if (err)
1389 return err;
1390
1391 atc->n_srcimp++;
1392 }
1393 srcimp_dsc.msr = 8; /* SRCIMPs for LINE/MICIn SRT */
1394 for (i = 0; i < (2*1); i++) {
1395 err = srcimp_mgr->get_srcimp(srcimp_mgr, &srcimp_dsc,
1396 (struct srcimp **)&atc->srcimps[2*1+i]);
1397 if (err)
1398 return err;
1399
1400 atc->n_srcimp++;
1401 }
1402
1403 sum_mgr = atc->rsc_mgrs[SUM];
1404 sum_dsc.msr = atc->msr;
1405 for (i = 0, atc->n_pcm = 0; i < (2*4); i++) {
1406 err = sum_mgr->get_sum(sum_mgr, &sum_dsc,
1407 (struct sum **)&atc->pcm[i]);
1408 if (err)
1409 return err;
1410
1411 atc->n_pcm++;
1412 }
1413
1414 err = ct_mixer_create(atc, (struct ct_mixer **)&atc->mixer);
1415 if (err) {
1416 printk(KERN_ERR "ctxfi: Failed to create mixer obj!!!\n");
1417 return err;
1418 }
1419
1420 return 0;
1421}
1422
1423static void __devinit
1424atc_connect_dai(struct src_mgr *src_mgr, struct dai *dai,
1425 struct src **srcs, struct srcimp **srcimps)
1426{
1427 struct rsc *rscs[2] = {NULL};
1428 struct src *src;
1429 struct srcimp *srcimp;
1430 int i = 0;
1431
1432 rscs[0] = &dai->daio.rscl;
1433 rscs[1] = &dai->daio.rscr;
1434 for (i = 0; i < 2; i++) {
1435 src = srcs[i];
1436 srcimp = srcimps[i];
1437 srcimp->ops->map(srcimp, src, rscs[i]);
1438 src_mgr->src_disable(src_mgr, src);
1439 }
1440
1441 src_mgr->commit_write(src_mgr); /* Actually disable SRCs */
1442
1443 src = srcs[0];
1444 src->ops->set_pm(src, 1);
1445 for (i = 0; i < 2; i++) {
1446 src = srcs[i];
1447 src->ops->set_state(src, SRC_STATE_RUN);
1448 src->ops->commit_write(src);
1449 src_mgr->src_enable_s(src_mgr, src);
1450 }
1451
1452 dai->ops->set_srt_srcl(dai, &(srcs[0]->rsc));
1453 dai->ops->set_srt_srcr(dai, &(srcs[1]->rsc));
1454
1455 dai->ops->set_enb_src(dai, 1);
1456 dai->ops->set_enb_srt(dai, 1);
1457 dai->ops->commit_write(dai);
1458
1459 src_mgr->commit_write(src_mgr); /* Synchronously enable SRCs */
1460}
1461
1462static void __devinit atc_connect_resources(struct ct_atc *atc)
1463{
1464 struct dai *dai;
1465 struct dao *dao;
1466 struct src *src;
1467 struct sum *sum;
1468 struct ct_mixer *mixer;
1469 struct rsc *rscs[2] = {NULL};
1470 int i, j;
1471
1472 mixer = atc->mixer;
1473
1474 for (i = MIX_WAVE_FRONT, j = LINEO1; i <= MIX_SPDIF_OUT; i++, j++) {
1475 mixer->get_output_ports(mixer, i, &rscs[0], &rscs[1]);
1476 dao = container_of(atc->daios[j], struct dao, daio);
1477 dao->ops->set_left_input(dao, rscs[0]);
1478 dao->ops->set_right_input(dao, rscs[1]);
1479 }
1480
1481 dai = container_of(atc->daios[LINEIM], struct dai, daio);
1482 atc_connect_dai(atc->rsc_mgrs[SRC], dai,
1483 (struct src **)&atc->srcs[2],
1484 (struct srcimp **)&atc->srcimps[2]);
1485 src = atc->srcs[2];
1486 mixer->set_input_left(mixer, MIX_LINE_IN, &src->rsc);
1487 src = atc->srcs[3];
1488 mixer->set_input_right(mixer, MIX_LINE_IN, &src->rsc);
1489
1490 dai = container_of(atc->daios[SPDIFIO], struct dai, daio);
1491 atc_connect_dai(atc->rsc_mgrs[SRC], dai,
1492 (struct src **)&atc->srcs[0],
1493 (struct srcimp **)&atc->srcimps[0]);
1494
1495 src = atc->srcs[0];
1496 mixer->set_input_left(mixer, MIX_SPDIF_IN, &src->rsc);
1497 src = atc->srcs[1];
1498 mixer->set_input_right(mixer, MIX_SPDIF_IN, &src->rsc);
1499
1500 for (i = MIX_PCMI_FRONT, j = 0; i <= MIX_PCMI_SURROUND; i++, j += 2) {
1501 sum = atc->pcm[j];
1502 mixer->set_input_left(mixer, i, &sum->rsc);
1503 sum = atc->pcm[j+1];
1504 mixer->set_input_right(mixer, i, &sum->rsc);
1505 }
1506}
1507
1508static struct ct_atc atc_preset __devinitdata = {
1509 .map_audio_buffer = ct_map_audio_buffer,
1510 .unmap_audio_buffer = ct_unmap_audio_buffer,
1511 .pcm_playback_prepare = atc_pcm_playback_prepare,
1512 .pcm_release_resources = atc_pcm_release_resources,
1513 .pcm_playback_start = atc_pcm_playback_start,
1514 .pcm_playback_stop = atc_pcm_stop,
1515 .pcm_playback_position = atc_pcm_playback_position,
1516 .pcm_capture_prepare = atc_pcm_capture_prepare,
1517 .pcm_capture_start = atc_pcm_capture_start,
1518 .pcm_capture_stop = atc_pcm_stop,
1519 .pcm_capture_position = atc_pcm_capture_position,
1520 .spdif_passthru_playback_prepare = spdif_passthru_playback_prepare,
1521 .get_ptp_phys = atc_get_ptp_phys,
1522 .select_line_in = atc_select_line_in,
1523 .select_mic_in = atc_select_mic_in,
1524 .select_digit_io = atc_select_digit_io,
1525 .line_front_unmute = atc_line_front_unmute,
1526 .line_surround_unmute = atc_line_surround_unmute,
1527 .line_clfe_unmute = atc_line_clfe_unmute,
1528 .line_rear_unmute = atc_line_rear_unmute,
1529 .line_in_unmute = atc_line_in_unmute,
1530 .spdif_out_unmute = atc_spdif_out_unmute,
1531 .spdif_in_unmute = atc_spdif_in_unmute,
1532 .spdif_out_get_status = atc_spdif_out_get_status,
1533 .spdif_out_set_status = atc_spdif_out_set_status,
1534 .spdif_out_passthru = atc_spdif_out_passthru,
1535 .have_digit_io_switch = atc_have_digit_io_switch,
1536};
1537
1538/**
1539 * ct_atc_create - create and initialize a hardware manager
1540 * @card: corresponding alsa card object
1541 * @pci: corresponding kernel pci device object
1542 * @ratc: return created object address in it
1543 *
1544 * Creates and initializes a hardware manager.
1545 *
1546 * Creates kmallocated ct_atc structure. Initializes hardware.
1547 * Returns 0 if suceeds, or negative error code if fails.
1548 */
1549
1550int __devinit ct_atc_create(struct snd_card *card, struct pci_dev *pci,
1551 unsigned int rsr, unsigned int msr,
1552 int chip_type, struct ct_atc **ratc)
1553{
1554 struct ct_atc *atc;
1555 static struct snd_device_ops ops = {
1556 .dev_free = atc_dev_free,
1557 };
1558 int err;
1559
1560 *ratc = NULL;
1561
1562 atc = kzalloc(sizeof(*atc), GFP_KERNEL);
1563 if (NULL == atc)
1564 return -ENOMEM;
1565
1566 /* Set operations */
1567 *atc = atc_preset;
1568
1569 atc->card = card;
1570 atc->pci = pci;
1571 atc->rsr = rsr;
1572 atc->msr = msr;
1573 atc->chip_type = chip_type;
1574
1575 spin_lock_init(&atc->atc_lock);
1576
1577 /* Find card model */
1578 err = atc_identify_card(atc);
1579 if (err < 0) {
1580 printk(KERN_ERR "ctatc: Card not recognised\n");
1581 goto error1;
1582 }
1583
1584 /* Set up device virtual memory management object */
1585 err = ct_vm_create(&atc->vm);
1586 if (err < 0)
1587 goto error1;
1588
1589 /* Create all atc hw devices */
1590 err = atc_create_hw_devs(atc);
1591 if (err < 0)
1592 goto error1;
1593
1594 /* Get resources */
1595 err = atc_get_resources(atc);
1596 if (err < 0)
1597 goto error1;
1598
1599 /* Build topology */
1600 atc_connect_resources(atc);
1601
1602 atc->timer = ct_timer_new(atc);
1603 if (!atc->timer)
1604 goto error1;
1605
1606 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, atc, &ops);
1607 if (err < 0)
1608 goto error1;
1609
1610 snd_card_set_dev(card, &pci->dev);
1611
1612 *ratc = atc;
1613 return 0;
1614
1615error1:
1616 ct_atc_destroy(atc);
1617 printk(KERN_ERR "ctxfi: Something wrong!!!\n");
1618 return err;
1619}
diff --git a/sound/pci/ctxfi/ctatc.h b/sound/pci/ctxfi/ctatc.h
new file mode 100644
index 00000000000..a03347232e8
--- /dev/null
+++ b/sound/pci/ctxfi/ctatc.h
@@ -0,0 +1,147 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File ctatc.h
9 *
10 * @Brief
11 * This file contains the definition of the device resource management object.
12 *
13 * @Author Liu Chun
14 * @Date Mar 28 2008
15 *
16 */
17
18#ifndef CTATC_H
19#define CTATC_H
20
21#include <linux/types.h>
22#include <linux/spinlock_types.h>
23#include <linux/pci.h>
24#include <linux/timer.h>
25#include <sound/core.h>
26
27#include "ctvmem.h"
28#include "ctresource.h"
29
30enum CTALSADEVS { /* Types of alsa devices */
31 FRONT,
32 SURROUND,
33 CLFE,
34 SIDE,
35 IEC958,
36 MIXER,
37 NUM_CTALSADEVS /* This should always be the last */
38};
39
40struct ct_atc_chip_sub_details {
41 u16 subsys;
42 const char *nm_model;
43};
44
45struct ct_atc_chip_details {
46 u16 vendor;
47 u16 device;
48 const struct ct_atc_chip_sub_details *sub_details;
49 const char *nm_card;
50};
51
52struct ct_atc;
53struct ct_timer;
54struct ct_timer_instance;
55
56/* alsa pcm stream descriptor */
57struct ct_atc_pcm {
58 struct snd_pcm_substream *substream;
59 void (*interrupt)(struct ct_atc_pcm *apcm);
60 struct ct_timer_instance *timer;
61 unsigned int started:1;
62
63 /* Only mono and interleaved modes are supported now. */
64 struct ct_vm_block *vm_block;
65 void *src; /* SRC for interacting with host memory */
66 void **srccs; /* SRCs for sample rate conversion */
67 void **srcimps; /* SRC Input Mappers */
68 void **amixers; /* AMIXERs for routing converted data */
69 void *mono; /* A SUM resource for mixing chs to one */
70 unsigned char n_srcc; /* Number of converting SRCs */
71 unsigned char n_srcimp; /* Number of SRC Input Mappers */
72 unsigned char n_amixer; /* Number of AMIXERs */
73};
74
75/* Chip resource management object */
76struct ct_atc {
77 struct pci_dev *pci;
78 struct snd_card *card;
79 unsigned int rsr; /* reference sample rate in Hz */
80 unsigned int msr; /* master sample rate in rsr */
81 unsigned int pll_rate; /* current rate of Phase Lock Loop */
82
83 int chip_type;
84 int model;
85 const char *chip_name;
86 const char *model_name;
87
88 struct ct_vm *vm; /* device virtual memory manager for this card */
89 int (*map_audio_buffer)(struct ct_atc *atc, struct ct_atc_pcm *apcm);
90 void (*unmap_audio_buffer)(struct ct_atc *atc, struct ct_atc_pcm *apcm);
91 unsigned long (*get_ptp_phys)(struct ct_atc *atc, int index);
92
93 spinlock_t atc_lock;
94
95 int (*pcm_playback_prepare)(struct ct_atc *atc,
96 struct ct_atc_pcm *apcm);
97 int (*pcm_playback_start)(struct ct_atc *atc, struct ct_atc_pcm *apcm);
98 int (*pcm_playback_stop)(struct ct_atc *atc, struct ct_atc_pcm *apcm);
99 int (*pcm_playback_position)(struct ct_atc *atc,
100 struct ct_atc_pcm *apcm);
101 int (*spdif_passthru_playback_prepare)(struct ct_atc *atc,
102 struct ct_atc_pcm *apcm);
103 int (*pcm_capture_prepare)(struct ct_atc *atc, struct ct_atc_pcm *apcm);
104 int (*pcm_capture_start)(struct ct_atc *atc, struct ct_atc_pcm *apcm);
105 int (*pcm_capture_stop)(struct ct_atc *atc, struct ct_atc_pcm *apcm);
106 int (*pcm_capture_position)(struct ct_atc *atc,
107 struct ct_atc_pcm *apcm);
108 int (*pcm_release_resources)(struct ct_atc *atc,
109 struct ct_atc_pcm *apcm);
110 int (*select_line_in)(struct ct_atc *atc);
111 int (*select_mic_in)(struct ct_atc *atc);
112 int (*select_digit_io)(struct ct_atc *atc);
113 int (*line_front_unmute)(struct ct_atc *atc, unsigned char state);
114 int (*line_surround_unmute)(struct ct_atc *atc, unsigned char state);
115 int (*line_clfe_unmute)(struct ct_atc *atc, unsigned char state);
116 int (*line_rear_unmute)(struct ct_atc *atc, unsigned char state);
117 int (*line_in_unmute)(struct ct_atc *atc, unsigned char state);
118 int (*spdif_out_unmute)(struct ct_atc *atc, unsigned char state);
119 int (*spdif_in_unmute)(struct ct_atc *atc, unsigned char state);
120 int (*spdif_out_get_status)(struct ct_atc *atc, unsigned int *status);
121 int (*spdif_out_set_status)(struct ct_atc *atc, unsigned int status);
122 int (*spdif_out_passthru)(struct ct_atc *atc, unsigned char state);
123 int (*have_digit_io_switch)(struct ct_atc *atc);
124
125 /* Don't touch! Used for internal object. */
126 void *rsc_mgrs[NUM_RSCTYP]; /* chip resource managers */
127 void *mixer; /* internal mixer object */
128 void *hw; /* chip specific hardware access object */
129 void **daios; /* digital audio io resources */
130 void **pcm; /* SUMs for collecting all pcm stream */
131 void **srcs; /* Sample Rate Converters for input signal */
132 void **srcimps; /* input mappers for SRCs */
133 unsigned char n_daio;
134 unsigned char n_src;
135 unsigned char n_srcimp;
136 unsigned char n_pcm;
137
138 struct ct_timer *timer;
139};
140
141
142int __devinit ct_atc_create(struct snd_card *card, struct pci_dev *pci,
143 unsigned int rsr, unsigned int msr, int chip_type,
144 struct ct_atc **ratc);
145int __devinit ct_atc_create_alsa_devs(struct ct_atc *atc);
146
147#endif /* CTATC_H */
diff --git a/sound/pci/ctxfi/ctdaio.c b/sound/pci/ctxfi/ctdaio.c
new file mode 100644
index 00000000000..082e35c08c0
--- /dev/null
+++ b/sound/pci/ctxfi/ctdaio.c
@@ -0,0 +1,769 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File ctdaio.c
9 *
10 * @Brief
11 * This file contains the implementation of Digital Audio Input Output
12 * resource management object.
13 *
14 * @Author Liu Chun
15 * @Date May 23 2008
16 *
17 */
18
19#include "ctdaio.h"
20#include "cthardware.h"
21#include "ctimap.h"
22#include <linux/slab.h>
23#include <linux/kernel.h>
24
25#define DAIO_RESOURCE_NUM NUM_DAIOTYP
26#define DAIO_OUT_MAX SPDIFOO
27
28union daio_usage {
29 struct {
30 unsigned short lineo1:1;
31 unsigned short lineo2:1;
32 unsigned short lineo3:1;
33 unsigned short lineo4:1;
34 unsigned short spdifoo:1;
35 unsigned short lineim:1;
36 unsigned short spdifio:1;
37 unsigned short spdifi1:1;
38 } bf;
39 unsigned short data;
40};
41
42struct daio_rsc_idx {
43 unsigned short left;
44 unsigned short right;
45};
46
47struct daio_rsc_idx idx_20k1[NUM_DAIOTYP] = {
48 [LINEO1] = {.left = 0x00, .right = 0x01},
49 [LINEO2] = {.left = 0x18, .right = 0x19},
50 [LINEO3] = {.left = 0x08, .right = 0x09},
51 [LINEO4] = {.left = 0x10, .right = 0x11},
52 [LINEIM] = {.left = 0x1b5, .right = 0x1bd},
53 [SPDIFOO] = {.left = 0x20, .right = 0x21},
54 [SPDIFIO] = {.left = 0x15, .right = 0x1d},
55 [SPDIFI1] = {.left = 0x95, .right = 0x9d},
56};
57
58struct daio_rsc_idx idx_20k2[NUM_DAIOTYP] = {
59 [LINEO1] = {.left = 0x40, .right = 0x41},
60 [LINEO2] = {.left = 0x70, .right = 0x71},
61 [LINEO3] = {.left = 0x50, .right = 0x51},
62 [LINEO4] = {.left = 0x60, .right = 0x61},
63 [LINEIM] = {.left = 0x45, .right = 0xc5},
64 [SPDIFOO] = {.left = 0x00, .right = 0x01},
65 [SPDIFIO] = {.left = 0x05, .right = 0x85},
66};
67
68static int daio_master(struct rsc *rsc)
69{
70 /* Actually, this is not the resource index of DAIO.
71 * For DAO, it is the input mapper index. And, for DAI,
72 * it is the output time-slot index. */
73 return rsc->conj = rsc->idx;
74}
75
76static int daio_index(const struct rsc *rsc)
77{
78 return rsc->conj;
79}
80
81static int daio_out_next_conj(struct rsc *rsc)
82{
83 return rsc->conj += 2;
84}
85
86static int daio_in_next_conj_20k1(struct rsc *rsc)
87{
88 return rsc->conj += 0x200;
89}
90
91static int daio_in_next_conj_20k2(struct rsc *rsc)
92{
93 return rsc->conj += 0x100;
94}
95
96static struct rsc_ops daio_out_rsc_ops = {
97 .master = daio_master,
98 .next_conj = daio_out_next_conj,
99 .index = daio_index,
100 .output_slot = NULL,
101};
102
103static struct rsc_ops daio_in_rsc_ops_20k1 = {
104 .master = daio_master,
105 .next_conj = daio_in_next_conj_20k1,
106 .index = NULL,
107 .output_slot = daio_index,
108};
109
110static struct rsc_ops daio_in_rsc_ops_20k2 = {
111 .master = daio_master,
112 .next_conj = daio_in_next_conj_20k2,
113 .index = NULL,
114 .output_slot = daio_index,
115};
116
117static unsigned int daio_device_index(enum DAIOTYP type, struct hw *hw)
118{
119 switch (hw->chip_type) {
120 case ATC20K1:
121 switch (type) {
122 case SPDIFOO: return 0;
123 case SPDIFIO: return 0;
124 case SPDIFI1: return 1;
125 case LINEO1: return 4;
126 case LINEO2: return 7;
127 case LINEO3: return 5;
128 case LINEO4: return 6;
129 case LINEIM: return 7;
130 default: return -EINVAL;
131 }
132 case ATC20K2:
133 switch (type) {
134 case SPDIFOO: return 0;
135 case SPDIFIO: return 0;
136 case LINEO1: return 4;
137 case LINEO2: return 7;
138 case LINEO3: return 5;
139 case LINEO4: return 6;
140 case LINEIM: return 4;
141 default: return -EINVAL;
142 }
143 default:
144 return -EINVAL;
145 }
146}
147
148static int dao_rsc_reinit(struct dao *dao, const struct dao_desc *desc);
149
150static int dao_spdif_get_spos(struct dao *dao, unsigned int *spos)
151{
152 ((struct hw *)dao->hw)->dao_get_spos(dao->ctrl_blk, spos);
153 return 0;
154}
155
156static int dao_spdif_set_spos(struct dao *dao, unsigned int spos)
157{
158 ((struct hw *)dao->hw)->dao_set_spos(dao->ctrl_blk, spos);
159 return 0;
160}
161
162static int dao_commit_write(struct dao *dao)
163{
164 ((struct hw *)dao->hw)->dao_commit_write(dao->hw,
165 daio_device_index(dao->daio.type, dao->hw), dao->ctrl_blk);
166 return 0;
167}
168
169static int dao_set_left_input(struct dao *dao, struct rsc *input)
170{
171 struct imapper *entry;
172 struct daio *daio = &dao->daio;
173 int i;
174
175 entry = kzalloc((sizeof(*entry) * daio->rscl.msr), GFP_KERNEL);
176 if (NULL == entry)
177 return -ENOMEM;
178
179 /* Program master and conjugate resources */
180 input->ops->master(input);
181 daio->rscl.ops->master(&daio->rscl);
182 for (i = 0; i < daio->rscl.msr; i++, entry++) {
183 entry->slot = input->ops->output_slot(input);
184 entry->user = entry->addr = daio->rscl.ops->index(&daio->rscl);
185 dao->mgr->imap_add(dao->mgr, entry);
186 dao->imappers[i] = entry;
187
188 input->ops->next_conj(input);
189 daio->rscl.ops->next_conj(&daio->rscl);
190 }
191 input->ops->master(input);
192 daio->rscl.ops->master(&daio->rscl);
193
194 return 0;
195}
196
197static int dao_set_right_input(struct dao *dao, struct rsc *input)
198{
199 struct imapper *entry;
200 struct daio *daio = &dao->daio;
201 int i;
202
203 entry = kzalloc((sizeof(*entry) * daio->rscr.msr), GFP_KERNEL);
204 if (NULL == entry)
205 return -ENOMEM;
206
207 /* Program master and conjugate resources */
208 input->ops->master(input);
209 daio->rscr.ops->master(&daio->rscr);
210 for (i = 0; i < daio->rscr.msr; i++, entry++) {
211 entry->slot = input->ops->output_slot(input);
212 entry->user = entry->addr = daio->rscr.ops->index(&daio->rscr);
213 dao->mgr->imap_add(dao->mgr, entry);
214 dao->imappers[daio->rscl.msr + i] = entry;
215
216 input->ops->next_conj(input);
217 daio->rscr.ops->next_conj(&daio->rscr);
218 }
219 input->ops->master(input);
220 daio->rscr.ops->master(&daio->rscr);
221
222 return 0;
223}
224
225static int dao_clear_left_input(struct dao *dao)
226{
227 struct imapper *entry;
228 struct daio *daio = &dao->daio;
229 int i;
230
231 if (NULL == dao->imappers[0])
232 return 0;
233
234 entry = dao->imappers[0];
235 dao->mgr->imap_delete(dao->mgr, entry);
236 /* Program conjugate resources */
237 for (i = 1; i < daio->rscl.msr; i++) {
238 entry = dao->imappers[i];
239 dao->mgr->imap_delete(dao->mgr, entry);
240 dao->imappers[i] = NULL;
241 }
242
243 kfree(dao->imappers[0]);
244 dao->imappers[0] = NULL;
245
246 return 0;
247}
248
249static int dao_clear_right_input(struct dao *dao)
250{
251 struct imapper *entry;
252 struct daio *daio = &dao->daio;
253 int i;
254
255 if (NULL == dao->imappers[daio->rscl.msr])
256 return 0;
257
258 entry = dao->imappers[daio->rscl.msr];
259 dao->mgr->imap_delete(dao->mgr, entry);
260 /* Program conjugate resources */
261 for (i = 1; i < daio->rscr.msr; i++) {
262 entry = dao->imappers[daio->rscl.msr + i];
263 dao->mgr->imap_delete(dao->mgr, entry);
264 dao->imappers[daio->rscl.msr + i] = NULL;
265 }
266
267 kfree(dao->imappers[daio->rscl.msr]);
268 dao->imappers[daio->rscl.msr] = NULL;
269
270 return 0;
271}
272
273static struct dao_rsc_ops dao_ops = {
274 .set_spos = dao_spdif_set_spos,
275 .commit_write = dao_commit_write,
276 .get_spos = dao_spdif_get_spos,
277 .reinit = dao_rsc_reinit,
278 .set_left_input = dao_set_left_input,
279 .set_right_input = dao_set_right_input,
280 .clear_left_input = dao_clear_left_input,
281 .clear_right_input = dao_clear_right_input,
282};
283
284static int dai_set_srt_srcl(struct dai *dai, struct rsc *src)
285{
286 src->ops->master(src);
287 ((struct hw *)dai->hw)->dai_srt_set_srcm(dai->ctrl_blk,
288 src->ops->index(src));
289 return 0;
290}
291
292static int dai_set_srt_srcr(struct dai *dai, struct rsc *src)
293{
294 src->ops->master(src);
295 ((struct hw *)dai->hw)->dai_srt_set_srco(dai->ctrl_blk,
296 src->ops->index(src));
297 return 0;
298}
299
300static int dai_set_srt_msr(struct dai *dai, unsigned int msr)
301{
302 unsigned int rsr;
303
304 for (rsr = 0; msr > 1; msr >>= 1)
305 rsr++;
306
307 ((struct hw *)dai->hw)->dai_srt_set_rsr(dai->ctrl_blk, rsr);
308 return 0;
309}
310
311static int dai_set_enb_src(struct dai *dai, unsigned int enb)
312{
313 ((struct hw *)dai->hw)->dai_srt_set_ec(dai->ctrl_blk, enb);
314 return 0;
315}
316
317static int dai_set_enb_srt(struct dai *dai, unsigned int enb)
318{
319 ((struct hw *)dai->hw)->dai_srt_set_et(dai->ctrl_blk, enb);
320 return 0;
321}
322
323static int dai_commit_write(struct dai *dai)
324{
325 ((struct hw *)dai->hw)->dai_commit_write(dai->hw,
326 daio_device_index(dai->daio.type, dai->hw), dai->ctrl_blk);
327 return 0;
328}
329
330static struct dai_rsc_ops dai_ops = {
331 .set_srt_srcl = dai_set_srt_srcl,
332 .set_srt_srcr = dai_set_srt_srcr,
333 .set_srt_msr = dai_set_srt_msr,
334 .set_enb_src = dai_set_enb_src,
335 .set_enb_srt = dai_set_enb_srt,
336 .commit_write = dai_commit_write,
337};
338
339static int daio_rsc_init(struct daio *daio,
340 const struct daio_desc *desc,
341 void *hw)
342{
343 int err;
344 unsigned int idx_l, idx_r;
345
346 switch (((struct hw *)hw)->chip_type) {
347 case ATC20K1:
348 idx_l = idx_20k1[desc->type].left;
349 idx_r = idx_20k1[desc->type].right;
350 break;
351 case ATC20K2:
352 idx_l = idx_20k2[desc->type].left;
353 idx_r = idx_20k2[desc->type].right;
354 break;
355 default:
356 return -EINVAL;
357 }
358 err = rsc_init(&daio->rscl, idx_l, DAIO, desc->msr, hw);
359 if (err)
360 return err;
361
362 err = rsc_init(&daio->rscr, idx_r, DAIO, desc->msr, hw);
363 if (err)
364 goto error1;
365
366 /* Set daio->rscl/r->ops to daio specific ones */
367 if (desc->type <= DAIO_OUT_MAX) {
368 daio->rscl.ops = daio->rscr.ops = &daio_out_rsc_ops;
369 } else {
370 switch (((struct hw *)hw)->chip_type) {
371 case ATC20K1:
372 daio->rscl.ops = daio->rscr.ops = &daio_in_rsc_ops_20k1;
373 break;
374 case ATC20K2:
375 daio->rscl.ops = daio->rscr.ops = &daio_in_rsc_ops_20k2;
376 break;
377 default:
378 break;
379 }
380 }
381 daio->type = desc->type;
382
383 return 0;
384
385error1:
386 rsc_uninit(&daio->rscl);
387 return err;
388}
389
390static int daio_rsc_uninit(struct daio *daio)
391{
392 rsc_uninit(&daio->rscl);
393 rsc_uninit(&daio->rscr);
394
395 return 0;
396}
397
398static int dao_rsc_init(struct dao *dao,
399 const struct daio_desc *desc,
400 struct daio_mgr *mgr)
401{
402 struct hw *hw = mgr->mgr.hw;
403 unsigned int conf;
404 int err;
405
406 err = daio_rsc_init(&dao->daio, desc, mgr->mgr.hw);
407 if (err)
408 return err;
409
410 dao->imappers = kzalloc(sizeof(void *)*desc->msr*2, GFP_KERNEL);
411 if (NULL == dao->imappers) {
412 err = -ENOMEM;
413 goto error1;
414 }
415 dao->ops = &dao_ops;
416 dao->mgr = mgr;
417 dao->hw = hw;
418 err = hw->dao_get_ctrl_blk(&dao->ctrl_blk);
419 if (err)
420 goto error2;
421
422 hw->daio_mgr_dsb_dao(mgr->mgr.ctrl_blk,
423 daio_device_index(dao->daio.type, hw));
424 hw->daio_mgr_commit_write(hw, mgr->mgr.ctrl_blk);
425
426 conf = (desc->msr & 0x7) | (desc->passthru << 3);
427 hw->daio_mgr_dao_init(mgr->mgr.ctrl_blk,
428 daio_device_index(dao->daio.type, hw), conf);
429 hw->daio_mgr_enb_dao(mgr->mgr.ctrl_blk,
430 daio_device_index(dao->daio.type, hw));
431 hw->daio_mgr_commit_write(hw, mgr->mgr.ctrl_blk);
432
433 return 0;
434
435error2:
436 kfree(dao->imappers);
437 dao->imappers = NULL;
438error1:
439 daio_rsc_uninit(&dao->daio);
440 return err;
441}
442
443static int dao_rsc_uninit(struct dao *dao)
444{
445 if (NULL != dao->imappers) {
446 if (NULL != dao->imappers[0])
447 dao_clear_left_input(dao);
448
449 if (NULL != dao->imappers[dao->daio.rscl.msr])
450 dao_clear_right_input(dao);
451
452 kfree(dao->imappers);
453 dao->imappers = NULL;
454 }
455 ((struct hw *)dao->hw)->dao_put_ctrl_blk(dao->ctrl_blk);
456 dao->hw = dao->ctrl_blk = NULL;
457 daio_rsc_uninit(&dao->daio);
458
459 return 0;
460}
461
462static int dao_rsc_reinit(struct dao *dao, const struct dao_desc *desc)
463{
464 struct daio_mgr *mgr = dao->mgr;
465 struct daio_desc dsc = {0};
466
467 dsc.type = dao->daio.type;
468 dsc.msr = desc->msr;
469 dsc.passthru = desc->passthru;
470 dao_rsc_uninit(dao);
471 return dao_rsc_init(dao, &dsc, mgr);
472}
473
474static int dai_rsc_init(struct dai *dai,
475 const struct daio_desc *desc,
476 struct daio_mgr *mgr)
477{
478 int err;
479 struct hw *hw = mgr->mgr.hw;
480 unsigned int rsr, msr;
481
482 err = daio_rsc_init(&dai->daio, desc, mgr->mgr.hw);
483 if (err)
484 return err;
485
486 dai->ops = &dai_ops;
487 dai->hw = mgr->mgr.hw;
488 err = hw->dai_get_ctrl_blk(&dai->ctrl_blk);
489 if (err)
490 goto error1;
491
492 for (rsr = 0, msr = desc->msr; msr > 1; msr >>= 1)
493 rsr++;
494
495 hw->dai_srt_set_rsr(dai->ctrl_blk, rsr);
496 hw->dai_srt_set_drat(dai->ctrl_blk, 0);
497 /* default to disabling control of a SRC */
498 hw->dai_srt_set_ec(dai->ctrl_blk, 0);
499 hw->dai_srt_set_et(dai->ctrl_blk, 0); /* default to disabling SRT */
500 hw->dai_commit_write(hw,
501 daio_device_index(dai->daio.type, dai->hw), dai->ctrl_blk);
502
503 return 0;
504
505error1:
506 daio_rsc_uninit(&dai->daio);
507 return err;
508}
509
510static int dai_rsc_uninit(struct dai *dai)
511{
512 ((struct hw *)dai->hw)->dai_put_ctrl_blk(dai->ctrl_blk);
513 dai->hw = dai->ctrl_blk = NULL;
514 daio_rsc_uninit(&dai->daio);
515 return 0;
516}
517
518static int daio_mgr_get_rsc(struct rsc_mgr *mgr, enum DAIOTYP type)
519{
520 if (((union daio_usage *)mgr->rscs)->data & (0x1 << type))
521 return -ENOENT;
522
523 ((union daio_usage *)mgr->rscs)->data |= (0x1 << type);
524
525 return 0;
526}
527
528static int daio_mgr_put_rsc(struct rsc_mgr *mgr, enum DAIOTYP type)
529{
530 ((union daio_usage *)mgr->rscs)->data &= ~(0x1 << type);
531
532 return 0;
533}
534
535static int get_daio_rsc(struct daio_mgr *mgr,
536 const struct daio_desc *desc,
537 struct daio **rdaio)
538{
539 int err;
540 struct dai *dai = NULL;
541 struct dao *dao = NULL;
542 unsigned long flags;
543
544 *rdaio = NULL;
545
546 /* Check whether there are sufficient daio resources to meet request. */
547 spin_lock_irqsave(&mgr->mgr_lock, flags);
548 err = daio_mgr_get_rsc(&mgr->mgr, desc->type);
549 spin_unlock_irqrestore(&mgr->mgr_lock, flags);
550 if (err) {
551 printk(KERN_ERR "Can't meet DAIO resource request!\n");
552 return err;
553 }
554
555 /* Allocate mem for daio resource */
556 if (desc->type <= DAIO_OUT_MAX) {
557 dao = kzalloc(sizeof(*dao), GFP_KERNEL);
558 if (NULL == dao) {
559 err = -ENOMEM;
560 goto error;
561 }
562 err = dao_rsc_init(dao, desc, mgr);
563 if (err)
564 goto error;
565
566 *rdaio = &dao->daio;
567 } else {
568 dai = kzalloc(sizeof(*dai), GFP_KERNEL);
569 if (NULL == dai) {
570 err = -ENOMEM;
571 goto error;
572 }
573 err = dai_rsc_init(dai, desc, mgr);
574 if (err)
575 goto error;
576
577 *rdaio = &dai->daio;
578 }
579
580 mgr->daio_enable(mgr, *rdaio);
581 mgr->commit_write(mgr);
582
583 return 0;
584
585error:
586 if (NULL != dao)
587 kfree(dao);
588 else if (NULL != dai)
589 kfree(dai);
590
591 spin_lock_irqsave(&mgr->mgr_lock, flags);
592 daio_mgr_put_rsc(&mgr->mgr, desc->type);
593 spin_unlock_irqrestore(&mgr->mgr_lock, flags);
594 return err;
595}
596
597static int put_daio_rsc(struct daio_mgr *mgr, struct daio *daio)
598{
599 unsigned long flags;
600
601 mgr->daio_disable(mgr, daio);
602 mgr->commit_write(mgr);
603
604 spin_lock_irqsave(&mgr->mgr_lock, flags);
605 daio_mgr_put_rsc(&mgr->mgr, daio->type);
606 spin_unlock_irqrestore(&mgr->mgr_lock, flags);
607
608 if (daio->type <= DAIO_OUT_MAX) {
609 dao_rsc_uninit(container_of(daio, struct dao, daio));
610 kfree(container_of(daio, struct dao, daio));
611 } else {
612 dai_rsc_uninit(container_of(daio, struct dai, daio));
613 kfree(container_of(daio, struct dai, daio));
614 }
615
616 return 0;
617}
618
619static int daio_mgr_enb_daio(struct daio_mgr *mgr, struct daio *daio)
620{
621 struct hw *hw = mgr->mgr.hw;
622
623 if (DAIO_OUT_MAX >= daio->type) {
624 hw->daio_mgr_enb_dao(mgr->mgr.ctrl_blk,
625 daio_device_index(daio->type, hw));
626 } else {
627 hw->daio_mgr_enb_dai(mgr->mgr.ctrl_blk,
628 daio_device_index(daio->type, hw));
629 }
630 return 0;
631}
632
633static int daio_mgr_dsb_daio(struct daio_mgr *mgr, struct daio *daio)
634{
635 struct hw *hw = mgr->mgr.hw;
636
637 if (DAIO_OUT_MAX >= daio->type) {
638 hw->daio_mgr_dsb_dao(mgr->mgr.ctrl_blk,
639 daio_device_index(daio->type, hw));
640 } else {
641 hw->daio_mgr_dsb_dai(mgr->mgr.ctrl_blk,
642 daio_device_index(daio->type, hw));
643 }
644 return 0;
645}
646
647static int daio_map_op(void *data, struct imapper *entry)
648{
649 struct rsc_mgr *mgr = &((struct daio_mgr *)data)->mgr;
650 struct hw *hw = mgr->hw;
651
652 hw->daio_mgr_set_imaparc(mgr->ctrl_blk, entry->slot);
653 hw->daio_mgr_set_imapnxt(mgr->ctrl_blk, entry->next);
654 hw->daio_mgr_set_imapaddr(mgr->ctrl_blk, entry->addr);
655 hw->daio_mgr_commit_write(mgr->hw, mgr->ctrl_blk);
656
657 return 0;
658}
659
660static int daio_imap_add(struct daio_mgr *mgr, struct imapper *entry)
661{
662 unsigned long flags;
663 int err;
664
665 spin_lock_irqsave(&mgr->imap_lock, flags);
666 if ((0 == entry->addr) && (mgr->init_imap_added)) {
667 input_mapper_delete(&mgr->imappers, mgr->init_imap,
668 daio_map_op, mgr);
669 mgr->init_imap_added = 0;
670 }
671 err = input_mapper_add(&mgr->imappers, entry, daio_map_op, mgr);
672 spin_unlock_irqrestore(&mgr->imap_lock, flags);
673
674 return err;
675}
676
677static int daio_imap_delete(struct daio_mgr *mgr, struct imapper *entry)
678{
679 unsigned long flags;
680 int err;
681
682 spin_lock_irqsave(&mgr->imap_lock, flags);
683 err = input_mapper_delete(&mgr->imappers, entry, daio_map_op, mgr);
684 if (list_empty(&mgr->imappers)) {
685 input_mapper_add(&mgr->imappers, mgr->init_imap,
686 daio_map_op, mgr);
687 mgr->init_imap_added = 1;
688 }
689 spin_unlock_irqrestore(&mgr->imap_lock, flags);
690
691 return err;
692}
693
694static int daio_mgr_commit_write(struct daio_mgr *mgr)
695{
696 struct hw *hw = mgr->mgr.hw;
697
698 hw->daio_mgr_commit_write(hw, mgr->mgr.ctrl_blk);
699 return 0;
700}
701
702int daio_mgr_create(void *hw, struct daio_mgr **rdaio_mgr)
703{
704 int err, i;
705 struct daio_mgr *daio_mgr;
706 struct imapper *entry;
707
708 *rdaio_mgr = NULL;
709 daio_mgr = kzalloc(sizeof(*daio_mgr), GFP_KERNEL);
710 if (NULL == daio_mgr)
711 return -ENOMEM;
712
713 err = rsc_mgr_init(&daio_mgr->mgr, DAIO, DAIO_RESOURCE_NUM, hw);
714 if (err)
715 goto error1;
716
717 spin_lock_init(&daio_mgr->mgr_lock);
718 spin_lock_init(&daio_mgr->imap_lock);
719 INIT_LIST_HEAD(&daio_mgr->imappers);
720 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
721 if (NULL == entry) {
722 err = -ENOMEM;
723 goto error2;
724 }
725 entry->slot = entry->addr = entry->next = entry->user = 0;
726 list_add(&entry->list, &daio_mgr->imappers);
727 daio_mgr->init_imap = entry;
728 daio_mgr->init_imap_added = 1;
729
730 daio_mgr->get_daio = get_daio_rsc;
731 daio_mgr->put_daio = put_daio_rsc;
732 daio_mgr->daio_enable = daio_mgr_enb_daio;
733 daio_mgr->daio_disable = daio_mgr_dsb_daio;
734 daio_mgr->imap_add = daio_imap_add;
735 daio_mgr->imap_delete = daio_imap_delete;
736 daio_mgr->commit_write = daio_mgr_commit_write;
737
738 for (i = 0; i < 8; i++) {
739 ((struct hw *)hw)->daio_mgr_dsb_dao(daio_mgr->mgr.ctrl_blk, i);
740 ((struct hw *)hw)->daio_mgr_dsb_dai(daio_mgr->mgr.ctrl_blk, i);
741 }
742 ((struct hw *)hw)->daio_mgr_commit_write(hw, daio_mgr->mgr.ctrl_blk);
743
744 *rdaio_mgr = daio_mgr;
745
746 return 0;
747
748error2:
749 rsc_mgr_uninit(&daio_mgr->mgr);
750error1:
751 kfree(daio_mgr);
752 return err;
753}
754
755int daio_mgr_destroy(struct daio_mgr *daio_mgr)
756{
757 unsigned long flags;
758
759 /* free daio input mapper list */
760 spin_lock_irqsave(&daio_mgr->imap_lock, flags);
761 free_input_mapper_list(&daio_mgr->imappers);
762 spin_unlock_irqrestore(&daio_mgr->imap_lock, flags);
763
764 rsc_mgr_uninit(&daio_mgr->mgr);
765 kfree(daio_mgr);
766
767 return 0;
768}
769
diff --git a/sound/pci/ctxfi/ctdaio.h b/sound/pci/ctxfi/ctdaio.h
new file mode 100644
index 00000000000..0f52ce571ee
--- /dev/null
+++ b/sound/pci/ctxfi/ctdaio.h
@@ -0,0 +1,122 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File ctdaio.h
9 *
10 * @Brief
11 * This file contains the definition of Digital Audio Input Output
12 * resource management object.
13 *
14 * @Author Liu Chun
15 * @Date May 23 2008
16 *
17 */
18
19#ifndef CTDAIO_H
20#define CTDAIO_H
21
22#include "ctresource.h"
23#include "ctimap.h"
24#include <linux/spinlock.h>
25#include <linux/list.h>
26
27/* Define the descriptor of a daio resource */
28enum DAIOTYP {
29 LINEO1,
30 LINEO2,
31 LINEO3,
32 LINEO4,
33 SPDIFOO, /* S/PDIF Out (Flexijack/Optical) */
34 LINEIM,
35 SPDIFIO, /* S/PDIF In (Flexijack/Optical) on the card */
36 SPDIFI1, /* S/PDIF In on internal Drive Bay */
37 NUM_DAIOTYP
38};
39
40struct dao_rsc_ops;
41struct dai_rsc_ops;
42struct daio_mgr;
43
44struct daio {
45 struct rsc rscl; /* Basic resource info for left TX/RX */
46 struct rsc rscr; /* Basic resource info for right TX/RX */
47 enum DAIOTYP type;
48};
49
50struct dao {
51 struct daio daio;
52 struct dao_rsc_ops *ops; /* DAO specific operations */
53 struct imapper **imappers;
54 struct daio_mgr *mgr;
55 void *hw;
56 void *ctrl_blk;
57};
58
59struct dai {
60 struct daio daio;
61 struct dai_rsc_ops *ops; /* DAI specific operations */
62 void *hw;
63 void *ctrl_blk;
64};
65
66struct dao_desc {
67 unsigned int msr:4;
68 unsigned int passthru:1;
69};
70
71struct dao_rsc_ops {
72 int (*set_spos)(struct dao *dao, unsigned int spos);
73 int (*commit_write)(struct dao *dao);
74 int (*get_spos)(struct dao *dao, unsigned int *spos);
75 int (*reinit)(struct dao *dao, const struct dao_desc *desc);
76 int (*set_left_input)(struct dao *dao, struct rsc *input);
77 int (*set_right_input)(struct dao *dao, struct rsc *input);
78 int (*clear_left_input)(struct dao *dao);
79 int (*clear_right_input)(struct dao *dao);
80};
81
82struct dai_rsc_ops {
83 int (*set_srt_srcl)(struct dai *dai, struct rsc *src);
84 int (*set_srt_srcr)(struct dai *dai, struct rsc *src);
85 int (*set_srt_msr)(struct dai *dai, unsigned int msr);
86 int (*set_enb_src)(struct dai *dai, unsigned int enb);
87 int (*set_enb_srt)(struct dai *dai, unsigned int enb);
88 int (*commit_write)(struct dai *dai);
89};
90
91/* Define daio resource request description info */
92struct daio_desc {
93 unsigned int type:4;
94 unsigned int msr:4;
95 unsigned int passthru:1;
96};
97
98struct daio_mgr {
99 struct rsc_mgr mgr; /* Basic resource manager info */
100 spinlock_t mgr_lock;
101 spinlock_t imap_lock;
102 struct list_head imappers;
103 struct imapper *init_imap;
104 unsigned int init_imap_added;
105
106 /* request one daio resource */
107 int (*get_daio)(struct daio_mgr *mgr,
108 const struct daio_desc *desc, struct daio **rdaio);
109 /* return one daio resource */
110 int (*put_daio)(struct daio_mgr *mgr, struct daio *daio);
111 int (*daio_enable)(struct daio_mgr *mgr, struct daio *daio);
112 int (*daio_disable)(struct daio_mgr *mgr, struct daio *daio);
113 int (*imap_add)(struct daio_mgr *mgr, struct imapper *entry);
114 int (*imap_delete)(struct daio_mgr *mgr, struct imapper *entry);
115 int (*commit_write)(struct daio_mgr *mgr);
116};
117
118/* Constructor and destructor of daio resource manager */
119int daio_mgr_create(void *hw, struct daio_mgr **rdaio_mgr);
120int daio_mgr_destroy(struct daio_mgr *daio_mgr);
121
122#endif /* CTDAIO_H */
diff --git a/sound/pci/ctxfi/cthardware.c b/sound/pci/ctxfi/cthardware.c
new file mode 100644
index 00000000000..8e64f4862e8
--- /dev/null
+++ b/sound/pci/ctxfi/cthardware.c
@@ -0,0 +1,91 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File cthardware.c
9 *
10 * @Brief
11 * This file contains the implementation of hardware access methord.
12 *
13 * @Author Liu Chun
14 * @Date Jun 26 2008
15 *
16 */
17
18#include "cthardware.h"
19#include "cthw20k1.h"
20#include "cthw20k2.h"
21#include <linux/bug.h>
22
23int __devinit create_hw_obj(struct pci_dev *pci, enum CHIPTYP chip_type,
24 enum CTCARDS model, struct hw **rhw)
25{
26 int err;
27
28 switch (chip_type) {
29 case ATC20K1:
30 err = create_20k1_hw_obj(rhw);
31 break;
32 case ATC20K2:
33 err = create_20k2_hw_obj(rhw);
34 break;
35 default:
36 err = -ENODEV;
37 break;
38 }
39 if (err)
40 return err;
41
42 (*rhw)->pci = pci;
43 (*rhw)->chip_type = chip_type;
44 (*rhw)->model = model;
45
46 return 0;
47}
48
49int destroy_hw_obj(struct hw *hw)
50{
51 int err;
52
53 switch (hw->pci->device) {
54 case 0x0005: /* 20k1 device */
55 err = destroy_20k1_hw_obj(hw);
56 break;
57 case 0x000B: /* 20k2 device */
58 err = destroy_20k2_hw_obj(hw);
59 break;
60 default:
61 err = -ENODEV;
62 break;
63 }
64
65 return err;
66}
67
68unsigned int get_field(unsigned int data, unsigned int field)
69{
70 int i;
71
72 BUG_ON(!field);
73 /* @field should always be greater than 0 */
74 for (i = 0; !(field & (1 << i)); )
75 i++;
76
77 return (data & field) >> i;
78}
79
80void set_field(unsigned int *data, unsigned int field, unsigned int value)
81{
82 int i;
83
84 BUG_ON(!field);
85 /* @field should always be greater than 0 */
86 for (i = 0; !(field & (1 << i)); )
87 i++;
88
89 *data = (*data & (~field)) | ((value << i) & field);
90}
91
diff --git a/sound/pci/ctxfi/cthardware.h b/sound/pci/ctxfi/cthardware.h
new file mode 100644
index 00000000000..4a8e04f090a
--- /dev/null
+++ b/sound/pci/ctxfi/cthardware.h
@@ -0,0 +1,196 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File cthardware.h
9 *
10 * @Brief
11 * This file contains the definition of hardware access methord.
12 *
13 * @Author Liu Chun
14 * @Date May 13 2008
15 *
16 */
17
18#ifndef CTHARDWARE_H
19#define CTHARDWARE_H
20
21#include <linux/types.h>
22#include <linux/pci.h>
23
24enum CHIPTYP {
25 ATC20K1,
26 ATC20K2,
27 ATCNONE
28};
29
30enum CTCARDS {
31 /* 20k1 models */
32 CTSB055X,
33 CTSB073X,
34 CTUAA,
35 CT20K1_UNKNOWN,
36 /* 20k2 models */
37 CTSB0760,
38 CTHENDRIX,
39 CTSB0880,
40 NUM_CTCARDS /* This should always be the last */
41};
42
43/* Type of input source for ADC */
44enum ADCSRC{
45 ADC_MICIN,
46 ADC_LINEIN,
47 ADC_VIDEO,
48 ADC_AUX,
49 ADC_NONE /* Switch to digital input */
50};
51
52struct card_conf {
53 /* device virtual mem page table page physical addr
54 * (supporting one page table page now) */
55 unsigned long vm_pgt_phys;
56 unsigned int rsr; /* reference sample rate in Hzs*/
57 unsigned int msr; /* master sample rate in rsrs */
58};
59
60struct hw {
61 int (*card_init)(struct hw *hw, struct card_conf *info);
62 int (*card_stop)(struct hw *hw);
63 int (*pll_init)(struct hw *hw, unsigned int rsr);
64 int (*is_adc_source_selected)(struct hw *hw, enum ADCSRC source);
65 int (*select_adc_source)(struct hw *hw, enum ADCSRC source);
66 int (*have_digit_io_switch)(struct hw *hw);
67
68 /* SRC operations */
69 int (*src_rsc_get_ctrl_blk)(void **rblk);
70 int (*src_rsc_put_ctrl_blk)(void *blk);
71 int (*src_set_state)(void *blk, unsigned int state);
72 int (*src_set_bm)(void *blk, unsigned int bm);
73 int (*src_set_rsr)(void *blk, unsigned int rsr);
74 int (*src_set_sf)(void *blk, unsigned int sf);
75 int (*src_set_wr)(void *blk, unsigned int wr);
76 int (*src_set_pm)(void *blk, unsigned int pm);
77 int (*src_set_rom)(void *blk, unsigned int rom);
78 int (*src_set_vo)(void *blk, unsigned int vo);
79 int (*src_set_st)(void *blk, unsigned int st);
80 int (*src_set_ie)(void *blk, unsigned int ie);
81 int (*src_set_ilsz)(void *blk, unsigned int ilsz);
82 int (*src_set_bp)(void *blk, unsigned int bp);
83 int (*src_set_cisz)(void *blk, unsigned int cisz);
84 int (*src_set_ca)(void *blk, unsigned int ca);
85 int (*src_set_sa)(void *blk, unsigned int sa);
86 int (*src_set_la)(void *blk, unsigned int la);
87 int (*src_set_pitch)(void *blk, unsigned int pitch);
88 int (*src_set_clear_zbufs)(void *blk, unsigned int clear);
89 int (*src_set_dirty)(void *blk, unsigned int flags);
90 int (*src_set_dirty_all)(void *blk);
91 int (*src_commit_write)(struct hw *hw, unsigned int idx, void *blk);
92 int (*src_get_ca)(struct hw *hw, unsigned int idx, void *blk);
93 unsigned int (*src_get_dirty)(void *blk);
94 unsigned int (*src_dirty_conj_mask)(void);
95 int (*src_mgr_get_ctrl_blk)(void **rblk);
96 int (*src_mgr_put_ctrl_blk)(void *blk);
97 /* syncly enable src @idx */
98 int (*src_mgr_enbs_src)(void *blk, unsigned int idx);
99 /* enable src @idx */
100 int (*src_mgr_enb_src)(void *blk, unsigned int idx);
101 /* disable src @idx */
102 int (*src_mgr_dsb_src)(void *blk, unsigned int idx);
103 int (*src_mgr_commit_write)(struct hw *hw, void *blk);
104
105 /* SRC Input Mapper operations */
106 int (*srcimp_mgr_get_ctrl_blk)(void **rblk);
107 int (*srcimp_mgr_put_ctrl_blk)(void *blk);
108 int (*srcimp_mgr_set_imaparc)(void *blk, unsigned int slot);
109 int (*srcimp_mgr_set_imapuser)(void *blk, unsigned int user);
110 int (*srcimp_mgr_set_imapnxt)(void *blk, unsigned int next);
111 int (*srcimp_mgr_set_imapaddr)(void *blk, unsigned int addr);
112 int (*srcimp_mgr_commit_write)(struct hw *hw, void *blk);
113
114 /* AMIXER operations */
115 int (*amixer_rsc_get_ctrl_blk)(void **rblk);
116 int (*amixer_rsc_put_ctrl_blk)(void *blk);
117 int (*amixer_mgr_get_ctrl_blk)(void **rblk);
118 int (*amixer_mgr_put_ctrl_blk)(void *blk);
119 int (*amixer_set_mode)(void *blk, unsigned int mode);
120 int (*amixer_set_iv)(void *blk, unsigned int iv);
121 int (*amixer_set_x)(void *blk, unsigned int x);
122 int (*amixer_set_y)(void *blk, unsigned int y);
123 int (*amixer_set_sadr)(void *blk, unsigned int sadr);
124 int (*amixer_set_se)(void *blk, unsigned int se);
125 int (*amixer_set_dirty)(void *blk, unsigned int flags);
126 int (*amixer_set_dirty_all)(void *blk);
127 int (*amixer_commit_write)(struct hw *hw, unsigned int idx, void *blk);
128 int (*amixer_get_y)(void *blk);
129 unsigned int (*amixer_get_dirty)(void *blk);
130
131 /* DAIO operations */
132 int (*dai_get_ctrl_blk)(void **rblk);
133 int (*dai_put_ctrl_blk)(void *blk);
134 int (*dai_srt_set_srco)(void *blk, unsigned int src);
135 int (*dai_srt_set_srcm)(void *blk, unsigned int src);
136 int (*dai_srt_set_rsr)(void *blk, unsigned int rsr);
137 int (*dai_srt_set_drat)(void *blk, unsigned int drat);
138 int (*dai_srt_set_ec)(void *blk, unsigned int ec);
139 int (*dai_srt_set_et)(void *blk, unsigned int et);
140 int (*dai_commit_write)(struct hw *hw, unsigned int idx, void *blk);
141 int (*dao_get_ctrl_blk)(void **rblk);
142 int (*dao_put_ctrl_blk)(void *blk);
143 int (*dao_set_spos)(void *blk, unsigned int spos);
144 int (*dao_commit_write)(struct hw *hw, unsigned int idx, void *blk);
145 int (*dao_get_spos)(void *blk, unsigned int *spos);
146
147 int (*daio_mgr_get_ctrl_blk)(struct hw *hw, void **rblk);
148 int (*daio_mgr_put_ctrl_blk)(void *blk);
149 int (*daio_mgr_enb_dai)(void *blk, unsigned int idx);
150 int (*daio_mgr_dsb_dai)(void *blk, unsigned int idx);
151 int (*daio_mgr_enb_dao)(void *blk, unsigned int idx);
152 int (*daio_mgr_dsb_dao)(void *blk, unsigned int idx);
153 int (*daio_mgr_dao_init)(void *blk, unsigned int idx,
154 unsigned int conf);
155 int (*daio_mgr_set_imaparc)(void *blk, unsigned int slot);
156 int (*daio_mgr_set_imapnxt)(void *blk, unsigned int next);
157 int (*daio_mgr_set_imapaddr)(void *blk, unsigned int addr);
158 int (*daio_mgr_commit_write)(struct hw *hw, void *blk);
159
160 int (*set_timer_irq)(struct hw *hw, int enable);
161 int (*set_timer_tick)(struct hw *hw, unsigned int tick);
162 unsigned int (*get_wc)(struct hw *hw);
163
164 void (*irq_callback)(void *data, unsigned int bit);
165 void *irq_callback_data;
166
167 struct pci_dev *pci; /* the pci kernel structure of this card */
168 int irq;
169 unsigned long io_base;
170 unsigned long mem_base;
171
172 enum CHIPTYP chip_type;
173 enum CTCARDS model;
174};
175
176int create_hw_obj(struct pci_dev *pci, enum CHIPTYP chip_type,
177 enum CTCARDS model, struct hw **rhw);
178int destroy_hw_obj(struct hw *hw);
179
180unsigned int get_field(unsigned int data, unsigned int field);
181void set_field(unsigned int *data, unsigned int field, unsigned int value);
182
183/* IRQ bits */
184#define PLL_INT (1 << 10) /* PLL input-clock out-of-range */
185#define FI_INT (1 << 9) /* forced interrupt */
186#define IT_INT (1 << 8) /* timer interrupt */
187#define PCI_INT (1 << 7) /* PCI bus error pending */
188#define URT_INT (1 << 6) /* UART Tx/Rx */
189#define GPI_INT (1 << 5) /* GPI pin */
190#define MIX_INT (1 << 4) /* mixer parameter segment FIFO channels */
191#define DAI_INT (1 << 3) /* DAI (SR-tracker or SPDIF-receiver) */
192#define TP_INT (1 << 2) /* transport priority queue */
193#define DSP_INT (1 << 1) /* DSP */
194#define SRC_INT (1 << 0) /* SRC channels */
195
196#endif /* CTHARDWARE_H */
diff --git a/sound/pci/ctxfi/cthw20k1.c b/sound/pci/ctxfi/cthw20k1.c
new file mode 100644
index 00000000000..cb69d9ddfbe
--- /dev/null
+++ b/sound/pci/ctxfi/cthw20k1.c
@@ -0,0 +1,2248 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File cthw20k1.c
9 *
10 * @Brief
11 * This file contains the implementation of hardware access methord for 20k1.
12 *
13 * @Author Liu Chun
14 * @Date Jun 24 2008
15 *
16 */
17
18#include <linux/types.h>
19#include <linux/slab.h>
20#include <linux/pci.h>
21#include <linux/io.h>
22#include <linux/string.h>
23#include <linux/spinlock.h>
24#include <linux/kernel.h>
25#include <linux/interrupt.h>
26#include <linux/delay.h>
27#include "cthw20k1.h"
28#include "ct20k1reg.h"
29
30#if BITS_PER_LONG == 32
31#define CT_XFI_DMA_MASK DMA_BIT_MASK(32) /* 32 bit PTE */
32#else
33#define CT_XFI_DMA_MASK DMA_BIT_MASK(64) /* 64 bit PTE */
34#endif
35
36struct hw20k1 {
37 struct hw hw;
38 spinlock_t reg_20k1_lock;
39 spinlock_t reg_pci_lock;
40};
41
42static u32 hw_read_20kx(struct hw *hw, u32 reg);
43static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
44static u32 hw_read_pci(struct hw *hw, u32 reg);
45static void hw_write_pci(struct hw *hw, u32 reg, u32 data);
46
47/*
48 * Type definition block.
49 * The layout of control structures can be directly applied on 20k2 chip.
50 */
51
52/*
53 * SRC control block definitions.
54 */
55
56/* SRC resource control block */
57#define SRCCTL_STATE 0x00000007
58#define SRCCTL_BM 0x00000008
59#define SRCCTL_RSR 0x00000030
60#define SRCCTL_SF 0x000001C0
61#define SRCCTL_WR 0x00000200
62#define SRCCTL_PM 0x00000400
63#define SRCCTL_ROM 0x00001800
64#define SRCCTL_VO 0x00002000
65#define SRCCTL_ST 0x00004000
66#define SRCCTL_IE 0x00008000
67#define SRCCTL_ILSZ 0x000F0000
68#define SRCCTL_BP 0x00100000
69
70#define SRCCCR_CISZ 0x000007FF
71#define SRCCCR_CWA 0x001FF800
72#define SRCCCR_D 0x00200000
73#define SRCCCR_RS 0x01C00000
74#define SRCCCR_NAL 0x3E000000
75#define SRCCCR_RA 0xC0000000
76
77#define SRCCA_CA 0x03FFFFFF
78#define SRCCA_RS 0x1C000000
79#define SRCCA_NAL 0xE0000000
80
81#define SRCSA_SA 0x03FFFFFF
82
83#define SRCLA_LA 0x03FFFFFF
84
85/* Mixer Parameter Ring ram Low and Hight register.
86 * Fixed-point value in 8.24 format for parameter channel */
87#define MPRLH_PITCH 0xFFFFFFFF
88
89/* SRC resource register dirty flags */
90union src_dirty {
91 struct {
92 u16 ctl:1;
93 u16 ccr:1;
94 u16 sa:1;
95 u16 la:1;
96 u16 ca:1;
97 u16 mpr:1;
98 u16 czbfs:1; /* Clear Z-Buffers */
99 u16 rsv:9;
100 } bf;
101 u16 data;
102};
103
104struct src_rsc_ctrl_blk {
105 unsigned int ctl;
106 unsigned int ccr;
107 unsigned int ca;
108 unsigned int sa;
109 unsigned int la;
110 unsigned int mpr;
111 union src_dirty dirty;
112};
113
114/* SRC manager control block */
115union src_mgr_dirty {
116 struct {
117 u16 enb0:1;
118 u16 enb1:1;
119 u16 enb2:1;
120 u16 enb3:1;
121 u16 enb4:1;
122 u16 enb5:1;
123 u16 enb6:1;
124 u16 enb7:1;
125 u16 enbsa:1;
126 u16 rsv:7;
127 } bf;
128 u16 data;
129};
130
131struct src_mgr_ctrl_blk {
132 unsigned int enbsa;
133 unsigned int enb[8];
134 union src_mgr_dirty dirty;
135};
136
137/* SRCIMP manager control block */
138#define SRCAIM_ARC 0x00000FFF
139#define SRCAIM_NXT 0x00FF0000
140#define SRCAIM_SRC 0xFF000000
141
142struct srcimap {
143 unsigned int srcaim;
144 unsigned int idx;
145};
146
147/* SRCIMP manager register dirty flags */
148union srcimp_mgr_dirty {
149 struct {
150 u16 srcimap:1;
151 u16 rsv:15;
152 } bf;
153 u16 data;
154};
155
156struct srcimp_mgr_ctrl_blk {
157 struct srcimap srcimap;
158 union srcimp_mgr_dirty dirty;
159};
160
161/*
162 * Function implementation block.
163 */
164
165static int src_get_rsc_ctrl_blk(void **rblk)
166{
167 struct src_rsc_ctrl_blk *blk;
168
169 *rblk = NULL;
170 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
171 if (NULL == blk)
172 return -ENOMEM;
173
174 *rblk = blk;
175
176 return 0;
177}
178
179static int src_put_rsc_ctrl_blk(void *blk)
180{
181 kfree((struct src_rsc_ctrl_blk *)blk);
182
183 return 0;
184}
185
186static int src_set_state(void *blk, unsigned int state)
187{
188 struct src_rsc_ctrl_blk *ctl = blk;
189
190 set_field(&ctl->ctl, SRCCTL_STATE, state);
191 ctl->dirty.bf.ctl = 1;
192 return 0;
193}
194
195static int src_set_bm(void *blk, unsigned int bm)
196{
197 struct src_rsc_ctrl_blk *ctl = blk;
198
199 set_field(&ctl->ctl, SRCCTL_BM, bm);
200 ctl->dirty.bf.ctl = 1;
201 return 0;
202}
203
204static int src_set_rsr(void *blk, unsigned int rsr)
205{
206 struct src_rsc_ctrl_blk *ctl = blk;
207
208 set_field(&ctl->ctl, SRCCTL_RSR, rsr);
209 ctl->dirty.bf.ctl = 1;
210 return 0;
211}
212
213static int src_set_sf(void *blk, unsigned int sf)
214{
215 struct src_rsc_ctrl_blk *ctl = blk;
216
217 set_field(&ctl->ctl, SRCCTL_SF, sf);
218 ctl->dirty.bf.ctl = 1;
219 return 0;
220}
221
222static int src_set_wr(void *blk, unsigned int wr)
223{
224 struct src_rsc_ctrl_blk *ctl = blk;
225
226 set_field(&ctl->ctl, SRCCTL_WR, wr);
227 ctl->dirty.bf.ctl = 1;
228 return 0;
229}
230
231static int src_set_pm(void *blk, unsigned int pm)
232{
233 struct src_rsc_ctrl_blk *ctl = blk;
234
235 set_field(&ctl->ctl, SRCCTL_PM, pm);
236 ctl->dirty.bf.ctl = 1;
237 return 0;
238}
239
240static int src_set_rom(void *blk, unsigned int rom)
241{
242 struct src_rsc_ctrl_blk *ctl = blk;
243
244 set_field(&ctl->ctl, SRCCTL_ROM, rom);
245 ctl->dirty.bf.ctl = 1;
246 return 0;
247}
248
249static int src_set_vo(void *blk, unsigned int vo)
250{
251 struct src_rsc_ctrl_blk *ctl = blk;
252
253 set_field(&ctl->ctl, SRCCTL_VO, vo);
254 ctl->dirty.bf.ctl = 1;
255 return 0;
256}
257
258static int src_set_st(void *blk, unsigned int st)
259{
260 struct src_rsc_ctrl_blk *ctl = blk;
261
262 set_field(&ctl->ctl, SRCCTL_ST, st);
263 ctl->dirty.bf.ctl = 1;
264 return 0;
265}
266
267static int src_set_ie(void *blk, unsigned int ie)
268{
269 struct src_rsc_ctrl_blk *ctl = blk;
270
271 set_field(&ctl->ctl, SRCCTL_IE, ie);
272 ctl->dirty.bf.ctl = 1;
273 return 0;
274}
275
276static int src_set_ilsz(void *blk, unsigned int ilsz)
277{
278 struct src_rsc_ctrl_blk *ctl = blk;
279
280 set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
281 ctl->dirty.bf.ctl = 1;
282 return 0;
283}
284
285static int src_set_bp(void *blk, unsigned int bp)
286{
287 struct src_rsc_ctrl_blk *ctl = blk;
288
289 set_field(&ctl->ctl, SRCCTL_BP, bp);
290 ctl->dirty.bf.ctl = 1;
291 return 0;
292}
293
294static int src_set_cisz(void *blk, unsigned int cisz)
295{
296 struct src_rsc_ctrl_blk *ctl = blk;
297
298 set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
299 ctl->dirty.bf.ccr = 1;
300 return 0;
301}
302
303static int src_set_ca(void *blk, unsigned int ca)
304{
305 struct src_rsc_ctrl_blk *ctl = blk;
306
307 set_field(&ctl->ca, SRCCA_CA, ca);
308 ctl->dirty.bf.ca = 1;
309 return 0;
310}
311
312static int src_set_sa(void *blk, unsigned int sa)
313{
314 struct src_rsc_ctrl_blk *ctl = blk;
315
316 set_field(&ctl->sa, SRCSA_SA, sa);
317 ctl->dirty.bf.sa = 1;
318 return 0;
319}
320
321static int src_set_la(void *blk, unsigned int la)
322{
323 struct src_rsc_ctrl_blk *ctl = blk;
324
325 set_field(&ctl->la, SRCLA_LA, la);
326 ctl->dirty.bf.la = 1;
327 return 0;
328}
329
330static int src_set_pitch(void *blk, unsigned int pitch)
331{
332 struct src_rsc_ctrl_blk *ctl = blk;
333
334 set_field(&ctl->mpr, MPRLH_PITCH, pitch);
335 ctl->dirty.bf.mpr = 1;
336 return 0;
337}
338
339static int src_set_clear_zbufs(void *blk, unsigned int clear)
340{
341 ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
342 return 0;
343}
344
345static int src_set_dirty(void *blk, unsigned int flags)
346{
347 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
348 return 0;
349}
350
351static int src_set_dirty_all(void *blk)
352{
353 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
354 return 0;
355}
356
357#define AR_SLOT_SIZE 4096
358#define AR_SLOT_BLOCK_SIZE 16
359#define AR_PTS_PITCH 6
360#define AR_PARAM_SRC_OFFSET 0x60
361
362static unsigned int src_param_pitch_mixer(unsigned int src_idx)
363{
364 return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE
365 - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
366
367}
368
369static int src_commit_write(struct hw *hw, unsigned int idx, void *blk)
370{
371 struct src_rsc_ctrl_blk *ctl = blk;
372 int i;
373
374 if (ctl->dirty.bf.czbfs) {
375 /* Clear Z-Buffer registers */
376 for (i = 0; i < 8; i++)
377 hw_write_20kx(hw, SRCUPZ+idx*0x100+i*0x4, 0);
378
379 for (i = 0; i < 4; i++)
380 hw_write_20kx(hw, SRCDN0Z+idx*0x100+i*0x4, 0);
381
382 for (i = 0; i < 8; i++)
383 hw_write_20kx(hw, SRCDN1Z+idx*0x100+i*0x4, 0);
384
385 ctl->dirty.bf.czbfs = 0;
386 }
387 if (ctl->dirty.bf.mpr) {
388 /* Take the parameter mixer resource in the same group as that
389 * the idx src is in for simplicity. Unlike src, all conjugate
390 * parameter mixer resources must be programmed for
391 * corresponding conjugate src resources. */
392 unsigned int pm_idx = src_param_pitch_mixer(idx);
393 hw_write_20kx(hw, PRING_LO_HI+4*pm_idx, ctl->mpr);
394 hw_write_20kx(hw, PMOPLO+8*pm_idx, 0x3);
395 hw_write_20kx(hw, PMOPHI+8*pm_idx, 0x0);
396 ctl->dirty.bf.mpr = 0;
397 }
398 if (ctl->dirty.bf.sa) {
399 hw_write_20kx(hw, SRCSA+idx*0x100, ctl->sa);
400 ctl->dirty.bf.sa = 0;
401 }
402 if (ctl->dirty.bf.la) {
403 hw_write_20kx(hw, SRCLA+idx*0x100, ctl->la);
404 ctl->dirty.bf.la = 0;
405 }
406 if (ctl->dirty.bf.ca) {
407 hw_write_20kx(hw, SRCCA+idx*0x100, ctl->ca);
408 ctl->dirty.bf.ca = 0;
409 }
410
411 /* Write srccf register */
412 hw_write_20kx(hw, SRCCF+idx*0x100, 0x0);
413
414 if (ctl->dirty.bf.ccr) {
415 hw_write_20kx(hw, SRCCCR+idx*0x100, ctl->ccr);
416 ctl->dirty.bf.ccr = 0;
417 }
418 if (ctl->dirty.bf.ctl) {
419 hw_write_20kx(hw, SRCCTL+idx*0x100, ctl->ctl);
420 ctl->dirty.bf.ctl = 0;
421 }
422
423 return 0;
424}
425
426static int src_get_ca(struct hw *hw, unsigned int idx, void *blk)
427{
428 struct src_rsc_ctrl_blk *ctl = blk;
429
430 ctl->ca = hw_read_20kx(hw, SRCCA+idx*0x100);
431 ctl->dirty.bf.ca = 0;
432
433 return get_field(ctl->ca, SRCCA_CA);
434}
435
436static unsigned int src_get_dirty(void *blk)
437{
438 return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
439}
440
441static unsigned int src_dirty_conj_mask(void)
442{
443 return 0x20;
444}
445
446static int src_mgr_enbs_src(void *blk, unsigned int idx)
447{
448 ((struct src_mgr_ctrl_blk *)blk)->enbsa = ~(0x0);
449 ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
450 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
451 return 0;
452}
453
454static int src_mgr_enb_src(void *blk, unsigned int idx)
455{
456 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
457 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
458 return 0;
459}
460
461static int src_mgr_dsb_src(void *blk, unsigned int idx)
462{
463 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
464 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
465 return 0;
466}
467
468static int src_mgr_commit_write(struct hw *hw, void *blk)
469{
470 struct src_mgr_ctrl_blk *ctl = blk;
471 int i;
472 unsigned int ret;
473
474 if (ctl->dirty.bf.enbsa) {
475 do {
476 ret = hw_read_20kx(hw, SRCENBSTAT);
477 } while (ret & 0x1);
478 hw_write_20kx(hw, SRCENBS, ctl->enbsa);
479 ctl->dirty.bf.enbsa = 0;
480 }
481 for (i = 0; i < 8; i++) {
482 if ((ctl->dirty.data & (0x1 << i))) {
483 hw_write_20kx(hw, SRCENB+(i*0x100), ctl->enb[i]);
484 ctl->dirty.data &= ~(0x1 << i);
485 }
486 }
487
488 return 0;
489}
490
491static int src_mgr_get_ctrl_blk(void **rblk)
492{
493 struct src_mgr_ctrl_blk *blk;
494
495 *rblk = NULL;
496 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
497 if (NULL == blk)
498 return -ENOMEM;
499
500 *rblk = blk;
501
502 return 0;
503}
504
505static int src_mgr_put_ctrl_blk(void *blk)
506{
507 kfree((struct src_mgr_ctrl_blk *)blk);
508
509 return 0;
510}
511
512static int srcimp_mgr_get_ctrl_blk(void **rblk)
513{
514 struct srcimp_mgr_ctrl_blk *blk;
515
516 *rblk = NULL;
517 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
518 if (NULL == blk)
519 return -ENOMEM;
520
521 *rblk = blk;
522
523 return 0;
524}
525
526static int srcimp_mgr_put_ctrl_blk(void *blk)
527{
528 kfree((struct srcimp_mgr_ctrl_blk *)blk);
529
530 return 0;
531}
532
533static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot)
534{
535 struct srcimp_mgr_ctrl_blk *ctl = blk;
536
537 set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
538 ctl->dirty.bf.srcimap = 1;
539 return 0;
540}
541
542static int srcimp_mgr_set_imapuser(void *blk, unsigned int user)
543{
544 struct srcimp_mgr_ctrl_blk *ctl = blk;
545
546 set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
547 ctl->dirty.bf.srcimap = 1;
548 return 0;
549}
550
551static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next)
552{
553 struct srcimp_mgr_ctrl_blk *ctl = blk;
554
555 set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
556 ctl->dirty.bf.srcimap = 1;
557 return 0;
558}
559
560static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr)
561{
562 struct srcimp_mgr_ctrl_blk *ctl = blk;
563
564 ctl->srcimap.idx = addr;
565 ctl->dirty.bf.srcimap = 1;
566 return 0;
567}
568
569static int srcimp_mgr_commit_write(struct hw *hw, void *blk)
570{
571 struct srcimp_mgr_ctrl_blk *ctl = blk;
572
573 if (ctl->dirty.bf.srcimap) {
574 hw_write_20kx(hw, SRCIMAP+ctl->srcimap.idx*0x100,
575 ctl->srcimap.srcaim);
576 ctl->dirty.bf.srcimap = 0;
577 }
578
579 return 0;
580}
581
582/*
583 * AMIXER control block definitions.
584 */
585
586#define AMOPLO_M 0x00000003
587#define AMOPLO_X 0x0003FFF0
588#define AMOPLO_Y 0xFFFC0000
589
590#define AMOPHI_SADR 0x000000FF
591#define AMOPHI_SE 0x80000000
592
593/* AMIXER resource register dirty flags */
594union amixer_dirty {
595 struct {
596 u16 amoplo:1;
597 u16 amophi:1;
598 u16 rsv:14;
599 } bf;
600 u16 data;
601};
602
603/* AMIXER resource control block */
604struct amixer_rsc_ctrl_blk {
605 unsigned int amoplo;
606 unsigned int amophi;
607 union amixer_dirty dirty;
608};
609
610static int amixer_set_mode(void *blk, unsigned int mode)
611{
612 struct amixer_rsc_ctrl_blk *ctl = blk;
613
614 set_field(&ctl->amoplo, AMOPLO_M, mode);
615 ctl->dirty.bf.amoplo = 1;
616 return 0;
617}
618
619static int amixer_set_iv(void *blk, unsigned int iv)
620{
621 /* 20k1 amixer does not have this field */
622 return 0;
623}
624
625static int amixer_set_x(void *blk, unsigned int x)
626{
627 struct amixer_rsc_ctrl_blk *ctl = blk;
628
629 set_field(&ctl->amoplo, AMOPLO_X, x);
630 ctl->dirty.bf.amoplo = 1;
631 return 0;
632}
633
634static int amixer_set_y(void *blk, unsigned int y)
635{
636 struct amixer_rsc_ctrl_blk *ctl = blk;
637
638 set_field(&ctl->amoplo, AMOPLO_Y, y);
639 ctl->dirty.bf.amoplo = 1;
640 return 0;
641}
642
643static int amixer_set_sadr(void *blk, unsigned int sadr)
644{
645 struct amixer_rsc_ctrl_blk *ctl = blk;
646
647 set_field(&ctl->amophi, AMOPHI_SADR, sadr);
648 ctl->dirty.bf.amophi = 1;
649 return 0;
650}
651
652static int amixer_set_se(void *blk, unsigned int se)
653{
654 struct amixer_rsc_ctrl_blk *ctl = blk;
655
656 set_field(&ctl->amophi, AMOPHI_SE, se);
657 ctl->dirty.bf.amophi = 1;
658 return 0;
659}
660
661static int amixer_set_dirty(void *blk, unsigned int flags)
662{
663 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
664 return 0;
665}
666
667static int amixer_set_dirty_all(void *blk)
668{
669 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
670 return 0;
671}
672
673static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk)
674{
675 struct amixer_rsc_ctrl_blk *ctl = blk;
676
677 if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
678 hw_write_20kx(hw, AMOPLO+idx*8, ctl->amoplo);
679 ctl->dirty.bf.amoplo = 0;
680 hw_write_20kx(hw, AMOPHI+idx*8, ctl->amophi);
681 ctl->dirty.bf.amophi = 0;
682 }
683
684 return 0;
685}
686
687static int amixer_get_y(void *blk)
688{
689 struct amixer_rsc_ctrl_blk *ctl = blk;
690
691 return get_field(ctl->amoplo, AMOPLO_Y);
692}
693
694static unsigned int amixer_get_dirty(void *blk)
695{
696 return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
697}
698
699static int amixer_rsc_get_ctrl_blk(void **rblk)
700{
701 struct amixer_rsc_ctrl_blk *blk;
702
703 *rblk = NULL;
704 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
705 if (NULL == blk)
706 return -ENOMEM;
707
708 *rblk = blk;
709
710 return 0;
711}
712
713static int amixer_rsc_put_ctrl_blk(void *blk)
714{
715 kfree((struct amixer_rsc_ctrl_blk *)blk);
716
717 return 0;
718}
719
720static int amixer_mgr_get_ctrl_blk(void **rblk)
721{
722 /*amixer_mgr_ctrl_blk_t *blk;*/
723
724 *rblk = NULL;
725 /*blk = kzalloc(sizeof(*blk), GFP_KERNEL);
726 if (NULL == blk)
727 return -ENOMEM;
728
729 *rblk = blk;*/
730
731 return 0;
732}
733
734static int amixer_mgr_put_ctrl_blk(void *blk)
735{
736 /*kfree((amixer_mgr_ctrl_blk_t *)blk);*/
737
738 return 0;
739}
740
741/*
742 * DAIO control block definitions.
743 */
744
745/* Receiver Sample Rate Tracker Control register */
746#define SRTCTL_SRCR 0x000000FF
747#define SRTCTL_SRCL 0x0000FF00
748#define SRTCTL_RSR 0x00030000
749#define SRTCTL_DRAT 0x000C0000
750#define SRTCTL_RLE 0x10000000
751#define SRTCTL_RLP 0x20000000
752#define SRTCTL_EC 0x40000000
753#define SRTCTL_ET 0x80000000
754
755/* DAIO Receiver register dirty flags */
756union dai_dirty {
757 struct {
758 u16 srtctl:1;
759 u16 rsv:15;
760 } bf;
761 u16 data;
762};
763
764/* DAIO Receiver control block */
765struct dai_ctrl_blk {
766 unsigned int srtctl;
767 union dai_dirty dirty;
768};
769
770/* S/PDIF Transmitter register dirty flags */
771union dao_dirty {
772 struct {
773 u16 spos:1;
774 u16 rsv:15;
775 } bf;
776 u16 data;
777};
778
779/* S/PDIF Transmitter control block */
780struct dao_ctrl_blk {
781 unsigned int spos; /* S/PDIF Output Channel Status Register */
782 union dao_dirty dirty;
783};
784
785/* Audio Input Mapper RAM */
786#define AIM_ARC 0x00000FFF
787#define AIM_NXT 0x007F0000
788
789struct daoimap {
790 unsigned int aim;
791 unsigned int idx;
792};
793
794/* I2S Transmitter/Receiver Control register */
795#define I2SCTL_EA 0x00000004
796#define I2SCTL_EI 0x00000010
797
798/* S/PDIF Transmitter Control register */
799#define SPOCTL_OE 0x00000001
800#define SPOCTL_OS 0x0000000E
801#define SPOCTL_RIV 0x00000010
802#define SPOCTL_LIV 0x00000020
803#define SPOCTL_SR 0x000000C0
804
805/* S/PDIF Receiver Control register */
806#define SPICTL_EN 0x00000001
807#define SPICTL_I24 0x00000002
808#define SPICTL_IB 0x00000004
809#define SPICTL_SM 0x00000008
810#define SPICTL_VM 0x00000010
811
812/* DAIO manager register dirty flags */
813union daio_mgr_dirty {
814 struct {
815 u32 i2soctl:4;
816 u32 i2sictl:4;
817 u32 spoctl:4;
818 u32 spictl:4;
819 u32 daoimap:1;
820 u32 rsv:15;
821 } bf;
822 u32 data;
823};
824
825/* DAIO manager control block */
826struct daio_mgr_ctrl_blk {
827 unsigned int i2sctl;
828 unsigned int spoctl;
829 unsigned int spictl;
830 struct daoimap daoimap;
831 union daio_mgr_dirty dirty;
832};
833
834static int dai_srt_set_srcr(void *blk, unsigned int src)
835{
836 struct dai_ctrl_blk *ctl = blk;
837
838 set_field(&ctl->srtctl, SRTCTL_SRCR, src);
839 ctl->dirty.bf.srtctl = 1;
840 return 0;
841}
842
843static int dai_srt_set_srcl(void *blk, unsigned int src)
844{
845 struct dai_ctrl_blk *ctl = blk;
846
847 set_field(&ctl->srtctl, SRTCTL_SRCL, src);
848 ctl->dirty.bf.srtctl = 1;
849 return 0;
850}
851
852static int dai_srt_set_rsr(void *blk, unsigned int rsr)
853{
854 struct dai_ctrl_blk *ctl = blk;
855
856 set_field(&ctl->srtctl, SRTCTL_RSR, rsr);
857 ctl->dirty.bf.srtctl = 1;
858 return 0;
859}
860
861static int dai_srt_set_drat(void *blk, unsigned int drat)
862{
863 struct dai_ctrl_blk *ctl = blk;
864
865 set_field(&ctl->srtctl, SRTCTL_DRAT, drat);
866 ctl->dirty.bf.srtctl = 1;
867 return 0;
868}
869
870static int dai_srt_set_ec(void *blk, unsigned int ec)
871{
872 struct dai_ctrl_blk *ctl = blk;
873
874 set_field(&ctl->srtctl, SRTCTL_EC, ec ? 1 : 0);
875 ctl->dirty.bf.srtctl = 1;
876 return 0;
877}
878
879static int dai_srt_set_et(void *blk, unsigned int et)
880{
881 struct dai_ctrl_blk *ctl = blk;
882
883 set_field(&ctl->srtctl, SRTCTL_ET, et ? 1 : 0);
884 ctl->dirty.bf.srtctl = 1;
885 return 0;
886}
887
888static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk)
889{
890 struct dai_ctrl_blk *ctl = blk;
891
892 if (ctl->dirty.bf.srtctl) {
893 if (idx < 4) {
894 /* S/PDIF SRTs */
895 hw_write_20kx(hw, SRTSCTL+0x4*idx, ctl->srtctl);
896 } else {
897 /* I2S SRT */
898 hw_write_20kx(hw, SRTICTL, ctl->srtctl);
899 }
900 ctl->dirty.bf.srtctl = 0;
901 }
902
903 return 0;
904}
905
906static int dai_get_ctrl_blk(void **rblk)
907{
908 struct dai_ctrl_blk *blk;
909
910 *rblk = NULL;
911 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
912 if (NULL == blk)
913 return -ENOMEM;
914
915 *rblk = blk;
916
917 return 0;
918}
919
920static int dai_put_ctrl_blk(void *blk)
921{
922 kfree((struct dai_ctrl_blk *)blk);
923
924 return 0;
925}
926
927static int dao_set_spos(void *blk, unsigned int spos)
928{
929 ((struct dao_ctrl_blk *)blk)->spos = spos;
930 ((struct dao_ctrl_blk *)blk)->dirty.bf.spos = 1;
931 return 0;
932}
933
934static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk)
935{
936 struct dao_ctrl_blk *ctl = blk;
937
938 if (ctl->dirty.bf.spos) {
939 if (idx < 4) {
940 /* S/PDIF SPOSx */
941 hw_write_20kx(hw, SPOS+0x4*idx, ctl->spos);
942 }
943 ctl->dirty.bf.spos = 0;
944 }
945
946 return 0;
947}
948
949static int dao_get_spos(void *blk, unsigned int *spos)
950{
951 *spos = ((struct dao_ctrl_blk *)blk)->spos;
952 return 0;
953}
954
955static int dao_get_ctrl_blk(void **rblk)
956{
957 struct dao_ctrl_blk *blk;
958
959 *rblk = NULL;
960 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
961 if (NULL == blk)
962 return -ENOMEM;
963
964 *rblk = blk;
965
966 return 0;
967}
968
969static int dao_put_ctrl_blk(void *blk)
970{
971 kfree((struct dao_ctrl_blk *)blk);
972
973 return 0;
974}
975
976static int daio_mgr_enb_dai(void *blk, unsigned int idx)
977{
978 struct daio_mgr_ctrl_blk *ctl = blk;
979
980 if (idx < 4) {
981 /* S/PDIF input */
982 set_field(&ctl->spictl, SPICTL_EN << (idx*8), 1);
983 ctl->dirty.bf.spictl |= (0x1 << idx);
984 } else {
985 /* I2S input */
986 idx %= 4;
987 set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 1);
988 ctl->dirty.bf.i2sictl |= (0x1 << idx);
989 }
990 return 0;
991}
992
993static int daio_mgr_dsb_dai(void *blk, unsigned int idx)
994{
995 struct daio_mgr_ctrl_blk *ctl = blk;
996
997 if (idx < 4) {
998 /* S/PDIF input */
999 set_field(&ctl->spictl, SPICTL_EN << (idx*8), 0);
1000 ctl->dirty.bf.spictl |= (0x1 << idx);
1001 } else {
1002 /* I2S input */
1003 idx %= 4;
1004 set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 0);
1005 ctl->dirty.bf.i2sictl |= (0x1 << idx);
1006 }
1007 return 0;
1008}
1009
1010static int daio_mgr_enb_dao(void *blk, unsigned int idx)
1011{
1012 struct daio_mgr_ctrl_blk *ctl = blk;
1013
1014 if (idx < 4) {
1015 /* S/PDIF output */
1016 set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 1);
1017 ctl->dirty.bf.spoctl |= (0x1 << idx);
1018 } else {
1019 /* I2S output */
1020 idx %= 4;
1021 set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 1);
1022 ctl->dirty.bf.i2soctl |= (0x1 << idx);
1023 }
1024 return 0;
1025}
1026
1027static int daio_mgr_dsb_dao(void *blk, unsigned int idx)
1028{
1029 struct daio_mgr_ctrl_blk *ctl = blk;
1030
1031 if (idx < 4) {
1032 /* S/PDIF output */
1033 set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 0);
1034 ctl->dirty.bf.spoctl |= (0x1 << idx);
1035 } else {
1036 /* I2S output */
1037 idx %= 4;
1038 set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 0);
1039 ctl->dirty.bf.i2soctl |= (0x1 << idx);
1040 }
1041 return 0;
1042}
1043
1044static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf)
1045{
1046 struct daio_mgr_ctrl_blk *ctl = blk;
1047
1048 if (idx < 4) {
1049 /* S/PDIF output */
1050 switch ((conf & 0x7)) {
1051 case 0:
1052 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 3);
1053 break; /* CDIF */
1054 case 1:
1055 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 0);
1056 break;
1057 case 2:
1058 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 1);
1059 break;
1060 case 4:
1061 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 2);
1062 break;
1063 default:
1064 break;
1065 }
1066 set_field(&ctl->spoctl, SPOCTL_LIV << (idx*8),
1067 (conf >> 4) & 0x1); /* Non-audio */
1068 set_field(&ctl->spoctl, SPOCTL_RIV << (idx*8),
1069 (conf >> 4) & 0x1); /* Non-audio */
1070 set_field(&ctl->spoctl, SPOCTL_OS << (idx*8),
1071 ((conf >> 3) & 0x1) ? 2 : 2); /* Raw */
1072
1073 ctl->dirty.bf.spoctl |= (0x1 << idx);
1074 } else {
1075 /* I2S output */
1076 /*idx %= 4; */
1077 }
1078 return 0;
1079}
1080
1081static int daio_mgr_set_imaparc(void *blk, unsigned int slot)
1082{
1083 struct daio_mgr_ctrl_blk *ctl = blk;
1084
1085 set_field(&ctl->daoimap.aim, AIM_ARC, slot);
1086 ctl->dirty.bf.daoimap = 1;
1087 return 0;
1088}
1089
1090static int daio_mgr_set_imapnxt(void *blk, unsigned int next)
1091{
1092 struct daio_mgr_ctrl_blk *ctl = blk;
1093
1094 set_field(&ctl->daoimap.aim, AIM_NXT, next);
1095 ctl->dirty.bf.daoimap = 1;
1096 return 0;
1097}
1098
1099static int daio_mgr_set_imapaddr(void *blk, unsigned int addr)
1100{
1101 struct daio_mgr_ctrl_blk *ctl = blk;
1102
1103 ctl->daoimap.idx = addr;
1104 ctl->dirty.bf.daoimap = 1;
1105 return 0;
1106}
1107
1108static int daio_mgr_commit_write(struct hw *hw, void *blk)
1109{
1110 struct daio_mgr_ctrl_blk *ctl = blk;
1111 int i;
1112
1113 if (ctl->dirty.bf.i2sictl || ctl->dirty.bf.i2soctl) {
1114 for (i = 0; i < 4; i++) {
1115 if ((ctl->dirty.bf.i2sictl & (0x1 << i)))
1116 ctl->dirty.bf.i2sictl &= ~(0x1 << i);
1117
1118 if ((ctl->dirty.bf.i2soctl & (0x1 << i)))
1119 ctl->dirty.bf.i2soctl &= ~(0x1 << i);
1120 }
1121 hw_write_20kx(hw, I2SCTL, ctl->i2sctl);
1122 mdelay(1);
1123 }
1124 if (ctl->dirty.bf.spoctl) {
1125 for (i = 0; i < 4; i++) {
1126 if ((ctl->dirty.bf.spoctl & (0x1 << i)))
1127 ctl->dirty.bf.spoctl &= ~(0x1 << i);
1128 }
1129 hw_write_20kx(hw, SPOCTL, ctl->spoctl);
1130 mdelay(1);
1131 }
1132 if (ctl->dirty.bf.spictl) {
1133 for (i = 0; i < 4; i++) {
1134 if ((ctl->dirty.bf.spictl & (0x1 << i)))
1135 ctl->dirty.bf.spictl &= ~(0x1 << i);
1136 }
1137 hw_write_20kx(hw, SPICTL, ctl->spictl);
1138 mdelay(1);
1139 }
1140 if (ctl->dirty.bf.daoimap) {
1141 hw_write_20kx(hw, DAOIMAP+ctl->daoimap.idx*4,
1142 ctl->daoimap.aim);
1143 ctl->dirty.bf.daoimap = 0;
1144 }
1145
1146 return 0;
1147}
1148
1149static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk)
1150{
1151 struct daio_mgr_ctrl_blk *blk;
1152
1153 *rblk = NULL;
1154 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
1155 if (NULL == blk)
1156 return -ENOMEM;
1157
1158 blk->i2sctl = hw_read_20kx(hw, I2SCTL);
1159 blk->spoctl = hw_read_20kx(hw, SPOCTL);
1160 blk->spictl = hw_read_20kx(hw, SPICTL);
1161
1162 *rblk = blk;
1163
1164 return 0;
1165}
1166
1167static int daio_mgr_put_ctrl_blk(void *blk)
1168{
1169 kfree((struct daio_mgr_ctrl_blk *)blk);
1170
1171 return 0;
1172}
1173
1174/* Timer interrupt */
1175static int set_timer_irq(struct hw *hw, int enable)
1176{
1177 hw_write_20kx(hw, GIE, enable ? IT_INT : 0);
1178 return 0;
1179}
1180
1181static int set_timer_tick(struct hw *hw, unsigned int ticks)
1182{
1183 if (ticks)
1184 ticks |= TIMR_IE | TIMR_IP;
1185 hw_write_20kx(hw, TIMR, ticks);
1186 return 0;
1187}
1188
1189static unsigned int get_wc(struct hw *hw)
1190{
1191 return hw_read_20kx(hw, WC);
1192}
1193
1194/* Card hardware initialization block */
1195struct dac_conf {
1196 unsigned int msr; /* master sample rate in rsrs */
1197};
1198
1199struct adc_conf {
1200 unsigned int msr; /* master sample rate in rsrs */
1201 unsigned char input; /* the input source of ADC */
1202 unsigned char mic20db; /* boost mic by 20db if input is microphone */
1203};
1204
1205struct daio_conf {
1206 unsigned int msr; /* master sample rate in rsrs */
1207};
1208
1209struct trn_conf {
1210 unsigned long vm_pgt_phys;
1211};
1212
1213static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
1214{
1215 u32 i2sorg;
1216 u32 spdorg;
1217
1218 /* Read I2S CTL. Keep original value. */
1219 /*i2sorg = hw_read_20kx(hw, I2SCTL);*/
1220 i2sorg = 0x94040404; /* enable all audio out and I2S-D input */
1221 /* Program I2S with proper master sample rate and enable
1222 * the correct I2S channel. */
1223 i2sorg &= 0xfffffffc;
1224
1225 /* Enable S/PDIF-out-A in fixed 24-bit data
1226 * format and default to 48kHz. */
1227 /* Disable all before doing any changes. */
1228 hw_write_20kx(hw, SPOCTL, 0x0);
1229 spdorg = 0x05;
1230
1231 switch (info->msr) {
1232 case 1:
1233 i2sorg |= 1;
1234 spdorg |= (0x0 << 6);
1235 break;
1236 case 2:
1237 i2sorg |= 2;
1238 spdorg |= (0x1 << 6);
1239 break;
1240 case 4:
1241 i2sorg |= 3;
1242 spdorg |= (0x2 << 6);
1243 break;
1244 default:
1245 i2sorg |= 1;
1246 break;
1247 }
1248
1249 hw_write_20kx(hw, I2SCTL, i2sorg);
1250 hw_write_20kx(hw, SPOCTL, spdorg);
1251
1252 /* Enable S/PDIF-in-A in fixed 24-bit data format. */
1253 /* Disable all before doing any changes. */
1254 hw_write_20kx(hw, SPICTL, 0x0);
1255 mdelay(1);
1256 spdorg = 0x0a0a0a0a;
1257 hw_write_20kx(hw, SPICTL, spdorg);
1258 mdelay(1);
1259
1260 return 0;
1261}
1262
1263/* TRANSPORT operations */
1264static int hw_trn_init(struct hw *hw, const struct trn_conf *info)
1265{
1266 u32 trnctl;
1267 u32 ptp_phys_low, ptp_phys_high;
1268
1269 /* Set up device page table */
1270 if ((~0UL) == info->vm_pgt_phys) {
1271 printk(KERN_ERR "Wrong device page table page address!\n");
1272 return -1;
1273 }
1274
1275 trnctl = 0x13; /* 32-bit, 4k-size page */
1276 ptp_phys_low = (u32)info->vm_pgt_phys;
1277 ptp_phys_high = upper_32_bits(info->vm_pgt_phys);
1278 if (sizeof(void *) == 8) /* 64bit address */
1279 trnctl |= (1 << 2);
1280#if 0 /* Only 4k h/w pages for simplicitiy */
1281#if PAGE_SIZE == 8192
1282 trnctl |= (1<<5);
1283#endif
1284#endif
1285 hw_write_20kx(hw, PTPALX, ptp_phys_low);
1286 hw_write_20kx(hw, PTPAHX, ptp_phys_high);
1287 hw_write_20kx(hw, TRNCTL, trnctl);
1288 hw_write_20kx(hw, TRNIS, 0x200c01); /* realy needed? */
1289
1290 return 0;
1291}
1292
1293/* Card initialization */
1294#define GCTL_EAC 0x00000001
1295#define GCTL_EAI 0x00000002
1296#define GCTL_BEP 0x00000004
1297#define GCTL_BES 0x00000008
1298#define GCTL_DSP 0x00000010
1299#define GCTL_DBP 0x00000020
1300#define GCTL_ABP 0x00000040
1301#define GCTL_TBP 0x00000080
1302#define GCTL_SBP 0x00000100
1303#define GCTL_FBP 0x00000200
1304#define GCTL_XA 0x00000400
1305#define GCTL_ET 0x00000800
1306#define GCTL_PR 0x00001000
1307#define GCTL_MRL 0x00002000
1308#define GCTL_SDE 0x00004000
1309#define GCTL_SDI 0x00008000
1310#define GCTL_SM 0x00010000
1311#define GCTL_SR 0x00020000
1312#define GCTL_SD 0x00040000
1313#define GCTL_SE 0x00080000
1314#define GCTL_AID 0x00100000
1315
1316static int hw_pll_init(struct hw *hw, unsigned int rsr)
1317{
1318 unsigned int pllctl;
1319 int i;
1320
1321 pllctl = (48000 == rsr) ? 0x1480a001 : 0x1480a731;
1322 for (i = 0; i < 3; i++) {
1323 if (hw_read_20kx(hw, PLLCTL) == pllctl)
1324 break;
1325
1326 hw_write_20kx(hw, PLLCTL, pllctl);
1327 mdelay(40);
1328 }
1329 if (i >= 3) {
1330 printk(KERN_ALERT "PLL initialization failed!!!\n");
1331 return -EBUSY;
1332 }
1333
1334 return 0;
1335}
1336
1337static int hw_auto_init(struct hw *hw)
1338{
1339 unsigned int gctl;
1340 int i;
1341
1342 gctl = hw_read_20kx(hw, GCTL);
1343 set_field(&gctl, GCTL_EAI, 0);
1344 hw_write_20kx(hw, GCTL, gctl);
1345 set_field(&gctl, GCTL_EAI, 1);
1346 hw_write_20kx(hw, GCTL, gctl);
1347 mdelay(10);
1348 for (i = 0; i < 400000; i++) {
1349 gctl = hw_read_20kx(hw, GCTL);
1350 if (get_field(gctl, GCTL_AID))
1351 break;
1352 }
1353 if (!get_field(gctl, GCTL_AID)) {
1354 printk(KERN_ALERT "Card Auto-init failed!!!\n");
1355 return -EBUSY;
1356 }
1357
1358 return 0;
1359}
1360
1361static int i2c_unlock(struct hw *hw)
1362{
1363 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1364 return 0;
1365
1366 hw_write_pci(hw, 0xcc, 0x8c);
1367 hw_write_pci(hw, 0xcc, 0x0e);
1368 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1369 return 0;
1370
1371 hw_write_pci(hw, 0xcc, 0xee);
1372 hw_write_pci(hw, 0xcc, 0xaa);
1373 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1374 return 0;
1375
1376 return -1;
1377}
1378
1379static void i2c_lock(struct hw *hw)
1380{
1381 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1382 hw_write_pci(hw, 0xcc, 0x00);
1383}
1384
1385static void i2c_write(struct hw *hw, u32 device, u32 addr, u32 data)
1386{
1387 unsigned int ret;
1388
1389 do {
1390 ret = hw_read_pci(hw, 0xEC);
1391 } while (!(ret & 0x800000));
1392 hw_write_pci(hw, 0xE0, device);
1393 hw_write_pci(hw, 0xE4, (data << 8) | (addr & 0xff));
1394}
1395
1396/* DAC operations */
1397
1398static int hw_reset_dac(struct hw *hw)
1399{
1400 u32 i;
1401 u16 gpioorg;
1402 unsigned int ret;
1403
1404 if (i2c_unlock(hw))
1405 return -1;
1406
1407 do {
1408 ret = hw_read_pci(hw, 0xEC);
1409 } while (!(ret & 0x800000));
1410 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1411
1412 /* To be effective, need to reset the DAC twice. */
1413 for (i = 0; i < 2; i++) {
1414 /* set gpio */
1415 mdelay(100);
1416 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1417 gpioorg &= 0xfffd;
1418 hw_write_20kx(hw, GPIO, gpioorg);
1419 mdelay(1);
1420 hw_write_20kx(hw, GPIO, gpioorg | 0x2);
1421 }
1422
1423 i2c_write(hw, 0x00180080, 0x01, 0x80);
1424 i2c_write(hw, 0x00180080, 0x02, 0x10);
1425
1426 i2c_lock(hw);
1427
1428 return 0;
1429}
1430
1431static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
1432{
1433 u32 data;
1434 u16 gpioorg;
1435 unsigned int ret;
1436
1437 if (hw->model == CTSB055X) {
1438 /* SB055x, unmute outputs */
1439 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1440 gpioorg &= 0xffbf; /* set GPIO6 to low */
1441 gpioorg |= 2; /* set GPIO1 to high */
1442 hw_write_20kx(hw, GPIO, gpioorg);
1443 return 0;
1444 }
1445
1446 /* mute outputs */
1447 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1448 gpioorg &= 0xffbf;
1449 hw_write_20kx(hw, GPIO, gpioorg);
1450
1451 hw_reset_dac(hw);
1452
1453 if (i2c_unlock(hw))
1454 return -1;
1455
1456 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1457 do {
1458 ret = hw_read_pci(hw, 0xEC);
1459 } while (!(ret & 0x800000));
1460
1461 switch (info->msr) {
1462 case 1:
1463 data = 0x24;
1464 break;
1465 case 2:
1466 data = 0x25;
1467 break;
1468 case 4:
1469 data = 0x26;
1470 break;
1471 default:
1472 data = 0x24;
1473 break;
1474 }
1475
1476 i2c_write(hw, 0x00180080, 0x06, data);
1477 i2c_write(hw, 0x00180080, 0x09, data);
1478 i2c_write(hw, 0x00180080, 0x0c, data);
1479 i2c_write(hw, 0x00180080, 0x0f, data);
1480
1481 i2c_lock(hw);
1482
1483 /* unmute outputs */
1484 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1485 gpioorg = gpioorg | 0x40;
1486 hw_write_20kx(hw, GPIO, gpioorg);
1487
1488 return 0;
1489}
1490
1491/* ADC operations */
1492
1493static int is_adc_input_selected_SB055x(struct hw *hw, enum ADCSRC type)
1494{
1495 return 0;
1496}
1497
1498static int is_adc_input_selected_SBx(struct hw *hw, enum ADCSRC type)
1499{
1500 u32 data;
1501
1502 data = hw_read_20kx(hw, GPIO);
1503 switch (type) {
1504 case ADC_MICIN:
1505 data = ((data & (0x1<<7)) && (data & (0x1<<8)));
1506 break;
1507 case ADC_LINEIN:
1508 data = (!(data & (0x1<<7)) && (data & (0x1<<8)));
1509 break;
1510 case ADC_NONE: /* Digital I/O */
1511 data = (!(data & (0x1<<8)));
1512 break;
1513 default:
1514 data = 0;
1515 }
1516 return data;
1517}
1518
1519static int is_adc_input_selected_hendrix(struct hw *hw, enum ADCSRC type)
1520{
1521 u32 data;
1522
1523 data = hw_read_20kx(hw, GPIO);
1524 switch (type) {
1525 case ADC_MICIN:
1526 data = (data & (0x1 << 7)) ? 1 : 0;
1527 break;
1528 case ADC_LINEIN:
1529 data = (data & (0x1 << 7)) ? 0 : 1;
1530 break;
1531 default:
1532 data = 0;
1533 }
1534 return data;
1535}
1536
1537static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type)
1538{
1539 switch (hw->model) {
1540 case CTSB055X:
1541 return is_adc_input_selected_SB055x(hw, type);
1542 case CTSB073X:
1543 return is_adc_input_selected_hendrix(hw, type);
1544 case CTUAA:
1545 return is_adc_input_selected_hendrix(hw, type);
1546 default:
1547 return is_adc_input_selected_SBx(hw, type);
1548 }
1549}
1550
1551static int
1552adc_input_select_SB055x(struct hw *hw, enum ADCSRC type, unsigned char boost)
1553{
1554 u32 data;
1555
1556 /*
1557 * check and set the following GPIO bits accordingly
1558 * ADC_Gain = GPIO2
1559 * DRM_off = GPIO3
1560 * Mic_Pwr_on = GPIO7
1561 * Digital_IO_Sel = GPIO8
1562 * Mic_Sw = GPIO9
1563 * Aux/MicLine_Sw = GPIO12
1564 */
1565 data = hw_read_20kx(hw, GPIO);
1566 data &= 0xec73;
1567 switch (type) {
1568 case ADC_MICIN:
1569 data |= (0x1<<7) | (0x1<<8) | (0x1<<9) ;
1570 data |= boost ? (0x1<<2) : 0;
1571 break;
1572 case ADC_LINEIN:
1573 data |= (0x1<<8);
1574 break;
1575 case ADC_AUX:
1576 data |= (0x1<<8) | (0x1<<12);
1577 break;
1578 case ADC_NONE:
1579 data |= (0x1<<12); /* set to digital */
1580 break;
1581 default:
1582 return -1;
1583 }
1584
1585 hw_write_20kx(hw, GPIO, data);
1586
1587 return 0;
1588}
1589
1590
1591static int
1592adc_input_select_SBx(struct hw *hw, enum ADCSRC type, unsigned char boost)
1593{
1594 u32 data;
1595 u32 i2c_data;
1596 unsigned int ret;
1597
1598 if (i2c_unlock(hw))
1599 return -1;
1600
1601 do {
1602 ret = hw_read_pci(hw, 0xEC);
1603 } while (!(ret & 0x800000)); /* i2c ready poll */
1604 /* set i2c access mode as Direct Control */
1605 hw_write_pci(hw, 0xEC, 0x05);
1606
1607 data = hw_read_20kx(hw, GPIO);
1608 switch (type) {
1609 case ADC_MICIN:
1610 data |= ((0x1 << 7) | (0x1 << 8));
1611 i2c_data = 0x1; /* Mic-in */
1612 break;
1613 case ADC_LINEIN:
1614 data &= ~(0x1 << 7);
1615 data |= (0x1 << 8);
1616 i2c_data = 0x2; /* Line-in */
1617 break;
1618 case ADC_NONE:
1619 data &= ~(0x1 << 8);
1620 i2c_data = 0x0; /* set to Digital */
1621 break;
1622 default:
1623 i2c_lock(hw);
1624 return -1;
1625 }
1626 hw_write_20kx(hw, GPIO, data);
1627 i2c_write(hw, 0x001a0080, 0x2a, i2c_data);
1628 if (boost) {
1629 i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */
1630 i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */
1631 } else {
1632 i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */
1633 i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */
1634 }
1635
1636 i2c_lock(hw);
1637
1638 return 0;
1639}
1640
1641static int
1642adc_input_select_hendrix(struct hw *hw, enum ADCSRC type, unsigned char boost)
1643{
1644 u32 data;
1645 u32 i2c_data;
1646 unsigned int ret;
1647
1648 if (i2c_unlock(hw))
1649 return -1;
1650
1651 do {
1652 ret = hw_read_pci(hw, 0xEC);
1653 } while (!(ret & 0x800000)); /* i2c ready poll */
1654 /* set i2c access mode as Direct Control */
1655 hw_write_pci(hw, 0xEC, 0x05);
1656
1657 data = hw_read_20kx(hw, GPIO);
1658 switch (type) {
1659 case ADC_MICIN:
1660 data |= (0x1 << 7);
1661 i2c_data = 0x1; /* Mic-in */
1662 break;
1663 case ADC_LINEIN:
1664 data &= ~(0x1 << 7);
1665 i2c_data = 0x2; /* Line-in */
1666 break;
1667 default:
1668 i2c_lock(hw);
1669 return -1;
1670 }
1671 hw_write_20kx(hw, GPIO, data);
1672 i2c_write(hw, 0x001a0080, 0x2a, i2c_data);
1673 if (boost) {
1674 i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */
1675 i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */
1676 } else {
1677 i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */
1678 i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */
1679 }
1680
1681 i2c_lock(hw);
1682
1683 return 0;
1684}
1685
1686static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
1687{
1688 int state = type == ADC_MICIN;
1689
1690 switch (hw->model) {
1691 case CTSB055X:
1692 return adc_input_select_SB055x(hw, type, state);
1693 case CTSB073X:
1694 return adc_input_select_hendrix(hw, type, state);
1695 case CTUAA:
1696 return adc_input_select_hendrix(hw, type, state);
1697 default:
1698 return adc_input_select_SBx(hw, type, state);
1699 }
1700}
1701
1702static int adc_init_SB055x(struct hw *hw, int input, int mic20db)
1703{
1704 return adc_input_select_SB055x(hw, input, mic20db);
1705}
1706
1707static int adc_init_SBx(struct hw *hw, int input, int mic20db)
1708{
1709 u16 gpioorg;
1710 u16 input_source;
1711 u32 adcdata;
1712 unsigned int ret;
1713
1714 input_source = 0x100; /* default to analog */
1715 switch (input) {
1716 case ADC_MICIN:
1717 adcdata = 0x1;
1718 input_source = 0x180; /* set GPIO7 to select Mic */
1719 break;
1720 case ADC_LINEIN:
1721 adcdata = 0x2;
1722 break;
1723 case ADC_VIDEO:
1724 adcdata = 0x4;
1725 break;
1726 case ADC_AUX:
1727 adcdata = 0x8;
1728 break;
1729 case ADC_NONE:
1730 adcdata = 0x0;
1731 input_source = 0x0; /* set to Digital */
1732 break;
1733 default:
1734 adcdata = 0x0;
1735 break;
1736 }
1737
1738 if (i2c_unlock(hw))
1739 return -1;
1740
1741 do {
1742 ret = hw_read_pci(hw, 0xEC);
1743 } while (!(ret & 0x800000)); /* i2c ready poll */
1744 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1745
1746 i2c_write(hw, 0x001a0080, 0x0e, 0x08);
1747 i2c_write(hw, 0x001a0080, 0x18, 0x0a);
1748 i2c_write(hw, 0x001a0080, 0x28, 0x86);
1749 i2c_write(hw, 0x001a0080, 0x2a, adcdata);
1750
1751 if (mic20db) {
1752 i2c_write(hw, 0x001a0080, 0x1c, 0xf7);
1753 i2c_write(hw, 0x001a0080, 0x1e, 0xf7);
1754 } else {
1755 i2c_write(hw, 0x001a0080, 0x1c, 0xcf);
1756 i2c_write(hw, 0x001a0080, 0x1e, 0xcf);
1757 }
1758
1759 if (!(hw_read_20kx(hw, ID0) & 0x100))
1760 i2c_write(hw, 0x001a0080, 0x16, 0x26);
1761
1762 i2c_lock(hw);
1763
1764 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1765 gpioorg &= 0xfe7f;
1766 gpioorg |= input_source;
1767 hw_write_20kx(hw, GPIO, gpioorg);
1768
1769 return 0;
1770}
1771
1772static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
1773{
1774 if (hw->model == CTSB055X)
1775 return adc_init_SB055x(hw, info->input, info->mic20db);
1776 else
1777 return adc_init_SBx(hw, info->input, info->mic20db);
1778}
1779
1780static int hw_have_digit_io_switch(struct hw *hw)
1781{
1782 /* SB073x and Vista compatible cards have no digit IO switch */
1783 return !(hw->model == CTSB073X || hw->model == CTUAA);
1784}
1785
1786#define CTLBITS(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d))
1787
1788#define UAA_CFG_PWRSTATUS 0x44
1789#define UAA_CFG_SPACE_FLAG 0xA0
1790#define UAA_CORE_CHANGE 0x3FFC
1791static int uaa_to_xfi(struct pci_dev *pci)
1792{
1793 unsigned int bar0, bar1, bar2, bar3, bar4, bar5;
1794 unsigned int cmd, irq, cl_size, l_timer, pwr;
1795 unsigned int is_uaa;
1796 unsigned int data[4] = {0};
1797 unsigned int io_base;
1798 void *mem_base;
1799 int i;
1800 const u32 CTLX = CTLBITS('C', 'T', 'L', 'X');
1801 const u32 CTL_ = CTLBITS('C', 'T', 'L', '-');
1802 const u32 CTLF = CTLBITS('C', 'T', 'L', 'F');
1803 const u32 CTLi = CTLBITS('C', 'T', 'L', 'i');
1804 const u32 CTLA = CTLBITS('C', 'T', 'L', 'A');
1805 const u32 CTLZ = CTLBITS('C', 'T', 'L', 'Z');
1806 const u32 CTLL = CTLBITS('C', 'T', 'L', 'L');
1807
1808 /* By default, Hendrix card UAA Bar0 should be using memory... */
1809 io_base = pci_resource_start(pci, 0);
1810 mem_base = ioremap(io_base, pci_resource_len(pci, 0));
1811 if (NULL == mem_base)
1812 return -ENOENT;
1813
1814 /* Read current mode from Mode Change Register */
1815 for (i = 0; i < 4; i++)
1816 data[i] = readl(mem_base + UAA_CORE_CHANGE);
1817
1818 /* Determine current mode... */
1819 if (data[0] == CTLA) {
1820 is_uaa = ((data[1] == CTLZ && data[2] == CTLL
1821 && data[3] == CTLA) || (data[1] == CTLA
1822 && data[2] == CTLZ && data[3] == CTLL));
1823 } else if (data[0] == CTLZ) {
1824 is_uaa = (data[1] == CTLL
1825 && data[2] == CTLA && data[3] == CTLA);
1826 } else if (data[0] == CTLL) {
1827 is_uaa = (data[1] == CTLA
1828 && data[2] == CTLA && data[3] == CTLZ);
1829 } else {
1830 is_uaa = 0;
1831 }
1832
1833 if (!is_uaa) {
1834 /* Not in UAA mode currently. Return directly. */
1835 iounmap(mem_base);
1836 return 0;
1837 }
1838
1839 pci_read_config_dword(pci, PCI_BASE_ADDRESS_0, &bar0);
1840 pci_read_config_dword(pci, PCI_BASE_ADDRESS_1, &bar1);
1841 pci_read_config_dword(pci, PCI_BASE_ADDRESS_2, &bar2);
1842 pci_read_config_dword(pci, PCI_BASE_ADDRESS_3, &bar3);
1843 pci_read_config_dword(pci, PCI_BASE_ADDRESS_4, &bar4);
1844 pci_read_config_dword(pci, PCI_BASE_ADDRESS_5, &bar5);
1845 pci_read_config_dword(pci, PCI_INTERRUPT_LINE, &irq);
1846 pci_read_config_dword(pci, PCI_CACHE_LINE_SIZE, &cl_size);
1847 pci_read_config_dword(pci, PCI_LATENCY_TIMER, &l_timer);
1848 pci_read_config_dword(pci, UAA_CFG_PWRSTATUS, &pwr);
1849 pci_read_config_dword(pci, PCI_COMMAND, &cmd);
1850
1851 /* Set up X-Fi core PCI configuration space. */
1852 /* Switch to X-Fi config space with BAR0 exposed. */
1853 pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x87654321);
1854 /* Copy UAA's BAR5 into X-Fi BAR0 */
1855 pci_write_config_dword(pci, PCI_BASE_ADDRESS_0, bar5);
1856 /* Switch to X-Fi config space without BAR0 exposed. */
1857 pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x12345678);
1858 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, bar1);
1859 pci_write_config_dword(pci, PCI_BASE_ADDRESS_2, bar2);
1860 pci_write_config_dword(pci, PCI_BASE_ADDRESS_3, bar3);
1861 pci_write_config_dword(pci, PCI_BASE_ADDRESS_4, bar4);
1862 pci_write_config_dword(pci, PCI_INTERRUPT_LINE, irq);
1863 pci_write_config_dword(pci, PCI_CACHE_LINE_SIZE, cl_size);
1864 pci_write_config_dword(pci, PCI_LATENCY_TIMER, l_timer);
1865 pci_write_config_dword(pci, UAA_CFG_PWRSTATUS, pwr);
1866 pci_write_config_dword(pci, PCI_COMMAND, cmd);
1867
1868 /* Switch to X-Fi mode */
1869 writel(CTLX, (mem_base + UAA_CORE_CHANGE));
1870 writel(CTL_, (mem_base + UAA_CORE_CHANGE));
1871 writel(CTLF, (mem_base + UAA_CORE_CHANGE));
1872 writel(CTLi, (mem_base + UAA_CORE_CHANGE));
1873
1874 iounmap(mem_base);
1875
1876 return 0;
1877}
1878
1879static irqreturn_t ct_20k1_interrupt(int irq, void *dev_id)
1880{
1881 struct hw *hw = dev_id;
1882 unsigned int status;
1883
1884 status = hw_read_20kx(hw, GIP);
1885 if (!status)
1886 return IRQ_NONE;
1887
1888 if (hw->irq_callback)
1889 hw->irq_callback(hw->irq_callback_data, status);
1890
1891 hw_write_20kx(hw, GIP, status);
1892 return IRQ_HANDLED;
1893}
1894
1895static int hw_card_start(struct hw *hw)
1896{
1897 int err;
1898 struct pci_dev *pci = hw->pci;
1899
1900 err = pci_enable_device(pci);
1901 if (err < 0)
1902 return err;
1903
1904 /* Set DMA transfer mask */
1905 if (pci_set_dma_mask(pci, CT_XFI_DMA_MASK) < 0 ||
1906 pci_set_consistent_dma_mask(pci, CT_XFI_DMA_MASK) < 0) {
1907 printk(KERN_ERR "architecture does not support PCI "
1908 "busmaster DMA with mask 0x%llx\n",
1909 CT_XFI_DMA_MASK);
1910 err = -ENXIO;
1911 goto error1;
1912 }
1913
1914 err = pci_request_regions(pci, "XFi");
1915 if (err < 0)
1916 goto error1;
1917
1918 /* Switch to X-Fi mode from UAA mode if neeeded */
1919 if (hw->model == CTUAA) {
1920 err = uaa_to_xfi(pci);
1921 if (err)
1922 goto error2;
1923
1924 hw->io_base = pci_resource_start(pci, 5);
1925 } else {
1926 hw->io_base = pci_resource_start(pci, 0);
1927 }
1928
1929 err = request_irq(pci->irq, ct_20k1_interrupt, IRQF_SHARED,
1930 "ctxfi", hw);
1931 if (err < 0) {
1932 printk(KERN_ERR "XFi: Cannot get irq %d\n", pci->irq);
1933 goto error2;
1934 }
1935 hw->irq = pci->irq;
1936
1937 pci_set_master(pci);
1938
1939 return 0;
1940
1941error2:
1942 pci_release_regions(pci);
1943 hw->io_base = 0;
1944error1:
1945 pci_disable_device(pci);
1946 return err;
1947}
1948
1949static int hw_card_stop(struct hw *hw)
1950{
1951 /* TODO: Disable interrupt and so on... */
1952 if (hw->irq >= 0)
1953 synchronize_irq(hw->irq);
1954 return 0;
1955}
1956
1957static int hw_card_shutdown(struct hw *hw)
1958{
1959 if (hw->irq >= 0)
1960 free_irq(hw->irq, hw);
1961
1962 hw->irq = -1;
1963
1964 if (NULL != ((void *)hw->mem_base))
1965 iounmap((void *)hw->mem_base);
1966
1967 hw->mem_base = (unsigned long)NULL;
1968
1969 if (hw->io_base)
1970 pci_release_regions(hw->pci);
1971
1972 hw->io_base = 0;
1973
1974 pci_disable_device(hw->pci);
1975
1976 return 0;
1977}
1978
1979static int hw_card_init(struct hw *hw, struct card_conf *info)
1980{
1981 int err;
1982 unsigned int gctl;
1983 u32 data;
1984 struct dac_conf dac_info = {0};
1985 struct adc_conf adc_info = {0};
1986 struct daio_conf daio_info = {0};
1987 struct trn_conf trn_info = {0};
1988
1989 /* Get PCI io port base address and do Hendrix switch if needed. */
1990 if (!hw->io_base) {
1991 err = hw_card_start(hw);
1992 if (err)
1993 return err;
1994 }
1995
1996 /* PLL init */
1997 err = hw_pll_init(hw, info->rsr);
1998 if (err < 0)
1999 return err;
2000
2001 /* kick off auto-init */
2002 err = hw_auto_init(hw);
2003 if (err < 0)
2004 return err;
2005
2006 /* Enable audio ring */
2007 gctl = hw_read_20kx(hw, GCTL);
2008 set_field(&gctl, GCTL_EAC, 1);
2009 set_field(&gctl, GCTL_DBP, 1);
2010 set_field(&gctl, GCTL_TBP, 1);
2011 set_field(&gctl, GCTL_FBP, 1);
2012 set_field(&gctl, GCTL_ET, 1);
2013 hw_write_20kx(hw, GCTL, gctl);
2014 mdelay(10);
2015
2016 /* Reset all global pending interrupts */
2017 hw_write_20kx(hw, GIE, 0);
2018 /* Reset all SRC pending interrupts */
2019 hw_write_20kx(hw, SRCIP, 0);
2020 mdelay(30);
2021
2022 /* Detect the card ID and configure GPIO accordingly. */
2023 switch (hw->model) {
2024 case CTSB055X:
2025 hw_write_20kx(hw, GPIOCTL, 0x13fe);
2026 break;
2027 case CTSB073X:
2028 hw_write_20kx(hw, GPIOCTL, 0x00e6);
2029 break;
2030 case CTUAA:
2031 hw_write_20kx(hw, GPIOCTL, 0x00c2);
2032 break;
2033 default:
2034 hw_write_20kx(hw, GPIOCTL, 0x01e6);
2035 break;
2036 }
2037
2038 trn_info.vm_pgt_phys = info->vm_pgt_phys;
2039 err = hw_trn_init(hw, &trn_info);
2040 if (err < 0)
2041 return err;
2042
2043 daio_info.msr = info->msr;
2044 err = hw_daio_init(hw, &daio_info);
2045 if (err < 0)
2046 return err;
2047
2048 dac_info.msr = info->msr;
2049 err = hw_dac_init(hw, &dac_info);
2050 if (err < 0)
2051 return err;
2052
2053 adc_info.msr = info->msr;
2054 adc_info.input = ADC_LINEIN;
2055 adc_info.mic20db = 0;
2056 err = hw_adc_init(hw, &adc_info);
2057 if (err < 0)
2058 return err;
2059
2060 data = hw_read_20kx(hw, SRCMCTL);
2061 data |= 0x1; /* Enables input from the audio ring */
2062 hw_write_20kx(hw, SRCMCTL, data);
2063
2064 return 0;
2065}
2066
2067static u32 hw_read_20kx(struct hw *hw, u32 reg)
2068{
2069 u32 value;
2070 unsigned long flags;
2071
2072 spin_lock_irqsave(
2073 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2074 outl(reg, hw->io_base + 0x0);
2075 value = inl(hw->io_base + 0x4);
2076 spin_unlock_irqrestore(
2077 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2078
2079 return value;
2080}
2081
2082static void hw_write_20kx(struct hw *hw, u32 reg, u32 data)
2083{
2084 unsigned long flags;
2085
2086 spin_lock_irqsave(
2087 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2088 outl(reg, hw->io_base + 0x0);
2089 outl(data, hw->io_base + 0x4);
2090 spin_unlock_irqrestore(
2091 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2092
2093}
2094
2095static u32 hw_read_pci(struct hw *hw, u32 reg)
2096{
2097 u32 value;
2098 unsigned long flags;
2099
2100 spin_lock_irqsave(
2101 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2102 outl(reg, hw->io_base + 0x10);
2103 value = inl(hw->io_base + 0x14);
2104 spin_unlock_irqrestore(
2105 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2106
2107 return value;
2108}
2109
2110static void hw_write_pci(struct hw *hw, u32 reg, u32 data)
2111{
2112 unsigned long flags;
2113
2114 spin_lock_irqsave(
2115 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2116 outl(reg, hw->io_base + 0x10);
2117 outl(data, hw->io_base + 0x14);
2118 spin_unlock_irqrestore(
2119 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2120}
2121
2122static struct hw ct20k1_preset __devinitdata = {
2123 .irq = -1,
2124
2125 .card_init = hw_card_init,
2126 .card_stop = hw_card_stop,
2127 .pll_init = hw_pll_init,
2128 .is_adc_source_selected = hw_is_adc_input_selected,
2129 .select_adc_source = hw_adc_input_select,
2130 .have_digit_io_switch = hw_have_digit_io_switch,
2131
2132 .src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk,
2133 .src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk,
2134 .src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk,
2135 .src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk,
2136 .src_set_state = src_set_state,
2137 .src_set_bm = src_set_bm,
2138 .src_set_rsr = src_set_rsr,
2139 .src_set_sf = src_set_sf,
2140 .src_set_wr = src_set_wr,
2141 .src_set_pm = src_set_pm,
2142 .src_set_rom = src_set_rom,
2143 .src_set_vo = src_set_vo,
2144 .src_set_st = src_set_st,
2145 .src_set_ie = src_set_ie,
2146 .src_set_ilsz = src_set_ilsz,
2147 .src_set_bp = src_set_bp,
2148 .src_set_cisz = src_set_cisz,
2149 .src_set_ca = src_set_ca,
2150 .src_set_sa = src_set_sa,
2151 .src_set_la = src_set_la,
2152 .src_set_pitch = src_set_pitch,
2153 .src_set_dirty = src_set_dirty,
2154 .src_set_clear_zbufs = src_set_clear_zbufs,
2155 .src_set_dirty_all = src_set_dirty_all,
2156 .src_commit_write = src_commit_write,
2157 .src_get_ca = src_get_ca,
2158 .src_get_dirty = src_get_dirty,
2159 .src_dirty_conj_mask = src_dirty_conj_mask,
2160 .src_mgr_enbs_src = src_mgr_enbs_src,
2161 .src_mgr_enb_src = src_mgr_enb_src,
2162 .src_mgr_dsb_src = src_mgr_dsb_src,
2163 .src_mgr_commit_write = src_mgr_commit_write,
2164
2165 .srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk,
2166 .srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk,
2167 .srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc,
2168 .srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser,
2169 .srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt,
2170 .srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr,
2171 .srcimp_mgr_commit_write = srcimp_mgr_commit_write,
2172
2173 .amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk,
2174 .amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk,
2175 .amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk,
2176 .amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk,
2177 .amixer_set_mode = amixer_set_mode,
2178 .amixer_set_iv = amixer_set_iv,
2179 .amixer_set_x = amixer_set_x,
2180 .amixer_set_y = amixer_set_y,
2181 .amixer_set_sadr = amixer_set_sadr,
2182 .amixer_set_se = amixer_set_se,
2183 .amixer_set_dirty = amixer_set_dirty,
2184 .amixer_set_dirty_all = amixer_set_dirty_all,
2185 .amixer_commit_write = amixer_commit_write,
2186 .amixer_get_y = amixer_get_y,
2187 .amixer_get_dirty = amixer_get_dirty,
2188
2189 .dai_get_ctrl_blk = dai_get_ctrl_blk,
2190 .dai_put_ctrl_blk = dai_put_ctrl_blk,
2191 .dai_srt_set_srco = dai_srt_set_srcr,
2192 .dai_srt_set_srcm = dai_srt_set_srcl,
2193 .dai_srt_set_rsr = dai_srt_set_rsr,
2194 .dai_srt_set_drat = dai_srt_set_drat,
2195 .dai_srt_set_ec = dai_srt_set_ec,
2196 .dai_srt_set_et = dai_srt_set_et,
2197 .dai_commit_write = dai_commit_write,
2198
2199 .dao_get_ctrl_blk = dao_get_ctrl_blk,
2200 .dao_put_ctrl_blk = dao_put_ctrl_blk,
2201 .dao_set_spos = dao_set_spos,
2202 .dao_commit_write = dao_commit_write,
2203 .dao_get_spos = dao_get_spos,
2204
2205 .daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk,
2206 .daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk,
2207 .daio_mgr_enb_dai = daio_mgr_enb_dai,
2208 .daio_mgr_dsb_dai = daio_mgr_dsb_dai,
2209 .daio_mgr_enb_dao = daio_mgr_enb_dao,
2210 .daio_mgr_dsb_dao = daio_mgr_dsb_dao,
2211 .daio_mgr_dao_init = daio_mgr_dao_init,
2212 .daio_mgr_set_imaparc = daio_mgr_set_imaparc,
2213 .daio_mgr_set_imapnxt = daio_mgr_set_imapnxt,
2214 .daio_mgr_set_imapaddr = daio_mgr_set_imapaddr,
2215 .daio_mgr_commit_write = daio_mgr_commit_write,
2216
2217 .set_timer_irq = set_timer_irq,
2218 .set_timer_tick = set_timer_tick,
2219 .get_wc = get_wc,
2220};
2221
2222int __devinit create_20k1_hw_obj(struct hw **rhw)
2223{
2224 struct hw20k1 *hw20k1;
2225
2226 *rhw = NULL;
2227 hw20k1 = kzalloc(sizeof(*hw20k1), GFP_KERNEL);
2228 if (NULL == hw20k1)
2229 return -ENOMEM;
2230
2231 spin_lock_init(&hw20k1->reg_20k1_lock);
2232 spin_lock_init(&hw20k1->reg_pci_lock);
2233
2234 hw20k1->hw = ct20k1_preset;
2235
2236 *rhw = &hw20k1->hw;
2237
2238 return 0;
2239}
2240
2241int destroy_20k1_hw_obj(struct hw *hw)
2242{
2243 if (hw->io_base)
2244 hw_card_shutdown(hw);
2245
2246 kfree(container_of(hw, struct hw20k1, hw));
2247 return 0;
2248}
diff --git a/sound/pci/ctxfi/cthw20k1.h b/sound/pci/ctxfi/cthw20k1.h
new file mode 100644
index 00000000000..02f72fb448a
--- /dev/null
+++ b/sound/pci/ctxfi/cthw20k1.h
@@ -0,0 +1,26 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File cthw20k1.h
9 *
10 * @Brief
11 * This file contains the definition of hardware access methord.
12 *
13 * @Author Liu Chun
14 * @Date May 13 2008
15 *
16 */
17
18#ifndef CTHW20K1_H
19#define CTHW20K1_H
20
21#include "cthardware.h"
22
23int create_20k1_hw_obj(struct hw **rhw);
24int destroy_20k1_hw_obj(struct hw *hw);
25
26#endif /* CTHW20K1_H */
diff --git a/sound/pci/ctxfi/cthw20k2.c b/sound/pci/ctxfi/cthw20k2.c
new file mode 100644
index 00000000000..4493a51c6b0
--- /dev/null
+++ b/sound/pci/ctxfi/cthw20k2.c
@@ -0,0 +1,2137 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File cthw20k2.c
9 *
10 * @Brief
11 * This file contains the implementation of hardware access methord for 20k2.
12 *
13 * @Author Liu Chun
14 * @Date May 14 2008
15 *
16 */
17
18#include <linux/types.h>
19#include <linux/slab.h>
20#include <linux/pci.h>
21#include <linux/io.h>
22#include <linux/string.h>
23#include <linux/kernel.h>
24#include <linux/interrupt.h>
25#include <linux/delay.h>
26#include "cthw20k2.h"
27#include "ct20k2reg.h"
28
29#if BITS_PER_LONG == 32
30#define CT_XFI_DMA_MASK DMA_BIT_MASK(32) /* 32 bit PTE */
31#else
32#define CT_XFI_DMA_MASK DMA_BIT_MASK(64) /* 64 bit PTE */
33#endif
34
35struct hw20k2 {
36 struct hw hw;
37 /* for i2c */
38 unsigned char dev_id;
39 unsigned char addr_size;
40 unsigned char data_size;
41};
42
43static u32 hw_read_20kx(struct hw *hw, u32 reg);
44static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
45
46/*
47 * Type definition block.
48 * The layout of control structures can be directly applied on 20k2 chip.
49 */
50
51/*
52 * SRC control block definitions.
53 */
54
55/* SRC resource control block */
56#define SRCCTL_STATE 0x00000007
57#define SRCCTL_BM 0x00000008
58#define SRCCTL_RSR 0x00000030
59#define SRCCTL_SF 0x000001C0
60#define SRCCTL_WR 0x00000200
61#define SRCCTL_PM 0x00000400
62#define SRCCTL_ROM 0x00001800
63#define SRCCTL_VO 0x00002000
64#define SRCCTL_ST 0x00004000
65#define SRCCTL_IE 0x00008000
66#define SRCCTL_ILSZ 0x000F0000
67#define SRCCTL_BP 0x00100000
68
69#define SRCCCR_CISZ 0x000007FF
70#define SRCCCR_CWA 0x001FF800
71#define SRCCCR_D 0x00200000
72#define SRCCCR_RS 0x01C00000
73#define SRCCCR_NAL 0x3E000000
74#define SRCCCR_RA 0xC0000000
75
76#define SRCCA_CA 0x0FFFFFFF
77#define SRCCA_RS 0xE0000000
78
79#define SRCSA_SA 0x0FFFFFFF
80
81#define SRCLA_LA 0x0FFFFFFF
82
83/* Mixer Parameter Ring ram Low and Hight register.
84 * Fixed-point value in 8.24 format for parameter channel */
85#define MPRLH_PITCH 0xFFFFFFFF
86
87/* SRC resource register dirty flags */
88union src_dirty {
89 struct {
90 u16 ctl:1;
91 u16 ccr:1;
92 u16 sa:1;
93 u16 la:1;
94 u16 ca:1;
95 u16 mpr:1;
96 u16 czbfs:1; /* Clear Z-Buffers */
97 u16 rsv:9;
98 } bf;
99 u16 data;
100};
101
102struct src_rsc_ctrl_blk {
103 unsigned int ctl;
104 unsigned int ccr;
105 unsigned int ca;
106 unsigned int sa;
107 unsigned int la;
108 unsigned int mpr;
109 union src_dirty dirty;
110};
111
112/* SRC manager control block */
113union src_mgr_dirty {
114 struct {
115 u16 enb0:1;
116 u16 enb1:1;
117 u16 enb2:1;
118 u16 enb3:1;
119 u16 enb4:1;
120 u16 enb5:1;
121 u16 enb6:1;
122 u16 enb7:1;
123 u16 enbsa:1;
124 u16 rsv:7;
125 } bf;
126 u16 data;
127};
128
129struct src_mgr_ctrl_blk {
130 unsigned int enbsa;
131 unsigned int enb[8];
132 union src_mgr_dirty dirty;
133};
134
135/* SRCIMP manager control block */
136#define SRCAIM_ARC 0x00000FFF
137#define SRCAIM_NXT 0x00FF0000
138#define SRCAIM_SRC 0xFF000000
139
140struct srcimap {
141 unsigned int srcaim;
142 unsigned int idx;
143};
144
145/* SRCIMP manager register dirty flags */
146union srcimp_mgr_dirty {
147 struct {
148 u16 srcimap:1;
149 u16 rsv:15;
150 } bf;
151 u16 data;
152};
153
154struct srcimp_mgr_ctrl_blk {
155 struct srcimap srcimap;
156 union srcimp_mgr_dirty dirty;
157};
158
159/*
160 * Function implementation block.
161 */
162
163static int src_get_rsc_ctrl_blk(void **rblk)
164{
165 struct src_rsc_ctrl_blk *blk;
166
167 *rblk = NULL;
168 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
169 if (NULL == blk)
170 return -ENOMEM;
171
172 *rblk = blk;
173
174 return 0;
175}
176
177static int src_put_rsc_ctrl_blk(void *blk)
178{
179 kfree(blk);
180
181 return 0;
182}
183
184static int src_set_state(void *blk, unsigned int state)
185{
186 struct src_rsc_ctrl_blk *ctl = blk;
187
188 set_field(&ctl->ctl, SRCCTL_STATE, state);
189 ctl->dirty.bf.ctl = 1;
190 return 0;
191}
192
193static int src_set_bm(void *blk, unsigned int bm)
194{
195 struct src_rsc_ctrl_blk *ctl = blk;
196
197 set_field(&ctl->ctl, SRCCTL_BM, bm);
198 ctl->dirty.bf.ctl = 1;
199 return 0;
200}
201
202static int src_set_rsr(void *blk, unsigned int rsr)
203{
204 struct src_rsc_ctrl_blk *ctl = blk;
205
206 set_field(&ctl->ctl, SRCCTL_RSR, rsr);
207 ctl->dirty.bf.ctl = 1;
208 return 0;
209}
210
211static int src_set_sf(void *blk, unsigned int sf)
212{
213 struct src_rsc_ctrl_blk *ctl = blk;
214
215 set_field(&ctl->ctl, SRCCTL_SF, sf);
216 ctl->dirty.bf.ctl = 1;
217 return 0;
218}
219
220static int src_set_wr(void *blk, unsigned int wr)
221{
222 struct src_rsc_ctrl_blk *ctl = blk;
223
224 set_field(&ctl->ctl, SRCCTL_WR, wr);
225 ctl->dirty.bf.ctl = 1;
226 return 0;
227}
228
229static int src_set_pm(void *blk, unsigned int pm)
230{
231 struct src_rsc_ctrl_blk *ctl = blk;
232
233 set_field(&ctl->ctl, SRCCTL_PM, pm);
234 ctl->dirty.bf.ctl = 1;
235 return 0;
236}
237
238static int src_set_rom(void *blk, unsigned int rom)
239{
240 struct src_rsc_ctrl_blk *ctl = blk;
241
242 set_field(&ctl->ctl, SRCCTL_ROM, rom);
243 ctl->dirty.bf.ctl = 1;
244 return 0;
245}
246
247static int src_set_vo(void *blk, unsigned int vo)
248{
249 struct src_rsc_ctrl_blk *ctl = blk;
250
251 set_field(&ctl->ctl, SRCCTL_VO, vo);
252 ctl->dirty.bf.ctl = 1;
253 return 0;
254}
255
256static int src_set_st(void *blk, unsigned int st)
257{
258 struct src_rsc_ctrl_blk *ctl = blk;
259
260 set_field(&ctl->ctl, SRCCTL_ST, st);
261 ctl->dirty.bf.ctl = 1;
262 return 0;
263}
264
265static int src_set_ie(void *blk, unsigned int ie)
266{
267 struct src_rsc_ctrl_blk *ctl = blk;
268
269 set_field(&ctl->ctl, SRCCTL_IE, ie);
270 ctl->dirty.bf.ctl = 1;
271 return 0;
272}
273
274static int src_set_ilsz(void *blk, unsigned int ilsz)
275{
276 struct src_rsc_ctrl_blk *ctl = blk;
277
278 set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
279 ctl->dirty.bf.ctl = 1;
280 return 0;
281}
282
283static int src_set_bp(void *blk, unsigned int bp)
284{
285 struct src_rsc_ctrl_blk *ctl = blk;
286
287 set_field(&ctl->ctl, SRCCTL_BP, bp);
288 ctl->dirty.bf.ctl = 1;
289 return 0;
290}
291
292static int src_set_cisz(void *blk, unsigned int cisz)
293{
294 struct src_rsc_ctrl_blk *ctl = blk;
295
296 set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
297 ctl->dirty.bf.ccr = 1;
298 return 0;
299}
300
301static int src_set_ca(void *blk, unsigned int ca)
302{
303 struct src_rsc_ctrl_blk *ctl = blk;
304
305 set_field(&ctl->ca, SRCCA_CA, ca);
306 ctl->dirty.bf.ca = 1;
307 return 0;
308}
309
310static int src_set_sa(void *blk, unsigned int sa)
311{
312 struct src_rsc_ctrl_blk *ctl = blk;
313
314 set_field(&ctl->sa, SRCSA_SA, sa);
315 ctl->dirty.bf.sa = 1;
316 return 0;
317}
318
319static int src_set_la(void *blk, unsigned int la)
320{
321 struct src_rsc_ctrl_blk *ctl = blk;
322
323 set_field(&ctl->la, SRCLA_LA, la);
324 ctl->dirty.bf.la = 1;
325 return 0;
326}
327
328static int src_set_pitch(void *blk, unsigned int pitch)
329{
330 struct src_rsc_ctrl_blk *ctl = blk;
331
332 set_field(&ctl->mpr, MPRLH_PITCH, pitch);
333 ctl->dirty.bf.mpr = 1;
334 return 0;
335}
336
337static int src_set_clear_zbufs(void *blk, unsigned int clear)
338{
339 ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
340 return 0;
341}
342
343static int src_set_dirty(void *blk, unsigned int flags)
344{
345 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
346 return 0;
347}
348
349static int src_set_dirty_all(void *blk)
350{
351 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
352 return 0;
353}
354
355#define AR_SLOT_SIZE 4096
356#define AR_SLOT_BLOCK_SIZE 16
357#define AR_PTS_PITCH 6
358#define AR_PARAM_SRC_OFFSET 0x60
359
360static unsigned int src_param_pitch_mixer(unsigned int src_idx)
361{
362 return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE
363 - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
364
365}
366
367static int src_commit_write(struct hw *hw, unsigned int idx, void *blk)
368{
369 struct src_rsc_ctrl_blk *ctl = blk;
370 int i;
371
372 if (ctl->dirty.bf.czbfs) {
373 /* Clear Z-Buffer registers */
374 for (i = 0; i < 8; i++)
375 hw_write_20kx(hw, SRC_UPZ+idx*0x100+i*0x4, 0);
376
377 for (i = 0; i < 4; i++)
378 hw_write_20kx(hw, SRC_DN0Z+idx*0x100+i*0x4, 0);
379
380 for (i = 0; i < 8; i++)
381 hw_write_20kx(hw, SRC_DN1Z+idx*0x100+i*0x4, 0);
382
383 ctl->dirty.bf.czbfs = 0;
384 }
385 if (ctl->dirty.bf.mpr) {
386 /* Take the parameter mixer resource in the same group as that
387 * the idx src is in for simplicity. Unlike src, all conjugate
388 * parameter mixer resources must be programmed for
389 * corresponding conjugate src resources. */
390 unsigned int pm_idx = src_param_pitch_mixer(idx);
391 hw_write_20kx(hw, MIXER_PRING_LO_HI+4*pm_idx, ctl->mpr);
392 hw_write_20kx(hw, MIXER_PMOPLO+8*pm_idx, 0x3);
393 hw_write_20kx(hw, MIXER_PMOPHI+8*pm_idx, 0x0);
394 ctl->dirty.bf.mpr = 0;
395 }
396 if (ctl->dirty.bf.sa) {
397 hw_write_20kx(hw, SRC_SA+idx*0x100, ctl->sa);
398 ctl->dirty.bf.sa = 0;
399 }
400 if (ctl->dirty.bf.la) {
401 hw_write_20kx(hw, SRC_LA+idx*0x100, ctl->la);
402 ctl->dirty.bf.la = 0;
403 }
404 if (ctl->dirty.bf.ca) {
405 hw_write_20kx(hw, SRC_CA+idx*0x100, ctl->ca);
406 ctl->dirty.bf.ca = 0;
407 }
408
409 /* Write srccf register */
410 hw_write_20kx(hw, SRC_CF+idx*0x100, 0x0);
411
412 if (ctl->dirty.bf.ccr) {
413 hw_write_20kx(hw, SRC_CCR+idx*0x100, ctl->ccr);
414 ctl->dirty.bf.ccr = 0;
415 }
416 if (ctl->dirty.bf.ctl) {
417 hw_write_20kx(hw, SRC_CTL+idx*0x100, ctl->ctl);
418 ctl->dirty.bf.ctl = 0;
419 }
420
421 return 0;
422}
423
424static int src_get_ca(struct hw *hw, unsigned int idx, void *blk)
425{
426 struct src_rsc_ctrl_blk *ctl = blk;
427
428 ctl->ca = hw_read_20kx(hw, SRC_CA+idx*0x100);
429 ctl->dirty.bf.ca = 0;
430
431 return get_field(ctl->ca, SRCCA_CA);
432}
433
434static unsigned int src_get_dirty(void *blk)
435{
436 return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
437}
438
439static unsigned int src_dirty_conj_mask(void)
440{
441 return 0x20;
442}
443
444static int src_mgr_enbs_src(void *blk, unsigned int idx)
445{
446 ((struct src_mgr_ctrl_blk *)blk)->enbsa |= (0x1 << ((idx%128)/4));
447 ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
448 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
449 return 0;
450}
451
452static int src_mgr_enb_src(void *blk, unsigned int idx)
453{
454 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
455 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
456 return 0;
457}
458
459static int src_mgr_dsb_src(void *blk, unsigned int idx)
460{
461 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
462 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
463 return 0;
464}
465
466static int src_mgr_commit_write(struct hw *hw, void *blk)
467{
468 struct src_mgr_ctrl_blk *ctl = blk;
469 int i;
470 unsigned int ret;
471
472 if (ctl->dirty.bf.enbsa) {
473 do {
474 ret = hw_read_20kx(hw, SRC_ENBSTAT);
475 } while (ret & 0x1);
476 hw_write_20kx(hw, SRC_ENBSA, ctl->enbsa);
477 ctl->dirty.bf.enbsa = 0;
478 }
479 for (i = 0; i < 8; i++) {
480 if ((ctl->dirty.data & (0x1 << i))) {
481 hw_write_20kx(hw, SRC_ENB+(i*0x100), ctl->enb[i]);
482 ctl->dirty.data &= ~(0x1 << i);
483 }
484 }
485
486 return 0;
487}
488
489static int src_mgr_get_ctrl_blk(void **rblk)
490{
491 struct src_mgr_ctrl_blk *blk;
492
493 *rblk = NULL;
494 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
495 if (NULL == blk)
496 return -ENOMEM;
497
498 *rblk = blk;
499
500 return 0;
501}
502
503static int src_mgr_put_ctrl_blk(void *blk)
504{
505 kfree(blk);
506
507 return 0;
508}
509
510static int srcimp_mgr_get_ctrl_blk(void **rblk)
511{
512 struct srcimp_mgr_ctrl_blk *blk;
513
514 *rblk = NULL;
515 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
516 if (NULL == blk)
517 return -ENOMEM;
518
519 *rblk = blk;
520
521 return 0;
522}
523
524static int srcimp_mgr_put_ctrl_blk(void *blk)
525{
526 kfree(blk);
527
528 return 0;
529}
530
531static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot)
532{
533 struct srcimp_mgr_ctrl_blk *ctl = blk;
534
535 set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
536 ctl->dirty.bf.srcimap = 1;
537 return 0;
538}
539
540static int srcimp_mgr_set_imapuser(void *blk, unsigned int user)
541{
542 struct srcimp_mgr_ctrl_blk *ctl = blk;
543
544 set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
545 ctl->dirty.bf.srcimap = 1;
546 return 0;
547}
548
549static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next)
550{
551 struct srcimp_mgr_ctrl_blk *ctl = blk;
552
553 set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
554 ctl->dirty.bf.srcimap = 1;
555 return 0;
556}
557
558static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr)
559{
560 ((struct srcimp_mgr_ctrl_blk *)blk)->srcimap.idx = addr;
561 ((struct srcimp_mgr_ctrl_blk *)blk)->dirty.bf.srcimap = 1;
562 return 0;
563}
564
565static int srcimp_mgr_commit_write(struct hw *hw, void *blk)
566{
567 struct srcimp_mgr_ctrl_blk *ctl = blk;
568
569 if (ctl->dirty.bf.srcimap) {
570 hw_write_20kx(hw, SRC_IMAP+ctl->srcimap.idx*0x100,
571 ctl->srcimap.srcaim);
572 ctl->dirty.bf.srcimap = 0;
573 }
574
575 return 0;
576}
577
578/*
579 * AMIXER control block definitions.
580 */
581
582#define AMOPLO_M 0x00000003
583#define AMOPLO_IV 0x00000004
584#define AMOPLO_X 0x0003FFF0
585#define AMOPLO_Y 0xFFFC0000
586
587#define AMOPHI_SADR 0x000000FF
588#define AMOPHI_SE 0x80000000
589
590/* AMIXER resource register dirty flags */
591union amixer_dirty {
592 struct {
593 u16 amoplo:1;
594 u16 amophi:1;
595 u16 rsv:14;
596 } bf;
597 u16 data;
598};
599
600/* AMIXER resource control block */
601struct amixer_rsc_ctrl_blk {
602 unsigned int amoplo;
603 unsigned int amophi;
604 union amixer_dirty dirty;
605};
606
607static int amixer_set_mode(void *blk, unsigned int mode)
608{
609 struct amixer_rsc_ctrl_blk *ctl = blk;
610
611 set_field(&ctl->amoplo, AMOPLO_M, mode);
612 ctl->dirty.bf.amoplo = 1;
613 return 0;
614}
615
616static int amixer_set_iv(void *blk, unsigned int iv)
617{
618 struct amixer_rsc_ctrl_blk *ctl = blk;
619
620 set_field(&ctl->amoplo, AMOPLO_IV, iv);
621 ctl->dirty.bf.amoplo = 1;
622 return 0;
623}
624
625static int amixer_set_x(void *blk, unsigned int x)
626{
627 struct amixer_rsc_ctrl_blk *ctl = blk;
628
629 set_field(&ctl->amoplo, AMOPLO_X, x);
630 ctl->dirty.bf.amoplo = 1;
631 return 0;
632}
633
634static int amixer_set_y(void *blk, unsigned int y)
635{
636 struct amixer_rsc_ctrl_blk *ctl = blk;
637
638 set_field(&ctl->amoplo, AMOPLO_Y, y);
639 ctl->dirty.bf.amoplo = 1;
640 return 0;
641}
642
643static int amixer_set_sadr(void *blk, unsigned int sadr)
644{
645 struct amixer_rsc_ctrl_blk *ctl = blk;
646
647 set_field(&ctl->amophi, AMOPHI_SADR, sadr);
648 ctl->dirty.bf.amophi = 1;
649 return 0;
650}
651
652static int amixer_set_se(void *blk, unsigned int se)
653{
654 struct amixer_rsc_ctrl_blk *ctl = blk;
655
656 set_field(&ctl->amophi, AMOPHI_SE, se);
657 ctl->dirty.bf.amophi = 1;
658 return 0;
659}
660
661static int amixer_set_dirty(void *blk, unsigned int flags)
662{
663 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
664 return 0;
665}
666
667static int amixer_set_dirty_all(void *blk)
668{
669 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
670 return 0;
671}
672
673static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk)
674{
675 struct amixer_rsc_ctrl_blk *ctl = blk;
676
677 if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
678 hw_write_20kx(hw, MIXER_AMOPLO+idx*8, ctl->amoplo);
679 ctl->dirty.bf.amoplo = 0;
680 hw_write_20kx(hw, MIXER_AMOPHI+idx*8, ctl->amophi);
681 ctl->dirty.bf.amophi = 0;
682 }
683
684 return 0;
685}
686
687static int amixer_get_y(void *blk)
688{
689 struct amixer_rsc_ctrl_blk *ctl = blk;
690
691 return get_field(ctl->amoplo, AMOPLO_Y);
692}
693
694static unsigned int amixer_get_dirty(void *blk)
695{
696 return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
697}
698
699static int amixer_rsc_get_ctrl_blk(void **rblk)
700{
701 struct amixer_rsc_ctrl_blk *blk;
702
703 *rblk = NULL;
704 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
705 if (NULL == blk)
706 return -ENOMEM;
707
708 *rblk = blk;
709
710 return 0;
711}
712
713static int amixer_rsc_put_ctrl_blk(void *blk)
714{
715 kfree(blk);
716
717 return 0;
718}
719
720static int amixer_mgr_get_ctrl_blk(void **rblk)
721{
722 *rblk = NULL;
723
724 return 0;
725}
726
727static int amixer_mgr_put_ctrl_blk(void *blk)
728{
729 return 0;
730}
731
732/*
733 * DAIO control block definitions.
734 */
735
736/* Receiver Sample Rate Tracker Control register */
737#define SRTCTL_SRCO 0x000000FF
738#define SRTCTL_SRCM 0x0000FF00
739#define SRTCTL_RSR 0x00030000
740#define SRTCTL_DRAT 0x00300000
741#define SRTCTL_EC 0x01000000
742#define SRTCTL_ET 0x10000000
743
744/* DAIO Receiver register dirty flags */
745union dai_dirty {
746 struct {
747 u16 srt:1;
748 u16 rsv:15;
749 } bf;
750 u16 data;
751};
752
753/* DAIO Receiver control block */
754struct dai_ctrl_blk {
755 unsigned int srt;
756 union dai_dirty dirty;
757};
758
759/* Audio Input Mapper RAM */
760#define AIM_ARC 0x00000FFF
761#define AIM_NXT 0x007F0000
762
763struct daoimap {
764 unsigned int aim;
765 unsigned int idx;
766};
767
768/* Audio Transmitter Control and Status register */
769#define ATXCTL_EN 0x00000001
770#define ATXCTL_MODE 0x00000010
771#define ATXCTL_CD 0x00000020
772#define ATXCTL_RAW 0x00000100
773#define ATXCTL_MT 0x00000200
774#define ATXCTL_NUC 0x00003000
775#define ATXCTL_BEN 0x00010000
776#define ATXCTL_BMUX 0x00700000
777#define ATXCTL_B24 0x01000000
778#define ATXCTL_CPF 0x02000000
779#define ATXCTL_RIV 0x10000000
780#define ATXCTL_LIV 0x20000000
781#define ATXCTL_RSAT 0x40000000
782#define ATXCTL_LSAT 0x80000000
783
784/* XDIF Transmitter register dirty flags */
785union dao_dirty {
786 struct {
787 u16 atxcsl:1;
788 u16 rsv:15;
789 } bf;
790 u16 data;
791};
792
793/* XDIF Transmitter control block */
794struct dao_ctrl_blk {
795 /* XDIF Transmitter Channel Status Low Register */
796 unsigned int atxcsl;
797 union dao_dirty dirty;
798};
799
800/* Audio Receiver Control register */
801#define ARXCTL_EN 0x00000001
802
803/* DAIO manager register dirty flags */
804union daio_mgr_dirty {
805 struct {
806 u32 atxctl:8;
807 u32 arxctl:8;
808 u32 daoimap:1;
809 u32 rsv:15;
810 } bf;
811 u32 data;
812};
813
814/* DAIO manager control block */
815struct daio_mgr_ctrl_blk {
816 struct daoimap daoimap;
817 unsigned int txctl[8];
818 unsigned int rxctl[8];
819 union daio_mgr_dirty dirty;
820};
821
822static int dai_srt_set_srco(void *blk, unsigned int src)
823{
824 struct dai_ctrl_blk *ctl = blk;
825
826 set_field(&ctl->srt, SRTCTL_SRCO, src);
827 ctl->dirty.bf.srt = 1;
828 return 0;
829}
830
831static int dai_srt_set_srcm(void *blk, unsigned int src)
832{
833 struct dai_ctrl_blk *ctl = blk;
834
835 set_field(&ctl->srt, SRTCTL_SRCM, src);
836 ctl->dirty.bf.srt = 1;
837 return 0;
838}
839
840static int dai_srt_set_rsr(void *blk, unsigned int rsr)
841{
842 struct dai_ctrl_blk *ctl = blk;
843
844 set_field(&ctl->srt, SRTCTL_RSR, rsr);
845 ctl->dirty.bf.srt = 1;
846 return 0;
847}
848
849static int dai_srt_set_drat(void *blk, unsigned int drat)
850{
851 struct dai_ctrl_blk *ctl = blk;
852
853 set_field(&ctl->srt, SRTCTL_DRAT, drat);
854 ctl->dirty.bf.srt = 1;
855 return 0;
856}
857
858static int dai_srt_set_ec(void *blk, unsigned int ec)
859{
860 struct dai_ctrl_blk *ctl = blk;
861
862 set_field(&ctl->srt, SRTCTL_EC, ec ? 1 : 0);
863 ctl->dirty.bf.srt = 1;
864 return 0;
865}
866
867static int dai_srt_set_et(void *blk, unsigned int et)
868{
869 struct dai_ctrl_blk *ctl = blk;
870
871 set_field(&ctl->srt, SRTCTL_ET, et ? 1 : 0);
872 ctl->dirty.bf.srt = 1;
873 return 0;
874}
875
876static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk)
877{
878 struct dai_ctrl_blk *ctl = blk;
879
880 if (ctl->dirty.bf.srt) {
881 hw_write_20kx(hw, AUDIO_IO_RX_SRT_CTL+0x40*idx, ctl->srt);
882 ctl->dirty.bf.srt = 0;
883 }
884
885 return 0;
886}
887
888static int dai_get_ctrl_blk(void **rblk)
889{
890 struct dai_ctrl_blk *blk;
891
892 *rblk = NULL;
893 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
894 if (NULL == blk)
895 return -ENOMEM;
896
897 *rblk = blk;
898
899 return 0;
900}
901
902static int dai_put_ctrl_blk(void *blk)
903{
904 kfree(blk);
905
906 return 0;
907}
908
909static int dao_set_spos(void *blk, unsigned int spos)
910{
911 ((struct dao_ctrl_blk *)blk)->atxcsl = spos;
912 ((struct dao_ctrl_blk *)blk)->dirty.bf.atxcsl = 1;
913 return 0;
914}
915
916static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk)
917{
918 struct dao_ctrl_blk *ctl = blk;
919
920 if (ctl->dirty.bf.atxcsl) {
921 if (idx < 4) {
922 /* S/PDIF SPOSx */
923 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+0x40*idx,
924 ctl->atxcsl);
925 }
926 ctl->dirty.bf.atxcsl = 0;
927 }
928
929 return 0;
930}
931
932static int dao_get_spos(void *blk, unsigned int *spos)
933{
934 *spos = ((struct dao_ctrl_blk *)blk)->atxcsl;
935 return 0;
936}
937
938static int dao_get_ctrl_blk(void **rblk)
939{
940 struct dao_ctrl_blk *blk;
941
942 *rblk = NULL;
943 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
944 if (NULL == blk)
945 return -ENOMEM;
946
947 *rblk = blk;
948
949 return 0;
950}
951
952static int dao_put_ctrl_blk(void *blk)
953{
954 kfree(blk);
955
956 return 0;
957}
958
959static int daio_mgr_enb_dai(void *blk, unsigned int idx)
960{
961 struct daio_mgr_ctrl_blk *ctl = blk;
962
963 set_field(&ctl->rxctl[idx], ARXCTL_EN, 1);
964 ctl->dirty.bf.arxctl |= (0x1 << idx);
965 return 0;
966}
967
968static int daio_mgr_dsb_dai(void *blk, unsigned int idx)
969{
970 struct daio_mgr_ctrl_blk *ctl = blk;
971
972 set_field(&ctl->rxctl[idx], ARXCTL_EN, 0);
973
974 ctl->dirty.bf.arxctl |= (0x1 << idx);
975 return 0;
976}
977
978static int daio_mgr_enb_dao(void *blk, unsigned int idx)
979{
980 struct daio_mgr_ctrl_blk *ctl = blk;
981
982 set_field(&ctl->txctl[idx], ATXCTL_EN, 1);
983 ctl->dirty.bf.atxctl |= (0x1 << idx);
984 return 0;
985}
986
987static int daio_mgr_dsb_dao(void *blk, unsigned int idx)
988{
989 struct daio_mgr_ctrl_blk *ctl = blk;
990
991 set_field(&ctl->txctl[idx], ATXCTL_EN, 0);
992 ctl->dirty.bf.atxctl |= (0x1 << idx);
993 return 0;
994}
995
996static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf)
997{
998 struct daio_mgr_ctrl_blk *ctl = blk;
999
1000 if (idx < 4) {
1001 /* S/PDIF output */
1002 switch ((conf & 0x7)) {
1003 case 1:
1004 set_field(&ctl->txctl[idx], ATXCTL_NUC, 0);
1005 break;
1006 case 2:
1007 set_field(&ctl->txctl[idx], ATXCTL_NUC, 1);
1008 break;
1009 case 4:
1010 set_field(&ctl->txctl[idx], ATXCTL_NUC, 2);
1011 break;
1012 case 8:
1013 set_field(&ctl->txctl[idx], ATXCTL_NUC, 3);
1014 break;
1015 default:
1016 break;
1017 }
1018 /* CDIF */
1019 set_field(&ctl->txctl[idx], ATXCTL_CD, (!(conf & 0x7)));
1020 /* Non-audio */
1021 set_field(&ctl->txctl[idx], ATXCTL_LIV, (conf >> 4) & 0x1);
1022 /* Non-audio */
1023 set_field(&ctl->txctl[idx], ATXCTL_RIV, (conf >> 4) & 0x1);
1024 set_field(&ctl->txctl[idx], ATXCTL_RAW,
1025 ((conf >> 3) & 0x1) ? 0 : 0);
1026 ctl->dirty.bf.atxctl |= (0x1 << idx);
1027 } else {
1028 /* I2S output */
1029 /*idx %= 4; */
1030 }
1031 return 0;
1032}
1033
1034static int daio_mgr_set_imaparc(void *blk, unsigned int slot)
1035{
1036 struct daio_mgr_ctrl_blk *ctl = blk;
1037
1038 set_field(&ctl->daoimap.aim, AIM_ARC, slot);
1039 ctl->dirty.bf.daoimap = 1;
1040 return 0;
1041}
1042
1043static int daio_mgr_set_imapnxt(void *blk, unsigned int next)
1044{
1045 struct daio_mgr_ctrl_blk *ctl = blk;
1046
1047 set_field(&ctl->daoimap.aim, AIM_NXT, next);
1048 ctl->dirty.bf.daoimap = 1;
1049 return 0;
1050}
1051
1052static int daio_mgr_set_imapaddr(void *blk, unsigned int addr)
1053{
1054 ((struct daio_mgr_ctrl_blk *)blk)->daoimap.idx = addr;
1055 ((struct daio_mgr_ctrl_blk *)blk)->dirty.bf.daoimap = 1;
1056 return 0;
1057}
1058
1059static int daio_mgr_commit_write(struct hw *hw, void *blk)
1060{
1061 struct daio_mgr_ctrl_blk *ctl = blk;
1062 unsigned int data;
1063 int i;
1064
1065 for (i = 0; i < 8; i++) {
1066 if ((ctl->dirty.bf.atxctl & (0x1 << i))) {
1067 data = ctl->txctl[i];
1068 hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data);
1069 ctl->dirty.bf.atxctl &= ~(0x1 << i);
1070 mdelay(1);
1071 }
1072 if ((ctl->dirty.bf.arxctl & (0x1 << i))) {
1073 data = ctl->rxctl[i];
1074 hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data);
1075 ctl->dirty.bf.arxctl &= ~(0x1 << i);
1076 mdelay(1);
1077 }
1078 }
1079 if (ctl->dirty.bf.daoimap) {
1080 hw_write_20kx(hw, AUDIO_IO_AIM+ctl->daoimap.idx*4,
1081 ctl->daoimap.aim);
1082 ctl->dirty.bf.daoimap = 0;
1083 }
1084
1085 return 0;
1086}
1087
1088static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk)
1089{
1090 struct daio_mgr_ctrl_blk *blk;
1091 int i;
1092
1093 *rblk = NULL;
1094 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
1095 if (NULL == blk)
1096 return -ENOMEM;
1097
1098 for (i = 0; i < 8; i++) {
1099 blk->txctl[i] = hw_read_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i));
1100 blk->rxctl[i] = hw_read_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i));
1101 }
1102
1103 *rblk = blk;
1104
1105 return 0;
1106}
1107
1108static int daio_mgr_put_ctrl_blk(void *blk)
1109{
1110 kfree(blk);
1111
1112 return 0;
1113}
1114
1115/* Card hardware initialization block */
1116struct dac_conf {
1117 unsigned int msr; /* master sample rate in rsrs */
1118};
1119
1120struct adc_conf {
1121 unsigned int msr; /* master sample rate in rsrs */
1122 unsigned char input; /* the input source of ADC */
1123 unsigned char mic20db; /* boost mic by 20db if input is microphone */
1124};
1125
1126struct daio_conf {
1127 unsigned int msr; /* master sample rate in rsrs */
1128};
1129
1130struct trn_conf {
1131 unsigned long vm_pgt_phys;
1132};
1133
1134static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
1135{
1136 u32 data;
1137 int i;
1138
1139 /* Program I2S with proper sample rate and enable the correct I2S
1140 * channel. ED(0/8/16/24): Enable all I2S/I2X master clock output */
1141 if (1 == info->msr) {
1142 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x01010101);
1143 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x01010101);
1144 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1145 } else if (2 == info->msr) {
1146 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11111111);
1147 /* Specify all playing 96khz
1148 * EA [0] - Enabled
1149 * RTA [4:5] - 96kHz
1150 * EB [8] - Enabled
1151 * RTB [12:13] - 96kHz
1152 * EC [16] - Enabled
1153 * RTC [20:21] - 96kHz
1154 * ED [24] - Enabled
1155 * RTD [28:29] - 96kHz */
1156 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x11111111);
1157 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1158 } else {
1159 printk(KERN_ALERT "ctxfi: ERROR!!! Invalid sampling rate!!!\n");
1160 return -EINVAL;
1161 }
1162
1163 for (i = 0; i < 8; i++) {
1164 if (i <= 3) {
1165 /* 1st 3 channels are SPDIFs (SB0960) */
1166 if (i == 3)
1167 data = 0x1001001;
1168 else
1169 data = 0x1000001;
1170
1171 hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data);
1172 hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data);
1173
1174 /* Initialize the SPDIF Out Channel status registers.
1175 * The value specified here is based on the typical
1176 * values provided in the specification, namely: Clock
1177 * Accuracy of 1000ppm, Sample Rate of 48KHz,
1178 * unspecified source number, Generation status = 1,
1179 * Category code = 0x12 (Digital Signal Mixer),
1180 * Mode = 0, Emph = 0, Copy Permitted, AN = 0
1181 * (indicating that we're transmitting digital audio,
1182 * and the Professional Use bit is 0. */
1183
1184 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+(0x40*i),
1185 0x02109204); /* Default to 48kHz */
1186
1187 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_H+(0x40*i), 0x0B);
1188 } else {
1189 /* Next 5 channels are I2S (SB0960) */
1190 data = 0x11;
1191 hw_write_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i), data);
1192 if (2 == info->msr) {
1193 /* Four channels per sample period */
1194 data |= 0x1000;
1195 }
1196 hw_write_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i), data);
1197 }
1198 }
1199
1200 return 0;
1201}
1202
1203/* TRANSPORT operations */
1204static int hw_trn_init(struct hw *hw, const struct trn_conf *info)
1205{
1206 u32 vmctl, data;
1207 u32 ptp_phys_low, ptp_phys_high;
1208 int i;
1209
1210 /* Set up device page table */
1211 if ((~0UL) == info->vm_pgt_phys) {
1212 printk(KERN_ALERT "ctxfi: "
1213 "Wrong device page table page address!!!\n");
1214 return -1;
1215 }
1216
1217 vmctl = 0x80000C0F; /* 32-bit, 4k-size page */
1218 ptp_phys_low = (u32)info->vm_pgt_phys;
1219 ptp_phys_high = upper_32_bits(info->vm_pgt_phys);
1220 if (sizeof(void *) == 8) /* 64bit address */
1221 vmctl |= (3 << 8);
1222 /* Write page table physical address to all PTPAL registers */
1223 for (i = 0; i < 64; i++) {
1224 hw_write_20kx(hw, VMEM_PTPAL+(16*i), ptp_phys_low);
1225 hw_write_20kx(hw, VMEM_PTPAH+(16*i), ptp_phys_high);
1226 }
1227 /* Enable virtual memory transfer */
1228 hw_write_20kx(hw, VMEM_CTL, vmctl);
1229 /* Enable transport bus master and queueing of request */
1230 hw_write_20kx(hw, TRANSPORT_CTL, 0x03);
1231 hw_write_20kx(hw, TRANSPORT_INT, 0x200c01);
1232 /* Enable transport ring */
1233 data = hw_read_20kx(hw, TRANSPORT_ENB);
1234 hw_write_20kx(hw, TRANSPORT_ENB, (data | 0x03));
1235
1236 return 0;
1237}
1238
1239/* Card initialization */
1240#define GCTL_AIE 0x00000001
1241#define GCTL_UAA 0x00000002
1242#define GCTL_DPC 0x00000004
1243#define GCTL_DBP 0x00000008
1244#define GCTL_ABP 0x00000010
1245#define GCTL_TBP 0x00000020
1246#define GCTL_SBP 0x00000040
1247#define GCTL_FBP 0x00000080
1248#define GCTL_ME 0x00000100
1249#define GCTL_AID 0x00001000
1250
1251#define PLLCTL_SRC 0x00000007
1252#define PLLCTL_SPE 0x00000008
1253#define PLLCTL_RD 0x000000F0
1254#define PLLCTL_FD 0x0001FF00
1255#define PLLCTL_OD 0x00060000
1256#define PLLCTL_B 0x00080000
1257#define PLLCTL_AS 0x00100000
1258#define PLLCTL_LF 0x03E00000
1259#define PLLCTL_SPS 0x1C000000
1260#define PLLCTL_AD 0x60000000
1261
1262#define PLLSTAT_CCS 0x00000007
1263#define PLLSTAT_SPL 0x00000008
1264#define PLLSTAT_CRD 0x000000F0
1265#define PLLSTAT_CFD 0x0001FF00
1266#define PLLSTAT_SL 0x00020000
1267#define PLLSTAT_FAS 0x00040000
1268#define PLLSTAT_B 0x00080000
1269#define PLLSTAT_PD 0x00100000
1270#define PLLSTAT_OCA 0x00200000
1271#define PLLSTAT_NCA 0x00400000
1272
1273static int hw_pll_init(struct hw *hw, unsigned int rsr)
1274{
1275 unsigned int pllenb;
1276 unsigned int pllctl;
1277 unsigned int pllstat;
1278 int i;
1279
1280 pllenb = 0xB;
1281 hw_write_20kx(hw, PLL_ENB, pllenb);
1282 pllctl = 0x20D00000;
1283 set_field(&pllctl, PLLCTL_FD, 16 - 4);
1284 hw_write_20kx(hw, PLL_CTL, pllctl);
1285 mdelay(40);
1286 pllctl = hw_read_20kx(hw, PLL_CTL);
1287 set_field(&pllctl, PLLCTL_B, 0);
1288 if (48000 == rsr) {
1289 set_field(&pllctl, PLLCTL_FD, 16 - 2);
1290 set_field(&pllctl, PLLCTL_RD, 1 - 1);
1291 } else { /* 44100 */
1292 set_field(&pllctl, PLLCTL_FD, 147 - 2);
1293 set_field(&pllctl, PLLCTL_RD, 10 - 1);
1294 }
1295 hw_write_20kx(hw, PLL_CTL, pllctl);
1296 mdelay(40);
1297 for (i = 0; i < 1000; i++) {
1298 pllstat = hw_read_20kx(hw, PLL_STAT);
1299 if (get_field(pllstat, PLLSTAT_PD))
1300 continue;
1301
1302 if (get_field(pllstat, PLLSTAT_B) !=
1303 get_field(pllctl, PLLCTL_B))
1304 continue;
1305
1306 if (get_field(pllstat, PLLSTAT_CCS) !=
1307 get_field(pllctl, PLLCTL_SRC))
1308 continue;
1309
1310 if (get_field(pllstat, PLLSTAT_CRD) !=
1311 get_field(pllctl, PLLCTL_RD))
1312 continue;
1313
1314 if (get_field(pllstat, PLLSTAT_CFD) !=
1315 get_field(pllctl, PLLCTL_FD))
1316 continue;
1317
1318 break;
1319 }
1320 if (i >= 1000) {
1321 printk(KERN_ALERT "ctxfi: PLL initialization failed!!!\n");
1322 return -EBUSY;
1323 }
1324
1325 return 0;
1326}
1327
1328static int hw_auto_init(struct hw *hw)
1329{
1330 unsigned int gctl;
1331 int i;
1332
1333 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1334 set_field(&gctl, GCTL_AIE, 0);
1335 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1336 set_field(&gctl, GCTL_AIE, 1);
1337 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1338 mdelay(10);
1339 for (i = 0; i < 400000; i++) {
1340 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1341 if (get_field(gctl, GCTL_AID))
1342 break;
1343 }
1344 if (!get_field(gctl, GCTL_AID)) {
1345 printk(KERN_ALERT "ctxfi: Card Auto-init failed!!!\n");
1346 return -EBUSY;
1347 }
1348
1349 return 0;
1350}
1351
1352/* DAC operations */
1353
1354#define CS4382_MC1 0x1
1355#define CS4382_MC2 0x2
1356#define CS4382_MC3 0x3
1357#define CS4382_FC 0x4
1358#define CS4382_IC 0x5
1359#define CS4382_XC1 0x6
1360#define CS4382_VCA1 0x7
1361#define CS4382_VCB1 0x8
1362#define CS4382_XC2 0x9
1363#define CS4382_VCA2 0xA
1364#define CS4382_VCB2 0xB
1365#define CS4382_XC3 0xC
1366#define CS4382_VCA3 0xD
1367#define CS4382_VCB3 0xE
1368#define CS4382_XC4 0xF
1369#define CS4382_VCA4 0x10
1370#define CS4382_VCB4 0x11
1371#define CS4382_CREV 0x12
1372
1373/* I2C status */
1374#define STATE_LOCKED 0x00
1375#define STATE_UNLOCKED 0xAA
1376#define DATA_READY 0x800000 /* Used with I2C_IF_STATUS */
1377#define DATA_ABORT 0x10000 /* Used with I2C_IF_STATUS */
1378
1379#define I2C_STATUS_DCM 0x00000001
1380#define I2C_STATUS_BC 0x00000006
1381#define I2C_STATUS_APD 0x00000008
1382#define I2C_STATUS_AB 0x00010000
1383#define I2C_STATUS_DR 0x00800000
1384
1385#define I2C_ADDRESS_PTAD 0x0000FFFF
1386#define I2C_ADDRESS_SLAD 0x007F0000
1387
1388struct regs_cs4382 {
1389 u32 mode_control_1;
1390 u32 mode_control_2;
1391 u32 mode_control_3;
1392
1393 u32 filter_control;
1394 u32 invert_control;
1395
1396 u32 mix_control_P1;
1397 u32 vol_control_A1;
1398 u32 vol_control_B1;
1399
1400 u32 mix_control_P2;
1401 u32 vol_control_A2;
1402 u32 vol_control_B2;
1403
1404 u32 mix_control_P3;
1405 u32 vol_control_A3;
1406 u32 vol_control_B3;
1407
1408 u32 mix_control_P4;
1409 u32 vol_control_A4;
1410 u32 vol_control_B4;
1411};
1412
1413static int hw20k2_i2c_unlock_full_access(struct hw *hw)
1414{
1415 u8 UnlockKeySequence_FLASH_FULLACCESS_MODE[2] = {0xB3, 0xD4};
1416
1417 /* Send keys for forced BIOS mode */
1418 hw_write_20kx(hw, I2C_IF_WLOCK,
1419 UnlockKeySequence_FLASH_FULLACCESS_MODE[0]);
1420 hw_write_20kx(hw, I2C_IF_WLOCK,
1421 UnlockKeySequence_FLASH_FULLACCESS_MODE[1]);
1422 /* Check whether the chip is unlocked */
1423 if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_UNLOCKED)
1424 return 0;
1425
1426 return -1;
1427}
1428
1429static int hw20k2_i2c_lock_chip(struct hw *hw)
1430{
1431 /* Write twice */
1432 hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
1433 hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
1434 if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_LOCKED)
1435 return 0;
1436
1437 return -1;
1438}
1439
1440static int hw20k2_i2c_init(struct hw *hw, u8 dev_id, u8 addr_size, u8 data_size)
1441{
1442 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1443 int err;
1444 unsigned int i2c_status;
1445 unsigned int i2c_addr;
1446
1447 err = hw20k2_i2c_unlock_full_access(hw);
1448 if (err < 0)
1449 return err;
1450
1451 hw20k2->addr_size = addr_size;
1452 hw20k2->data_size = data_size;
1453 hw20k2->dev_id = dev_id;
1454
1455 i2c_addr = 0;
1456 set_field(&i2c_addr, I2C_ADDRESS_SLAD, dev_id);
1457
1458 hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr);
1459
1460 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1461
1462 set_field(&i2c_status, I2C_STATUS_DCM, 1); /* Direct control mode */
1463
1464 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1465
1466 return 0;
1467}
1468
1469static int hw20k2_i2c_uninit(struct hw *hw)
1470{
1471 unsigned int i2c_status;
1472 unsigned int i2c_addr;
1473
1474 i2c_addr = 0;
1475 set_field(&i2c_addr, I2C_ADDRESS_SLAD, 0x57); /* I2C id */
1476
1477 hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr);
1478
1479 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1480
1481 set_field(&i2c_status, I2C_STATUS_DCM, 0); /* I2C mode */
1482
1483 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1484
1485 return hw20k2_i2c_lock_chip(hw);
1486}
1487
1488static int hw20k2_i2c_wait_data_ready(struct hw *hw)
1489{
1490 int i = 0x400000;
1491 unsigned int ret;
1492
1493 do {
1494 ret = hw_read_20kx(hw, I2C_IF_STATUS);
1495 } while ((!(ret & DATA_READY)) && --i);
1496
1497 return i;
1498}
1499
1500static int hw20k2_i2c_read(struct hw *hw, u16 addr, u32 *datap)
1501{
1502 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1503 unsigned int i2c_status;
1504
1505 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1506 set_field(&i2c_status, I2C_STATUS_BC,
1507 (4 == hw20k2->addr_size) ? 0 : hw20k2->addr_size);
1508 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1509 if (!hw20k2_i2c_wait_data_ready(hw))
1510 return -1;
1511
1512 hw_write_20kx(hw, I2C_IF_WDATA, addr);
1513 if (!hw20k2_i2c_wait_data_ready(hw))
1514 return -1;
1515
1516 /* Force a read operation */
1517 hw_write_20kx(hw, I2C_IF_RDATA, 0);
1518 if (!hw20k2_i2c_wait_data_ready(hw))
1519 return -1;
1520
1521 *datap = hw_read_20kx(hw, I2C_IF_RDATA);
1522
1523 return 0;
1524}
1525
1526static int hw20k2_i2c_write(struct hw *hw, u16 addr, u32 data)
1527{
1528 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1529 unsigned int i2c_data = (data << (hw20k2->addr_size * 8)) | addr;
1530 unsigned int i2c_status;
1531
1532 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1533
1534 set_field(&i2c_status, I2C_STATUS_BC,
1535 (4 == (hw20k2->addr_size + hw20k2->data_size)) ?
1536 0 : (hw20k2->addr_size + hw20k2->data_size));
1537
1538 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1539 hw20k2_i2c_wait_data_ready(hw);
1540 /* Dummy write to trigger the write oprtation */
1541 hw_write_20kx(hw, I2C_IF_WDATA, 0);
1542 hw20k2_i2c_wait_data_ready(hw);
1543
1544 /* This is the real data */
1545 hw_write_20kx(hw, I2C_IF_WDATA, i2c_data);
1546 hw20k2_i2c_wait_data_ready(hw);
1547
1548 return 0;
1549}
1550
1551static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
1552{
1553 int err;
1554 u32 data;
1555 int i;
1556 struct regs_cs4382 cs_read = {0};
1557 struct regs_cs4382 cs_def = {
1558 0x00000001, /* Mode Control 1 */
1559 0x00000000, /* Mode Control 2 */
1560 0x00000084, /* Mode Control 3 */
1561 0x00000000, /* Filter Control */
1562 0x00000000, /* Invert Control */
1563 0x00000024, /* Mixing Control Pair 1 */
1564 0x00000000, /* Vol Control A1 */
1565 0x00000000, /* Vol Control B1 */
1566 0x00000024, /* Mixing Control Pair 2 */
1567 0x00000000, /* Vol Control A2 */
1568 0x00000000, /* Vol Control B2 */
1569 0x00000024, /* Mixing Control Pair 3 */
1570 0x00000000, /* Vol Control A3 */
1571 0x00000000, /* Vol Control B3 */
1572 0x00000024, /* Mixing Control Pair 4 */
1573 0x00000000, /* Vol Control A4 */
1574 0x00000000 /* Vol Control B4 */
1575 };
1576
1577 /* Set DAC reset bit as output */
1578 data = hw_read_20kx(hw, GPIO_CTRL);
1579 data |= 0x02;
1580 hw_write_20kx(hw, GPIO_CTRL, data);
1581
1582 err = hw20k2_i2c_init(hw, 0x18, 1, 1);
1583 if (err < 0)
1584 goto End;
1585
1586 for (i = 0; i < 2; i++) {
1587 /* Reset DAC twice just in-case the chip
1588 * didn't initialized properly */
1589 data = hw_read_20kx(hw, GPIO_DATA);
1590 /* GPIO data bit 1 */
1591 data &= 0xFFFFFFFD;
1592 hw_write_20kx(hw, GPIO_DATA, data);
1593 mdelay(10);
1594 data |= 0x2;
1595 hw_write_20kx(hw, GPIO_DATA, data);
1596 mdelay(50);
1597
1598 /* Reset the 2nd time */
1599 data &= 0xFFFFFFFD;
1600 hw_write_20kx(hw, GPIO_DATA, data);
1601 mdelay(10);
1602 data |= 0x2;
1603 hw_write_20kx(hw, GPIO_DATA, data);
1604 mdelay(50);
1605
1606 if (hw20k2_i2c_read(hw, CS4382_MC1, &cs_read.mode_control_1))
1607 continue;
1608
1609 if (hw20k2_i2c_read(hw, CS4382_MC2, &cs_read.mode_control_2))
1610 continue;
1611
1612 if (hw20k2_i2c_read(hw, CS4382_MC3, &cs_read.mode_control_3))
1613 continue;
1614
1615 if (hw20k2_i2c_read(hw, CS4382_FC, &cs_read.filter_control))
1616 continue;
1617
1618 if (hw20k2_i2c_read(hw, CS4382_IC, &cs_read.invert_control))
1619 continue;
1620
1621 if (hw20k2_i2c_read(hw, CS4382_XC1, &cs_read.mix_control_P1))
1622 continue;
1623
1624 if (hw20k2_i2c_read(hw, CS4382_VCA1, &cs_read.vol_control_A1))
1625 continue;
1626
1627 if (hw20k2_i2c_read(hw, CS4382_VCB1, &cs_read.vol_control_B1))
1628 continue;
1629
1630 if (hw20k2_i2c_read(hw, CS4382_XC2, &cs_read.mix_control_P2))
1631 continue;
1632
1633 if (hw20k2_i2c_read(hw, CS4382_VCA2, &cs_read.vol_control_A2))
1634 continue;
1635
1636 if (hw20k2_i2c_read(hw, CS4382_VCB2, &cs_read.vol_control_B2))
1637 continue;
1638
1639 if (hw20k2_i2c_read(hw, CS4382_XC3, &cs_read.mix_control_P3))
1640 continue;
1641
1642 if (hw20k2_i2c_read(hw, CS4382_VCA3, &cs_read.vol_control_A3))
1643 continue;
1644
1645 if (hw20k2_i2c_read(hw, CS4382_VCB3, &cs_read.vol_control_B3))
1646 continue;
1647
1648 if (hw20k2_i2c_read(hw, CS4382_XC4, &cs_read.mix_control_P4))
1649 continue;
1650
1651 if (hw20k2_i2c_read(hw, CS4382_VCA4, &cs_read.vol_control_A4))
1652 continue;
1653
1654 if (hw20k2_i2c_read(hw, CS4382_VCB4, &cs_read.vol_control_B4))
1655 continue;
1656
1657 if (memcmp(&cs_read, &cs_def, sizeof(cs_read)))
1658 continue;
1659 else
1660 break;
1661 }
1662
1663 if (i >= 2)
1664 goto End;
1665
1666 /* Note: Every I2C write must have some delay.
1667 * This is not a requirement but the delay works here... */
1668 hw20k2_i2c_write(hw, CS4382_MC1, 0x80);
1669 hw20k2_i2c_write(hw, CS4382_MC2, 0x10);
1670 if (1 == info->msr) {
1671 hw20k2_i2c_write(hw, CS4382_XC1, 0x24);
1672 hw20k2_i2c_write(hw, CS4382_XC2, 0x24);
1673 hw20k2_i2c_write(hw, CS4382_XC3, 0x24);
1674 hw20k2_i2c_write(hw, CS4382_XC4, 0x24);
1675 } else if (2 == info->msr) {
1676 hw20k2_i2c_write(hw, CS4382_XC1, 0x25);
1677 hw20k2_i2c_write(hw, CS4382_XC2, 0x25);
1678 hw20k2_i2c_write(hw, CS4382_XC3, 0x25);
1679 hw20k2_i2c_write(hw, CS4382_XC4, 0x25);
1680 } else {
1681 hw20k2_i2c_write(hw, CS4382_XC1, 0x26);
1682 hw20k2_i2c_write(hw, CS4382_XC2, 0x26);
1683 hw20k2_i2c_write(hw, CS4382_XC3, 0x26);
1684 hw20k2_i2c_write(hw, CS4382_XC4, 0x26);
1685 }
1686
1687 return 0;
1688End:
1689
1690 hw20k2_i2c_uninit(hw);
1691 return -1;
1692}
1693
1694/* ADC operations */
1695#define MAKE_WM8775_ADDR(addr, data) (u32)(((addr<<1)&0xFE)|((data>>8)&0x1))
1696#define MAKE_WM8775_DATA(data) (u32)(data&0xFF)
1697
1698#define WM8775_IC 0x0B
1699#define WM8775_MMC 0x0C
1700#define WM8775_AADCL 0x0E
1701#define WM8775_AADCR 0x0F
1702#define WM8775_ADCMC 0x15
1703#define WM8775_RESET 0x17
1704
1705static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type)
1706{
1707 u32 data;
1708
1709 data = hw_read_20kx(hw, GPIO_DATA);
1710 switch (type) {
1711 case ADC_MICIN:
1712 data = (data & (0x1 << 14)) ? 1 : 0;
1713 break;
1714 case ADC_LINEIN:
1715 data = (data & (0x1 << 14)) ? 0 : 1;
1716 break;
1717 default:
1718 data = 0;
1719 }
1720 return data;
1721}
1722
1723static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
1724{
1725 u32 data;
1726
1727 data = hw_read_20kx(hw, GPIO_DATA);
1728 switch (type) {
1729 case ADC_MICIN:
1730 data |= (0x1 << 14);
1731 hw_write_20kx(hw, GPIO_DATA, data);
1732 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x101),
1733 MAKE_WM8775_DATA(0x101)); /* Mic-in */
1734 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xE7),
1735 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1736 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xE7),
1737 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1738 break;
1739 case ADC_LINEIN:
1740 data &= ~(0x1 << 14);
1741 hw_write_20kx(hw, GPIO_DATA, data);
1742 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x102),
1743 MAKE_WM8775_DATA(0x102)); /* Line-in */
1744 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xCF),
1745 MAKE_WM8775_DATA(0xCF)); /* No boost */
1746 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xCF),
1747 MAKE_WM8775_DATA(0xCF)); /* No boost */
1748 break;
1749 default:
1750 break;
1751 }
1752
1753 return 0;
1754}
1755
1756static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
1757{
1758 int err;
1759 u32 mux = 2, data, ctl;
1760
1761 /* Set ADC reset bit as output */
1762 data = hw_read_20kx(hw, GPIO_CTRL);
1763 data |= (0x1 << 15);
1764 hw_write_20kx(hw, GPIO_CTRL, data);
1765
1766 /* Initialize I2C */
1767 err = hw20k2_i2c_init(hw, 0x1A, 1, 1);
1768 if (err < 0) {
1769 printk(KERN_ALERT "ctxfi: Failure to acquire I2C!!!\n");
1770 goto error;
1771 }
1772
1773 /* Make ADC in normal operation */
1774 data = hw_read_20kx(hw, GPIO_DATA);
1775 data &= ~(0x1 << 15);
1776 mdelay(10);
1777 data |= (0x1 << 15);
1778 hw_write_20kx(hw, GPIO_DATA, data);
1779 mdelay(50);
1780
1781 /* Set the master mode (256fs) */
1782 if (1 == info->msr) {
1783 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x02),
1784 MAKE_WM8775_DATA(0x02));
1785 } else if (2 == info->msr) {
1786 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A),
1787 MAKE_WM8775_DATA(0x0A));
1788 } else {
1789 printk(KERN_ALERT "ctxfi: Invalid master sampling "
1790 "rate (msr %d)!!!\n", info->msr);
1791 err = -EINVAL;
1792 goto error;
1793 }
1794
1795 /* Configure GPIO bit 14 change to line-in/mic-in */
1796 ctl = hw_read_20kx(hw, GPIO_CTRL);
1797 ctl |= 0x1 << 14;
1798 hw_write_20kx(hw, GPIO_CTRL, ctl);
1799
1800 /* Check using Mic-in or Line-in */
1801 data = hw_read_20kx(hw, GPIO_DATA);
1802
1803 if (mux == 1) {
1804 /* Configures GPIO data to select Mic-in */
1805 data |= 0x1 << 14;
1806 hw_write_20kx(hw, GPIO_DATA, data);
1807
1808 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x101),
1809 MAKE_WM8775_DATA(0x101)); /* Mic-in */
1810 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xE7),
1811 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1812 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xE7),
1813 MAKE_WM8775_DATA(0xE7)); /* +12dB boost */
1814 } else if (mux == 2) {
1815 /* Configures GPIO data to select Line-in */
1816 data &= ~(0x1 << 14);
1817 hw_write_20kx(hw, GPIO_DATA, data);
1818
1819 /* Setup ADC */
1820 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, 0x102),
1821 MAKE_WM8775_DATA(0x102)); /* Line-in */
1822 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, 0xCF),
1823 MAKE_WM8775_DATA(0xCF)); /* No boost */
1824 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, 0xCF),
1825 MAKE_WM8775_DATA(0xCF)); /* No boost */
1826 } else {
1827 printk(KERN_ALERT "ctxfi: ERROR!!! Invalid input mux!!!\n");
1828 err = -EINVAL;
1829 goto error;
1830 }
1831
1832 return 0;
1833
1834error:
1835 hw20k2_i2c_uninit(hw);
1836 return err;
1837}
1838
1839static int hw_have_digit_io_switch(struct hw *hw)
1840{
1841 return 0;
1842}
1843
1844static int hw_card_start(struct hw *hw)
1845{
1846 int err = 0;
1847 struct pci_dev *pci = hw->pci;
1848 unsigned int gctl;
1849
1850 err = pci_enable_device(pci);
1851 if (err < 0)
1852 return err;
1853
1854 /* Set DMA transfer mask */
1855 if (pci_set_dma_mask(pci, CT_XFI_DMA_MASK) < 0 ||
1856 pci_set_consistent_dma_mask(pci, CT_XFI_DMA_MASK) < 0) {
1857 printk(KERN_ERR "ctxfi: architecture does not support PCI "
1858 "busmaster DMA with mask 0x%llx\n", CT_XFI_DMA_MASK);
1859 err = -ENXIO;
1860 goto error1;
1861 }
1862
1863 err = pci_request_regions(pci, "XFi");
1864 if (err < 0)
1865 goto error1;
1866
1867 hw->io_base = pci_resource_start(hw->pci, 2);
1868 hw->mem_base = (unsigned long)ioremap(hw->io_base,
1869 pci_resource_len(hw->pci, 2));
1870 if (NULL == (void *)hw->mem_base) {
1871 err = -ENOENT;
1872 goto error2;
1873 }
1874
1875 /* Switch to 20k2 mode from UAA mode. */
1876 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1877 set_field(&gctl, GCTL_UAA, 0);
1878 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1879
1880 /*if ((err = request_irq(pci->irq, ct_atc_interrupt, IRQF_SHARED,
1881 atc->chip_details->nm_card, hw))) {
1882 goto error3;
1883 }
1884 hw->irq = pci->irq;
1885 */
1886
1887 pci_set_master(pci);
1888
1889 return 0;
1890
1891/*error3:
1892 iounmap((void *)hw->mem_base);
1893 hw->mem_base = (unsigned long)NULL;*/
1894error2:
1895 pci_release_regions(pci);
1896 hw->io_base = 0;
1897error1:
1898 pci_disable_device(pci);
1899 return err;
1900}
1901
1902static int hw_card_stop(struct hw *hw)
1903{
1904 /* TODO: Disable interrupt and so on... */
1905 return 0;
1906}
1907
1908static int hw_card_shutdown(struct hw *hw)
1909{
1910 if (hw->irq >= 0)
1911 free_irq(hw->irq, hw);
1912
1913 hw->irq = -1;
1914
1915 if (NULL != ((void *)hw->mem_base))
1916 iounmap((void *)hw->mem_base);
1917
1918 hw->mem_base = (unsigned long)NULL;
1919
1920 if (hw->io_base)
1921 pci_release_regions(hw->pci);
1922
1923 hw->io_base = 0;
1924
1925 pci_disable_device(hw->pci);
1926
1927 return 0;
1928}
1929
1930static int hw_card_init(struct hw *hw, struct card_conf *info)
1931{
1932 int err;
1933 unsigned int gctl;
1934 u32 data = 0;
1935 struct dac_conf dac_info = {0};
1936 struct adc_conf adc_info = {0};
1937 struct daio_conf daio_info = {0};
1938 struct trn_conf trn_info = {0};
1939
1940 /* Get PCI io port/memory base address and
1941 * do 20kx core switch if needed. */
1942 if (!hw->io_base) {
1943 err = hw_card_start(hw);
1944 if (err)
1945 return err;
1946 }
1947
1948 /* PLL init */
1949 err = hw_pll_init(hw, info->rsr);
1950 if (err < 0)
1951 return err;
1952
1953 /* kick off auto-init */
1954 err = hw_auto_init(hw);
1955 if (err < 0)
1956 return err;
1957
1958 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1959 set_field(&gctl, GCTL_DBP, 1);
1960 set_field(&gctl, GCTL_TBP, 1);
1961 set_field(&gctl, GCTL_FBP, 1);
1962 set_field(&gctl, GCTL_DPC, 0);
1963 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1964
1965 /* Reset all global pending interrupts */
1966 hw_write_20kx(hw, INTERRUPT_GIE, 0);
1967 /* Reset all SRC pending interrupts */
1968 hw_write_20kx(hw, SRC_IP, 0);
1969
1970 /* TODO: detect the card ID and configure GPIO accordingly. */
1971 /* Configures GPIO (0xD802 0x98028) */
1972 /*hw_write_20kx(hw, GPIO_CTRL, 0x7F07);*/
1973 /* Configures GPIO (SB0880) */
1974 /*hw_write_20kx(hw, GPIO_CTRL, 0xFF07);*/
1975 hw_write_20kx(hw, GPIO_CTRL, 0xD802);
1976
1977 /* Enable audio ring */
1978 hw_write_20kx(hw, MIXER_AR_ENABLE, 0x01);
1979
1980 trn_info.vm_pgt_phys = info->vm_pgt_phys;
1981 err = hw_trn_init(hw, &trn_info);
1982 if (err < 0)
1983 return err;
1984
1985 daio_info.msr = info->msr;
1986 err = hw_daio_init(hw, &daio_info);
1987 if (err < 0)
1988 return err;
1989
1990 dac_info.msr = info->msr;
1991 err = hw_dac_init(hw, &dac_info);
1992 if (err < 0)
1993 return err;
1994
1995 adc_info.msr = info->msr;
1996 adc_info.input = ADC_LINEIN;
1997 adc_info.mic20db = 0;
1998 err = hw_adc_init(hw, &adc_info);
1999 if (err < 0)
2000 return err;
2001
2002 data = hw_read_20kx(hw, SRC_MCTL);
2003 data |= 0x1; /* Enables input from the audio ring */
2004 hw_write_20kx(hw, SRC_MCTL, data);
2005
2006 return 0;
2007}
2008
2009static u32 hw_read_20kx(struct hw *hw, u32 reg)
2010{
2011 return readl((void *)(hw->mem_base + reg));
2012}
2013
2014static void hw_write_20kx(struct hw *hw, u32 reg, u32 data)
2015{
2016 writel(data, (void *)(hw->mem_base + reg));
2017}
2018
2019static struct hw ct20k2_preset __devinitdata = {
2020 .irq = -1,
2021
2022 .card_init = hw_card_init,
2023 .card_stop = hw_card_stop,
2024 .pll_init = hw_pll_init,
2025 .is_adc_source_selected = hw_is_adc_input_selected,
2026 .select_adc_source = hw_adc_input_select,
2027 .have_digit_io_switch = hw_have_digit_io_switch,
2028
2029 .src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk,
2030 .src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk,
2031 .src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk,
2032 .src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk,
2033 .src_set_state = src_set_state,
2034 .src_set_bm = src_set_bm,
2035 .src_set_rsr = src_set_rsr,
2036 .src_set_sf = src_set_sf,
2037 .src_set_wr = src_set_wr,
2038 .src_set_pm = src_set_pm,
2039 .src_set_rom = src_set_rom,
2040 .src_set_vo = src_set_vo,
2041 .src_set_st = src_set_st,
2042 .src_set_ie = src_set_ie,
2043 .src_set_ilsz = src_set_ilsz,
2044 .src_set_bp = src_set_bp,
2045 .src_set_cisz = src_set_cisz,
2046 .src_set_ca = src_set_ca,
2047 .src_set_sa = src_set_sa,
2048 .src_set_la = src_set_la,
2049 .src_set_pitch = src_set_pitch,
2050 .src_set_dirty = src_set_dirty,
2051 .src_set_clear_zbufs = src_set_clear_zbufs,
2052 .src_set_dirty_all = src_set_dirty_all,
2053 .src_commit_write = src_commit_write,
2054 .src_get_ca = src_get_ca,
2055 .src_get_dirty = src_get_dirty,
2056 .src_dirty_conj_mask = src_dirty_conj_mask,
2057 .src_mgr_enbs_src = src_mgr_enbs_src,
2058 .src_mgr_enb_src = src_mgr_enb_src,
2059 .src_mgr_dsb_src = src_mgr_dsb_src,
2060 .src_mgr_commit_write = src_mgr_commit_write,
2061
2062 .srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk,
2063 .srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk,
2064 .srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc,
2065 .srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser,
2066 .srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt,
2067 .srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr,
2068 .srcimp_mgr_commit_write = srcimp_mgr_commit_write,
2069
2070 .amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk,
2071 .amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk,
2072 .amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk,
2073 .amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk,
2074 .amixer_set_mode = amixer_set_mode,
2075 .amixer_set_iv = amixer_set_iv,
2076 .amixer_set_x = amixer_set_x,
2077 .amixer_set_y = amixer_set_y,
2078 .amixer_set_sadr = amixer_set_sadr,
2079 .amixer_set_se = amixer_set_se,
2080 .amixer_set_dirty = amixer_set_dirty,
2081 .amixer_set_dirty_all = amixer_set_dirty_all,
2082 .amixer_commit_write = amixer_commit_write,
2083 .amixer_get_y = amixer_get_y,
2084 .amixer_get_dirty = amixer_get_dirty,
2085
2086 .dai_get_ctrl_blk = dai_get_ctrl_blk,
2087 .dai_put_ctrl_blk = dai_put_ctrl_blk,
2088 .dai_srt_set_srco = dai_srt_set_srco,
2089 .dai_srt_set_srcm = dai_srt_set_srcm,
2090 .dai_srt_set_rsr = dai_srt_set_rsr,
2091 .dai_srt_set_drat = dai_srt_set_drat,
2092 .dai_srt_set_ec = dai_srt_set_ec,
2093 .dai_srt_set_et = dai_srt_set_et,
2094 .dai_commit_write = dai_commit_write,
2095
2096 .dao_get_ctrl_blk = dao_get_ctrl_blk,
2097 .dao_put_ctrl_blk = dao_put_ctrl_blk,
2098 .dao_set_spos = dao_set_spos,
2099 .dao_commit_write = dao_commit_write,
2100 .dao_get_spos = dao_get_spos,
2101
2102 .daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk,
2103 .daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk,
2104 .daio_mgr_enb_dai = daio_mgr_enb_dai,
2105 .daio_mgr_dsb_dai = daio_mgr_dsb_dai,
2106 .daio_mgr_enb_dao = daio_mgr_enb_dao,
2107 .daio_mgr_dsb_dao = daio_mgr_dsb_dao,
2108 .daio_mgr_dao_init = daio_mgr_dao_init,
2109 .daio_mgr_set_imaparc = daio_mgr_set_imaparc,
2110 .daio_mgr_set_imapnxt = daio_mgr_set_imapnxt,
2111 .daio_mgr_set_imapaddr = daio_mgr_set_imapaddr,
2112 .daio_mgr_commit_write = daio_mgr_commit_write,
2113};
2114
2115int __devinit create_20k2_hw_obj(struct hw **rhw)
2116{
2117 struct hw20k2 *hw20k2;
2118
2119 *rhw = NULL;
2120 hw20k2 = kzalloc(sizeof(*hw20k2), GFP_KERNEL);
2121 if (!hw20k2)
2122 return -ENOMEM;
2123
2124 hw20k2->hw = ct20k2_preset;
2125 *rhw = &hw20k2->hw;
2126
2127 return 0;
2128}
2129
2130int destroy_20k2_hw_obj(struct hw *hw)
2131{
2132 if (hw->io_base)
2133 hw_card_shutdown(hw);
2134
2135 kfree(hw);
2136 return 0;
2137}
diff --git a/sound/pci/ctxfi/cthw20k2.h b/sound/pci/ctxfi/cthw20k2.h
new file mode 100644
index 00000000000..d2b7daab681
--- /dev/null
+++ b/sound/pci/ctxfi/cthw20k2.h
@@ -0,0 +1,26 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File cthw20k2.h
9 *
10 * @Brief
11 * This file contains the definition of hardware access methord.
12 *
13 * @Author Liu Chun
14 * @Date May 13 2008
15 *
16 */
17
18#ifndef CTHW20K2_H
19#define CTHW20K2_H
20
21#include "cthardware.h"
22
23int create_20k2_hw_obj(struct hw **rhw);
24int destroy_20k2_hw_obj(struct hw *hw);
25
26#endif /* CTHW20K2_H */
diff --git a/sound/pci/ctxfi/ctimap.c b/sound/pci/ctxfi/ctimap.c
new file mode 100644
index 00000000000..0b73368a4df
--- /dev/null
+++ b/sound/pci/ctxfi/ctimap.c
@@ -0,0 +1,112 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File ctimap.c
9 *
10 * @Brief
11 * This file contains the implementation of generic input mapper operations
12 * for input mapper management.
13 *
14 * @Author Liu Chun
15 * @Date May 23 2008
16 *
17 */
18
19#include "ctimap.h"
20#include <linux/slab.h>
21
22int input_mapper_add(struct list_head *mappers, struct imapper *entry,
23 int (*map_op)(void *, struct imapper *), void *data)
24{
25 struct list_head *pos, *pre, *head;
26 struct imapper *pre_ent, *pos_ent;
27
28 head = mappers;
29
30 if (list_empty(head)) {
31 entry->next = entry->addr;
32 map_op(data, entry);
33 list_add(&entry->list, head);
34 return 0;
35 }
36
37 list_for_each(pos, head) {
38 pos_ent = list_entry(pos, struct imapper, list);
39 if (pos_ent->slot > entry->slot) {
40 /* found a position in list */
41 break;
42 }
43 }
44
45 if (pos != head) {
46 pre = pos->prev;
47 if (pre == head)
48 pre = head->prev;
49
50 __list_add(&entry->list, pos->prev, pos);
51 } else {
52 pre = head->prev;
53 pos = head->next;
54 list_add_tail(&entry->list, head);
55 }
56
57 pre_ent = list_entry(pre, struct imapper, list);
58 pos_ent = list_entry(pos, struct imapper, list);
59
60 entry->next = pos_ent->addr;
61 map_op(data, entry);
62 pre_ent->next = entry->addr;
63 map_op(data, pre_ent);
64
65 return 0;
66}
67
68int input_mapper_delete(struct list_head *mappers, struct imapper *entry,
69 int (*map_op)(void *, struct imapper *), void *data)
70{
71 struct list_head *next, *pre, *head;
72 struct imapper *pre_ent, *next_ent;
73
74 head = mappers;
75
76 if (list_empty(head))
77 return 0;
78
79 pre = (entry->list.prev == head) ? head->prev : entry->list.prev;
80 next = (entry->list.next == head) ? head->next : entry->list.next;
81
82 if (pre == &entry->list) {
83 /* entry is the only one node in mappers list */
84 entry->next = entry->addr = entry->user = entry->slot = 0;
85 map_op(data, entry);
86 list_del(&entry->list);
87 return 0;
88 }
89
90 pre_ent = list_entry(pre, struct imapper, list);
91 next_ent = list_entry(next, struct imapper, list);
92
93 pre_ent->next = next_ent->addr;
94 map_op(data, pre_ent);
95 list_del(&entry->list);
96
97 return 0;
98}
99
100void free_input_mapper_list(struct list_head *head)
101{
102 struct imapper *entry;
103 struct list_head *pos;
104
105 while (!list_empty(head)) {
106 pos = head->next;
107 list_del(pos);
108 entry = list_entry(pos, struct imapper, list);
109 kfree(entry);
110 }
111}
112
diff --git a/sound/pci/ctxfi/ctimap.h b/sound/pci/ctxfi/ctimap.h
new file mode 100644
index 00000000000..53ccf9be8b6
--- /dev/null
+++ b/sound/pci/ctxfi/ctimap.h
@@ -0,0 +1,40 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File ctimap.h
9 *
10 * @Brief
11 * This file contains the definition of generic input mapper operations
12 * for input mapper management.
13 *
14 * @Author Liu Chun
15 * @Date May 23 2008
16 *
17 */
18
19#ifndef CTIMAP_H
20#define CTIMAP_H
21
22#include <linux/list.h>
23
24struct imapper {
25 unsigned short slot; /* the id of the slot containing input data */
26 unsigned short user; /* the id of the user resource consuming data */
27 unsigned short addr; /* the input mapper ram id */
28 unsigned short next; /* the next input mapper ram id */
29 struct list_head list;
30};
31
32int input_mapper_add(struct list_head *mappers, struct imapper *entry,
33 int (*map_op)(void *, struct imapper *), void *data);
34
35int input_mapper_delete(struct list_head *mappers, struct imapper *entry,
36 int (*map_op)(void *, struct imapper *), void *data);
37
38void free_input_mapper_list(struct list_head *mappers);
39
40#endif /* CTIMAP_H */
diff --git a/sound/pci/ctxfi/ctmixer.c b/sound/pci/ctxfi/ctmixer.c
new file mode 100644
index 00000000000..666722d9de4
--- /dev/null
+++ b/sound/pci/ctxfi/ctmixer.c
@@ -0,0 +1,1123 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File ctmixer.c
9 *
10 * @Brief
11 * This file contains the implementation of alsa mixer device functions.
12 *
13 * @Author Liu Chun
14 * @Date May 28 2008
15 *
16 */
17
18
19#include "ctmixer.h"
20#include "ctamixer.h"
21#include <linux/slab.h>
22#include <sound/core.h>
23#include <sound/control.h>
24#include <sound/asoundef.h>
25#include <sound/pcm.h>
26#include <sound/tlv.h>
27
28enum CT_SUM_CTL {
29 SUM_IN_F,
30 SUM_IN_R,
31 SUM_IN_C,
32 SUM_IN_S,
33 SUM_IN_F_C,
34
35 NUM_CT_SUMS
36};
37
38enum CT_AMIXER_CTL {
39 /* volume control mixers */
40 AMIXER_MASTER_F,
41 AMIXER_MASTER_R,
42 AMIXER_MASTER_C,
43 AMIXER_MASTER_S,
44 AMIXER_PCM_F,
45 AMIXER_PCM_R,
46 AMIXER_PCM_C,
47 AMIXER_PCM_S,
48 AMIXER_SPDIFI,
49 AMIXER_LINEIN,
50 AMIXER_MIC,
51 AMIXER_SPDIFO,
52 AMIXER_WAVE_F,
53 AMIXER_WAVE_R,
54 AMIXER_WAVE_C,
55 AMIXER_WAVE_S,
56 AMIXER_MASTER_F_C,
57 AMIXER_PCM_F_C,
58 AMIXER_SPDIFI_C,
59 AMIXER_LINEIN_C,
60 AMIXER_MIC_C,
61
62 /* this should always be the last one */
63 NUM_CT_AMIXERS
64};
65
66enum CTALSA_MIXER_CTL {
67 /* volume control mixers */
68 MIXER_MASTER_P,
69 MIXER_PCM_P,
70 MIXER_LINEIN_P,
71 MIXER_MIC_P,
72 MIXER_SPDIFI_P,
73 MIXER_SPDIFO_P,
74 MIXER_WAVEF_P,
75 MIXER_WAVER_P,
76 MIXER_WAVEC_P,
77 MIXER_WAVES_P,
78 MIXER_MASTER_C,
79 MIXER_PCM_C,
80 MIXER_LINEIN_C,
81 MIXER_MIC_C,
82 MIXER_SPDIFI_C,
83
84 /* switch control mixers */
85 MIXER_PCM_C_S,
86 MIXER_LINEIN_C_S,
87 MIXER_MIC_C_S,
88 MIXER_SPDIFI_C_S,
89 MIXER_LINEIN_P_S,
90 MIXER_SPDIFO_P_S,
91 MIXER_SPDIFI_P_S,
92 MIXER_WAVEF_P_S,
93 MIXER_WAVER_P_S,
94 MIXER_WAVEC_P_S,
95 MIXER_WAVES_P_S,
96 MIXER_DIGITAL_IO_S,
97 MIXER_IEC958_MASK,
98 MIXER_IEC958_DEFAULT,
99 MIXER_IEC958_STREAM,
100
101 /* this should always be the last one */
102 NUM_CTALSA_MIXERS
103};
104
105#define VOL_MIXER_START MIXER_MASTER_P
106#define VOL_MIXER_END MIXER_SPDIFI_C
107#define VOL_MIXER_NUM (VOL_MIXER_END - VOL_MIXER_START + 1)
108#define SWH_MIXER_START MIXER_PCM_C_S
109#define SWH_MIXER_END MIXER_DIGITAL_IO_S
110#define SWH_CAPTURE_START MIXER_PCM_C_S
111#define SWH_CAPTURE_END MIXER_SPDIFI_C_S
112
113#define CHN_NUM 2
114
115struct ct_kcontrol_init {
116 unsigned char ctl;
117 char *name;
118};
119
120static struct ct_kcontrol_init
121ct_kcontrol_init_table[NUM_CTALSA_MIXERS] = {
122 [MIXER_MASTER_P] = {
123 .ctl = 1,
124 .name = "Master Playback Volume",
125 },
126 [MIXER_MASTER_C] = {
127 .ctl = 1,
128 .name = "Master Capture Volume",
129 },
130 [MIXER_PCM_P] = {
131 .ctl = 1,
132 .name = "PCM Playback Volume",
133 },
134 [MIXER_PCM_C] = {
135 .ctl = 1,
136 .name = "PCM Capture Volume",
137 },
138 [MIXER_LINEIN_P] = {
139 .ctl = 1,
140 .name = "Line-in Playback Volume",
141 },
142 [MIXER_LINEIN_C] = {
143 .ctl = 1,
144 .name = "Line-in Capture Volume",
145 },
146 [MIXER_MIC_P] = {
147 .ctl = 1,
148 .name = "Mic Playback Volume",
149 },
150 [MIXER_MIC_C] = {
151 .ctl = 1,
152 .name = "Mic Capture Volume",
153 },
154 [MIXER_SPDIFI_P] = {
155 .ctl = 1,
156 .name = "S/PDIF-in Playback Volume",
157 },
158 [MIXER_SPDIFI_C] = {
159 .ctl = 1,
160 .name = "S/PDIF-in Capture Volume",
161 },
162 [MIXER_SPDIFO_P] = {
163 .ctl = 1,
164 .name = "S/PDIF-out Playback Volume",
165 },
166 [MIXER_WAVEF_P] = {
167 .ctl = 1,
168 .name = "Front Playback Volume",
169 },
170 [MIXER_WAVES_P] = {
171 .ctl = 1,
172 .name = "Side Playback Volume",
173 },
174 [MIXER_WAVEC_P] = {
175 .ctl = 1,
176 .name = "Center/LFE Playback Volume",
177 },
178 [MIXER_WAVER_P] = {
179 .ctl = 1,
180 .name = "Surround Playback Volume",
181 },
182
183 [MIXER_PCM_C_S] = {
184 .ctl = 1,
185 .name = "PCM Capture Switch",
186 },
187 [MIXER_LINEIN_C_S] = {
188 .ctl = 1,
189 .name = "Line-in Capture Switch",
190 },
191 [MIXER_MIC_C_S] = {
192 .ctl = 1,
193 .name = "Mic Capture Switch",
194 },
195 [MIXER_SPDIFI_C_S] = {
196 .ctl = 1,
197 .name = "S/PDIF-in Capture Switch",
198 },
199 [MIXER_LINEIN_P_S] = {
200 .ctl = 1,
201 .name = "Line-in Playback Switch",
202 },
203 [MIXER_SPDIFO_P_S] = {
204 .ctl = 1,
205 .name = "S/PDIF-out Playback Switch",
206 },
207 [MIXER_SPDIFI_P_S] = {
208 .ctl = 1,
209 .name = "S/PDIF-in Playback Switch",
210 },
211 [MIXER_WAVEF_P_S] = {
212 .ctl = 1,
213 .name = "Front Playback Switch",
214 },
215 [MIXER_WAVES_P_S] = {
216 .ctl = 1,
217 .name = "Side Playback Switch",
218 },
219 [MIXER_WAVEC_P_S] = {
220 .ctl = 1,
221 .name = "Center/LFE Playback Switch",
222 },
223 [MIXER_WAVER_P_S] = {
224 .ctl = 1,
225 .name = "Surround Playback Switch",
226 },
227 [MIXER_DIGITAL_IO_S] = {
228 .ctl = 0,
229 .name = "Digit-IO Playback Switch",
230 },
231};
232
233static void
234ct_mixer_recording_select(struct ct_mixer *mixer, enum CT_AMIXER_CTL type);
235
236static void
237ct_mixer_recording_unselect(struct ct_mixer *mixer, enum CT_AMIXER_CTL type);
238
239static struct snd_kcontrol *kctls[2] = {NULL};
240
241static enum CT_AMIXER_CTL get_amixer_index(enum CTALSA_MIXER_CTL alsa_index)
242{
243 switch (alsa_index) {
244 case MIXER_MASTER_P: return AMIXER_MASTER_F;
245 case MIXER_MASTER_C: return AMIXER_MASTER_F_C;
246 case MIXER_PCM_P: return AMIXER_PCM_F;
247 case MIXER_PCM_C:
248 case MIXER_PCM_C_S: return AMIXER_PCM_F_C;
249 case MIXER_LINEIN_P: return AMIXER_LINEIN;
250 case MIXER_LINEIN_C:
251 case MIXER_LINEIN_C_S: return AMIXER_LINEIN_C;
252 case MIXER_MIC_P: return AMIXER_MIC;
253 case MIXER_MIC_C:
254 case MIXER_MIC_C_S: return AMIXER_MIC_C;
255 case MIXER_SPDIFI_P: return AMIXER_SPDIFI;
256 case MIXER_SPDIFI_C:
257 case MIXER_SPDIFI_C_S: return AMIXER_SPDIFI_C;
258 case MIXER_SPDIFO_P: return AMIXER_SPDIFO;
259 case MIXER_WAVEF_P: return AMIXER_WAVE_F;
260 case MIXER_WAVES_P: return AMIXER_WAVE_S;
261 case MIXER_WAVEC_P: return AMIXER_WAVE_C;
262 case MIXER_WAVER_P: return AMIXER_WAVE_R;
263 default: return NUM_CT_AMIXERS;
264 }
265}
266
267static enum CT_AMIXER_CTL get_recording_amixer(enum CT_AMIXER_CTL index)
268{
269 switch (index) {
270 case AMIXER_MASTER_F: return AMIXER_MASTER_F_C;
271 case AMIXER_PCM_F: return AMIXER_PCM_F_C;
272 case AMIXER_SPDIFI: return AMIXER_SPDIFI_C;
273 case AMIXER_LINEIN: return AMIXER_LINEIN_C;
274 case AMIXER_MIC: return AMIXER_MIC_C;
275 default: return NUM_CT_AMIXERS;
276 }
277}
278
279static unsigned char
280get_switch_state(struct ct_mixer *mixer, enum CTALSA_MIXER_CTL type)
281{
282 return (mixer->switch_state & (0x1 << (type - SWH_MIXER_START)))
283 ? 1 : 0;
284}
285
286static void
287set_switch_state(struct ct_mixer *mixer,
288 enum CTALSA_MIXER_CTL type, unsigned char state)
289{
290 if (state)
291 mixer->switch_state |= (0x1 << (type - SWH_MIXER_START));
292 else
293 mixer->switch_state &= ~(0x1 << (type - SWH_MIXER_START));
294}
295
296#if 0 /* not used */
297/* Map integer value ranging from 0 to 65535 to 14-bit float value ranging
298 * from 2^-6 to (1+1023/1024) */
299static unsigned int uint16_to_float14(unsigned int x)
300{
301 unsigned int i;
302
303 if (x < 17)
304 return 0;
305
306 x *= 2031;
307 x /= 65535;
308 x += 16;
309
310 /* i <= 6 */
311 for (i = 0; !(x & 0x400); i++)
312 x <<= 1;
313
314 x = (((7 - i) & 0x7) << 10) | (x & 0x3ff);
315
316 return x;
317}
318
319static unsigned int float14_to_uint16(unsigned int x)
320{
321 unsigned int e;
322
323 if (!x)
324 return x;
325
326 e = (x >> 10) & 0x7;
327 x &= 0x3ff;
328 x += 1024;
329 x >>= (7 - e);
330 x -= 16;
331 x *= 65535;
332 x /= 2031;
333
334 return x;
335}
336#endif /* not used */
337
338#define VOL_SCALE 0x1c
339#define VOL_MAX 0x100
340
341static const DECLARE_TLV_DB_SCALE(ct_vol_db_scale, -6400, 25, 1);
342
343static int ct_alsa_mix_volume_info(struct snd_kcontrol *kcontrol,
344 struct snd_ctl_elem_info *uinfo)
345{
346 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
347 uinfo->count = 2;
348 uinfo->value.integer.min = 0;
349 uinfo->value.integer.max = VOL_MAX;
350
351 return 0;
352}
353
354static int ct_alsa_mix_volume_get(struct snd_kcontrol *kcontrol,
355 struct snd_ctl_elem_value *ucontrol)
356{
357 struct ct_atc *atc = snd_kcontrol_chip(kcontrol);
358 enum CT_AMIXER_CTL type = get_amixer_index(kcontrol->private_value);
359 struct amixer *amixer;
360 int i, val;
361
362 for (i = 0; i < 2; i++) {
363 amixer = ((struct ct_mixer *)atc->mixer)->
364 amixers[type*CHN_NUM+i];
365 val = amixer->ops->get_scale(amixer) / VOL_SCALE;
366 if (val < 0)
367 val = 0;
368 else if (val > VOL_MAX)
369 val = VOL_MAX;
370 ucontrol->value.integer.value[i] = val;
371 }
372
373 return 0;
374}
375
376static int ct_alsa_mix_volume_put(struct snd_kcontrol *kcontrol,
377 struct snd_ctl_elem_value *ucontrol)
378{
379 struct ct_atc *atc = snd_kcontrol_chip(kcontrol);
380 struct ct_mixer *mixer = atc->mixer;
381 enum CT_AMIXER_CTL type = get_amixer_index(kcontrol->private_value);
382 struct amixer *amixer;
383 int i, j, val, oval, change = 0;
384
385 for (i = 0; i < 2; i++) {
386 val = ucontrol->value.integer.value[i];
387 if (val < 0)
388 val = 0;
389 else if (val > VOL_MAX)
390 val = VOL_MAX;
391 val *= VOL_SCALE;
392 amixer = mixer->amixers[type*CHN_NUM+i];
393 oval = amixer->ops->get_scale(amixer);
394 if (val != oval) {
395 amixer->ops->set_scale(amixer, val);
396 amixer->ops->commit_write(amixer);
397 change = 1;
398 /* Synchronize Master/PCM playback AMIXERs. */
399 if (AMIXER_MASTER_F == type || AMIXER_PCM_F == type) {
400 for (j = 1; j < 4; j++) {
401 amixer = mixer->
402 amixers[(type+j)*CHN_NUM+i];
403 amixer->ops->set_scale(amixer, val);
404 amixer->ops->commit_write(amixer);
405 }
406 }
407 }
408 }
409
410 return change;
411}
412
413static struct snd_kcontrol_new vol_ctl = {
414 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
415 SNDRV_CTL_ELEM_ACCESS_TLV_READ,
416 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
417 .info = ct_alsa_mix_volume_info,
418 .get = ct_alsa_mix_volume_get,
419 .put = ct_alsa_mix_volume_put,
420 .tlv = { .p = ct_vol_db_scale },
421};
422
423static void
424do_line_mic_switch(struct ct_atc *atc, enum CTALSA_MIXER_CTL type)
425{
426
427 if (MIXER_LINEIN_C_S == type) {
428 atc->select_line_in(atc);
429 set_switch_state(atc->mixer, MIXER_MIC_C_S, 0);
430 snd_ctl_notify(atc->card, SNDRV_CTL_EVENT_MASK_VALUE,
431 &kctls[1]->id);
432 } else if (MIXER_MIC_C_S == type) {
433 atc->select_mic_in(atc);
434 set_switch_state(atc->mixer, MIXER_LINEIN_C_S, 0);
435 snd_ctl_notify(atc->card, SNDRV_CTL_EVENT_MASK_VALUE,
436 &kctls[0]->id);
437 }
438}
439
440static void
441do_digit_io_switch(struct ct_atc *atc, int state)
442{
443 struct ct_mixer *mixer = atc->mixer;
444
445 if (state) {
446 atc->select_digit_io(atc);
447 atc->spdif_out_unmute(atc,
448 get_switch_state(mixer, MIXER_SPDIFO_P_S));
449 atc->spdif_in_unmute(atc, 1);
450 atc->line_in_unmute(atc, 0);
451 return;
452 }
453
454 if (get_switch_state(mixer, MIXER_LINEIN_C_S))
455 atc->select_line_in(atc);
456 else if (get_switch_state(mixer, MIXER_MIC_C_S))
457 atc->select_mic_in(atc);
458
459 atc->spdif_out_unmute(atc, 0);
460 atc->spdif_in_unmute(atc, 0);
461 atc->line_in_unmute(atc, 1);
462 return;
463}
464
465static int ct_alsa_mix_switch_info(struct snd_kcontrol *kcontrol,
466 struct snd_ctl_elem_info *uinfo)
467{
468 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
469 uinfo->count = 1;
470 uinfo->value.integer.min = 0;
471 uinfo->value.integer.max = 1;
472 uinfo->value.integer.step = 1;
473
474 return 0;
475}
476
477static int ct_alsa_mix_switch_get(struct snd_kcontrol *kcontrol,
478 struct snd_ctl_elem_value *ucontrol)
479{
480 struct ct_mixer *mixer =
481 ((struct ct_atc *)snd_kcontrol_chip(kcontrol))->mixer;
482 enum CTALSA_MIXER_CTL type = kcontrol->private_value;
483
484 ucontrol->value.integer.value[0] = get_switch_state(mixer, type);
485 return 0;
486}
487
488static int ct_alsa_mix_switch_put(struct snd_kcontrol *kcontrol,
489 struct snd_ctl_elem_value *ucontrol)
490{
491 struct ct_atc *atc = snd_kcontrol_chip(kcontrol);
492 struct ct_mixer *mixer = atc->mixer;
493 enum CTALSA_MIXER_CTL type = kcontrol->private_value;
494 int state;
495
496 state = ucontrol->value.integer.value[0];
497 if (get_switch_state(mixer, type) == state)
498 return 0;
499
500 set_switch_state(mixer, type, state);
501 /* Do changes in mixer. */
502 if ((SWH_CAPTURE_START <= type) && (SWH_CAPTURE_END >= type)) {
503 if (state) {
504 ct_mixer_recording_select(mixer,
505 get_amixer_index(type));
506 } else {
507 ct_mixer_recording_unselect(mixer,
508 get_amixer_index(type));
509 }
510 }
511 /* Do changes out of mixer. */
512 if (state && (MIXER_LINEIN_C_S == type || MIXER_MIC_C_S == type))
513 do_line_mic_switch(atc, type);
514 else if (MIXER_WAVEF_P_S == type)
515 atc->line_front_unmute(atc, state);
516 else if (MIXER_WAVES_P_S == type)
517 atc->line_surround_unmute(atc, state);
518 else if (MIXER_WAVEC_P_S == type)
519 atc->line_clfe_unmute(atc, state);
520 else if (MIXER_WAVER_P_S == type)
521 atc->line_rear_unmute(atc, state);
522 else if (MIXER_LINEIN_P_S == type)
523 atc->line_in_unmute(atc, state);
524 else if (MIXER_SPDIFO_P_S == type)
525 atc->spdif_out_unmute(atc, state);
526 else if (MIXER_SPDIFI_P_S == type)
527 atc->spdif_in_unmute(atc, state);
528 else if (MIXER_DIGITAL_IO_S == type)
529 do_digit_io_switch(atc, state);
530
531 return 1;
532}
533
534static struct snd_kcontrol_new swh_ctl = {
535 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
536 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
537 .info = ct_alsa_mix_switch_info,
538 .get = ct_alsa_mix_switch_get,
539 .put = ct_alsa_mix_switch_put
540};
541
542static int ct_spdif_info(struct snd_kcontrol *kcontrol,
543 struct snd_ctl_elem_info *uinfo)
544{
545 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
546 uinfo->count = 1;
547 return 0;
548}
549
550static int ct_spdif_get_mask(struct snd_kcontrol *kcontrol,
551 struct snd_ctl_elem_value *ucontrol)
552{
553 ucontrol->value.iec958.status[0] = 0xff;
554 ucontrol->value.iec958.status[1] = 0xff;
555 ucontrol->value.iec958.status[2] = 0xff;
556 ucontrol->value.iec958.status[3] = 0xff;
557 return 0;
558}
559
560static int ct_spdif_default_get(struct snd_kcontrol *kcontrol,
561 struct snd_ctl_elem_value *ucontrol)
562{
563 unsigned int status = SNDRV_PCM_DEFAULT_CON_SPDIF;
564
565 ucontrol->value.iec958.status[0] = (status >> 0) & 0xff;
566 ucontrol->value.iec958.status[1] = (status >> 8) & 0xff;
567 ucontrol->value.iec958.status[2] = (status >> 16) & 0xff;
568 ucontrol->value.iec958.status[3] = (status >> 24) & 0xff;
569
570 return 0;
571}
572
573static int ct_spdif_get(struct snd_kcontrol *kcontrol,
574 struct snd_ctl_elem_value *ucontrol)
575{
576 struct ct_atc *atc = snd_kcontrol_chip(kcontrol);
577 unsigned int status;
578
579 atc->spdif_out_get_status(atc, &status);
580 ucontrol->value.iec958.status[0] = (status >> 0) & 0xff;
581 ucontrol->value.iec958.status[1] = (status >> 8) & 0xff;
582 ucontrol->value.iec958.status[2] = (status >> 16) & 0xff;
583 ucontrol->value.iec958.status[3] = (status >> 24) & 0xff;
584
585 return 0;
586}
587
588static int ct_spdif_put(struct snd_kcontrol *kcontrol,
589 struct snd_ctl_elem_value *ucontrol)
590{
591 struct ct_atc *atc = snd_kcontrol_chip(kcontrol);
592 int change;
593 unsigned int status, old_status;
594
595 status = (ucontrol->value.iec958.status[0] << 0) |
596 (ucontrol->value.iec958.status[1] << 8) |
597 (ucontrol->value.iec958.status[2] << 16) |
598 (ucontrol->value.iec958.status[3] << 24);
599
600 atc->spdif_out_get_status(atc, &old_status);
601 change = (old_status != status);
602 if (change)
603 atc->spdif_out_set_status(atc, status);
604
605 return change;
606}
607
608static struct snd_kcontrol_new iec958_mask_ctl = {
609 .access = SNDRV_CTL_ELEM_ACCESS_READ,
610 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
611 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
612 .count = 1,
613 .info = ct_spdif_info,
614 .get = ct_spdif_get_mask,
615 .private_value = MIXER_IEC958_MASK
616};
617
618static struct snd_kcontrol_new iec958_default_ctl = {
619 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
620 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
621 .count = 1,
622 .info = ct_spdif_info,
623 .get = ct_spdif_default_get,
624 .put = ct_spdif_put,
625 .private_value = MIXER_IEC958_DEFAULT
626};
627
628static struct snd_kcontrol_new iec958_ctl = {
629 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
630 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
631 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
632 .count = 1,
633 .info = ct_spdif_info,
634 .get = ct_spdif_get,
635 .put = ct_spdif_put,
636 .private_value = MIXER_IEC958_STREAM
637};
638
639#define NUM_IEC958_CTL 3
640
641static int
642ct_mixer_kcontrol_new(struct ct_mixer *mixer, struct snd_kcontrol_new *new)
643{
644 struct snd_kcontrol *kctl;
645 int err;
646
647 kctl = snd_ctl_new1(new, mixer->atc);
648 if (NULL == kctl)
649 return -ENOMEM;
650
651 if (SNDRV_CTL_ELEM_IFACE_PCM == kctl->id.iface)
652 kctl->id.device = IEC958;
653
654 err = snd_ctl_add(mixer->atc->card, kctl);
655 if (err)
656 return err;
657
658 switch (new->private_value) {
659 case MIXER_LINEIN_C_S:
660 kctls[0] = kctl; break;
661 case MIXER_MIC_C_S:
662 kctls[1] = kctl; break;
663 default:
664 break;
665 }
666
667 return 0;
668}
669
670static int ct_mixer_kcontrols_create(struct ct_mixer *mixer)
671{
672 enum CTALSA_MIXER_CTL type;
673 struct ct_atc *atc = mixer->atc;
674 int err;
675
676 /* Create snd kcontrol instances on demand */
677 for (type = VOL_MIXER_START; type <= VOL_MIXER_END; type++) {
678 if (ct_kcontrol_init_table[type].ctl) {
679 vol_ctl.name = ct_kcontrol_init_table[type].name;
680 vol_ctl.private_value = (unsigned long)type;
681 err = ct_mixer_kcontrol_new(mixer, &vol_ctl);
682 if (err)
683 return err;
684 }
685 }
686
687 ct_kcontrol_init_table[MIXER_DIGITAL_IO_S].ctl =
688 atc->have_digit_io_switch(atc);
689 for (type = SWH_MIXER_START; type <= SWH_MIXER_END; type++) {
690 if (ct_kcontrol_init_table[type].ctl) {
691 swh_ctl.name = ct_kcontrol_init_table[type].name;
692 swh_ctl.private_value = (unsigned long)type;
693 err = ct_mixer_kcontrol_new(mixer, &swh_ctl);
694 if (err)
695 return err;
696 }
697 }
698
699 err = ct_mixer_kcontrol_new(mixer, &iec958_mask_ctl);
700 if (err)
701 return err;
702
703 err = ct_mixer_kcontrol_new(mixer, &iec958_default_ctl);
704 if (err)
705 return err;
706
707 err = ct_mixer_kcontrol_new(mixer, &iec958_ctl);
708 if (err)
709 return err;
710
711 atc->line_front_unmute(atc, 1);
712 set_switch_state(mixer, MIXER_WAVEF_P_S, 1);
713 atc->line_surround_unmute(atc, 0);
714 set_switch_state(mixer, MIXER_WAVES_P_S, 0);
715 atc->line_clfe_unmute(atc, 0);
716 set_switch_state(mixer, MIXER_WAVEC_P_S, 0);
717 atc->line_rear_unmute(atc, 0);
718 set_switch_state(mixer, MIXER_WAVER_P_S, 0);
719 atc->spdif_out_unmute(atc, 0);
720 set_switch_state(mixer, MIXER_SPDIFO_P_S, 0);
721 atc->line_in_unmute(atc, 0);
722 set_switch_state(mixer, MIXER_LINEIN_P_S, 0);
723 atc->spdif_in_unmute(atc, 0);
724 set_switch_state(mixer, MIXER_SPDIFI_P_S, 0);
725
726 set_switch_state(mixer, MIXER_PCM_C_S, 1);
727 set_switch_state(mixer, MIXER_LINEIN_C_S, 1);
728 set_switch_state(mixer, MIXER_SPDIFI_C_S, 1);
729
730 return 0;
731}
732
733static void
734ct_mixer_recording_select(struct ct_mixer *mixer, enum CT_AMIXER_CTL type)
735{
736 struct amixer *amix_d;
737 struct sum *sum_c;
738 int i;
739
740 for (i = 0; i < 2; i++) {
741 amix_d = mixer->amixers[type*CHN_NUM+i];
742 sum_c = mixer->sums[SUM_IN_F_C*CHN_NUM+i];
743 amix_d->ops->set_sum(amix_d, sum_c);
744 amix_d->ops->commit_write(amix_d);
745 }
746}
747
748static void
749ct_mixer_recording_unselect(struct ct_mixer *mixer, enum CT_AMIXER_CTL type)
750{
751 struct amixer *amix_d;
752 int i;
753
754 for (i = 0; i < 2; i++) {
755 amix_d = mixer->amixers[type*CHN_NUM+i];
756 amix_d->ops->set_sum(amix_d, NULL);
757 amix_d->ops->commit_write(amix_d);
758 }
759}
760
761static int ct_mixer_get_resources(struct ct_mixer *mixer)
762{
763 struct sum_mgr *sum_mgr;
764 struct sum *sum;
765 struct sum_desc sum_desc = {0};
766 struct amixer_mgr *amixer_mgr;
767 struct amixer *amixer;
768 struct amixer_desc am_desc = {0};
769 int err;
770 int i;
771
772 /* Allocate sum resources for mixer obj */
773 sum_mgr = (struct sum_mgr *)mixer->atc->rsc_mgrs[SUM];
774 sum_desc.msr = mixer->atc->msr;
775 for (i = 0; i < (NUM_CT_SUMS * CHN_NUM); i++) {
776 err = sum_mgr->get_sum(sum_mgr, &sum_desc, &sum);
777 if (err) {
778 printk(KERN_ERR "ctxfi:Failed to get sum resources for "
779 "front output!\n");
780 break;
781 }
782 mixer->sums[i] = sum;
783 }
784 if (err)
785 goto error1;
786
787 /* Allocate amixer resources for mixer obj */
788 amixer_mgr = (struct amixer_mgr *)mixer->atc->rsc_mgrs[AMIXER];
789 am_desc.msr = mixer->atc->msr;
790 for (i = 0; i < (NUM_CT_AMIXERS * CHN_NUM); i++) {
791 err = amixer_mgr->get_amixer(amixer_mgr, &am_desc, &amixer);
792 if (err) {
793 printk(KERN_ERR "ctxfi:Failed to get amixer resources "
794 "for mixer obj!\n");
795 break;
796 }
797 mixer->amixers[i] = amixer;
798 }
799 if (err)
800 goto error2;
801
802 return 0;
803
804error2:
805 for (i = 0; i < (NUM_CT_AMIXERS * CHN_NUM); i++) {
806 if (NULL != mixer->amixers[i]) {
807 amixer = mixer->amixers[i];
808 amixer_mgr->put_amixer(amixer_mgr, amixer);
809 mixer->amixers[i] = NULL;
810 }
811 }
812error1:
813 for (i = 0; i < (NUM_CT_SUMS * CHN_NUM); i++) {
814 if (NULL != mixer->sums[i]) {
815 sum_mgr->put_sum(sum_mgr, (struct sum *)mixer->sums[i]);
816 mixer->sums[i] = NULL;
817 }
818 }
819
820 return err;
821}
822
823static int ct_mixer_get_mem(struct ct_mixer **rmixer)
824{
825 struct ct_mixer *mixer;
826 int err;
827
828 *rmixer = NULL;
829 /* Allocate mem for mixer obj */
830 mixer = kzalloc(sizeof(*mixer), GFP_KERNEL);
831 if (NULL == mixer)
832 return -ENOMEM;
833
834 mixer->amixers = kzalloc(sizeof(void *)*(NUM_CT_AMIXERS*CHN_NUM),
835 GFP_KERNEL);
836 if (NULL == mixer->amixers) {
837 err = -ENOMEM;
838 goto error1;
839 }
840 mixer->sums = kzalloc(sizeof(void *)*(NUM_CT_SUMS*CHN_NUM), GFP_KERNEL);
841 if (NULL == mixer->sums) {
842 err = -ENOMEM;
843 goto error2;
844 }
845
846 *rmixer = mixer;
847 return 0;
848
849error2:
850 kfree(mixer->amixers);
851error1:
852 kfree(mixer);
853 return err;
854}
855
856static int ct_mixer_topology_build(struct ct_mixer *mixer)
857{
858 struct sum *sum;
859 struct amixer *amix_d, *amix_s;
860 enum CT_AMIXER_CTL i, j;
861
862 /* Build topology from destination to source */
863
864 /* Set up Master mixer */
865 for (i = AMIXER_MASTER_F, j = SUM_IN_F;
866 i <= AMIXER_MASTER_S; i++, j++) {
867 amix_d = mixer->amixers[i*CHN_NUM];
868 sum = mixer->sums[j*CHN_NUM];
869 amix_d->ops->setup(amix_d, &sum->rsc, INIT_VOL, NULL);
870 amix_d = mixer->amixers[i*CHN_NUM+1];
871 sum = mixer->sums[j*CHN_NUM+1];
872 amix_d->ops->setup(amix_d, &sum->rsc, INIT_VOL, NULL);
873 }
874
875 /* Set up Wave-out mixer */
876 for (i = AMIXER_WAVE_F, j = AMIXER_MASTER_F;
877 i <= AMIXER_WAVE_S; i++, j++) {
878 amix_d = mixer->amixers[i*CHN_NUM];
879 amix_s = mixer->amixers[j*CHN_NUM];
880 amix_d->ops->setup(amix_d, &amix_s->rsc, INIT_VOL, NULL);
881 amix_d = mixer->amixers[i*CHN_NUM+1];
882 amix_s = mixer->amixers[j*CHN_NUM+1];
883 amix_d->ops->setup(amix_d, &amix_s->rsc, INIT_VOL, NULL);
884 }
885
886 /* Set up S/PDIF-out mixer */
887 amix_d = mixer->amixers[AMIXER_SPDIFO*CHN_NUM];
888 amix_s = mixer->amixers[AMIXER_MASTER_F*CHN_NUM];
889 amix_d->ops->setup(amix_d, &amix_s->rsc, INIT_VOL, NULL);
890 amix_d = mixer->amixers[AMIXER_SPDIFO*CHN_NUM+1];
891 amix_s = mixer->amixers[AMIXER_MASTER_F*CHN_NUM+1];
892 amix_d->ops->setup(amix_d, &amix_s->rsc, INIT_VOL, NULL);
893
894 /* Set up PCM-in mixer */
895 for (i = AMIXER_PCM_F, j = SUM_IN_F; i <= AMIXER_PCM_S; i++, j++) {
896 amix_d = mixer->amixers[i*CHN_NUM];
897 sum = mixer->sums[j*CHN_NUM];
898 amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum);
899 amix_d = mixer->amixers[i*CHN_NUM+1];
900 sum = mixer->sums[j*CHN_NUM+1];
901 amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum);
902 }
903
904 /* Set up Line-in mixer */
905 amix_d = mixer->amixers[AMIXER_LINEIN*CHN_NUM];
906 sum = mixer->sums[SUM_IN_F*CHN_NUM];
907 amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum);
908 amix_d = mixer->amixers[AMIXER_LINEIN*CHN_NUM+1];
909 sum = mixer->sums[SUM_IN_F*CHN_NUM+1];
910 amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum);
911
912 /* Set up Mic-in mixer */
913 amix_d = mixer->amixers[AMIXER_MIC*CHN_NUM];
914 sum = mixer->sums[SUM_IN_F*CHN_NUM];
915 amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum);
916 amix_d = mixer->amixers[AMIXER_MIC*CHN_NUM+1];
917 sum = mixer->sums[SUM_IN_F*CHN_NUM+1];
918 amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum);
919
920 /* Set up S/PDIF-in mixer */
921 amix_d = mixer->amixers[AMIXER_SPDIFI*CHN_NUM];
922 sum = mixer->sums[SUM_IN_F*CHN_NUM];
923 amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum);
924 amix_d = mixer->amixers[AMIXER_SPDIFI*CHN_NUM+1];
925 sum = mixer->sums[SUM_IN_F*CHN_NUM+1];
926 amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum);
927
928 /* Set up Master recording mixer */
929 amix_d = mixer->amixers[AMIXER_MASTER_F_C*CHN_NUM];
930 sum = mixer->sums[SUM_IN_F_C*CHN_NUM];
931 amix_d->ops->setup(amix_d, &sum->rsc, INIT_VOL, NULL);
932 amix_d = mixer->amixers[AMIXER_MASTER_F_C*CHN_NUM+1];
933 sum = mixer->sums[SUM_IN_F_C*CHN_NUM+1];
934 amix_d->ops->setup(amix_d, &sum->rsc, INIT_VOL, NULL);
935
936 /* Set up PCM-in recording mixer */
937 amix_d = mixer->amixers[AMIXER_PCM_F_C*CHN_NUM];
938 sum = mixer->sums[SUM_IN_F_C*CHN_NUM];
939 amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum);
940 amix_d = mixer->amixers[AMIXER_PCM_F_C*CHN_NUM+1];
941 sum = mixer->sums[SUM_IN_F_C*CHN_NUM+1];
942 amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum);
943
944 /* Set up Line-in recording mixer */
945 amix_d = mixer->amixers[AMIXER_LINEIN_C*CHN_NUM];
946 sum = mixer->sums[SUM_IN_F_C*CHN_NUM];
947 amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum);
948 amix_d = mixer->amixers[AMIXER_LINEIN_C*CHN_NUM+1];
949 sum = mixer->sums[SUM_IN_F_C*CHN_NUM+1];
950 amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum);
951
952 /* Set up Mic-in recording mixer */
953 amix_d = mixer->amixers[AMIXER_MIC_C*CHN_NUM];
954 sum = mixer->sums[SUM_IN_F_C*CHN_NUM];
955 amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum);
956 amix_d = mixer->amixers[AMIXER_MIC_C*CHN_NUM+1];
957 sum = mixer->sums[SUM_IN_F_C*CHN_NUM+1];
958 amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum);
959
960 /* Set up S/PDIF-in recording mixer */
961 amix_d = mixer->amixers[AMIXER_SPDIFI_C*CHN_NUM];
962 sum = mixer->sums[SUM_IN_F_C*CHN_NUM];
963 amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum);
964 amix_d = mixer->amixers[AMIXER_SPDIFI_C*CHN_NUM+1];
965 sum = mixer->sums[SUM_IN_F_C*CHN_NUM+1];
966 amix_d->ops->setup(amix_d, NULL, INIT_VOL, sum);
967
968 return 0;
969}
970
971static int mixer_set_input_port(struct amixer *amixer, struct rsc *rsc)
972{
973 amixer->ops->set_input(amixer, rsc);
974 amixer->ops->commit_write(amixer);
975
976 return 0;
977}
978
979static enum CT_AMIXER_CTL port_to_amixer(enum MIXER_PORT_T type)
980{
981 switch (type) {
982 case MIX_WAVE_FRONT: return AMIXER_WAVE_F;
983 case MIX_WAVE_SURROUND: return AMIXER_WAVE_S;
984 case MIX_WAVE_CENTLFE: return AMIXER_WAVE_C;
985 case MIX_WAVE_REAR: return AMIXER_WAVE_R;
986 case MIX_PCMO_FRONT: return AMIXER_MASTER_F_C;
987 case MIX_SPDIF_OUT: return AMIXER_SPDIFO;
988 case MIX_LINE_IN: return AMIXER_LINEIN;
989 case MIX_MIC_IN: return AMIXER_MIC;
990 case MIX_SPDIF_IN: return AMIXER_SPDIFI;
991 case MIX_PCMI_FRONT: return AMIXER_PCM_F;
992 case MIX_PCMI_SURROUND: return AMIXER_PCM_S;
993 case MIX_PCMI_CENTLFE: return AMIXER_PCM_C;
994 case MIX_PCMI_REAR: return AMIXER_PCM_R;
995 default: return 0;
996 }
997}
998
999static int mixer_get_output_ports(struct ct_mixer *mixer,
1000 enum MIXER_PORT_T type,
1001 struct rsc **rleft, struct rsc **rright)
1002{
1003 enum CT_AMIXER_CTL amix = port_to_amixer(type);
1004
1005 if (NULL != rleft)
1006 *rleft = &((struct amixer *)mixer->amixers[amix*CHN_NUM])->rsc;
1007
1008 if (NULL != rright)
1009 *rright =
1010 &((struct amixer *)mixer->amixers[amix*CHN_NUM+1])->rsc;
1011
1012 return 0;
1013}
1014
1015static int mixer_set_input_left(struct ct_mixer *mixer,
1016 enum MIXER_PORT_T type, struct rsc *rsc)
1017{
1018 enum CT_AMIXER_CTL amix = port_to_amixer(type);
1019
1020 mixer_set_input_port(mixer->amixers[amix*CHN_NUM], rsc);
1021 amix = get_recording_amixer(amix);
1022 if (amix < NUM_CT_AMIXERS)
1023 mixer_set_input_port(mixer->amixers[amix*CHN_NUM], rsc);
1024
1025 return 0;
1026}
1027
1028static int
1029mixer_set_input_right(struct ct_mixer *mixer,
1030 enum MIXER_PORT_T type, struct rsc *rsc)
1031{
1032 enum CT_AMIXER_CTL amix = port_to_amixer(type);
1033
1034 mixer_set_input_port(mixer->amixers[amix*CHN_NUM+1], rsc);
1035 amix = get_recording_amixer(amix);
1036 if (amix < NUM_CT_AMIXERS)
1037 mixer_set_input_port(mixer->amixers[amix*CHN_NUM+1], rsc);
1038
1039 return 0;
1040}
1041
1042int ct_mixer_destroy(struct ct_mixer *mixer)
1043{
1044 struct sum_mgr *sum_mgr = (struct sum_mgr *)mixer->atc->rsc_mgrs[SUM];
1045 struct amixer_mgr *amixer_mgr =
1046 (struct amixer_mgr *)mixer->atc->rsc_mgrs[AMIXER];
1047 struct amixer *amixer;
1048 int i = 0;
1049
1050 /* Release amixer resources */
1051 for (i = 0; i < (NUM_CT_AMIXERS * CHN_NUM); i++) {
1052 if (NULL != mixer->amixers[i]) {
1053 amixer = mixer->amixers[i];
1054 amixer_mgr->put_amixer(amixer_mgr, amixer);
1055 }
1056 }
1057
1058 /* Release sum resources */
1059 for (i = 0; i < (NUM_CT_SUMS * CHN_NUM); i++) {
1060 if (NULL != mixer->sums[i])
1061 sum_mgr->put_sum(sum_mgr, (struct sum *)mixer->sums[i]);
1062 }
1063
1064 /* Release mem assigned to mixer object */
1065 kfree(mixer->sums);
1066 kfree(mixer->amixers);
1067 kfree(mixer);
1068
1069 return 0;
1070}
1071
1072int ct_mixer_create(struct ct_atc *atc, struct ct_mixer **rmixer)
1073{
1074 struct ct_mixer *mixer;
1075 int err;
1076
1077 *rmixer = NULL;
1078
1079 /* Allocate mem for mixer obj */
1080 err = ct_mixer_get_mem(&mixer);
1081 if (err)
1082 return err;
1083
1084 mixer->switch_state = 0;
1085 mixer->atc = atc;
1086 /* Set operations */
1087 mixer->get_output_ports = mixer_get_output_ports;
1088 mixer->set_input_left = mixer_set_input_left;
1089 mixer->set_input_right = mixer_set_input_right;
1090
1091 /* Allocate chip resources for mixer obj */
1092 err = ct_mixer_get_resources(mixer);
1093 if (err)
1094 goto error;
1095
1096 /* Build internal mixer topology */
1097 ct_mixer_topology_build(mixer);
1098
1099 *rmixer = mixer;
1100
1101 return 0;
1102
1103error:
1104 ct_mixer_destroy(mixer);
1105 return err;
1106}
1107
1108int ct_alsa_mix_create(struct ct_atc *atc,
1109 enum CTALSADEVS device,
1110 const char *device_name)
1111{
1112 int err;
1113
1114 /* Create snd kcontrol instances on demand */
1115 /* vol_ctl.device = swh_ctl.device = device; */ /* better w/ device 0 */
1116 err = ct_mixer_kcontrols_create((struct ct_mixer *)atc->mixer);
1117 if (err)
1118 return err;
1119
1120 strcpy(atc->card->mixername, device_name);
1121
1122 return 0;
1123}
diff --git a/sound/pci/ctxfi/ctmixer.h b/sound/pci/ctxfi/ctmixer.h
new file mode 100644
index 00000000000..e2d96ebde74
--- /dev/null
+++ b/sound/pci/ctxfi/ctmixer.h
@@ -0,0 +1,67 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File ctmixer.h
9 *
10 * @Brief
11 * This file contains the definition of the mixer device functions.
12 *
13 * @Author Liu Chun
14 * @Date Mar 28 2008
15 *
16 */
17
18#ifndef CTMIXER_H
19#define CTMIXER_H
20
21#include "ctatc.h"
22#include "ctresource.h"
23
24#define INIT_VOL 0x1c00
25
26enum MIXER_PORT_T {
27 MIX_WAVE_FRONT,
28 MIX_WAVE_REAR,
29 MIX_WAVE_CENTLFE,
30 MIX_WAVE_SURROUND,
31 MIX_SPDIF_OUT,
32 MIX_PCMO_FRONT,
33 MIX_MIC_IN,
34 MIX_LINE_IN,
35 MIX_SPDIF_IN,
36 MIX_PCMI_FRONT,
37 MIX_PCMI_REAR,
38 MIX_PCMI_CENTLFE,
39 MIX_PCMI_SURROUND,
40
41 NUM_MIX_PORTS
42};
43
44/* alsa mixer descriptor */
45struct ct_mixer {
46 struct ct_atc *atc;
47
48 void **amixers; /* amixer resources for volume control */
49 void **sums; /* sum resources for signal collection */
50 unsigned int switch_state; /* A bit-map to indicate state of switches */
51
52 int (*get_output_ports)(struct ct_mixer *mixer, enum MIXER_PORT_T type,
53 struct rsc **rleft, struct rsc **rright);
54
55 int (*set_input_left)(struct ct_mixer *mixer,
56 enum MIXER_PORT_T type, struct rsc *rsc);
57 int (*set_input_right)(struct ct_mixer *mixer,
58 enum MIXER_PORT_T type, struct rsc *rsc);
59};
60
61int ct_alsa_mix_create(struct ct_atc *atc,
62 enum CTALSADEVS device,
63 const char *device_name);
64int ct_mixer_create(struct ct_atc *atc, struct ct_mixer **rmixer);
65int ct_mixer_destroy(struct ct_mixer *mixer);
66
67#endif /* CTMIXER_H */
diff --git a/sound/pci/ctxfi/ctpcm.c b/sound/pci/ctxfi/ctpcm.c
new file mode 100644
index 00000000000..9e5c0c4da72
--- /dev/null
+++ b/sound/pci/ctxfi/ctpcm.c
@@ -0,0 +1,426 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File ctpcm.c
9 *
10 * @Brief
11 * This file contains the definition of the pcm device functions.
12 *
13 * @Author Liu Chun
14 * @Date Apr 2 2008
15 *
16 */
17
18#include "ctpcm.h"
19#include "cttimer.h"
20#include <sound/pcm.h>
21
22/* Hardware descriptions for playback */
23static struct snd_pcm_hardware ct_pcm_playback_hw = {
24 .info = (SNDRV_PCM_INFO_MMAP |
25 SNDRV_PCM_INFO_INTERLEAVED |
26 SNDRV_PCM_INFO_BLOCK_TRANSFER |
27 SNDRV_PCM_INFO_MMAP_VALID |
28 SNDRV_PCM_INFO_PAUSE),
29 .formats = (SNDRV_PCM_FMTBIT_U8 |
30 SNDRV_PCM_FMTBIT_S16_LE |
31 SNDRV_PCM_FMTBIT_S24_3LE |
32 SNDRV_PCM_FMTBIT_S32_LE |
33 SNDRV_PCM_FMTBIT_FLOAT_LE),
34 .rates = (SNDRV_PCM_RATE_CONTINUOUS |
35 SNDRV_PCM_RATE_8000_192000),
36 .rate_min = 8000,
37 .rate_max = 192000,
38 .channels_min = 1,
39 .channels_max = 2,
40 .buffer_bytes_max = (128*1024),
41 .period_bytes_min = (64),
42 .period_bytes_max = (128*1024),
43 .periods_min = 2,
44 .periods_max = 1024,
45 .fifo_size = 0,
46};
47
48static struct snd_pcm_hardware ct_spdif_passthru_playback_hw = {
49 .info = (SNDRV_PCM_INFO_MMAP |
50 SNDRV_PCM_INFO_INTERLEAVED |
51 SNDRV_PCM_INFO_BLOCK_TRANSFER |
52 SNDRV_PCM_INFO_MMAP_VALID |
53 SNDRV_PCM_INFO_PAUSE),
54 .formats = SNDRV_PCM_FMTBIT_S16_LE,
55 .rates = (SNDRV_PCM_RATE_48000 |
56 SNDRV_PCM_RATE_44100 |
57 SNDRV_PCM_RATE_32000),
58 .rate_min = 32000,
59 .rate_max = 48000,
60 .channels_min = 2,
61 .channels_max = 2,
62 .buffer_bytes_max = (128*1024),
63 .period_bytes_min = (64),
64 .period_bytes_max = (128*1024),
65 .periods_min = 2,
66 .periods_max = 1024,
67 .fifo_size = 0,
68};
69
70/* Hardware descriptions for capture */
71static struct snd_pcm_hardware ct_pcm_capture_hw = {
72 .info = (SNDRV_PCM_INFO_MMAP |
73 SNDRV_PCM_INFO_INTERLEAVED |
74 SNDRV_PCM_INFO_BLOCK_TRANSFER |
75 SNDRV_PCM_INFO_PAUSE |
76 SNDRV_PCM_INFO_MMAP_VALID),
77 .formats = (SNDRV_PCM_FMTBIT_U8 |
78 SNDRV_PCM_FMTBIT_S16_LE |
79 SNDRV_PCM_FMTBIT_S24_3LE |
80 SNDRV_PCM_FMTBIT_S32_LE |
81 SNDRV_PCM_FMTBIT_FLOAT_LE),
82 .rates = (SNDRV_PCM_RATE_CONTINUOUS |
83 SNDRV_PCM_RATE_8000_96000),
84 .rate_min = 8000,
85 .rate_max = 96000,
86 .channels_min = 1,
87 .channels_max = 2,
88 .buffer_bytes_max = (128*1024),
89 .period_bytes_min = (384),
90 .period_bytes_max = (64*1024),
91 .periods_min = 2,
92 .periods_max = 1024,
93 .fifo_size = 0,
94};
95
96static void ct_atc_pcm_interrupt(struct ct_atc_pcm *atc_pcm)
97{
98 struct ct_atc_pcm *apcm = atc_pcm;
99
100 if (NULL == apcm->substream)
101 return;
102
103 snd_pcm_period_elapsed(apcm->substream);
104}
105
106static void ct_atc_pcm_free_substream(struct snd_pcm_runtime *runtime)
107{
108 struct ct_atc_pcm *apcm = runtime->private_data;
109 struct ct_atc *atc = snd_pcm_substream_chip(apcm->substream);
110
111 atc->pcm_release_resources(atc, apcm);
112 ct_timer_instance_free(apcm->timer);
113 kfree(apcm);
114 runtime->private_data = NULL;
115}
116
117/* pcm playback operations */
118static int ct_pcm_playback_open(struct snd_pcm_substream *substream)
119{
120 struct ct_atc *atc = snd_pcm_substream_chip(substream);
121 struct snd_pcm_runtime *runtime = substream->runtime;
122 struct ct_atc_pcm *apcm;
123 int err;
124
125 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
126 if (NULL == apcm)
127 return -ENOMEM;
128
129 apcm->substream = substream;
130 apcm->interrupt = ct_atc_pcm_interrupt;
131 runtime->private_data = apcm;
132 runtime->private_free = ct_atc_pcm_free_substream;
133 if (IEC958 == substream->pcm->device) {
134 runtime->hw = ct_spdif_passthru_playback_hw;
135 atc->spdif_out_passthru(atc, 1);
136 } else {
137 runtime->hw = ct_pcm_playback_hw;
138 if (FRONT == substream->pcm->device)
139 runtime->hw.channels_max = 8;
140 }
141
142 err = snd_pcm_hw_constraint_integer(runtime,
143 SNDRV_PCM_HW_PARAM_PERIODS);
144 if (err < 0) {
145 kfree(apcm);
146 return err;
147 }
148 err = snd_pcm_hw_constraint_minmax(runtime,
149 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
150 1024, UINT_MAX);
151 if (err < 0) {
152 kfree(apcm);
153 return err;
154 }
155
156 apcm->timer = ct_timer_instance_new(atc->timer, apcm);
157 if (!apcm->timer)
158 return -ENOMEM;
159
160 return 0;
161}
162
163static int ct_pcm_playback_close(struct snd_pcm_substream *substream)
164{
165 struct ct_atc *atc = snd_pcm_substream_chip(substream);
166
167 /* TODO: Notify mixer inactive. */
168 if (IEC958 == substream->pcm->device)
169 atc->spdif_out_passthru(atc, 0);
170
171 /* The ct_atc_pcm object will be freed by runtime->private_free */
172
173 return 0;
174}
175
176static int ct_pcm_hw_params(struct snd_pcm_substream *substream,
177 struct snd_pcm_hw_params *hw_params)
178{
179 struct ct_atc *atc = snd_pcm_substream_chip(substream);
180 struct ct_atc_pcm *apcm = substream->runtime->private_data;
181 int err;
182
183 err = snd_pcm_lib_malloc_pages(substream,
184 params_buffer_bytes(hw_params));
185 if (err < 0)
186 return err;
187 /* clear previous resources */
188 atc->pcm_release_resources(atc, apcm);
189 return err;
190}
191
192static int ct_pcm_hw_free(struct snd_pcm_substream *substream)
193{
194 struct ct_atc *atc = snd_pcm_substream_chip(substream);
195 struct ct_atc_pcm *apcm = substream->runtime->private_data;
196
197 /* clear previous resources */
198 atc->pcm_release_resources(atc, apcm);
199 /* Free snd-allocated pages */
200 return snd_pcm_lib_free_pages(substream);
201}
202
203
204static int ct_pcm_playback_prepare(struct snd_pcm_substream *substream)
205{
206 int err;
207 struct ct_atc *atc = snd_pcm_substream_chip(substream);
208 struct snd_pcm_runtime *runtime = substream->runtime;
209 struct ct_atc_pcm *apcm = runtime->private_data;
210
211 if (IEC958 == substream->pcm->device)
212 err = atc->spdif_passthru_playback_prepare(atc, apcm);
213 else
214 err = atc->pcm_playback_prepare(atc, apcm);
215
216 if (err < 0) {
217 printk(KERN_ERR "ctxfi: Preparing pcm playback failed!!!\n");
218 return err;
219 }
220
221 return 0;
222}
223
224static int
225ct_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd)
226{
227 struct ct_atc *atc = snd_pcm_substream_chip(substream);
228 struct snd_pcm_runtime *runtime = substream->runtime;
229 struct ct_atc_pcm *apcm = runtime->private_data;
230
231 switch (cmd) {
232 case SNDRV_PCM_TRIGGER_START:
233 case SNDRV_PCM_TRIGGER_RESUME:
234 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
235 atc->pcm_playback_start(atc, apcm);
236 break;
237 case SNDRV_PCM_TRIGGER_STOP:
238 case SNDRV_PCM_TRIGGER_SUSPEND:
239 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
240 atc->pcm_playback_stop(atc, apcm);
241 break;
242 default:
243 break;
244 }
245
246 return 0;
247}
248
249static snd_pcm_uframes_t
250ct_pcm_playback_pointer(struct snd_pcm_substream *substream)
251{
252 unsigned long position;
253 struct ct_atc *atc = snd_pcm_substream_chip(substream);
254 struct snd_pcm_runtime *runtime = substream->runtime;
255 struct ct_atc_pcm *apcm = runtime->private_data;
256
257 /* Read out playback position */
258 position = atc->pcm_playback_position(atc, apcm);
259 position = bytes_to_frames(runtime, position);
260 if (position >= runtime->buffer_size)
261 position = 0;
262 return position;
263}
264
265/* pcm capture operations */
266static int ct_pcm_capture_open(struct snd_pcm_substream *substream)
267{
268 struct ct_atc *atc = snd_pcm_substream_chip(substream);
269 struct snd_pcm_runtime *runtime = substream->runtime;
270 struct ct_atc_pcm *apcm;
271 int err;
272
273 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
274 if (NULL == apcm)
275 return -ENOMEM;
276
277 apcm->started = 0;
278 apcm->substream = substream;
279 apcm->interrupt = ct_atc_pcm_interrupt;
280 runtime->private_data = apcm;
281 runtime->private_free = ct_atc_pcm_free_substream;
282 runtime->hw = ct_pcm_capture_hw;
283 runtime->hw.rate_max = atc->rsr * atc->msr;
284
285 err = snd_pcm_hw_constraint_integer(runtime,
286 SNDRV_PCM_HW_PARAM_PERIODS);
287 if (err < 0) {
288 kfree(apcm);
289 return err;
290 }
291 err = snd_pcm_hw_constraint_minmax(runtime,
292 SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
293 1024, UINT_MAX);
294 if (err < 0) {
295 kfree(apcm);
296 return err;
297 }
298
299 apcm->timer = ct_timer_instance_new(atc->timer, apcm);
300 if (!apcm->timer)
301 return -ENOMEM;
302
303 return 0;
304}
305
306static int ct_pcm_capture_close(struct snd_pcm_substream *substream)
307{
308 /* The ct_atc_pcm object will be freed by runtime->private_free */
309 /* TODO: Notify mixer inactive. */
310 return 0;
311}
312
313static int ct_pcm_capture_prepare(struct snd_pcm_substream *substream)
314{
315 int err;
316 struct ct_atc *atc = snd_pcm_substream_chip(substream);
317 struct snd_pcm_runtime *runtime = substream->runtime;
318 struct ct_atc_pcm *apcm = runtime->private_data;
319
320 err = atc->pcm_capture_prepare(atc, apcm);
321 if (err < 0) {
322 printk(KERN_ERR "ctxfi: Preparing pcm capture failed!!!\n");
323 return err;
324 }
325
326 return 0;
327}
328
329static int
330ct_pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd)
331{
332 struct ct_atc *atc = snd_pcm_substream_chip(substream);
333 struct snd_pcm_runtime *runtime = substream->runtime;
334 struct ct_atc_pcm *apcm = runtime->private_data;
335
336 switch (cmd) {
337 case SNDRV_PCM_TRIGGER_START:
338 atc->pcm_capture_start(atc, apcm);
339 break;
340 case SNDRV_PCM_TRIGGER_STOP:
341 atc->pcm_capture_stop(atc, apcm);
342 break;
343 default:
344 atc->pcm_capture_stop(atc, apcm);
345 break;
346 }
347
348 return 0;
349}
350
351static snd_pcm_uframes_t
352ct_pcm_capture_pointer(struct snd_pcm_substream *substream)
353{
354 unsigned long position;
355 struct ct_atc *atc = snd_pcm_substream_chip(substream);
356 struct snd_pcm_runtime *runtime = substream->runtime;
357 struct ct_atc_pcm *apcm = runtime->private_data;
358
359 /* Read out playback position */
360 position = atc->pcm_capture_position(atc, apcm);
361 position = bytes_to_frames(runtime, position);
362 if (position >= runtime->buffer_size)
363 position = 0;
364 return position;
365}
366
367/* PCM operators for playback */
368static struct snd_pcm_ops ct_pcm_playback_ops = {
369 .open = ct_pcm_playback_open,
370 .close = ct_pcm_playback_close,
371 .ioctl = snd_pcm_lib_ioctl,
372 .hw_params = ct_pcm_hw_params,
373 .hw_free = ct_pcm_hw_free,
374 .prepare = ct_pcm_playback_prepare,
375 .trigger = ct_pcm_playback_trigger,
376 .pointer = ct_pcm_playback_pointer,
377 .page = snd_pcm_sgbuf_ops_page,
378};
379
380/* PCM operators for capture */
381static struct snd_pcm_ops ct_pcm_capture_ops = {
382 .open = ct_pcm_capture_open,
383 .close = ct_pcm_capture_close,
384 .ioctl = snd_pcm_lib_ioctl,
385 .hw_params = ct_pcm_hw_params,
386 .hw_free = ct_pcm_hw_free,
387 .prepare = ct_pcm_capture_prepare,
388 .trigger = ct_pcm_capture_trigger,
389 .pointer = ct_pcm_capture_pointer,
390 .page = snd_pcm_sgbuf_ops_page,
391};
392
393/* Create ALSA pcm device */
394int ct_alsa_pcm_create(struct ct_atc *atc,
395 enum CTALSADEVS device,
396 const char *device_name)
397{
398 struct snd_pcm *pcm;
399 int err;
400 int playback_count, capture_count;
401
402 playback_count = (IEC958 == device) ? 1 : 8;
403 capture_count = (FRONT == device) ? 1 : 0;
404 err = snd_pcm_new(atc->card, "ctxfi", device,
405 playback_count, capture_count, &pcm);
406 if (err < 0) {
407 printk(KERN_ERR "ctxfi: snd_pcm_new failed!! Err=%d\n", err);
408 return err;
409 }
410
411 pcm->private_data = atc;
412 pcm->info_flags = 0;
413 pcm->dev_subclass = SNDRV_PCM_SUBCLASS_GENERIC_MIX;
414 strlcpy(pcm->name, device_name, sizeof(pcm->name));
415
416 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &ct_pcm_playback_ops);
417
418 if (FRONT == device)
419 snd_pcm_set_ops(pcm,
420 SNDRV_PCM_STREAM_CAPTURE, &ct_pcm_capture_ops);
421
422 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
423 snd_dma_pci_data(atc->pci), 128*1024, 128*1024);
424
425 return 0;
426}
diff --git a/sound/pci/ctxfi/ctpcm.h b/sound/pci/ctxfi/ctpcm.h
new file mode 100644
index 00000000000..178da0dca64
--- /dev/null
+++ b/sound/pci/ctxfi/ctpcm.h
@@ -0,0 +1,27 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File ctpcm.h
9 *
10 * @Brief
11 * This file contains the definition of the pcm device functions.
12 *
13 * @Author Liu Chun
14 * @Date Mar 28 2008
15 *
16 */
17
18#ifndef CTPCM_H
19#define CTPCM_H
20
21#include "ctatc.h"
22
23int ct_alsa_pcm_create(struct ct_atc *atc,
24 enum CTALSADEVS device,
25 const char *device_name);
26
27#endif /* CTPCM_H */
diff --git a/sound/pci/ctxfi/ctresource.c b/sound/pci/ctxfi/ctresource.c
new file mode 100644
index 00000000000..889c495bb7d
--- /dev/null
+++ b/sound/pci/ctxfi/ctresource.c
@@ -0,0 +1,301 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File ctresource.c
9 *
10 * @Brief
11 * This file contains the implementation of some generic helper functions.
12 *
13 * @Author Liu Chun
14 * @Date May 15 2008
15 *
16 */
17
18#include "ctresource.h"
19#include "cthardware.h"
20#include <linux/err.h>
21#include <linux/slab.h>
22
23#define AUDIO_SLOT_BLOCK_NUM 256
24
25/* Resource allocation based on bit-map management mechanism */
26static int
27get_resource(u8 *rscs, unsigned int amount,
28 unsigned int multi, unsigned int *ridx)
29{
30 int i, j, k, n;
31
32 /* Check whether there are sufficient resources to meet request. */
33 for (i = 0, n = multi; i < amount; i++) {
34 j = i / 8;
35 k = i % 8;
36 if (rscs[j] & ((u8)1 << k)) {
37 n = multi;
38 continue;
39 }
40 if (!(--n))
41 break; /* found sufficient contiguous resources */
42 }
43
44 if (i >= amount) {
45 /* Can not find sufficient contiguous resources */
46 return -ENOENT;
47 }
48
49 /* Mark the contiguous bits in resource bit-map as used */
50 for (n = multi; n > 0; n--) {
51 j = i / 8;
52 k = i % 8;
53 rscs[j] |= ((u8)1 << k);
54 i--;
55 }
56
57 *ridx = i + 1;
58
59 return 0;
60}
61
62static int put_resource(u8 *rscs, unsigned int multi, unsigned int idx)
63{
64 unsigned int i, j, k, n;
65
66 /* Mark the contiguous bits in resource bit-map as used */
67 for (n = multi, i = idx; n > 0; n--) {
68 j = i / 8;
69 k = i % 8;
70 rscs[j] &= ~((u8)1 << k);
71 i++;
72 }
73
74 return 0;
75}
76
77int mgr_get_resource(struct rsc_mgr *mgr, unsigned int n, unsigned int *ridx)
78{
79 int err;
80
81 if (n > mgr->avail)
82 return -ENOENT;
83
84 err = get_resource(mgr->rscs, mgr->amount, n, ridx);
85 if (!err)
86 mgr->avail -= n;
87
88 return err;
89}
90
91int mgr_put_resource(struct rsc_mgr *mgr, unsigned int n, unsigned int idx)
92{
93 put_resource(mgr->rscs, n, idx);
94 mgr->avail += n;
95
96 return 0;
97}
98
99static unsigned char offset_in_audio_slot_block[NUM_RSCTYP] = {
100 /* SRC channel is at Audio Ring slot 1 every 16 slots. */
101 [SRC] = 0x1,
102 [AMIXER] = 0x4,
103 [SUM] = 0xc,
104};
105
106static int rsc_index(const struct rsc *rsc)
107{
108 return rsc->conj;
109}
110
111static int audio_ring_slot(const struct rsc *rsc)
112{
113 return (rsc->conj << 4) + offset_in_audio_slot_block[rsc->type];
114}
115
116static int rsc_next_conj(struct rsc *rsc)
117{
118 unsigned int i;
119 for (i = 0; (i < 8) && (!(rsc->msr & (0x1 << i))); )
120 i++;
121 rsc->conj += (AUDIO_SLOT_BLOCK_NUM >> i);
122 return rsc->conj;
123}
124
125static int rsc_master(struct rsc *rsc)
126{
127 return rsc->conj = rsc->idx;
128}
129
130static struct rsc_ops rsc_generic_ops = {
131 .index = rsc_index,
132 .output_slot = audio_ring_slot,
133 .master = rsc_master,
134 .next_conj = rsc_next_conj,
135};
136
137int rsc_init(struct rsc *rsc, u32 idx, enum RSCTYP type, u32 msr, void *hw)
138{
139 int err = 0;
140
141 rsc->idx = idx;
142 rsc->conj = idx;
143 rsc->type = type;
144 rsc->msr = msr;
145 rsc->hw = hw;
146 rsc->ops = &rsc_generic_ops;
147 if (NULL == hw) {
148 rsc->ctrl_blk = NULL;
149 return 0;
150 }
151
152 switch (type) {
153 case SRC:
154 err = ((struct hw *)hw)->src_rsc_get_ctrl_blk(&rsc->ctrl_blk);
155 break;
156 case AMIXER:
157 err = ((struct hw *)hw)->
158 amixer_rsc_get_ctrl_blk(&rsc->ctrl_blk);
159 break;
160 case SRCIMP:
161 case SUM:
162 case DAIO:
163 break;
164 default:
165 printk(KERN_ERR
166 "ctxfi: Invalid resource type value %d!\n", type);
167 return -EINVAL;
168 }
169
170 if (err) {
171 printk(KERN_ERR
172 "ctxfi: Failed to get resource control block!\n");
173 return err;
174 }
175
176 return 0;
177}
178
179int rsc_uninit(struct rsc *rsc)
180{
181 if ((NULL != rsc->hw) && (NULL != rsc->ctrl_blk)) {
182 switch (rsc->type) {
183 case SRC:
184 ((struct hw *)rsc->hw)->
185 src_rsc_put_ctrl_blk(rsc->ctrl_blk);
186 break;
187 case AMIXER:
188 ((struct hw *)rsc->hw)->
189 amixer_rsc_put_ctrl_blk(rsc->ctrl_blk);
190 break;
191 case SUM:
192 case DAIO:
193 break;
194 default:
195 printk(KERN_ERR "ctxfi: "
196 "Invalid resource type value %d!\n", rsc->type);
197 break;
198 }
199
200 rsc->hw = rsc->ctrl_blk = NULL;
201 }
202
203 rsc->idx = rsc->conj = 0;
204 rsc->type = NUM_RSCTYP;
205 rsc->msr = 0;
206
207 return 0;
208}
209
210int rsc_mgr_init(struct rsc_mgr *mgr, enum RSCTYP type,
211 unsigned int amount, void *hw_obj)
212{
213 int err = 0;
214 struct hw *hw = hw_obj;
215
216 mgr->type = NUM_RSCTYP;
217
218 mgr->rscs = kzalloc(((amount + 8 - 1) / 8), GFP_KERNEL);
219 if (NULL == mgr->rscs)
220 return -ENOMEM;
221
222 switch (type) {
223 case SRC:
224 err = hw->src_mgr_get_ctrl_blk(&mgr->ctrl_blk);
225 break;
226 case SRCIMP:
227 err = hw->srcimp_mgr_get_ctrl_blk(&mgr->ctrl_blk);
228 break;
229 case AMIXER:
230 err = hw->amixer_mgr_get_ctrl_blk(&mgr->ctrl_blk);
231 break;
232 case DAIO:
233 err = hw->daio_mgr_get_ctrl_blk(hw, &mgr->ctrl_blk);
234 break;
235 case SUM:
236 break;
237 default:
238 printk(KERN_ERR
239 "ctxfi: Invalid resource type value %d!\n", type);
240 err = -EINVAL;
241 goto error;
242 }
243
244 if (err) {
245 printk(KERN_ERR
246 "ctxfi: Failed to get manager control block!\n");
247 goto error;
248 }
249
250 mgr->type = type;
251 mgr->avail = mgr->amount = amount;
252 mgr->hw = hw;
253
254 return 0;
255
256error:
257 kfree(mgr->rscs);
258 return err;
259}
260
261int rsc_mgr_uninit(struct rsc_mgr *mgr)
262{
263 if (NULL != mgr->rscs) {
264 kfree(mgr->rscs);
265 mgr->rscs = NULL;
266 }
267
268 if ((NULL != mgr->hw) && (NULL != mgr->ctrl_blk)) {
269 switch (mgr->type) {
270 case SRC:
271 ((struct hw *)mgr->hw)->
272 src_mgr_put_ctrl_blk(mgr->ctrl_blk);
273 break;
274 case SRCIMP:
275 ((struct hw *)mgr->hw)->
276 srcimp_mgr_put_ctrl_blk(mgr->ctrl_blk);
277 break;
278 case AMIXER:
279 ((struct hw *)mgr->hw)->
280 amixer_mgr_put_ctrl_blk(mgr->ctrl_blk);
281 break;
282 case DAIO:
283 ((struct hw *)mgr->hw)->
284 daio_mgr_put_ctrl_blk(mgr->ctrl_blk);
285 break;
286 case SUM:
287 break;
288 default:
289 printk(KERN_ERR "ctxfi: "
290 "Invalid resource type value %d!\n", mgr->type);
291 break;
292 }
293
294 mgr->hw = mgr->ctrl_blk = NULL;
295 }
296
297 mgr->type = NUM_RSCTYP;
298 mgr->avail = mgr->amount = 0;
299
300 return 0;
301}
diff --git a/sound/pci/ctxfi/ctresource.h b/sound/pci/ctxfi/ctresource.h
new file mode 100644
index 00000000000..0838c2e84f8
--- /dev/null
+++ b/sound/pci/ctxfi/ctresource.h
@@ -0,0 +1,72 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File ctresource.h
9 *
10 * @Brief
11 * This file contains the definition of generic hardware resources for
12 * resource management.
13 *
14 * @Author Liu Chun
15 * @Date May 13 2008
16 *
17 */
18
19#ifndef CTRESOURCE_H
20#define CTRESOURCE_H
21
22#include <linux/types.h>
23
24enum RSCTYP {
25 SRC,
26 SRCIMP,
27 AMIXER,
28 SUM,
29 DAIO,
30 NUM_RSCTYP /* This must be the last one and less than 16 */
31};
32
33struct rsc_ops;
34
35struct rsc {
36 u32 idx:12; /* The index of a resource */
37 u32 type:4; /* The type (RSCTYP) of a resource */
38 u32 conj:12; /* Current conjugate index */
39 u32 msr:4; /* The Master Sample Rate a resource working on */
40 void *ctrl_blk; /* Chip specific control info block for a resource */
41 void *hw; /* Chip specific object for hardware access means */
42 struct rsc_ops *ops; /* Generic resource operations */
43};
44
45struct rsc_ops {
46 int (*master)(struct rsc *rsc); /* Move to master resource */
47 int (*next_conj)(struct rsc *rsc); /* Move to next conjugate resource */
48 int (*index)(const struct rsc *rsc); /* Return the index of resource */
49 /* Return the output slot number */
50 int (*output_slot)(const struct rsc *rsc);
51};
52
53int rsc_init(struct rsc *rsc, u32 idx, enum RSCTYP type, u32 msr, void *hw);
54int rsc_uninit(struct rsc *rsc);
55
56struct rsc_mgr {
57 enum RSCTYP type; /* The type (RSCTYP) of resource to manage */
58 unsigned int amount; /* The total amount of a kind of resource */
59 unsigned int avail; /* The amount of currently available resources */
60 unsigned char *rscs; /* The bit-map for resource allocation */
61 void *ctrl_blk; /* Chip specific control info block */
62 void *hw; /* Chip specific object for hardware access */
63};
64
65/* Resource management is based on bit-map mechanism */
66int rsc_mgr_init(struct rsc_mgr *mgr, enum RSCTYP type,
67 unsigned int amount, void *hw);
68int rsc_mgr_uninit(struct rsc_mgr *mgr);
69int mgr_get_resource(struct rsc_mgr *mgr, unsigned int n, unsigned int *ridx);
70int mgr_put_resource(struct rsc_mgr *mgr, unsigned int n, unsigned int idx);
71
72#endif /* CTRESOURCE_H */
diff --git a/sound/pci/ctxfi/ctsrc.c b/sound/pci/ctxfi/ctsrc.c
new file mode 100644
index 00000000000..e1c145d8b70
--- /dev/null
+++ b/sound/pci/ctxfi/ctsrc.c
@@ -0,0 +1,886 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File ctsrc.c
9 *
10 * @Brief
11 * This file contains the implementation of the Sample Rate Convertor
12 * resource management object.
13 *
14 * @Author Liu Chun
15 * @Date May 13 2008
16 *
17 */
18
19#include "ctsrc.h"
20#include "cthardware.h"
21#include <linux/slab.h>
22
23#define SRC_RESOURCE_NUM 64
24#define SRCIMP_RESOURCE_NUM 256
25
26static unsigned int conj_mask;
27
28static int src_default_config_memrd(struct src *src);
29static int src_default_config_memwr(struct src *src);
30static int src_default_config_arcrw(struct src *src);
31
32static int (*src_default_config[3])(struct src *) = {
33 [MEMRD] = src_default_config_memrd,
34 [MEMWR] = src_default_config_memwr,
35 [ARCRW] = src_default_config_arcrw
36};
37
38static int src_set_state(struct src *src, unsigned int state)
39{
40 struct hw *hw;
41
42 hw = src->rsc.hw;
43 hw->src_set_state(src->rsc.ctrl_blk, state);
44
45 return 0;
46}
47
48static int src_set_bm(struct src *src, unsigned int bm)
49{
50 struct hw *hw;
51
52 hw = src->rsc.hw;
53 hw->src_set_bm(src->rsc.ctrl_blk, bm);
54
55 return 0;
56}
57
58static int src_set_sf(struct src *src, unsigned int sf)
59{
60 struct hw *hw;
61
62 hw = src->rsc.hw;
63 hw->src_set_sf(src->rsc.ctrl_blk, sf);
64
65 return 0;
66}
67
68static int src_set_pm(struct src *src, unsigned int pm)
69{
70 struct hw *hw;
71
72 hw = src->rsc.hw;
73 hw->src_set_pm(src->rsc.ctrl_blk, pm);
74
75 return 0;
76}
77
78static int src_set_rom(struct src *src, unsigned int rom)
79{
80 struct hw *hw;
81
82 hw = src->rsc.hw;
83 hw->src_set_rom(src->rsc.ctrl_blk, rom);
84
85 return 0;
86}
87
88static int src_set_vo(struct src *src, unsigned int vo)
89{
90 struct hw *hw;
91
92 hw = src->rsc.hw;
93 hw->src_set_vo(src->rsc.ctrl_blk, vo);
94
95 return 0;
96}
97
98static int src_set_st(struct src *src, unsigned int st)
99{
100 struct hw *hw;
101
102 hw = src->rsc.hw;
103 hw->src_set_st(src->rsc.ctrl_blk, st);
104
105 return 0;
106}
107
108static int src_set_bp(struct src *src, unsigned int bp)
109{
110 struct hw *hw;
111
112 hw = src->rsc.hw;
113 hw->src_set_bp(src->rsc.ctrl_blk, bp);
114
115 return 0;
116}
117
118static int src_set_cisz(struct src *src, unsigned int cisz)
119{
120 struct hw *hw;
121
122 hw = src->rsc.hw;
123 hw->src_set_cisz(src->rsc.ctrl_blk, cisz);
124
125 return 0;
126}
127
128static int src_set_ca(struct src *src, unsigned int ca)
129{
130 struct hw *hw;
131
132 hw = src->rsc.hw;
133 hw->src_set_ca(src->rsc.ctrl_blk, ca);
134
135 return 0;
136}
137
138static int src_set_sa(struct src *src, unsigned int sa)
139{
140 struct hw *hw;
141
142 hw = src->rsc.hw;
143 hw->src_set_sa(src->rsc.ctrl_blk, sa);
144
145 return 0;
146}
147
148static int src_set_la(struct src *src, unsigned int la)
149{
150 struct hw *hw;
151
152 hw = src->rsc.hw;
153 hw->src_set_la(src->rsc.ctrl_blk, la);
154
155 return 0;
156}
157
158static int src_set_pitch(struct src *src, unsigned int pitch)
159{
160 struct hw *hw;
161
162 hw = src->rsc.hw;
163 hw->src_set_pitch(src->rsc.ctrl_blk, pitch);
164
165 return 0;
166}
167
168static int src_set_clear_zbufs(struct src *src)
169{
170 struct hw *hw;
171
172 hw = src->rsc.hw;
173 hw->src_set_clear_zbufs(src->rsc.ctrl_blk, 1);
174
175 return 0;
176}
177
178static int src_commit_write(struct src *src)
179{
180 struct hw *hw;
181 int i;
182 unsigned int dirty = 0;
183
184 hw = src->rsc.hw;
185 src->rsc.ops->master(&src->rsc);
186 if (src->rsc.msr > 1) {
187 /* Save dirty flags for conjugate resource programming */
188 dirty = hw->src_get_dirty(src->rsc.ctrl_blk) & conj_mask;
189 }
190 hw->src_commit_write(hw, src->rsc.ops->index(&src->rsc),
191 src->rsc.ctrl_blk);
192
193 /* Program conjugate parameter mixer resources */
194 if (MEMWR == src->mode)
195 return 0;
196
197 for (i = 1; i < src->rsc.msr; i++) {
198 src->rsc.ops->next_conj(&src->rsc);
199 hw->src_set_dirty(src->rsc.ctrl_blk, dirty);
200 hw->src_commit_write(hw, src->rsc.ops->index(&src->rsc),
201 src->rsc.ctrl_blk);
202 }
203 src->rsc.ops->master(&src->rsc);
204
205 return 0;
206}
207
208static int src_get_ca(struct src *src)
209{
210 struct hw *hw;
211
212 hw = src->rsc.hw;
213 return hw->src_get_ca(hw, src->rsc.ops->index(&src->rsc),
214 src->rsc.ctrl_blk);
215}
216
217static int src_init(struct src *src)
218{
219 src_default_config[src->mode](src);
220
221 return 0;
222}
223
224static struct src *src_next_interleave(struct src *src)
225{
226 return src->intlv;
227}
228
229static int src_default_config_memrd(struct src *src)
230{
231 struct hw *hw = src->rsc.hw;
232 unsigned int rsr, msr;
233
234 hw->src_set_state(src->rsc.ctrl_blk, SRC_STATE_OFF);
235 hw->src_set_bm(src->rsc.ctrl_blk, 1);
236 for (rsr = 0, msr = src->rsc.msr; msr > 1; msr >>= 1)
237 rsr++;
238
239 hw->src_set_rsr(src->rsc.ctrl_blk, rsr);
240 hw->src_set_sf(src->rsc.ctrl_blk, SRC_SF_S16);
241 hw->src_set_wr(src->rsc.ctrl_blk, 0);
242 hw->src_set_pm(src->rsc.ctrl_blk, 0);
243 hw->src_set_rom(src->rsc.ctrl_blk, 0);
244 hw->src_set_vo(src->rsc.ctrl_blk, 0);
245 hw->src_set_st(src->rsc.ctrl_blk, 0);
246 hw->src_set_ilsz(src->rsc.ctrl_blk, src->multi - 1);
247 hw->src_set_cisz(src->rsc.ctrl_blk, 0x80);
248 hw->src_set_sa(src->rsc.ctrl_blk, 0x0);
249 hw->src_set_la(src->rsc.ctrl_blk, 0x1000);
250 hw->src_set_ca(src->rsc.ctrl_blk, 0x80);
251 hw->src_set_pitch(src->rsc.ctrl_blk, 0x1000000);
252 hw->src_set_clear_zbufs(src->rsc.ctrl_blk, 1);
253
254 src->rsc.ops->master(&src->rsc);
255 hw->src_commit_write(hw, src->rsc.ops->index(&src->rsc),
256 src->rsc.ctrl_blk);
257
258 for (msr = 1; msr < src->rsc.msr; msr++) {
259 src->rsc.ops->next_conj(&src->rsc);
260 hw->src_set_pitch(src->rsc.ctrl_blk, 0x1000000);
261 hw->src_commit_write(hw, src->rsc.ops->index(&src->rsc),
262 src->rsc.ctrl_blk);
263 }
264 src->rsc.ops->master(&src->rsc);
265
266 return 0;
267}
268
269static int src_default_config_memwr(struct src *src)
270{
271 struct hw *hw = src->rsc.hw;
272
273 hw->src_set_state(src->rsc.ctrl_blk, SRC_STATE_OFF);
274 hw->src_set_bm(src->rsc.ctrl_blk, 1);
275 hw->src_set_rsr(src->rsc.ctrl_blk, 0);
276 hw->src_set_sf(src->rsc.ctrl_blk, SRC_SF_S16);
277 hw->src_set_wr(src->rsc.ctrl_blk, 1);
278 hw->src_set_pm(src->rsc.ctrl_blk, 0);
279 hw->src_set_rom(src->rsc.ctrl_blk, 0);
280 hw->src_set_vo(src->rsc.ctrl_blk, 0);
281 hw->src_set_st(src->rsc.ctrl_blk, 0);
282 hw->src_set_ilsz(src->rsc.ctrl_blk, 0);
283 hw->src_set_cisz(src->rsc.ctrl_blk, 0x80);
284 hw->src_set_sa(src->rsc.ctrl_blk, 0x0);
285 hw->src_set_la(src->rsc.ctrl_blk, 0x1000);
286 hw->src_set_ca(src->rsc.ctrl_blk, 0x80);
287 hw->src_set_pitch(src->rsc.ctrl_blk, 0x1000000);
288 hw->src_set_clear_zbufs(src->rsc.ctrl_blk, 1);
289
290 src->rsc.ops->master(&src->rsc);
291 hw->src_commit_write(hw, src->rsc.ops->index(&src->rsc),
292 src->rsc.ctrl_blk);
293
294 return 0;
295}
296
297static int src_default_config_arcrw(struct src *src)
298{
299 struct hw *hw = src->rsc.hw;
300 unsigned int rsr, msr;
301 unsigned int dirty;
302
303 hw->src_set_state(src->rsc.ctrl_blk, SRC_STATE_OFF);
304 hw->src_set_bm(src->rsc.ctrl_blk, 0);
305 for (rsr = 0, msr = src->rsc.msr; msr > 1; msr >>= 1)
306 rsr++;
307
308 hw->src_set_rsr(src->rsc.ctrl_blk, rsr);
309 hw->src_set_sf(src->rsc.ctrl_blk, SRC_SF_F32);
310 hw->src_set_wr(src->rsc.ctrl_blk, 0);
311 hw->src_set_pm(src->rsc.ctrl_blk, 0);
312 hw->src_set_rom(src->rsc.ctrl_blk, 0);
313 hw->src_set_vo(src->rsc.ctrl_blk, 0);
314 hw->src_set_st(src->rsc.ctrl_blk, 0);
315 hw->src_set_ilsz(src->rsc.ctrl_blk, 0);
316 hw->src_set_cisz(src->rsc.ctrl_blk, 0x80);
317 hw->src_set_sa(src->rsc.ctrl_blk, 0x0);
318 /*hw->src_set_sa(src->rsc.ctrl_blk, 0x100);*/
319 hw->src_set_la(src->rsc.ctrl_blk, 0x1000);
320 /*hw->src_set_la(src->rsc.ctrl_blk, 0x03ffffe0);*/
321 hw->src_set_ca(src->rsc.ctrl_blk, 0x80);
322 hw->src_set_pitch(src->rsc.ctrl_blk, 0x1000000);
323 hw->src_set_clear_zbufs(src->rsc.ctrl_blk, 1);
324
325 dirty = hw->src_get_dirty(src->rsc.ctrl_blk);
326 src->rsc.ops->master(&src->rsc);
327 for (msr = 0; msr < src->rsc.msr; msr++) {
328 hw->src_set_dirty(src->rsc.ctrl_blk, dirty);
329 hw->src_commit_write(hw, src->rsc.ops->index(&src->rsc),
330 src->rsc.ctrl_blk);
331 src->rsc.ops->next_conj(&src->rsc);
332 }
333 src->rsc.ops->master(&src->rsc);
334
335 return 0;
336}
337
338static struct src_rsc_ops src_rsc_ops = {
339 .set_state = src_set_state,
340 .set_bm = src_set_bm,
341 .set_sf = src_set_sf,
342 .set_pm = src_set_pm,
343 .set_rom = src_set_rom,
344 .set_vo = src_set_vo,
345 .set_st = src_set_st,
346 .set_bp = src_set_bp,
347 .set_cisz = src_set_cisz,
348 .set_ca = src_set_ca,
349 .set_sa = src_set_sa,
350 .set_la = src_set_la,
351 .set_pitch = src_set_pitch,
352 .set_clr_zbufs = src_set_clear_zbufs,
353 .commit_write = src_commit_write,
354 .get_ca = src_get_ca,
355 .init = src_init,
356 .next_interleave = src_next_interleave,
357};
358
359static int
360src_rsc_init(struct src *src, u32 idx,
361 const struct src_desc *desc, struct src_mgr *mgr)
362{
363 int err;
364 int i, n;
365 struct src *p;
366
367 n = (MEMRD == desc->mode) ? desc->multi : 1;
368 for (i = 0, p = src; i < n; i++, p++) {
369 err = rsc_init(&p->rsc, idx + i, SRC, desc->msr, mgr->mgr.hw);
370 if (err)
371 goto error1;
372
373 /* Initialize src specific rsc operations */
374 p->ops = &src_rsc_ops;
375 p->multi = (0 == i) ? desc->multi : 1;
376 p->mode = desc->mode;
377 src_default_config[desc->mode](p);
378 mgr->src_enable(mgr, p);
379 p->intlv = p + 1;
380 }
381 (--p)->intlv = NULL; /* Set @intlv of the last SRC to NULL */
382
383 mgr->commit_write(mgr);
384
385 return 0;
386
387error1:
388 for (i--, p--; i >= 0; i--, p--) {
389 mgr->src_disable(mgr, p);
390 rsc_uninit(&p->rsc);
391 }
392 mgr->commit_write(mgr);
393 return err;
394}
395
396static int src_rsc_uninit(struct src *src, struct src_mgr *mgr)
397{
398 int i, n;
399 struct src *p;
400
401 n = (MEMRD == src->mode) ? src->multi : 1;
402 for (i = 0, p = src; i < n; i++, p++) {
403 mgr->src_disable(mgr, p);
404 rsc_uninit(&p->rsc);
405 p->multi = 0;
406 p->ops = NULL;
407 p->mode = NUM_SRCMODES;
408 p->intlv = NULL;
409 }
410 mgr->commit_write(mgr);
411
412 return 0;
413}
414
415static int
416get_src_rsc(struct src_mgr *mgr, const struct src_desc *desc, struct src **rsrc)
417{
418 unsigned int idx = SRC_RESOURCE_NUM;
419 int err;
420 struct src *src;
421 unsigned long flags;
422
423 *rsrc = NULL;
424
425 /* Check whether there are sufficient src resources to meet request. */
426 spin_lock_irqsave(&mgr->mgr_lock, flags);
427 if (MEMRD == desc->mode)
428 err = mgr_get_resource(&mgr->mgr, desc->multi, &idx);
429 else
430 err = mgr_get_resource(&mgr->mgr, 1, &idx);
431
432 spin_unlock_irqrestore(&mgr->mgr_lock, flags);
433 if (err) {
434 printk(KERN_ERR "ctxfi: Can't meet SRC resource request!\n");
435 return err;
436 }
437
438 /* Allocate mem for master src resource */
439 if (MEMRD == desc->mode)
440 src = kzalloc(sizeof(*src)*desc->multi, GFP_KERNEL);
441 else
442 src = kzalloc(sizeof(*src), GFP_KERNEL);
443
444 if (NULL == src) {
445 err = -ENOMEM;
446 goto error1;
447 }
448
449 err = src_rsc_init(src, idx, desc, mgr);
450 if (err)
451 goto error2;
452
453 *rsrc = src;
454
455 return 0;
456
457error2:
458 kfree(src);
459error1:
460 spin_lock_irqsave(&mgr->mgr_lock, flags);
461 if (MEMRD == desc->mode)
462 mgr_put_resource(&mgr->mgr, desc->multi, idx);
463 else
464 mgr_put_resource(&mgr->mgr, 1, idx);
465
466 spin_unlock_irqrestore(&mgr->mgr_lock, flags);
467 return err;
468}
469
470static int put_src_rsc(struct src_mgr *mgr, struct src *src)
471{
472 unsigned long flags;
473
474 spin_lock_irqsave(&mgr->mgr_lock, flags);
475 src->rsc.ops->master(&src->rsc);
476 if (MEMRD == src->mode)
477 mgr_put_resource(&mgr->mgr, src->multi,
478 src->rsc.ops->index(&src->rsc));
479 else
480 mgr_put_resource(&mgr->mgr, 1, src->rsc.ops->index(&src->rsc));
481
482 spin_unlock_irqrestore(&mgr->mgr_lock, flags);
483 src_rsc_uninit(src, mgr);
484 kfree(src);
485
486 return 0;
487}
488
489static int src_enable_s(struct src_mgr *mgr, struct src *src)
490{
491 struct hw *hw = mgr->mgr.hw;
492 int i;
493
494 src->rsc.ops->master(&src->rsc);
495 for (i = 0; i < src->rsc.msr; i++) {
496 hw->src_mgr_enbs_src(mgr->mgr.ctrl_blk,
497 src->rsc.ops->index(&src->rsc));
498 src->rsc.ops->next_conj(&src->rsc);
499 }
500 src->rsc.ops->master(&src->rsc);
501
502 return 0;
503}
504
505static int src_enable(struct src_mgr *mgr, struct src *src)
506{
507 struct hw *hw = mgr->mgr.hw;
508 int i;
509
510 src->rsc.ops->master(&src->rsc);
511 for (i = 0; i < src->rsc.msr; i++) {
512 hw->src_mgr_enb_src(mgr->mgr.ctrl_blk,
513 src->rsc.ops->index(&src->rsc));
514 src->rsc.ops->next_conj(&src->rsc);
515 }
516 src->rsc.ops->master(&src->rsc);
517
518 return 0;
519}
520
521static int src_disable(struct src_mgr *mgr, struct src *src)
522{
523 struct hw *hw = mgr->mgr.hw;
524 int i;
525
526 src->rsc.ops->master(&src->rsc);
527 for (i = 0; i < src->rsc.msr; i++) {
528 hw->src_mgr_dsb_src(mgr->mgr.ctrl_blk,
529 src->rsc.ops->index(&src->rsc));
530 src->rsc.ops->next_conj(&src->rsc);
531 }
532 src->rsc.ops->master(&src->rsc);
533
534 return 0;
535}
536
537static int src_mgr_commit_write(struct src_mgr *mgr)
538{
539 struct hw *hw = mgr->mgr.hw;
540
541 hw->src_mgr_commit_write(hw, mgr->mgr.ctrl_blk);
542
543 return 0;
544}
545
546int src_mgr_create(void *hw, struct src_mgr **rsrc_mgr)
547{
548 int err, i;
549 struct src_mgr *src_mgr;
550
551 *rsrc_mgr = NULL;
552 src_mgr = kzalloc(sizeof(*src_mgr), GFP_KERNEL);
553 if (NULL == src_mgr)
554 return -ENOMEM;
555
556 err = rsc_mgr_init(&src_mgr->mgr, SRC, SRC_RESOURCE_NUM, hw);
557 if (err)
558 goto error1;
559
560 spin_lock_init(&src_mgr->mgr_lock);
561 conj_mask = ((struct hw *)hw)->src_dirty_conj_mask();
562
563 src_mgr->get_src = get_src_rsc;
564 src_mgr->put_src = put_src_rsc;
565 src_mgr->src_enable_s = src_enable_s;
566 src_mgr->src_enable = src_enable;
567 src_mgr->src_disable = src_disable;
568 src_mgr->commit_write = src_mgr_commit_write;
569
570 /* Disable all SRC resources. */
571 for (i = 0; i < 256; i++)
572 ((struct hw *)hw)->src_mgr_dsb_src(src_mgr->mgr.ctrl_blk, i);
573
574 ((struct hw *)hw)->src_mgr_commit_write(hw, src_mgr->mgr.ctrl_blk);
575
576 *rsrc_mgr = src_mgr;
577
578 return 0;
579
580error1:
581 kfree(src_mgr);
582 return err;
583}
584
585int src_mgr_destroy(struct src_mgr *src_mgr)
586{
587 rsc_mgr_uninit(&src_mgr->mgr);
588 kfree(src_mgr);
589
590 return 0;
591}
592
593/* SRCIMP resource manager operations */
594
595static int srcimp_master(struct rsc *rsc)
596{
597 rsc->conj = 0;
598 return rsc->idx = container_of(rsc, struct srcimp, rsc)->idx[0];
599}
600
601static int srcimp_next_conj(struct rsc *rsc)
602{
603 rsc->conj++;
604 return container_of(rsc, struct srcimp, rsc)->idx[rsc->conj];
605}
606
607static int srcimp_index(const struct rsc *rsc)
608{
609 return container_of(rsc, struct srcimp, rsc)->idx[rsc->conj];
610}
611
612static struct rsc_ops srcimp_basic_rsc_ops = {
613 .master = srcimp_master,
614 .next_conj = srcimp_next_conj,
615 .index = srcimp_index,
616 .output_slot = NULL,
617};
618
619static int srcimp_map(struct srcimp *srcimp, struct src *src, struct rsc *input)
620{
621 struct imapper *entry;
622 int i;
623
624 srcimp->rsc.ops->master(&srcimp->rsc);
625 src->rsc.ops->master(&src->rsc);
626 input->ops->master(input);
627
628 /* Program master and conjugate resources */
629 for (i = 0; i < srcimp->rsc.msr; i++) {
630 entry = &srcimp->imappers[i];
631 entry->slot = input->ops->output_slot(input);
632 entry->user = src->rsc.ops->index(&src->rsc);
633 entry->addr = srcimp->rsc.ops->index(&srcimp->rsc);
634 srcimp->mgr->imap_add(srcimp->mgr, entry);
635 srcimp->mapped |= (0x1 << i);
636
637 srcimp->rsc.ops->next_conj(&srcimp->rsc);
638 input->ops->next_conj(input);
639 }
640
641 srcimp->rsc.ops->master(&srcimp->rsc);
642 input->ops->master(input);
643
644 return 0;
645}
646
647static int srcimp_unmap(struct srcimp *srcimp)
648{
649 int i;
650
651 /* Program master and conjugate resources */
652 for (i = 0; i < srcimp->rsc.msr; i++) {
653 if (srcimp->mapped & (0x1 << i)) {
654 srcimp->mgr->imap_delete(srcimp->mgr,
655 &srcimp->imappers[i]);
656 srcimp->mapped &= ~(0x1 << i);
657 }
658 }
659
660 return 0;
661}
662
663static struct srcimp_rsc_ops srcimp_ops = {
664 .map = srcimp_map,
665 .unmap = srcimp_unmap
666};
667
668static int srcimp_rsc_init(struct srcimp *srcimp,
669 const struct srcimp_desc *desc,
670 struct srcimp_mgr *mgr)
671{
672 int err;
673
674 err = rsc_init(&srcimp->rsc, srcimp->idx[0],
675 SRCIMP, desc->msr, mgr->mgr.hw);
676 if (err)
677 return err;
678
679 /* Reserve memory for imapper nodes */
680 srcimp->imappers = kzalloc(sizeof(struct imapper)*desc->msr,
681 GFP_KERNEL);
682 if (NULL == srcimp->imappers) {
683 err = -ENOMEM;
684 goto error1;
685 }
686
687 /* Set srcimp specific operations */
688 srcimp->rsc.ops = &srcimp_basic_rsc_ops;
689 srcimp->ops = &srcimp_ops;
690 srcimp->mgr = mgr;
691
692 srcimp->rsc.ops->master(&srcimp->rsc);
693
694 return 0;
695
696error1:
697 rsc_uninit(&srcimp->rsc);
698 return err;
699}
700
701static int srcimp_rsc_uninit(struct srcimp *srcimp)
702{
703 if (NULL != srcimp->imappers) {
704 kfree(srcimp->imappers);
705 srcimp->imappers = NULL;
706 }
707 srcimp->ops = NULL;
708 srcimp->mgr = NULL;
709 rsc_uninit(&srcimp->rsc);
710
711 return 0;
712}
713
714static int get_srcimp_rsc(struct srcimp_mgr *mgr,
715 const struct srcimp_desc *desc,
716 struct srcimp **rsrcimp)
717{
718 int err, i;
719 unsigned int idx;
720 struct srcimp *srcimp;
721 unsigned long flags;
722
723 *rsrcimp = NULL;
724
725 /* Allocate mem for SRCIMP resource */
726 srcimp = kzalloc(sizeof(*srcimp), GFP_KERNEL);
727 if (NULL == srcimp) {
728 err = -ENOMEM;
729 return err;
730 }
731
732 /* Check whether there are sufficient SRCIMP resources. */
733 spin_lock_irqsave(&mgr->mgr_lock, flags);
734 for (i = 0; i < desc->msr; i++) {
735 err = mgr_get_resource(&mgr->mgr, 1, &idx);
736 if (err)
737 break;
738
739 srcimp->idx[i] = idx;
740 }
741 spin_unlock_irqrestore(&mgr->mgr_lock, flags);
742 if (err) {
743 printk(KERN_ERR "ctxfi: Can't meet SRCIMP resource request!\n");
744 goto error1;
745 }
746
747 err = srcimp_rsc_init(srcimp, desc, mgr);
748 if (err)
749 goto error1;
750
751 *rsrcimp = srcimp;
752
753 return 0;
754
755error1:
756 spin_lock_irqsave(&mgr->mgr_lock, flags);
757 for (i--; i >= 0; i--)
758 mgr_put_resource(&mgr->mgr, 1, srcimp->idx[i]);
759
760 spin_unlock_irqrestore(&mgr->mgr_lock, flags);
761 kfree(srcimp);
762 return err;
763}
764
765static int put_srcimp_rsc(struct srcimp_mgr *mgr, struct srcimp *srcimp)
766{
767 unsigned long flags;
768 int i;
769
770 spin_lock_irqsave(&mgr->mgr_lock, flags);
771 for (i = 0; i < srcimp->rsc.msr; i++)
772 mgr_put_resource(&mgr->mgr, 1, srcimp->idx[i]);
773
774 spin_unlock_irqrestore(&mgr->mgr_lock, flags);
775 srcimp_rsc_uninit(srcimp);
776 kfree(srcimp);
777
778 return 0;
779}
780
781static int srcimp_map_op(void *data, struct imapper *entry)
782{
783 struct rsc_mgr *mgr = &((struct srcimp_mgr *)data)->mgr;
784 struct hw *hw = mgr->hw;
785
786 hw->srcimp_mgr_set_imaparc(mgr->ctrl_blk, entry->slot);
787 hw->srcimp_mgr_set_imapuser(mgr->ctrl_blk, entry->user);
788 hw->srcimp_mgr_set_imapnxt(mgr->ctrl_blk, entry->next);
789 hw->srcimp_mgr_set_imapaddr(mgr->ctrl_blk, entry->addr);
790 hw->srcimp_mgr_commit_write(mgr->hw, mgr->ctrl_blk);
791
792 return 0;
793}
794
795static int srcimp_imap_add(struct srcimp_mgr *mgr, struct imapper *entry)
796{
797 unsigned long flags;
798 int err;
799
800 spin_lock_irqsave(&mgr->imap_lock, flags);
801 if ((0 == entry->addr) && (mgr->init_imap_added)) {
802 input_mapper_delete(&mgr->imappers,
803 mgr->init_imap, srcimp_map_op, mgr);
804 mgr->init_imap_added = 0;
805 }
806 err = input_mapper_add(&mgr->imappers, entry, srcimp_map_op, mgr);
807 spin_unlock_irqrestore(&mgr->imap_lock, flags);
808
809 return err;
810}
811
812static int srcimp_imap_delete(struct srcimp_mgr *mgr, struct imapper *entry)
813{
814 unsigned long flags;
815 int err;
816
817 spin_lock_irqsave(&mgr->imap_lock, flags);
818 err = input_mapper_delete(&mgr->imappers, entry, srcimp_map_op, mgr);
819 if (list_empty(&mgr->imappers)) {
820 input_mapper_add(&mgr->imappers, mgr->init_imap,
821 srcimp_map_op, mgr);
822 mgr->init_imap_added = 1;
823 }
824 spin_unlock_irqrestore(&mgr->imap_lock, flags);
825
826 return err;
827}
828
829int srcimp_mgr_create(void *hw, struct srcimp_mgr **rsrcimp_mgr)
830{
831 int err;
832 struct srcimp_mgr *srcimp_mgr;
833 struct imapper *entry;
834
835 *rsrcimp_mgr = NULL;
836 srcimp_mgr = kzalloc(sizeof(*srcimp_mgr), GFP_KERNEL);
837 if (NULL == srcimp_mgr)
838 return -ENOMEM;
839
840 err = rsc_mgr_init(&srcimp_mgr->mgr, SRCIMP, SRCIMP_RESOURCE_NUM, hw);
841 if (err)
842 goto error1;
843
844 spin_lock_init(&srcimp_mgr->mgr_lock);
845 spin_lock_init(&srcimp_mgr->imap_lock);
846 INIT_LIST_HEAD(&srcimp_mgr->imappers);
847 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
848 if (NULL == entry) {
849 err = -ENOMEM;
850 goto error2;
851 }
852 entry->slot = entry->addr = entry->next = entry->user = 0;
853 list_add(&entry->list, &srcimp_mgr->imappers);
854 srcimp_mgr->init_imap = entry;
855 srcimp_mgr->init_imap_added = 1;
856
857 srcimp_mgr->get_srcimp = get_srcimp_rsc;
858 srcimp_mgr->put_srcimp = put_srcimp_rsc;
859 srcimp_mgr->imap_add = srcimp_imap_add;
860 srcimp_mgr->imap_delete = srcimp_imap_delete;
861
862 *rsrcimp_mgr = srcimp_mgr;
863
864 return 0;
865
866error2:
867 rsc_mgr_uninit(&srcimp_mgr->mgr);
868error1:
869 kfree(srcimp_mgr);
870 return err;
871}
872
873int srcimp_mgr_destroy(struct srcimp_mgr *srcimp_mgr)
874{
875 unsigned long flags;
876
877 /* free src input mapper list */
878 spin_lock_irqsave(&srcimp_mgr->imap_lock, flags);
879 free_input_mapper_list(&srcimp_mgr->imappers);
880 spin_unlock_irqrestore(&srcimp_mgr->imap_lock, flags);
881
882 rsc_mgr_uninit(&srcimp_mgr->mgr);
883 kfree(srcimp_mgr);
884
885 return 0;
886}
diff --git a/sound/pci/ctxfi/ctsrc.h b/sound/pci/ctxfi/ctsrc.h
new file mode 100644
index 00000000000..259366aabca
--- /dev/null
+++ b/sound/pci/ctxfi/ctsrc.h
@@ -0,0 +1,149 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File ctsrc.h
9 *
10 * @Brief
11 * This file contains the definition of the Sample Rate Convertor
12 * resource management object.
13 *
14 * @Author Liu Chun
15 * @Date May 13 2008
16 *
17 */
18
19#ifndef CTSRC_H
20#define CTSRC_H
21
22#include "ctresource.h"
23#include "ctimap.h"
24#include <linux/spinlock.h>
25#include <linux/list.h>
26
27#define SRC_STATE_OFF 0x0
28#define SRC_STATE_INIT 0x4
29#define SRC_STATE_RUN 0x5
30
31#define SRC_SF_U8 0x0
32#define SRC_SF_S16 0x1
33#define SRC_SF_S24 0x2
34#define SRC_SF_S32 0x3
35#define SRC_SF_F32 0x4
36
37/* Define the descriptor of a src resource */
38enum SRCMODE {
39 MEMRD, /* Read data from host memory */
40 MEMWR, /* Write data to host memory */
41 ARCRW, /* Read from and write to audio ring channel */
42 NUM_SRCMODES
43};
44
45struct src_rsc_ops;
46
47struct src {
48 struct rsc rsc; /* Basic resource info */
49 struct src *intlv; /* Pointer to next interleaved SRC in a series */
50 struct src_rsc_ops *ops; /* SRC specific operations */
51 /* Number of contiguous srcs for interleaved usage */
52 unsigned char multi;
53 unsigned char mode; /* Working mode of this SRC resource */
54};
55
56struct src_rsc_ops {
57 int (*set_state)(struct src *src, unsigned int state);
58 int (*set_bm)(struct src *src, unsigned int bm);
59 int (*set_sf)(struct src *src, unsigned int sf);
60 int (*set_pm)(struct src *src, unsigned int pm);
61 int (*set_rom)(struct src *src, unsigned int rom);
62 int (*set_vo)(struct src *src, unsigned int vo);
63 int (*set_st)(struct src *src, unsigned int st);
64 int (*set_bp)(struct src *src, unsigned int bp);
65 int (*set_cisz)(struct src *src, unsigned int cisz);
66 int (*set_ca)(struct src *src, unsigned int ca);
67 int (*set_sa)(struct src *src, unsigned int sa);
68 int (*set_la)(struct src *src, unsigned int la);
69 int (*set_pitch)(struct src *src, unsigned int pitch);
70 int (*set_clr_zbufs)(struct src *src);
71 int (*commit_write)(struct src *src);
72 int (*get_ca)(struct src *src);
73 int (*init)(struct src *src);
74 struct src* (*next_interleave)(struct src *src);
75};
76
77/* Define src resource request description info */
78struct src_desc {
79 /* Number of contiguous master srcs for interleaved usage */
80 unsigned char multi;
81 unsigned char msr;
82 unsigned char mode; /* Working mode of the requested srcs */
83};
84
85/* Define src manager object */
86struct src_mgr {
87 struct rsc_mgr mgr; /* Basic resource manager info */
88 spinlock_t mgr_lock;
89
90 /* request src resource */
91 int (*get_src)(struct src_mgr *mgr,
92 const struct src_desc *desc, struct src **rsrc);
93 /* return src resource */
94 int (*put_src)(struct src_mgr *mgr, struct src *src);
95 int (*src_enable_s)(struct src_mgr *mgr, struct src *src);
96 int (*src_enable)(struct src_mgr *mgr, struct src *src);
97 int (*src_disable)(struct src_mgr *mgr, struct src *src);
98 int (*commit_write)(struct src_mgr *mgr);
99};
100
101/* Define the descriptor of a SRC Input Mapper resource */
102struct srcimp_mgr;
103struct srcimp_rsc_ops;
104
105struct srcimp {
106 struct rsc rsc;
107 unsigned char idx[8];
108 struct imapper *imappers;
109 unsigned int mapped; /* A bit-map indicating which conj rsc is mapped */
110 struct srcimp_mgr *mgr;
111 struct srcimp_rsc_ops *ops;
112};
113
114struct srcimp_rsc_ops {
115 int (*map)(struct srcimp *srcimp, struct src *user, struct rsc *input);
116 int (*unmap)(struct srcimp *srcimp);
117};
118
119/* Define SRCIMP resource request description info */
120struct srcimp_desc {
121 unsigned int msr;
122};
123
124struct srcimp_mgr {
125 struct rsc_mgr mgr; /* Basic resource manager info */
126 spinlock_t mgr_lock;
127 spinlock_t imap_lock;
128 struct list_head imappers;
129 struct imapper *init_imap;
130 unsigned int init_imap_added;
131
132 /* request srcimp resource */
133 int (*get_srcimp)(struct srcimp_mgr *mgr,
134 const struct srcimp_desc *desc,
135 struct srcimp **rsrcimp);
136 /* return srcimp resource */
137 int (*put_srcimp)(struct srcimp_mgr *mgr, struct srcimp *srcimp);
138 int (*imap_add)(struct srcimp_mgr *mgr, struct imapper *entry);
139 int (*imap_delete)(struct srcimp_mgr *mgr, struct imapper *entry);
140};
141
142/* Constructor and destructor of SRC resource manager */
143int src_mgr_create(void *hw, struct src_mgr **rsrc_mgr);
144int src_mgr_destroy(struct src_mgr *src_mgr);
145/* Constructor and destructor of SRCIMP resource manager */
146int srcimp_mgr_create(void *hw, struct srcimp_mgr **rsrc_mgr);
147int srcimp_mgr_destroy(struct srcimp_mgr *srcimp_mgr);
148
149#endif /* CTSRC_H */
diff --git a/sound/pci/ctxfi/cttimer.c b/sound/pci/ctxfi/cttimer.c
new file mode 100644
index 00000000000..779c6c3591a
--- /dev/null
+++ b/sound/pci/ctxfi/cttimer.c
@@ -0,0 +1,441 @@
1/*
2 * PCM timer handling on ctxfi
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 */
8
9#include <linux/slab.h>
10#include <linux/math64.h>
11#include <linux/moduleparam.h>
12#include <sound/core.h>
13#include <sound/pcm.h>
14#include "ctatc.h"
15#include "cthardware.h"
16#include "cttimer.h"
17
18static int use_system_timer;
19MODULE_PARM_DESC(use_system_timer, "Foce to use system-timer");
20module_param(use_system_timer, bool, S_IRUGO);
21
22struct ct_timer_ops {
23 void (*init)(struct ct_timer_instance *);
24 void (*prepare)(struct ct_timer_instance *);
25 void (*start)(struct ct_timer_instance *);
26 void (*stop)(struct ct_timer_instance *);
27 void (*free_instance)(struct ct_timer_instance *);
28 void (*interrupt)(struct ct_timer *);
29 void (*free_global)(struct ct_timer *);
30};
31
32/* timer instance -- assigned to each PCM stream */
33struct ct_timer_instance {
34 spinlock_t lock;
35 struct ct_timer *timer_base;
36 struct ct_atc_pcm *apcm;
37 struct snd_pcm_substream *substream;
38 struct timer_list timer;
39 struct list_head instance_list;
40 struct list_head running_list;
41 unsigned int position;
42 unsigned int frag_count;
43 unsigned int running:1;
44 unsigned int need_update:1;
45};
46
47/* timer instance manager */
48struct ct_timer {
49 spinlock_t lock; /* global timer lock (for xfitimer) */
50 spinlock_t list_lock; /* lock for instance list */
51 struct ct_atc *atc;
52 struct ct_timer_ops *ops;
53 struct list_head instance_head;
54 struct list_head running_head;
55 unsigned int wc; /* current wallclock */
56 unsigned int irq_handling:1; /* in IRQ handling */
57 unsigned int reprogram:1; /* need to reprogram the internval */
58 unsigned int running:1; /* global timer running */
59};
60
61
62/*
63 * system-timer-based updates
64 */
65
66static void ct_systimer_callback(unsigned long data)
67{
68 struct ct_timer_instance *ti = (struct ct_timer_instance *)data;
69 struct snd_pcm_substream *substream = ti->substream;
70 struct snd_pcm_runtime *runtime = substream->runtime;
71 struct ct_atc_pcm *apcm = ti->apcm;
72 unsigned int period_size = runtime->period_size;
73 unsigned int buffer_size = runtime->buffer_size;
74 unsigned long flags;
75 unsigned int position, dist, interval;
76
77 position = substream->ops->pointer(substream);
78 dist = (position + buffer_size - ti->position) % buffer_size;
79 if (dist >= period_size ||
80 position / period_size != ti->position / period_size) {
81 apcm->interrupt(apcm);
82 ti->position = position;
83 }
84 /* Add extra HZ*5/1000 to avoid overrun issue when recording
85 * at 8kHz in 8-bit format or at 88kHz in 24-bit format. */
86 interval = ((period_size - (position % period_size))
87 * HZ + (runtime->rate - 1)) / runtime->rate + HZ * 5 / 1000;
88 spin_lock_irqsave(&ti->lock, flags);
89 if (ti->running)
90 mod_timer(&ti->timer, jiffies + interval);
91 spin_unlock_irqrestore(&ti->lock, flags);
92}
93
94static void ct_systimer_init(struct ct_timer_instance *ti)
95{
96 setup_timer(&ti->timer, ct_systimer_callback,
97 (unsigned long)ti);
98}
99
100static void ct_systimer_start(struct ct_timer_instance *ti)
101{
102 struct snd_pcm_runtime *runtime = ti->substream->runtime;
103 unsigned long flags;
104
105 spin_lock_irqsave(&ti->lock, flags);
106 ti->running = 1;
107 mod_timer(&ti->timer,
108 jiffies + (runtime->period_size * HZ +
109 (runtime->rate - 1)) / runtime->rate);
110 spin_unlock_irqrestore(&ti->lock, flags);
111}
112
113static void ct_systimer_stop(struct ct_timer_instance *ti)
114{
115 unsigned long flags;
116
117 spin_lock_irqsave(&ti->lock, flags);
118 ti->running = 0;
119 del_timer(&ti->timer);
120 spin_unlock_irqrestore(&ti->lock, flags);
121}
122
123static void ct_systimer_prepare(struct ct_timer_instance *ti)
124{
125 ct_systimer_stop(ti);
126 try_to_del_timer_sync(&ti->timer);
127}
128
129#define ct_systimer_free ct_systimer_prepare
130
131static struct ct_timer_ops ct_systimer_ops = {
132 .init = ct_systimer_init,
133 .free_instance = ct_systimer_free,
134 .prepare = ct_systimer_prepare,
135 .start = ct_systimer_start,
136 .stop = ct_systimer_stop,
137};
138
139
140/*
141 * Handling multiple streams using a global emu20k1 timer irq
142 */
143
144#define CT_TIMER_FREQ 48000
145#define MIN_TICKS 1
146#define MAX_TICKS ((1 << 13) - 1)
147
148static void ct_xfitimer_irq_rearm(struct ct_timer *atimer, int ticks)
149{
150 struct hw *hw = atimer->atc->hw;
151 if (ticks > MAX_TICKS)
152 ticks = MAX_TICKS;
153 hw->set_timer_tick(hw, ticks);
154 if (!atimer->running)
155 hw->set_timer_irq(hw, 1);
156 atimer->running = 1;
157}
158
159static void ct_xfitimer_irq_stop(struct ct_timer *atimer)
160{
161 if (atimer->running) {
162 struct hw *hw = atimer->atc->hw;
163 hw->set_timer_irq(hw, 0);
164 hw->set_timer_tick(hw, 0);
165 atimer->running = 0;
166 }
167}
168
169static inline unsigned int ct_xfitimer_get_wc(struct ct_timer *atimer)
170{
171 struct hw *hw = atimer->atc->hw;
172 return hw->get_wc(hw);
173}
174
175/*
176 * reprogram the timer interval;
177 * checks the running instance list and determines the next timer interval.
178 * also updates the each stream position, returns the number of streams
179 * to call snd_pcm_period_elapsed() appropriately
180 *
181 * call this inside the lock and irq disabled
182 */
183static int ct_xfitimer_reprogram(struct ct_timer *atimer)
184{
185 struct ct_timer_instance *ti;
186 unsigned int min_intr = (unsigned int)-1;
187 int updates = 0;
188 unsigned int wc, diff;
189
190 if (list_empty(&atimer->running_head)) {
191 ct_xfitimer_irq_stop(atimer);
192 atimer->reprogram = 0; /* clear flag */
193 return 0;
194 }
195
196 wc = ct_xfitimer_get_wc(atimer);
197 diff = wc - atimer->wc;
198 atimer->wc = wc;
199 list_for_each_entry(ti, &atimer->running_head, running_list) {
200 if (ti->frag_count > diff)
201 ti->frag_count -= diff;
202 else {
203 unsigned int pos;
204 unsigned int period_size, rate;
205
206 period_size = ti->substream->runtime->period_size;
207 rate = ti->substream->runtime->rate;
208 pos = ti->substream->ops->pointer(ti->substream);
209 if (pos / period_size != ti->position / period_size) {
210 ti->need_update = 1;
211 ti->position = pos;
212 updates++;
213 }
214 pos %= period_size;
215 pos = period_size - pos;
216 ti->frag_count = div_u64((u64)pos * CT_TIMER_FREQ +
217 rate - 1, rate);
218 }
219 if (ti->frag_count < min_intr)
220 min_intr = ti->frag_count;
221 }
222
223 if (min_intr < MIN_TICKS)
224 min_intr = MIN_TICKS;
225 ct_xfitimer_irq_rearm(atimer, min_intr);
226 atimer->reprogram = 0; /* clear flag */
227 return updates;
228}
229
230/* look through the instance list and call period_elapsed if needed */
231static void ct_xfitimer_check_period(struct ct_timer *atimer)
232{
233 struct ct_timer_instance *ti;
234 unsigned long flags;
235
236 spin_lock_irqsave(&atimer->list_lock, flags);
237 list_for_each_entry(ti, &atimer->instance_head, instance_list) {
238 if (ti->need_update) {
239 ti->need_update = 0;
240 ti->apcm->interrupt(ti->apcm);
241 }
242 }
243 spin_unlock_irqrestore(&atimer->list_lock, flags);
244}
245
246/* Handle timer-interrupt */
247static void ct_xfitimer_callback(struct ct_timer *atimer)
248{
249 int update;
250 unsigned long flags;
251
252 spin_lock_irqsave(&atimer->lock, flags);
253 atimer->irq_handling = 1;
254 do {
255 update = ct_xfitimer_reprogram(atimer);
256 spin_unlock(&atimer->lock);
257 if (update)
258 ct_xfitimer_check_period(atimer);
259 spin_lock(&atimer->lock);
260 } while (atimer->reprogram);
261 atimer->irq_handling = 0;
262 spin_unlock_irqrestore(&atimer->lock, flags);
263}
264
265static void ct_xfitimer_prepare(struct ct_timer_instance *ti)
266{
267 ti->frag_count = ti->substream->runtime->period_size;
268 ti->need_update = 0;
269}
270
271
272/* start/stop the timer */
273static void ct_xfitimer_update(struct ct_timer *atimer)
274{
275 unsigned long flags;
276 int update;
277
278 spin_lock_irqsave(&atimer->lock, flags);
279 if (atimer->irq_handling) {
280 /* reached from IRQ handler; let it handle later */
281 atimer->reprogram = 1;
282 spin_unlock_irqrestore(&atimer->lock, flags);
283 return;
284 }
285
286 ct_xfitimer_irq_stop(atimer);
287 update = ct_xfitimer_reprogram(atimer);
288 spin_unlock_irqrestore(&atimer->lock, flags);
289 if (update)
290 ct_xfitimer_check_period(atimer);
291}
292
293static void ct_xfitimer_start(struct ct_timer_instance *ti)
294{
295 struct ct_timer *atimer = ti->timer_base;
296 unsigned long flags;
297
298 spin_lock_irqsave(&atimer->lock, flags);
299 if (list_empty(&ti->running_list))
300 atimer->wc = ct_xfitimer_get_wc(atimer);
301 list_add(&ti->running_list, &atimer->running_head);
302 spin_unlock_irqrestore(&atimer->lock, flags);
303 ct_xfitimer_update(atimer);
304}
305
306static void ct_xfitimer_stop(struct ct_timer_instance *ti)
307{
308 struct ct_timer *atimer = ti->timer_base;
309 unsigned long flags;
310
311 spin_lock_irqsave(&atimer->lock, flags);
312 list_del_init(&ti->running_list);
313 ti->need_update = 0;
314 spin_unlock_irqrestore(&atimer->lock, flags);
315 ct_xfitimer_update(atimer);
316}
317
318static void ct_xfitimer_free_global(struct ct_timer *atimer)
319{
320 ct_xfitimer_irq_stop(atimer);
321}
322
323static struct ct_timer_ops ct_xfitimer_ops = {
324 .prepare = ct_xfitimer_prepare,
325 .start = ct_xfitimer_start,
326 .stop = ct_xfitimer_stop,
327 .interrupt = ct_xfitimer_callback,
328 .free_global = ct_xfitimer_free_global,
329};
330
331/*
332 * timer instance
333 */
334
335struct ct_timer_instance *
336ct_timer_instance_new(struct ct_timer *atimer, struct ct_atc_pcm *apcm)
337{
338 struct ct_timer_instance *ti;
339
340 ti = kzalloc(sizeof(*ti), GFP_KERNEL);
341 if (!ti)
342 return NULL;
343 spin_lock_init(&ti->lock);
344 INIT_LIST_HEAD(&ti->instance_list);
345 INIT_LIST_HEAD(&ti->running_list);
346 ti->timer_base = atimer;
347 ti->apcm = apcm;
348 ti->substream = apcm->substream;
349 if (atimer->ops->init)
350 atimer->ops->init(ti);
351
352 spin_lock_irq(&atimer->list_lock);
353 list_add(&ti->instance_list, &atimer->instance_head);
354 spin_unlock_irq(&atimer->list_lock);
355
356 return ti;
357}
358
359void ct_timer_prepare(struct ct_timer_instance *ti)
360{
361 if (ti->timer_base->ops->prepare)
362 ti->timer_base->ops->prepare(ti);
363 ti->position = 0;
364 ti->running = 0;
365}
366
367void ct_timer_start(struct ct_timer_instance *ti)
368{
369 struct ct_timer *atimer = ti->timer_base;
370 atimer->ops->start(ti);
371}
372
373void ct_timer_stop(struct ct_timer_instance *ti)
374{
375 struct ct_timer *atimer = ti->timer_base;
376 atimer->ops->stop(ti);
377}
378
379void ct_timer_instance_free(struct ct_timer_instance *ti)
380{
381 struct ct_timer *atimer = ti->timer_base;
382
383 atimer->ops->stop(ti); /* to be sure */
384 if (atimer->ops->free_instance)
385 atimer->ops->free_instance(ti);
386
387 spin_lock_irq(&atimer->list_lock);
388 list_del(&ti->instance_list);
389 spin_unlock_irq(&atimer->list_lock);
390
391 kfree(ti);
392}
393
394/*
395 * timer manager
396 */
397
398static void ct_timer_interrupt(void *data, unsigned int status)
399{
400 struct ct_timer *timer = data;
401
402 /* Interval timer interrupt */
403 if ((status & IT_INT) && timer->ops->interrupt)
404 timer->ops->interrupt(timer);
405}
406
407struct ct_timer *ct_timer_new(struct ct_atc *atc)
408{
409 struct ct_timer *atimer;
410 struct hw *hw;
411
412 atimer = kzalloc(sizeof(*atimer), GFP_KERNEL);
413 if (!atimer)
414 return NULL;
415 spin_lock_init(&atimer->lock);
416 spin_lock_init(&atimer->list_lock);
417 INIT_LIST_HEAD(&atimer->instance_head);
418 INIT_LIST_HEAD(&atimer->running_head);
419 atimer->atc = atc;
420 hw = atc->hw;
421 if (!use_system_timer && hw->set_timer_irq) {
422 snd_printd(KERN_INFO "ctxfi: Use xfi-native timer\n");
423 atimer->ops = &ct_xfitimer_ops;
424 hw->irq_callback_data = atimer;
425 hw->irq_callback = ct_timer_interrupt;
426 } else {
427 snd_printd(KERN_INFO "ctxfi: Use system timer\n");
428 atimer->ops = &ct_systimer_ops;
429 }
430 return atimer;
431}
432
433void ct_timer_free(struct ct_timer *atimer)
434{
435 struct hw *hw = atimer->atc->hw;
436 hw->irq_callback = NULL;
437 if (atimer->ops->free_global)
438 atimer->ops->free_global(atimer);
439 kfree(atimer);
440}
441
diff --git a/sound/pci/ctxfi/cttimer.h b/sound/pci/ctxfi/cttimer.h
new file mode 100644
index 00000000000..97934822929
--- /dev/null
+++ b/sound/pci/ctxfi/cttimer.h
@@ -0,0 +1,29 @@
1/*
2 * Timer handling
3 */
4
5#ifndef __CTTIMER_H
6#define __CTTIMER_H
7
8#include <linux/spinlock.h>
9#include <linux/timer.h>
10#include <linux/list.h>
11
12struct snd_pcm_substream;
13struct ct_atc;
14struct ct_atc_pcm;
15
16struct ct_timer;
17struct ct_timer_instance;
18
19struct ct_timer *ct_timer_new(struct ct_atc *atc);
20void ct_timer_free(struct ct_timer *atimer);
21
22struct ct_timer_instance *
23ct_timer_instance_new(struct ct_timer *atimer, struct ct_atc_pcm *apcm);
24void ct_timer_instance_free(struct ct_timer_instance *ti);
25void ct_timer_start(struct ct_timer_instance *ti);
26void ct_timer_stop(struct ct_timer_instance *ti);
27void ct_timer_prepare(struct ct_timer_instance *ti);
28
29#endif /* __CTTIMER_H */
diff --git a/sound/pci/ctxfi/ctvmem.c b/sound/pci/ctxfi/ctvmem.c
new file mode 100644
index 00000000000..67665a7e43c
--- /dev/null
+++ b/sound/pci/ctxfi/ctvmem.c
@@ -0,0 +1,250 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File ctvmem.c
9 *
10 * @Brief
11 * This file contains the implementation of virtual memory management object
12 * for card device.
13 *
14 * @Author Liu Chun
15 * @Date Apr 1 2008
16 */
17
18#include "ctvmem.h"
19#include <linux/slab.h>
20#include <linux/mm.h>
21#include <linux/io.h>
22#include <sound/pcm.h>
23
24#define CT_PTES_PER_PAGE (CT_PAGE_SIZE / sizeof(void *))
25#define CT_ADDRS_PER_PAGE (CT_PTES_PER_PAGE * CT_PAGE_SIZE)
26
27/* *
28 * Find or create vm block based on requested @size.
29 * @size must be page aligned.
30 * */
31static struct ct_vm_block *
32get_vm_block(struct ct_vm *vm, unsigned int size)
33{
34 struct ct_vm_block *block = NULL, *entry;
35 struct list_head *pos;
36
37 size = CT_PAGE_ALIGN(size);
38 if (size > vm->size) {
39 printk(KERN_ERR "ctxfi: Fail! No sufficient device virtural "
40 "memory space available!\n");
41 return NULL;
42 }
43
44 mutex_lock(&vm->lock);
45 list_for_each(pos, &vm->unused) {
46 entry = list_entry(pos, struct ct_vm_block, list);
47 if (entry->size >= size)
48 break; /* found a block that is big enough */
49 }
50 if (pos == &vm->unused)
51 goto out;
52
53 if (entry->size == size) {
54 /* Move the vm node from unused list to used list directly */
55 list_del(&entry->list);
56 list_add(&entry->list, &vm->used);
57 vm->size -= size;
58 block = entry;
59 goto out;
60 }
61
62 block = kzalloc(sizeof(*block), GFP_KERNEL);
63 if (NULL == block)
64 goto out;
65
66 block->addr = entry->addr;
67 block->size = size;
68 list_add(&block->list, &vm->used);
69 entry->addr += size;
70 entry->size -= size;
71 vm->size -= size;
72
73 out:
74 mutex_unlock(&vm->lock);
75 return block;
76}
77
78static void put_vm_block(struct ct_vm *vm, struct ct_vm_block *block)
79{
80 struct ct_vm_block *entry, *pre_ent;
81 struct list_head *pos, *pre;
82
83 block->size = CT_PAGE_ALIGN(block->size);
84
85 mutex_lock(&vm->lock);
86 list_del(&block->list);
87 vm->size += block->size;
88
89 list_for_each(pos, &vm->unused) {
90 entry = list_entry(pos, struct ct_vm_block, list);
91 if (entry->addr >= (block->addr + block->size))
92 break; /* found a position */
93 }
94 if (pos == &vm->unused) {
95 list_add_tail(&block->list, &vm->unused);
96 entry = block;
97 } else {
98 if ((block->addr + block->size) == entry->addr) {
99 entry->addr = block->addr;
100 entry->size += block->size;
101 kfree(block);
102 } else {
103 __list_add(&block->list, pos->prev, pos);
104 entry = block;
105 }
106 }
107
108 pos = &entry->list;
109 pre = pos->prev;
110 while (pre != &vm->unused) {
111 entry = list_entry(pos, struct ct_vm_block, list);
112 pre_ent = list_entry(pre, struct ct_vm_block, list);
113 if ((pre_ent->addr + pre_ent->size) > entry->addr)
114 break;
115
116 pre_ent->size += entry->size;
117 list_del(pos);
118 kfree(entry);
119 pos = pre;
120 pre = pos->prev;
121 }
122 mutex_unlock(&vm->lock);
123}
124
125/* Map host addr (kmalloced/vmalloced) to device logical addr. */
126static struct ct_vm_block *
127ct_vm_map(struct ct_vm *vm, struct snd_pcm_substream *substream, int size)
128{
129 struct ct_vm_block *block;
130 unsigned int pte_start;
131 unsigned i, pages;
132 unsigned long *ptp;
133
134 block = get_vm_block(vm, size);
135 if (block == NULL) {
136 printk(KERN_ERR "ctxfi: No virtual memory block that is big "
137 "enough to allocate!\n");
138 return NULL;
139 }
140
141 ptp = vm->ptp[0];
142 pte_start = (block->addr >> CT_PAGE_SHIFT);
143 pages = block->size >> CT_PAGE_SHIFT;
144 for (i = 0; i < pages; i++) {
145 unsigned long addr;
146 addr = snd_pcm_sgbuf_get_addr(substream, i << CT_PAGE_SHIFT);
147 ptp[pte_start + i] = addr;
148 }
149
150 block->size = size;
151 return block;
152}
153
154static void ct_vm_unmap(struct ct_vm *vm, struct ct_vm_block *block)
155{
156 /* do unmapping */
157 put_vm_block(vm, block);
158}
159
160/* *
161 * return the host (kmalloced) addr of the @index-th device
162 * page talbe page on success, or NULL on failure.
163 * The first returned NULL indicates the termination.
164 * */
165static void *
166ct_get_ptp_virt(struct ct_vm *vm, int index)
167{
168 void *addr;
169
170 addr = (index >= CT_PTP_NUM) ? NULL : vm->ptp[index];
171
172 return addr;
173}
174
175int ct_vm_create(struct ct_vm **rvm)
176{
177 struct ct_vm *vm;
178 struct ct_vm_block *block;
179 int i;
180
181 *rvm = NULL;
182
183 vm = kzalloc(sizeof(*vm), GFP_KERNEL);
184 if (NULL == vm)
185 return -ENOMEM;
186
187 mutex_init(&vm->lock);
188
189 /* Allocate page table pages */
190 for (i = 0; i < CT_PTP_NUM; i++) {
191 vm->ptp[i] = kmalloc(PAGE_SIZE, GFP_KERNEL);
192 if (NULL == vm->ptp[i])
193 break;
194 }
195 if (!i) {
196 /* no page table pages are allocated */
197 kfree(vm);
198 return -ENOMEM;
199 }
200 vm->size = CT_ADDRS_PER_PAGE * i;
201 /* Initialise remaining ptps */
202 for (; i < CT_PTP_NUM; i++)
203 vm->ptp[i] = NULL;
204
205 vm->map = ct_vm_map;
206 vm->unmap = ct_vm_unmap;
207 vm->get_ptp_virt = ct_get_ptp_virt;
208 INIT_LIST_HEAD(&vm->unused);
209 INIT_LIST_HEAD(&vm->used);
210 block = kzalloc(sizeof(*block), GFP_KERNEL);
211 if (NULL != block) {
212 block->addr = 0;
213 block->size = vm->size;
214 list_add(&block->list, &vm->unused);
215 }
216
217 *rvm = vm;
218 return 0;
219}
220
221/* The caller must ensure no mapping pages are being used
222 * by hardware before calling this function */
223void ct_vm_destroy(struct ct_vm *vm)
224{
225 int i;
226 struct list_head *pos;
227 struct ct_vm_block *entry;
228
229 /* free used and unused list nodes */
230 while (!list_empty(&vm->used)) {
231 pos = vm->used.next;
232 list_del(pos);
233 entry = list_entry(pos, struct ct_vm_block, list);
234 kfree(entry);
235 }
236 while (!list_empty(&vm->unused)) {
237 pos = vm->unused.next;
238 list_del(pos);
239 entry = list_entry(pos, struct ct_vm_block, list);
240 kfree(entry);
241 }
242
243 /* free allocated page table pages */
244 for (i = 0; i < CT_PTP_NUM; i++)
245 kfree(vm->ptp[i]);
246
247 vm->size = 0;
248
249 kfree(vm);
250}
diff --git a/sound/pci/ctxfi/ctvmem.h b/sound/pci/ctxfi/ctvmem.h
new file mode 100644
index 00000000000..01e4fd0386a
--- /dev/null
+++ b/sound/pci/ctxfi/ctvmem.h
@@ -0,0 +1,61 @@
1/**
2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
3 *
4 * This source file is released under GPL v2 license (no other versions).
5 * See the COPYING file included in the main directory of this source
6 * distribution for the license terms and conditions.
7 *
8 * @File ctvmem.h
9 *
10 * @Brief
11 * This file contains the definition of virtual memory management object
12 * for card device.
13 *
14 * @Author Liu Chun
15 * @Date Mar 28 2008
16 */
17
18#ifndef CTVMEM_H
19#define CTVMEM_H
20
21#define CT_PTP_NUM 1 /* num of device page table pages */
22
23#include <linux/mutex.h>
24#include <linux/list.h>
25
26/* The chip can handle the page table of 4k pages
27 * (emu20k1 can handle even 8k pages, but we don't use it right now)
28 */
29#define CT_PAGE_SIZE 4096
30#define CT_PAGE_SHIFT 12
31#define CT_PAGE_MASK (~(PAGE_SIZE - 1))
32#define CT_PAGE_ALIGN(addr) ALIGN(addr, CT_PAGE_SIZE)
33
34struct ct_vm_block {
35 unsigned int addr; /* starting logical addr of this block */
36 unsigned int size; /* size of this device virtual mem block */
37 struct list_head list;
38};
39
40struct snd_pcm_substream;
41
42/* Virtual memory management object for card device */
43struct ct_vm {
44 void *ptp[CT_PTP_NUM]; /* Device page table pages */
45 unsigned int size; /* Available addr space in bytes */
46 struct list_head unused; /* List of unused blocks */
47 struct list_head used; /* List of used blocks */
48 struct mutex lock;
49
50 /* Map host addr (kmalloced/vmalloced) to device logical addr. */
51 struct ct_vm_block *(*map)(struct ct_vm *, struct snd_pcm_substream *,
52 int size);
53 /* Unmap device logical addr area. */
54 void (*unmap)(struct ct_vm *, struct ct_vm_block *block);
55 void *(*get_ptp_virt)(struct ct_vm *vm, int index);
56};
57
58int ct_vm_create(struct ct_vm **rvm);
59void ct_vm_destroy(struct ct_vm *vm);
60
61#endif /* CTVMEM_H */
diff --git a/sound/pci/ctxfi/xfi.c b/sound/pci/ctxfi/xfi.c
new file mode 100644
index 00000000000..2d3dd89af15
--- /dev/null
+++ b/sound/pci/ctxfi/xfi.c
@@ -0,0 +1,142 @@
1/*
2 * xfi linux driver.
3 *
4 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
5 *
6 * This source file is released under GPL v2 license (no other versions).
7 * See the COPYING file included in the main directory of this source
8 * distribution for the license terms and conditions.
9 */
10
11#include <linux/init.h>
12#include <linux/pci.h>
13#include <linux/moduleparam.h>
14#include <linux/pci_ids.h>
15#include <sound/core.h>
16#include <sound/initval.h>
17#include "ctatc.h"
18#include "cthardware.h"
19
20MODULE_AUTHOR("Creative Technology Ltd");
21MODULE_DESCRIPTION("X-Fi driver version 1.03");
22MODULE_LICENSE("GPL v2");
23MODULE_SUPPORTED_DEVICE("{{Creative Labs, Sound Blaster X-Fi}");
24
25static unsigned int reference_rate = 48000;
26static unsigned int multiple = 2;
27MODULE_PARM_DESC(reference_rate, "Reference rate (default=48000)");
28module_param(reference_rate, uint, S_IRUGO);
29MODULE_PARM_DESC(multiple, "Rate multiplier (default=2)");
30module_param(multiple, uint, S_IRUGO);
31
32static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
33static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
34static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
35
36module_param_array(index, int, NULL, 0444);
37MODULE_PARM_DESC(index, "Index value for Creative X-Fi driver");
38module_param_array(id, charp, NULL, 0444);
39MODULE_PARM_DESC(id, "ID string for Creative X-Fi driver");
40module_param_array(enable, bool, NULL, 0444);
41MODULE_PARM_DESC(enable, "Enable Creative X-Fi driver");
42
43static struct pci_device_id ct_pci_dev_ids[] = {
44 /* only X-Fi is supported, so... */
45 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_20K1),
46 .driver_data = ATC20K1,
47 },
48 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_20K2),
49 .driver_data = ATC20K2,
50 },
51 { 0, }
52};
53MODULE_DEVICE_TABLE(pci, ct_pci_dev_ids);
54
55static int __devinit
56ct_card_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
57{
58 static int dev;
59 struct snd_card *card;
60 struct ct_atc *atc;
61 int err;
62
63 if (dev >= SNDRV_CARDS)
64 return -ENODEV;
65
66 if (!enable[dev]) {
67 dev++;
68 return -ENOENT;
69 }
70 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
71 if (err)
72 return err;
73 if ((reference_rate != 48000) && (reference_rate != 44100)) {
74 printk(KERN_ERR "ctxfi: Invalid reference_rate value %u!!!\n",
75 reference_rate);
76 printk(KERN_ERR "ctxfi: The valid values for reference_rate "
77 "are 48000 and 44100, Value 48000 is assumed.\n");
78 reference_rate = 48000;
79 }
80 if ((multiple != 1) && (multiple != 2)) {
81 printk(KERN_ERR "ctxfi: Invalid multiple value %u!!!\n",
82 multiple);
83 printk(KERN_ERR "ctxfi: The valid values for multiple are "
84 "1 and 2, Value 2 is assumed.\n");
85 multiple = 2;
86 }
87 err = ct_atc_create(card, pci, reference_rate, multiple,
88 pci_id->driver_data, &atc);
89 if (err < 0)
90 goto error;
91
92 card->private_data = atc;
93
94 /* Create alsa devices supported by this card */
95 err = ct_atc_create_alsa_devs(atc);
96 if (err < 0)
97 goto error;
98
99 strcpy(card->driver, "SB-XFi");
100 strcpy(card->shortname, "Creative X-Fi");
101 snprintf(card->longname, sizeof(card->longname), "%s %s %s",
102 card->shortname, atc->chip_name, atc->model_name);
103
104 err = snd_card_register(card);
105 if (err < 0)
106 goto error;
107
108 pci_set_drvdata(pci, card);
109 dev++;
110
111 return 0;
112
113error:
114 snd_card_free(card);
115 return err;
116}
117
118static void __devexit ct_card_remove(struct pci_dev *pci)
119{
120 snd_card_free(pci_get_drvdata(pci));
121 pci_set_drvdata(pci, NULL);
122}
123
124static struct pci_driver ct_driver = {
125 .name = "SB-XFi",
126 .id_table = ct_pci_dev_ids,
127 .probe = ct_card_probe,
128 .remove = __devexit_p(ct_card_remove),
129};
130
131static int __init ct_card_init(void)
132{
133 return pci_register_driver(&ct_driver);
134}
135
136static void __exit ct_card_exit(void)
137{
138 pci_unregister_driver(&ct_driver);
139}
140
141module_init(ct_card_init)
142module_exit(ct_card_exit)
diff --git a/sound/pci/echoaudio/indigodjx.c b/sound/pci/echoaudio/indigodjx.c
index 3482ef69f49..2e44316530a 100644
--- a/sound/pci/echoaudio/indigodjx.c
+++ b/sound/pci/echoaudio/indigodjx.c
@@ -88,6 +88,7 @@ static struct snd_pcm_hardware pcm_hardware_skel = {
88 .rates = SNDRV_PCM_RATE_32000 | 88 .rates = SNDRV_PCM_RATE_32000 |
89 SNDRV_PCM_RATE_44100 | 89 SNDRV_PCM_RATE_44100 |
90 SNDRV_PCM_RATE_48000 | 90 SNDRV_PCM_RATE_48000 |
91 SNDRV_PCM_RATE_64000 |
91 SNDRV_PCM_RATE_88200 | 92 SNDRV_PCM_RATE_88200 |
92 SNDRV_PCM_RATE_96000, 93 SNDRV_PCM_RATE_96000,
93 .rate_min = 32000, 94 .rate_min = 32000,
diff --git a/sound/pci/echoaudio/indigoiox.c b/sound/pci/echoaudio/indigoiox.c
index aebee27a40f..eb3819f9654 100644
--- a/sound/pci/echoaudio/indigoiox.c
+++ b/sound/pci/echoaudio/indigoiox.c
@@ -89,6 +89,7 @@ static struct snd_pcm_hardware pcm_hardware_skel = {
89 .rates = SNDRV_PCM_RATE_32000 | 89 .rates = SNDRV_PCM_RATE_32000 |
90 SNDRV_PCM_RATE_44100 | 90 SNDRV_PCM_RATE_44100 |
91 SNDRV_PCM_RATE_48000 | 91 SNDRV_PCM_RATE_48000 |
92 SNDRV_PCM_RATE_64000 |
92 SNDRV_PCM_RATE_88200 | 93 SNDRV_PCM_RATE_88200 |
93 SNDRV_PCM_RATE_96000, 94 SNDRV_PCM_RATE_96000,
94 .rate_min = 32000, 95 .rate_min = 32000,
diff --git a/sound/pci/emu10k1/Makefile b/sound/pci/emu10k1/Makefile
index cf2d5636d8b..fc5591e7777 100644
--- a/sound/pci/emu10k1/Makefile
+++ b/sound/pci/emu10k1/Makefile
@@ -9,15 +9,7 @@ snd-emu10k1-objs := emu10k1.o emu10k1_main.o \
9snd-emu10k1-synth-objs := emu10k1_synth.o emu10k1_callback.o emu10k1_patch.o 9snd-emu10k1-synth-objs := emu10k1_synth.o emu10k1_callback.o emu10k1_patch.o
10snd-emu10k1x-objs := emu10k1x.o 10snd-emu10k1x-objs := emu10k1x.o
11 11
12#
13# this function returns:
14# "m" - CONFIG_SND_SEQUENCER is m
15# <empty string> - CONFIG_SND_SEQUENCER is undefined
16# otherwise parameter #1 value
17#
18sequencer = $(if $(subst y,,$(CONFIG_SND_SEQUENCER)),$(if $(1),m),$(if $(CONFIG_SND_SEQUENCER),$(1)))
19
20# Toplevel Module Dependency 12# Toplevel Module Dependency
21obj-$(CONFIG_SND_EMU10K1) += snd-emu10k1.o 13obj-$(CONFIG_SND_EMU10K1) += snd-emu10k1.o
22obj-$(call sequencer,$(CONFIG_SND_EMU10K1)) += snd-emu10k1-synth.o 14obj-$(CONFIG_SND_EMU10K1_SEQ) += snd-emu10k1-synth.o
23obj-$(CONFIG_SND_EMU10K1X) += snd-emu10k1x.o 15obj-$(CONFIG_SND_EMU10K1X) += snd-emu10k1x.o
diff --git a/sound/pci/emu10k1/emu10k1x.c b/sound/pci/emu10k1/emu10k1x.c
index 1970f0e70f3..4d3ad793e98 100644
--- a/sound/pci/emu10k1/emu10k1x.c
+++ b/sound/pci/emu10k1/emu10k1x.c
@@ -858,7 +858,6 @@ static int __devinit snd_emu10k1x_pcm(struct emu10k1x *emu, int device, struct s
858 } 858 }
859 859
860 pcm->info_flags = 0; 860 pcm->info_flags = 0;
861 pcm->dev_subclass = SNDRV_PCM_SUBCLASS_GENERIC_MIX;
862 switch(device) { 861 switch(device) {
863 case 0: 862 case 0:
864 strcpy(pcm->name, "EMU10K1X Front"); 863 strcpy(pcm->name, "EMU10K1X Front");
diff --git a/sound/pci/emu10k1/emupcm.c b/sound/pci/emu10k1/emupcm.c
index 78f62fd404c..55b83ef73c6 100644
--- a/sound/pci/emu10k1/emupcm.c
+++ b/sound/pci/emu10k1/emupcm.c
@@ -1736,7 +1736,7 @@ static struct snd_pcm_hardware snd_emu10k1_fx8010_playback =
1736 .buffer_bytes_max = (128*1024), 1736 .buffer_bytes_max = (128*1024),
1737 .period_bytes_min = 1024, 1737 .period_bytes_min = 1024,
1738 .period_bytes_max = (128*1024), 1738 .period_bytes_max = (128*1024),
1739 .periods_min = 1, 1739 .periods_min = 2,
1740 .periods_max = 1024, 1740 .periods_max = 1024,
1741 .fifo_size = 0, 1741 .fifo_size = 0,
1742}; 1742};
diff --git a/sound/pci/emu10k1/io.c b/sound/pci/emu10k1/io.c
index 4bfc31d1b28..c1a5aa15af8 100644
--- a/sound/pci/emu10k1/io.c
+++ b/sound/pci/emu10k1/io.c
@@ -490,7 +490,7 @@ void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait)
490 if (newtime != curtime) 490 if (newtime != curtime)
491 break; 491 break;
492 } 492 }
493 if (count >= 16384) 493 if (count > 16384)
494 break; 494 break;
495 curtime = newtime; 495 curtime = newtime;
496 } 496 }
diff --git a/sound/pci/ice1712/Makefile b/sound/pci/ice1712/Makefile
index f99fe089495..536eae2ccf9 100644
--- a/sound/pci/ice1712/Makefile
+++ b/sound/pci/ice1712/Makefile
@@ -5,7 +5,7 @@
5 5
6snd-ice17xx-ak4xxx-objs := ak4xxx.o 6snd-ice17xx-ak4xxx-objs := ak4xxx.o
7snd-ice1712-objs := ice1712.o delta.o hoontech.o ews.o 7snd-ice1712-objs := ice1712.o delta.o hoontech.o ews.o
8snd-ice1724-objs := ice1724.o amp.o revo.o aureon.o vt1720_mobo.o pontis.o prodigy192.o prodigy_hifi.o juli.o phase.o wtm.o se.o 8snd-ice1724-objs := ice1724.o amp.o revo.o aureon.o vt1720_mobo.o pontis.o prodigy192.o prodigy_hifi.o juli.o phase.o wtm.o se.o maya44.o
9 9
10# Toplevel Module Dependency 10# Toplevel Module Dependency
11obj-$(CONFIG_SND_ICE1712) += snd-ice1712.o snd-ice17xx-ak4xxx.o 11obj-$(CONFIG_SND_ICE1712) += snd-ice1712.o snd-ice17xx-ak4xxx.o
diff --git a/sound/pci/ice1712/ice1712.h b/sound/pci/ice1712/ice1712.h
index fdae6deba16..adc909ec125 100644
--- a/sound/pci/ice1712/ice1712.h
+++ b/sound/pci/ice1712/ice1712.h
@@ -335,6 +335,7 @@ struct snd_ice1712 {
335 unsigned int force_rdma1:1; /* VT1720/4 - RDMA1 as non-spdif */ 335 unsigned int force_rdma1:1; /* VT1720/4 - RDMA1 as non-spdif */
336 unsigned int midi_output:1; /* VT1720/4: MIDI output triggered */ 336 unsigned int midi_output:1; /* VT1720/4: MIDI output triggered */
337 unsigned int midi_input:1; /* VT1720/4: MIDI input triggered */ 337 unsigned int midi_input:1; /* VT1720/4: MIDI input triggered */
338 unsigned int own_routing:1; /* VT1720/4: use own routing ctls */
338 unsigned int num_total_dacs; /* total DACs */ 339 unsigned int num_total_dacs; /* total DACs */
339 unsigned int num_total_adcs; /* total ADCs */ 340 unsigned int num_total_adcs; /* total ADCs */
340 unsigned int cur_rate; /* current rate */ 341 unsigned int cur_rate; /* current rate */
@@ -458,10 +459,17 @@ static inline int snd_ice1712_gpio_read_bits(struct snd_ice1712 *ice,
458 return snd_ice1712_gpio_read(ice) & mask; 459 return snd_ice1712_gpio_read(ice) & mask;
459} 460}
460 461
462/* route access functions */
463int snd_ice1724_get_route_val(struct snd_ice1712 *ice, int shift);
464int snd_ice1724_put_route_val(struct snd_ice1712 *ice, unsigned int val,
465 int shift);
466
461int snd_ice1712_spdif_build_controls(struct snd_ice1712 *ice); 467int snd_ice1712_spdif_build_controls(struct snd_ice1712 *ice);
462 468
463int snd_ice1712_akm4xxx_init(struct snd_akm4xxx *ak, const struct snd_akm4xxx *template, 469int snd_ice1712_akm4xxx_init(struct snd_akm4xxx *ak,
464 const struct snd_ak4xxx_private *priv, struct snd_ice1712 *ice); 470 const struct snd_akm4xxx *template,
471 const struct snd_ak4xxx_private *priv,
472 struct snd_ice1712 *ice);
465void snd_ice1712_akm4xxx_free(struct snd_ice1712 *ice); 473void snd_ice1712_akm4xxx_free(struct snd_ice1712 *ice);
466int snd_ice1712_akm4xxx_build_controls(struct snd_ice1712 *ice); 474int snd_ice1712_akm4xxx_build_controls(struct snd_ice1712 *ice);
467 475
diff --git a/sound/pci/ice1712/ice1724.c b/sound/pci/ice1712/ice1724.c
index 128510e77a7..36ade77cf37 100644
--- a/sound/pci/ice1712/ice1724.c
+++ b/sound/pci/ice1712/ice1724.c
@@ -49,6 +49,7 @@
49#include "prodigy192.h" 49#include "prodigy192.h"
50#include "prodigy_hifi.h" 50#include "prodigy_hifi.h"
51#include "juli.h" 51#include "juli.h"
52#include "maya44.h"
52#include "phase.h" 53#include "phase.h"
53#include "wtm.h" 54#include "wtm.h"
54#include "se.h" 55#include "se.h"
@@ -65,6 +66,7 @@ MODULE_SUPPORTED_DEVICE("{"
65 PRODIGY192_DEVICE_DESC 66 PRODIGY192_DEVICE_DESC
66 PRODIGY_HIFI_DEVICE_DESC 67 PRODIGY_HIFI_DEVICE_DESC
67 JULI_DEVICE_DESC 68 JULI_DEVICE_DESC
69 MAYA44_DEVICE_DESC
68 PHASE_DEVICE_DESC 70 PHASE_DEVICE_DESC
69 WTM_DEVICE_DESC 71 WTM_DEVICE_DESC
70 SE_DEVICE_DESC 72 SE_DEVICE_DESC
@@ -626,7 +628,7 @@ static unsigned char stdclock_set_mclk(struct snd_ice1712 *ice,
626 return 0; 628 return 0;
627} 629}
628 630
629static void snd_vt1724_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate, 631static int snd_vt1724_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate,
630 int force) 632 int force)
631{ 633{
632 unsigned long flags; 634 unsigned long flags;
@@ -634,17 +636,18 @@ static void snd_vt1724_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate,
634 unsigned int i, old_rate; 636 unsigned int i, old_rate;
635 637
636 if (rate > ice->hw_rates->list[ice->hw_rates->count - 1]) 638 if (rate > ice->hw_rates->list[ice->hw_rates->count - 1])
637 return; 639 return -EINVAL;
640
638 spin_lock_irqsave(&ice->reg_lock, flags); 641 spin_lock_irqsave(&ice->reg_lock, flags);
639 if ((inb(ICEMT1724(ice, DMA_CONTROL)) & DMA_STARTS) || 642 if ((inb(ICEMT1724(ice, DMA_CONTROL)) & DMA_STARTS) ||
640 (inb(ICEMT1724(ice, DMA_PAUSE)) & DMA_PAUSES)) { 643 (inb(ICEMT1724(ice, DMA_PAUSE)) & DMA_PAUSES)) {
641 /* running? we cannot change the rate now... */ 644 /* running? we cannot change the rate now... */
642 spin_unlock_irqrestore(&ice->reg_lock, flags); 645 spin_unlock_irqrestore(&ice->reg_lock, flags);
643 return; 646 return -EBUSY;
644 } 647 }
645 if (!force && is_pro_rate_locked(ice)) { 648 if (!force && is_pro_rate_locked(ice)) {
646 spin_unlock_irqrestore(&ice->reg_lock, flags); 649 spin_unlock_irqrestore(&ice->reg_lock, flags);
647 return; 650 return (rate == ice->cur_rate) ? 0 : -EBUSY;
648 } 651 }
649 652
650 old_rate = ice->get_rate(ice); 653 old_rate = ice->get_rate(ice);
@@ -652,7 +655,7 @@ static void snd_vt1724_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate,
652 ice->set_rate(ice, rate); 655 ice->set_rate(ice, rate);
653 else if (rate == ice->cur_rate) { 656 else if (rate == ice->cur_rate) {
654 spin_unlock_irqrestore(&ice->reg_lock, flags); 657 spin_unlock_irqrestore(&ice->reg_lock, flags);
655 return; 658 return 0;
656 } 659 }
657 660
658 ice->cur_rate = rate; 661 ice->cur_rate = rate;
@@ -674,13 +677,15 @@ static void snd_vt1724_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate,
674 } 677 }
675 if (ice->spdif.ops.setup_rate) 678 if (ice->spdif.ops.setup_rate)
676 ice->spdif.ops.setup_rate(ice, rate); 679 ice->spdif.ops.setup_rate(ice, rate);
680
681 return 0;
677} 682}
678 683
679static int snd_vt1724_pcm_hw_params(struct snd_pcm_substream *substream, 684static int snd_vt1724_pcm_hw_params(struct snd_pcm_substream *substream,
680 struct snd_pcm_hw_params *hw_params) 685 struct snd_pcm_hw_params *hw_params)
681{ 686{
682 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream); 687 struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
683 int i, chs; 688 int i, chs, err;
684 689
685 chs = params_channels(hw_params); 690 chs = params_channels(hw_params);
686 mutex_lock(&ice->open_mutex); 691 mutex_lock(&ice->open_mutex);
@@ -715,7 +720,11 @@ static int snd_vt1724_pcm_hw_params(struct snd_pcm_substream *substream,
715 } 720 }
716 } 721 }
717 mutex_unlock(&ice->open_mutex); 722 mutex_unlock(&ice->open_mutex);
718 snd_vt1724_set_pro_rate(ice, params_rate(hw_params), 0); 723
724 err = snd_vt1724_set_pro_rate(ice, params_rate(hw_params), 0);
725 if (err < 0)
726 return err;
727
719 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 728 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
720} 729}
721 730
@@ -848,20 +857,39 @@ static snd_pcm_uframes_t snd_vt1724_pcm_pointer(struct snd_pcm_substream *substr
848#endif 857#endif
849} 858}
850 859
851static const struct vt1724_pcm_reg vt1724_playback_pro_reg = { 860static const struct vt1724_pcm_reg vt1724_pdma0_reg = {
852 .addr = VT1724_MT_PLAYBACK_ADDR, 861 .addr = VT1724_MT_PLAYBACK_ADDR,
853 .size = VT1724_MT_PLAYBACK_SIZE, 862 .size = VT1724_MT_PLAYBACK_SIZE,
854 .count = VT1724_MT_PLAYBACK_COUNT, 863 .count = VT1724_MT_PLAYBACK_COUNT,
855 .start = VT1724_PDMA0_START, 864 .start = VT1724_PDMA0_START,
856}; 865};
857 866
858static const struct vt1724_pcm_reg vt1724_capture_pro_reg = { 867static const struct vt1724_pcm_reg vt1724_pdma4_reg = {
868 .addr = VT1724_MT_PDMA4_ADDR,
869 .size = VT1724_MT_PDMA4_SIZE,
870 .count = VT1724_MT_PDMA4_COUNT,
871 .start = VT1724_PDMA4_START,
872};
873
874static const struct vt1724_pcm_reg vt1724_rdma0_reg = {
859 .addr = VT1724_MT_CAPTURE_ADDR, 875 .addr = VT1724_MT_CAPTURE_ADDR,
860 .size = VT1724_MT_CAPTURE_SIZE, 876 .size = VT1724_MT_CAPTURE_SIZE,
861 .count = VT1724_MT_CAPTURE_COUNT, 877 .count = VT1724_MT_CAPTURE_COUNT,
862 .start = VT1724_RDMA0_START, 878 .start = VT1724_RDMA0_START,
863}; 879};
864 880
881static const struct vt1724_pcm_reg vt1724_rdma1_reg = {
882 .addr = VT1724_MT_RDMA1_ADDR,
883 .size = VT1724_MT_RDMA1_SIZE,
884 .count = VT1724_MT_RDMA1_COUNT,
885 .start = VT1724_RDMA1_START,
886};
887
888#define vt1724_playback_pro_reg vt1724_pdma0_reg
889#define vt1724_playback_spdif_reg vt1724_pdma4_reg
890#define vt1724_capture_pro_reg vt1724_rdma0_reg
891#define vt1724_capture_spdif_reg vt1724_rdma1_reg
892
865static const struct snd_pcm_hardware snd_vt1724_playback_pro = { 893static const struct snd_pcm_hardware snd_vt1724_playback_pro = {
866 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 894 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
867 SNDRV_PCM_INFO_BLOCK_TRANSFER | 895 SNDRV_PCM_INFO_BLOCK_TRANSFER |
@@ -1077,20 +1105,6 @@ static int __devinit snd_vt1724_pcm_profi(struct snd_ice1712 *ice, int device)
1077 * SPDIF PCM 1105 * SPDIF PCM
1078 */ 1106 */
1079 1107
1080static const struct vt1724_pcm_reg vt1724_playback_spdif_reg = {
1081 .addr = VT1724_MT_PDMA4_ADDR,
1082 .size = VT1724_MT_PDMA4_SIZE,
1083 .count = VT1724_MT_PDMA4_COUNT,
1084 .start = VT1724_PDMA4_START,
1085};
1086
1087static const struct vt1724_pcm_reg vt1724_capture_spdif_reg = {
1088 .addr = VT1724_MT_RDMA1_ADDR,
1089 .size = VT1724_MT_RDMA1_SIZE,
1090 .count = VT1724_MT_RDMA1_COUNT,
1091 .start = VT1724_RDMA1_START,
1092};
1093
1094/* update spdif control bits; call with reg_lock */ 1108/* update spdif control bits; call with reg_lock */
1095static void update_spdif_bits(struct snd_ice1712 *ice, unsigned int val) 1109static void update_spdif_bits(struct snd_ice1712 *ice, unsigned int val)
1096{ 1110{
@@ -1963,7 +1977,7 @@ static inline int digital_route_shift(int idx)
1963 return idx * 3; 1977 return idx * 3;
1964} 1978}
1965 1979
1966static int get_route_val(struct snd_ice1712 *ice, int shift) 1980int snd_ice1724_get_route_val(struct snd_ice1712 *ice, int shift)
1967{ 1981{
1968 unsigned long val; 1982 unsigned long val;
1969 unsigned char eitem; 1983 unsigned char eitem;
@@ -1982,7 +1996,8 @@ static int get_route_val(struct snd_ice1712 *ice, int shift)
1982 return eitem; 1996 return eitem;
1983} 1997}
1984 1998
1985static int put_route_val(struct snd_ice1712 *ice, unsigned int val, int shift) 1999int snd_ice1724_put_route_val(struct snd_ice1712 *ice, unsigned int val,
2000 int shift)
1986{ 2001{
1987 unsigned int old_val, nval; 2002 unsigned int old_val, nval;
1988 int change; 2003 int change;
@@ -2010,7 +2025,7 @@ static int snd_vt1724_pro_route_analog_get(struct snd_kcontrol *kcontrol,
2010 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol); 2025 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
2011 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 2026 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2012 ucontrol->value.enumerated.item[0] = 2027 ucontrol->value.enumerated.item[0] =
2013 get_route_val(ice, analog_route_shift(idx)); 2028 snd_ice1724_get_route_val(ice, analog_route_shift(idx));
2014 return 0; 2029 return 0;
2015} 2030}
2016 2031
@@ -2019,8 +2034,9 @@ static int snd_vt1724_pro_route_analog_put(struct snd_kcontrol *kcontrol,
2019{ 2034{
2020 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol); 2035 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
2021 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 2036 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2022 return put_route_val(ice, ucontrol->value.enumerated.item[0], 2037 return snd_ice1724_put_route_val(ice,
2023 analog_route_shift(idx)); 2038 ucontrol->value.enumerated.item[0],
2039 analog_route_shift(idx));
2024} 2040}
2025 2041
2026static int snd_vt1724_pro_route_spdif_get(struct snd_kcontrol *kcontrol, 2042static int snd_vt1724_pro_route_spdif_get(struct snd_kcontrol *kcontrol,
@@ -2029,7 +2045,7 @@ static int snd_vt1724_pro_route_spdif_get(struct snd_kcontrol *kcontrol,
2029 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol); 2045 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
2030 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 2046 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2031 ucontrol->value.enumerated.item[0] = 2047 ucontrol->value.enumerated.item[0] =
2032 get_route_val(ice, digital_route_shift(idx)); 2048 snd_ice1724_get_route_val(ice, digital_route_shift(idx));
2033 return 0; 2049 return 0;
2034} 2050}
2035 2051
@@ -2038,11 +2054,13 @@ static int snd_vt1724_pro_route_spdif_put(struct snd_kcontrol *kcontrol,
2038{ 2054{
2039 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol); 2055 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
2040 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); 2056 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2041 return put_route_val(ice, ucontrol->value.enumerated.item[0], 2057 return snd_ice1724_put_route_val(ice,
2042 digital_route_shift(idx)); 2058 ucontrol->value.enumerated.item[0],
2059 digital_route_shift(idx));
2043} 2060}
2044 2061
2045static struct snd_kcontrol_new snd_vt1724_mixer_pro_analog_route __devinitdata = { 2062static struct snd_kcontrol_new snd_vt1724_mixer_pro_analog_route __devinitdata =
2063{
2046 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2064 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2047 .name = "H/W Playback Route", 2065 .name = "H/W Playback Route",
2048 .info = snd_vt1724_pro_route_info, 2066 .info = snd_vt1724_pro_route_info,
@@ -2109,6 +2127,7 @@ static struct snd_ice1712_card_info *card_tables[] __devinitdata = {
2109 snd_vt1724_prodigy_hifi_cards, 2127 snd_vt1724_prodigy_hifi_cards,
2110 snd_vt1724_prodigy192_cards, 2128 snd_vt1724_prodigy192_cards,
2111 snd_vt1724_juli_cards, 2129 snd_vt1724_juli_cards,
2130 snd_vt1724_maya44_cards,
2112 snd_vt1724_phase_cards, 2131 snd_vt1724_phase_cards,
2113 snd_vt1724_wtm_cards, 2132 snd_vt1724_wtm_cards,
2114 snd_vt1724_se_cards, 2133 snd_vt1724_se_cards,
@@ -2246,8 +2265,10 @@ static int __devinit snd_vt1724_read_eeprom(struct snd_ice1712 *ice,
2246static void __devinit snd_vt1724_chip_reset(struct snd_ice1712 *ice) 2265static void __devinit snd_vt1724_chip_reset(struct snd_ice1712 *ice)
2247{ 2266{
2248 outb(VT1724_RESET , ICEREG1724(ice, CONTROL)); 2267 outb(VT1724_RESET , ICEREG1724(ice, CONTROL));
2268 inb(ICEREG1724(ice, CONTROL)); /* pci posting flush */
2249 msleep(10); 2269 msleep(10);
2250 outb(0, ICEREG1724(ice, CONTROL)); 2270 outb(0, ICEREG1724(ice, CONTROL));
2271 inb(ICEREG1724(ice, CONTROL)); /* pci posting flush */
2251 msleep(10); 2272 msleep(10);
2252} 2273}
2253 2274
@@ -2277,9 +2298,12 @@ static int __devinit snd_vt1724_spdif_build_controls(struct snd_ice1712 *ice)
2277 if (snd_BUG_ON(!ice->pcm)) 2298 if (snd_BUG_ON(!ice->pcm))
2278 return -EIO; 2299 return -EIO;
2279 2300
2280 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_mixer_pro_spdif_route, ice)); 2301 if (!ice->own_routing) {
2281 if (err < 0) 2302 err = snd_ctl_add(ice->card,
2282 return err; 2303 snd_ctl_new1(&snd_vt1724_mixer_pro_spdif_route, ice));
2304 if (err < 0)
2305 return err;
2306 }
2283 2307
2284 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_spdif_switch, ice)); 2308 err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_spdif_switch, ice));
2285 if (err < 0) 2309 if (err < 0)
@@ -2326,7 +2350,7 @@ static int __devinit snd_vt1724_build_controls(struct snd_ice1712 *ice)
2326 if (err < 0) 2350 if (err < 0)
2327 return err; 2351 return err;
2328 2352
2329 if (ice->num_total_dacs > 0) { 2353 if (!ice->own_routing && ice->num_total_dacs > 0) {
2330 struct snd_kcontrol_new tmp = snd_vt1724_mixer_pro_analog_route; 2354 struct snd_kcontrol_new tmp = snd_vt1724_mixer_pro_analog_route;
2331 tmp.count = ice->num_total_dacs; 2355 tmp.count = ice->num_total_dacs;
2332 if (ice->vt1720 && tmp.count > 2) 2356 if (ice->vt1720 && tmp.count > 2)
diff --git a/sound/pci/ice1712/maya44.c b/sound/pci/ice1712/maya44.c
new file mode 100644
index 00000000000..3e1c20ae2f1
--- /dev/null
+++ b/sound/pci/ice1712/maya44.c
@@ -0,0 +1,779 @@
1/*
2 * ALSA driver for ICEnsemble VT1724 (Envy24HT)
3 *
4 * Lowlevel functions for ESI Maya44 cards
5 *
6 * Copyright (c) 2009 Takashi Iwai <tiwai@suse.de>
7 * Based on the patches by Rainer Zimmermann <mail@lightshed.de>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#include <linux/init.h>
26#include <linux/slab.h>
27#include <linux/io.h>
28#include <sound/core.h>
29#include <sound/control.h>
30#include <sound/pcm.h>
31#include <sound/tlv.h>
32
33#include "ice1712.h"
34#include "envy24ht.h"
35#include "maya44.h"
36
37/* WM8776 register indexes */
38#define WM8776_REG_HEADPHONE_L 0x00
39#define WM8776_REG_HEADPHONE_R 0x01
40#define WM8776_REG_HEADPHONE_MASTER 0x02
41#define WM8776_REG_DAC_ATTEN_L 0x03
42#define WM8776_REG_DAC_ATTEN_R 0x04
43#define WM8776_REG_DAC_ATTEN_MASTER 0x05
44#define WM8776_REG_DAC_PHASE 0x06
45#define WM8776_REG_DAC_CONTROL 0x07
46#define WM8776_REG_DAC_MUTE 0x08
47#define WM8776_REG_DAC_DEEMPH 0x09
48#define WM8776_REG_DAC_IF_CONTROL 0x0a
49#define WM8776_REG_ADC_IF_CONTROL 0x0b
50#define WM8776_REG_MASTER_MODE_CONTROL 0x0c
51#define WM8776_REG_POWERDOWN 0x0d
52#define WM8776_REG_ADC_ATTEN_L 0x0e
53#define WM8776_REG_ADC_ATTEN_R 0x0f
54#define WM8776_REG_ADC_ALC1 0x10
55#define WM8776_REG_ADC_ALC2 0x11
56#define WM8776_REG_ADC_ALC3 0x12
57#define WM8776_REG_ADC_NOISE_GATE 0x13
58#define WM8776_REG_ADC_LIMITER 0x14
59#define WM8776_REG_ADC_MUX 0x15
60#define WM8776_REG_OUTPUT_MUX 0x16
61#define WM8776_REG_RESET 0x17
62
63#define WM8776_NUM_REGS 0x18
64
65/* clock ratio identifiers for snd_wm8776_set_rate() */
66#define WM8776_CLOCK_RATIO_128FS 0
67#define WM8776_CLOCK_RATIO_192FS 1
68#define WM8776_CLOCK_RATIO_256FS 2
69#define WM8776_CLOCK_RATIO_384FS 3
70#define WM8776_CLOCK_RATIO_512FS 4
71#define WM8776_CLOCK_RATIO_768FS 5
72
73enum { WM_VOL_HP, WM_VOL_DAC, WM_VOL_ADC, WM_NUM_VOLS };
74enum { WM_SW_DAC, WM_SW_BYPASS, WM_NUM_SWITCHES };
75
76struct snd_wm8776 {
77 unsigned char addr;
78 unsigned short regs[WM8776_NUM_REGS];
79 unsigned char volumes[WM_NUM_VOLS][2];
80 unsigned int switch_bits;
81};
82
83struct snd_maya44 {
84 struct snd_ice1712 *ice;
85 struct snd_wm8776 wm[2];
86 struct mutex mutex;
87};
88
89
90/* write the given register and save the data to the cache */
91static void wm8776_write(struct snd_ice1712 *ice, struct snd_wm8776 *wm,
92 unsigned char reg, unsigned short val)
93{
94 /*
95 * WM8776 registers are up to 9 bits wide, bit 8 is placed in the LSB
96 * of the address field
97 */
98 snd_vt1724_write_i2c(ice, wm->addr,
99 (reg << 1) | ((val >> 8) & 1),
100 val & 0xff);
101 wm->regs[reg] = val;
102}
103
104/*
105 * update the given register with and/or mask and save the data to the cache
106 */
107static int wm8776_write_bits(struct snd_ice1712 *ice, struct snd_wm8776 *wm,
108 unsigned char reg,
109 unsigned short mask, unsigned short val)
110{
111 val |= wm->regs[reg] & ~mask;
112 if (val != wm->regs[reg]) {
113 wm8776_write(ice, wm, reg, val);
114 return 1;
115 }
116 return 0;
117}
118
119
120/*
121 * WM8776 volume controls
122 */
123
124struct maya_vol_info {
125 unsigned int maxval; /* volume range: 0..maxval */
126 unsigned char regs[2]; /* left and right registers */
127 unsigned short mask; /* value mask */
128 unsigned short offset; /* zero-value offset */
129 unsigned short mute; /* mute bit */
130 unsigned short update; /* update bits */
131 unsigned char mux_bits[2]; /* extra bits for ADC mute */
132};
133
134static struct maya_vol_info vol_info[WM_NUM_VOLS] = {
135 [WM_VOL_HP] = {
136 .maxval = 80,
137 .regs = { WM8776_REG_HEADPHONE_L, WM8776_REG_HEADPHONE_R },
138 .mask = 0x7f,
139 .offset = 0x30,
140 .mute = 0x00,
141 .update = 0x180, /* update and zero-cross enable */
142 },
143 [WM_VOL_DAC] = {
144 .maxval = 255,
145 .regs = { WM8776_REG_DAC_ATTEN_L, WM8776_REG_DAC_ATTEN_R },
146 .mask = 0xff,
147 .offset = 0x01,
148 .mute = 0x00,
149 .update = 0x100, /* zero-cross enable */
150 },
151 [WM_VOL_ADC] = {
152 .maxval = 91,
153 .regs = { WM8776_REG_ADC_ATTEN_L, WM8776_REG_ADC_ATTEN_R },
154 .mask = 0xff,
155 .offset = 0xa5,
156 .mute = 0xa5,
157 .update = 0x100, /* update */
158 .mux_bits = { 0x80, 0x40 }, /* ADCMUX bits */
159 },
160};
161
162/*
163 * dB tables
164 */
165/* headphone output: mute, -73..+6db (1db step) */
166static const DECLARE_TLV_DB_SCALE(db_scale_hp, -7400, 100, 1);
167/* DAC output: mute, -127..0db (0.5db step) */
168static const DECLARE_TLV_DB_SCALE(db_scale_dac, -12750, 50, 1);
169/* ADC gain: mute, -21..+24db (0.5db step) */
170static const DECLARE_TLV_DB_SCALE(db_scale_adc, -2100, 50, 1);
171
172static int maya_vol_info(struct snd_kcontrol *kcontrol,
173 struct snd_ctl_elem_info *uinfo)
174{
175 unsigned int idx = kcontrol->private_value;
176 struct maya_vol_info *vol = &vol_info[idx];
177
178 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
179 uinfo->count = 2;
180 uinfo->value.integer.min = 0;
181 uinfo->value.integer.max = vol->maxval;
182 return 0;
183}
184
185static int maya_vol_get(struct snd_kcontrol *kcontrol,
186 struct snd_ctl_elem_value *ucontrol)
187{
188 struct snd_maya44 *chip = snd_kcontrol_chip(kcontrol);
189 struct snd_wm8776 *wm =
190 &chip->wm[snd_ctl_get_ioff(kcontrol, &ucontrol->id)];
191 unsigned int idx = kcontrol->private_value;
192
193 mutex_lock(&chip->mutex);
194 ucontrol->value.integer.value[0] = wm->volumes[idx][0];
195 ucontrol->value.integer.value[1] = wm->volumes[idx][1];
196 mutex_unlock(&chip->mutex);
197 return 0;
198}
199
200static int maya_vol_put(struct snd_kcontrol *kcontrol,
201 struct snd_ctl_elem_value *ucontrol)
202{
203 struct snd_maya44 *chip = snd_kcontrol_chip(kcontrol);
204 struct snd_wm8776 *wm =
205 &chip->wm[snd_ctl_get_ioff(kcontrol, &ucontrol->id)];
206 unsigned int idx = kcontrol->private_value;
207 struct maya_vol_info *vol = &vol_info[idx];
208 unsigned int val, data;
209 int ch, changed = 0;
210
211 mutex_lock(&chip->mutex);
212 for (ch = 0; ch < 2; ch++) {
213 val = ucontrol->value.integer.value[ch];
214 if (val > vol->maxval)
215 val = vol->maxval;
216 if (val == wm->volumes[idx][ch])
217 continue;
218 if (!val)
219 data = vol->mute;
220 else
221 data = (val - 1) + vol->offset;
222 data |= vol->update;
223 changed |= wm8776_write_bits(chip->ice, wm, vol->regs[ch],
224 vol->mask | vol->update, data);
225 if (vol->mux_bits[ch])
226 wm8776_write_bits(chip->ice, wm, WM8776_REG_ADC_MUX,
227 vol->mux_bits[ch],
228 val ? 0 : vol->mux_bits[ch]);
229 wm->volumes[idx][ch] = val;
230 }
231 mutex_unlock(&chip->mutex);
232 return changed;
233}
234
235/*
236 * WM8776 switch controls
237 */
238
239#define COMPOSE_SW_VAL(idx, reg, mask) ((idx) | ((reg) << 8) | ((mask) << 16))
240#define GET_SW_VAL_IDX(val) ((val) & 0xff)
241#define GET_SW_VAL_REG(val) (((val) >> 8) & 0xff)
242#define GET_SW_VAL_MASK(val) (((val) >> 16) & 0xff)
243
244#define maya_sw_info snd_ctl_boolean_mono_info
245
246static int maya_sw_get(struct snd_kcontrol *kcontrol,
247 struct snd_ctl_elem_value *ucontrol)
248{
249 struct snd_maya44 *chip = snd_kcontrol_chip(kcontrol);
250 struct snd_wm8776 *wm =
251 &chip->wm[snd_ctl_get_ioff(kcontrol, &ucontrol->id)];
252 unsigned int idx = GET_SW_VAL_IDX(kcontrol->private_value);
253
254 ucontrol->value.integer.value[0] = (wm->switch_bits >> idx) & 1;
255 return 0;
256}
257
258static int maya_sw_put(struct snd_kcontrol *kcontrol,
259 struct snd_ctl_elem_value *ucontrol)
260{
261 struct snd_maya44 *chip = snd_kcontrol_chip(kcontrol);
262 struct snd_wm8776 *wm =
263 &chip->wm[snd_ctl_get_ioff(kcontrol, &ucontrol->id)];
264 unsigned int idx = GET_SW_VAL_IDX(kcontrol->private_value);
265 unsigned int mask, val;
266 int changed;
267
268 mutex_lock(&chip->mutex);
269 mask = 1 << idx;
270 wm->switch_bits &= ~mask;
271 val = ucontrol->value.integer.value[0];
272 if (val)
273 wm->switch_bits |= mask;
274 mask = GET_SW_VAL_MASK(kcontrol->private_value);
275 changed = wm8776_write_bits(chip->ice, wm,
276 GET_SW_VAL_REG(kcontrol->private_value),
277 mask, val ? mask : 0);
278 mutex_unlock(&chip->mutex);
279 return changed;
280}
281
282/*
283 * GPIO pins (known ones for maya44)
284 */
285#define GPIO_PHANTOM_OFF 2
286#define GPIO_MIC_RELAY 4
287#define GPIO_SPDIF_IN_INV 5
288#define GPIO_MUST_BE_0 7
289
290/*
291 * GPIO switch controls
292 */
293
294#define COMPOSE_GPIO_VAL(shift, inv) ((shift) | ((inv) << 8))
295#define GET_GPIO_VAL_SHIFT(val) ((val) & 0xff)
296#define GET_GPIO_VAL_INV(val) (((val) >> 8) & 1)
297
298static int maya_set_gpio_bits(struct snd_ice1712 *ice, unsigned int mask,
299 unsigned int bits)
300{
301 unsigned int data;
302 data = snd_ice1712_gpio_read(ice);
303 if ((data & mask) == bits)
304 return 0;
305 snd_ice1712_gpio_write(ice, (data & ~mask) | bits);
306 return 1;
307}
308
309#define maya_gpio_sw_info snd_ctl_boolean_mono_info
310
311static int maya_gpio_sw_get(struct snd_kcontrol *kcontrol,
312 struct snd_ctl_elem_value *ucontrol)
313{
314 struct snd_maya44 *chip = snd_kcontrol_chip(kcontrol);
315 unsigned int shift = GET_GPIO_VAL_SHIFT(kcontrol->private_value);
316 unsigned int val;
317
318 val = (snd_ice1712_gpio_read(chip->ice) >> shift) & 1;
319 if (GET_GPIO_VAL_INV(kcontrol->private_value))
320 val = !val;
321 ucontrol->value.integer.value[0] = val;
322 return 0;
323}
324
325static int maya_gpio_sw_put(struct snd_kcontrol *kcontrol,
326 struct snd_ctl_elem_value *ucontrol)
327{
328 struct snd_maya44 *chip = snd_kcontrol_chip(kcontrol);
329 unsigned int shift = GET_GPIO_VAL_SHIFT(kcontrol->private_value);
330 unsigned int val, mask;
331 int changed;
332
333 mutex_lock(&chip->mutex);
334 mask = 1 << shift;
335 val = ucontrol->value.integer.value[0];
336 if (GET_GPIO_VAL_INV(kcontrol->private_value))
337 val = !val;
338 val = val ? mask : 0;
339 changed = maya_set_gpio_bits(chip->ice, mask, val);
340 mutex_unlock(&chip->mutex);
341 return changed;
342}
343
344/*
345 * capture source selection
346 */
347
348/* known working input slots (0-4) */
349#define MAYA_LINE_IN 1 /* in-2 */
350#define MAYA_MIC_IN 4 /* in-5 */
351
352static void wm8776_select_input(struct snd_maya44 *chip, int idx, int line)
353{
354 wm8776_write_bits(chip->ice, &chip->wm[idx], WM8776_REG_ADC_MUX,
355 0x1f, 1 << line);
356}
357
358static int maya_rec_src_info(struct snd_kcontrol *kcontrol,
359 struct snd_ctl_elem_info *uinfo)
360{
361 static char *texts[] = { "Line", "Mic" };
362
363 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
364 uinfo->count = 1;
365 uinfo->value.enumerated.items = ARRAY_SIZE(texts);
366 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
367 uinfo->value.enumerated.item =
368 uinfo->value.enumerated.items - 1;
369 strcpy(uinfo->value.enumerated.name,
370 texts[uinfo->value.enumerated.item]);
371 return 0;
372}
373
374static int maya_rec_src_get(struct snd_kcontrol *kcontrol,
375 struct snd_ctl_elem_value *ucontrol)
376{
377 struct snd_maya44 *chip = snd_kcontrol_chip(kcontrol);
378 int sel;
379
380 if (snd_ice1712_gpio_read(chip->ice) & (1 << GPIO_MIC_RELAY))
381 sel = 1;
382 else
383 sel = 0;
384 ucontrol->value.enumerated.item[0] = sel;
385 return 0;
386}
387
388static int maya_rec_src_put(struct snd_kcontrol *kcontrol,
389 struct snd_ctl_elem_value *ucontrol)
390{
391 struct snd_maya44 *chip = snd_kcontrol_chip(kcontrol);
392 int sel = ucontrol->value.enumerated.item[0];
393 int changed;
394
395 mutex_lock(&chip->mutex);
396 changed = maya_set_gpio_bits(chip->ice, GPIO_MIC_RELAY,
397 sel ? GPIO_MIC_RELAY : 0);
398 wm8776_select_input(chip, 0, sel ? MAYA_MIC_IN : MAYA_LINE_IN);
399 mutex_unlock(&chip->mutex);
400 return changed;
401}
402
403/*
404 * Maya44 routing switch settings have different meanings than the standard
405 * ice1724 switches as defined in snd_vt1724_pro_route_info (ice1724.c).
406 */
407static int maya_pb_route_info(struct snd_kcontrol *kcontrol,
408 struct snd_ctl_elem_info *uinfo)
409{
410 static char *texts[] = {
411 "PCM Out", /* 0 */
412 "Input 1", "Input 2", "Input 3", "Input 4"
413 };
414
415 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
416 uinfo->count = 1;
417 uinfo->value.enumerated.items = ARRAY_SIZE(texts);
418 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
419 uinfo->value.enumerated.item =
420 uinfo->value.enumerated.items - 1;
421 strcpy(uinfo->value.enumerated.name,
422 texts[uinfo->value.enumerated.item]);
423 return 0;
424}
425
426static int maya_pb_route_shift(int idx)
427{
428 static const unsigned char shift[10] =
429 { 8, 20, 0, 3, 11, 23, 14, 26, 17, 29 };
430 return shift[idx % 10];
431}
432
433static int maya_pb_route_get(struct snd_kcontrol *kcontrol,
434 struct snd_ctl_elem_value *ucontrol)
435{
436 struct snd_maya44 *chip = snd_kcontrol_chip(kcontrol);
437 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
438 ucontrol->value.enumerated.item[0] =
439 snd_ice1724_get_route_val(chip->ice, maya_pb_route_shift(idx));
440 return 0;
441}
442
443static int maya_pb_route_put(struct snd_kcontrol *kcontrol,
444 struct snd_ctl_elem_value *ucontrol)
445{
446 struct snd_maya44 *chip = snd_kcontrol_chip(kcontrol);
447 int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
448 return snd_ice1724_put_route_val(chip->ice,
449 ucontrol->value.enumerated.item[0],
450 maya_pb_route_shift(idx));
451}
452
453
454/*
455 * controls to be added
456 */
457
458static struct snd_kcontrol_new maya_controls[] __devinitdata = {
459 {
460 .name = "Crossmix Playback Volume",
461 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
462 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
463 SNDRV_CTL_ELEM_ACCESS_TLV_READ,
464 .info = maya_vol_info,
465 .get = maya_vol_get,
466 .put = maya_vol_put,
467 .tlv = { .p = db_scale_hp },
468 .private_value = WM_VOL_HP,
469 .count = 2,
470 },
471 {
472 .name = "PCM Playback Volume",
473 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
474 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
475 SNDRV_CTL_ELEM_ACCESS_TLV_READ,
476 .info = maya_vol_info,
477 .get = maya_vol_get,
478 .put = maya_vol_put,
479 .tlv = { .p = db_scale_dac },
480 .private_value = WM_VOL_DAC,
481 .count = 2,
482 },
483 {
484 .name = "Line Capture Volume",
485 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
486 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
487 SNDRV_CTL_ELEM_ACCESS_TLV_READ,
488 .info = maya_vol_info,
489 .get = maya_vol_get,
490 .put = maya_vol_put,
491 .tlv = { .p = db_scale_adc },
492 .private_value = WM_VOL_ADC,
493 .count = 2,
494 },
495 {
496 .name = "PCM Playback Switch",
497 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
498 .info = maya_sw_info,
499 .get = maya_sw_get,
500 .put = maya_sw_put,
501 .private_value = COMPOSE_SW_VAL(WM_SW_DAC,
502 WM8776_REG_OUTPUT_MUX, 0x01),
503 .count = 2,
504 },
505 {
506 .name = "Bypass Playback Switch",
507 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
508 .info = maya_sw_info,
509 .get = maya_sw_get,
510 .put = maya_sw_put,
511 .private_value = COMPOSE_SW_VAL(WM_SW_BYPASS,
512 WM8776_REG_OUTPUT_MUX, 0x04),
513 .count = 2,
514 },
515 {
516 .name = "Capture Source",
517 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
518 .info = maya_rec_src_info,
519 .get = maya_rec_src_get,
520 .put = maya_rec_src_put,
521 },
522 {
523 .name = "Mic Phantom Power Switch",
524 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
525 .info = maya_gpio_sw_info,
526 .get = maya_gpio_sw_get,
527 .put = maya_gpio_sw_put,
528 .private_value = COMPOSE_GPIO_VAL(GPIO_PHANTOM_OFF, 1),
529 },
530 {
531 .name = "SPDIF Capture Switch",
532 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
533 .info = maya_gpio_sw_info,
534 .get = maya_gpio_sw_get,
535 .put = maya_gpio_sw_put,
536 .private_value = COMPOSE_GPIO_VAL(GPIO_SPDIF_IN_INV, 1),
537 },
538 {
539 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
540 .name = "H/W Playback Route",
541 .info = maya_pb_route_info,
542 .get = maya_pb_route_get,
543 .put = maya_pb_route_put,
544 .count = 4, /* FIXME: do controls 5-9 have any meaning? */
545 },
546};
547
548static int __devinit maya44_add_controls(struct snd_ice1712 *ice)
549{
550 int err, i;
551
552 for (i = 0; i < ARRAY_SIZE(maya_controls); i++) {
553 err = snd_ctl_add(ice->card, snd_ctl_new1(&maya_controls[i],
554 ice->spec));
555 if (err < 0)
556 return err;
557 }
558 return 0;
559}
560
561
562/*
563 * initialize a wm8776 chip
564 */
565static void __devinit wm8776_init(struct snd_ice1712 *ice,
566 struct snd_wm8776 *wm, unsigned int addr)
567{
568 static const unsigned short inits_wm8776[] = {
569 0x02, 0x100, /* R2: headphone L+R muted + update */
570 0x05, 0x100, /* R5: DAC output L+R muted + update */
571 0x06, 0x000, /* R6: DAC output phase normal */
572 0x07, 0x091, /* R7: DAC enable zero cross detection,
573 normal output */
574 0x08, 0x000, /* R8: DAC soft mute off */
575 0x09, 0x000, /* R9: no deemph, DAC zero detect disabled */
576 0x0a, 0x022, /* R10: DAC I2C mode, std polarities, 24bit */
577 0x0b, 0x022, /* R11: ADC I2C mode, std polarities, 24bit,
578 highpass filter enabled */
579 0x0c, 0x042, /* R12: ADC+DAC slave, ADC+DAC 44,1kHz */
580 0x0d, 0x000, /* R13: all power up */
581 0x0e, 0x100, /* R14: ADC left muted,
582 enable zero cross detection */
583 0x0f, 0x100, /* R15: ADC right muted,
584 enable zero cross detection */
585 /* R16: ALC...*/
586 0x11, 0x000, /* R17: disable ALC */
587 /* R18: ALC...*/
588 /* R19: noise gate...*/
589 0x15, 0x000, /* R21: ADC input mux init, mute all inputs */
590 0x16, 0x001, /* R22: output mux, select DAC */
591 0xff, 0xff
592 };
593
594 const unsigned short *ptr;
595 unsigned char reg;
596 unsigned short data;
597
598 wm->addr = addr;
599 /* enable DAC output; mute bypass, aux & all inputs */
600 wm->switch_bits = (1 << WM_SW_DAC);
601
602 ptr = inits_wm8776;
603 while (*ptr != 0xff) {
604 reg = *ptr++;
605 data = *ptr++;
606 wm8776_write(ice, wm, reg, data);
607 }
608}
609
610
611/*
612 * change the rate on the WM8776 codecs.
613 * this assumes that the VT17xx's rate is changed by the calling function.
614 * NOTE: even though the WM8776's are running in slave mode and rate
615 * selection is automatic, we need to call snd_wm8776_set_rate() here
616 * to make sure some flags are set correctly.
617 */
618static void set_rate(struct snd_ice1712 *ice, unsigned int rate)
619{
620 struct snd_maya44 *chip = ice->spec;
621 unsigned int ratio, adc_ratio, val;
622 int i;
623
624 switch (rate) {
625 case 192000:
626 ratio = WM8776_CLOCK_RATIO_128FS;
627 break;
628 case 176400:
629 ratio = WM8776_CLOCK_RATIO_128FS;
630 break;
631 case 96000:
632 ratio = WM8776_CLOCK_RATIO_256FS;
633 break;
634 case 88200:
635 ratio = WM8776_CLOCK_RATIO_384FS;
636 break;
637 case 48000:
638 ratio = WM8776_CLOCK_RATIO_512FS;
639 break;
640 case 44100:
641 ratio = WM8776_CLOCK_RATIO_512FS;
642 break;
643 case 32000:
644 ratio = WM8776_CLOCK_RATIO_768FS;
645 break;
646 case 0:
647 /* no hint - S/PDIF input is master, simply return */
648 return;
649 default:
650 snd_BUG();
651 return;
652 }
653
654 /*
655 * this currently sets the same rate for ADC and DAC, but limits
656 * ADC rate to 256X (96kHz). For 256X mode (96kHz), this sets ADC
657 * oversampling to 64x, as recommended by WM8776 datasheet.
658 * Setting the rate is not really necessary in slave mode.
659 */
660 adc_ratio = ratio;
661 if (adc_ratio < WM8776_CLOCK_RATIO_256FS)
662 adc_ratio = WM8776_CLOCK_RATIO_256FS;
663
664 val = adc_ratio;
665 if (adc_ratio == WM8776_CLOCK_RATIO_256FS)
666 val |= 8;
667 val |= ratio << 4;
668
669 mutex_lock(&chip->mutex);
670 for (i = 0; i < 2; i++)
671 wm8776_write_bits(ice, &chip->wm[i],
672 WM8776_REG_MASTER_MODE_CONTROL,
673 0x180, val);
674 mutex_unlock(&chip->mutex);
675}
676
677/*
678 * supported sample rates (to override the default one)
679 */
680
681static unsigned int rates[] = {
682 32000, 44100, 48000, 64000, 88200, 96000, 176400, 192000
683};
684
685/* playback rates: 32..192 kHz */
686static struct snd_pcm_hw_constraint_list dac_rates = {
687 .count = ARRAY_SIZE(rates),
688 .list = rates,
689 .mask = 0
690};
691
692
693/*
694 * chip addresses on I2C bus
695 */
696static unsigned char wm8776_addr[2] __devinitdata = {
697 0x34, 0x36, /* codec 0 & 1 */
698};
699
700/*
701 * initialize the chip
702 */
703static int __devinit maya44_init(struct snd_ice1712 *ice)
704{
705 int i;
706 struct snd_maya44 *chip;
707
708 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
709 if (!chip)
710 return -ENOMEM;
711 mutex_init(&chip->mutex);
712 chip->ice = ice;
713 ice->spec = chip;
714
715 /* initialise codecs */
716 ice->num_total_dacs = 4;
717 ice->num_total_adcs = 4;
718 ice->akm_codecs = 0;
719
720 for (i = 0; i < 2; i++) {
721 wm8776_init(ice, &chip->wm[i], wm8776_addr[i]);
722 wm8776_select_input(chip, i, MAYA_LINE_IN);
723 }
724
725 /* set card specific rates */
726 ice->hw_rates = &dac_rates;
727
728 /* register change rate notifier */
729 ice->gpio.set_pro_rate = set_rate;
730
731 /* RDMA1 (2nd input channel) is used for ADC by default */
732 ice->force_rdma1 = 1;
733
734 /* have an own routing control */
735 ice->own_routing = 1;
736
737 return 0;
738}
739
740
741/*
742 * Maya44 boards don't provide the EEPROM data except for the vendor IDs.
743 * hence the driver needs to sets up it properly.
744 */
745
746static unsigned char maya44_eeprom[] __devinitdata = {
747 [ICE_EEP2_SYSCONF] = 0x45,
748 /* clock xin1=49.152MHz, mpu401, 2 stereo ADCs+DACs */
749 [ICE_EEP2_ACLINK] = 0x80,
750 /* I2S */
751 [ICE_EEP2_I2S] = 0xf8,
752 /* vol, 96k, 24bit, 192k */
753 [ICE_EEP2_SPDIF] = 0xc3,
754 /* enable spdif out, spdif out supp, spdif-in, ext spdif out */
755 [ICE_EEP2_GPIO_DIR] = 0xff,
756 [ICE_EEP2_GPIO_DIR1] = 0xff,
757 [ICE_EEP2_GPIO_DIR2] = 0xff,
758 [ICE_EEP2_GPIO_MASK] = 0/*0x9f*/,
759 [ICE_EEP2_GPIO_MASK1] = 0/*0xff*/,
760 [ICE_EEP2_GPIO_MASK2] = 0/*0x7f*/,
761 [ICE_EEP2_GPIO_STATE] = (1 << GPIO_PHANTOM_OFF) |
762 (1 << GPIO_SPDIF_IN_INV),
763 [ICE_EEP2_GPIO_STATE1] = 0x00,
764 [ICE_EEP2_GPIO_STATE2] = 0x00,
765};
766
767/* entry point */
768struct snd_ice1712_card_info snd_vt1724_maya44_cards[] __devinitdata = {
769 {
770 .subvendor = VT1724_SUBDEVICE_MAYA44,
771 .name = "ESI Maya44",
772 .model = "maya44",
773 .chip_init = maya44_init,
774 .build_controls = maya44_add_controls,
775 .eeprom_size = sizeof(maya44_eeprom),
776 .eeprom_data = maya44_eeprom,
777 },
778 { } /* terminator */
779};
diff --git a/sound/pci/ice1712/maya44.h b/sound/pci/ice1712/maya44.h
new file mode 100644
index 00000000000..eafd03a8f4b
--- /dev/null
+++ b/sound/pci/ice1712/maya44.h
@@ -0,0 +1,10 @@
1#ifndef __SOUND_MAYA44_H
2#define __SOUND_MAYA44_H
3
4#define MAYA44_DEVICE_DESC "{ESI,Maya44},"
5
6#define VT1724_SUBDEVICE_MAYA44 0x34315441 /* Maya44 */
7
8extern struct snd_ice1712_card_info snd_vt1724_maya44_cards[];
9
10#endif /* __SOUND_MAYA44_H */
diff --git a/sound/pci/intel8x0.c b/sound/pci/intel8x0.c
index 5dced5b7938..173bebf9f51 100644
--- a/sound/pci/intel8x0.c
+++ b/sound/pci/intel8x0.c
@@ -1854,6 +1854,12 @@ static struct ac97_quirk ac97_quirks[] __devinitdata = {
1854 }, 1854 },
1855 { 1855 {
1856 .subvendor = 0x1028, 1856 .subvendor = 0x1028,
1857 .subdevice = 0x016a,
1858 .name = "Dell Inspiron 8600", /* STAC9750/51 */
1859 .type = AC97_TUNE_HP_ONLY
1860 },
1861 {
1862 .subvendor = 0x1028,
1857 .subdevice = 0x0186, 1863 .subdevice = 0x0186,
1858 .name = "Dell Latitude D810", /* cf. Malone #41015 */ 1864 .name = "Dell Latitude D810", /* cf. Malone #41015 */
1859 .type = AC97_TUNE_HP_MUTE_LED 1865 .type = AC97_TUNE_HP_MUTE_LED
@@ -1896,12 +1902,6 @@ static struct ac97_quirk ac97_quirks[] __devinitdata = {
1896 }, 1902 },
1897 { 1903 {
1898 .subvendor = 0x103c, 1904 .subvendor = 0x103c,
1899 .subdevice = 0x0934,
1900 .name = "HP nx8220",
1901 .type = AC97_TUNE_MUTE_LED
1902 },
1903 {
1904 .subvendor = 0x103c,
1905 .subdevice = 0x129d, 1905 .subdevice = 0x129d,
1906 .name = "HP xw8000", 1906 .name = "HP xw8000",
1907 .type = AC97_TUNE_HP_ONLY 1907 .type = AC97_TUNE_HP_ONLY
@@ -2751,11 +2751,12 @@ static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2751 if (pos == 0) { 2751 if (pos == 0) {
2752 snd_printk(KERN_ERR "intel8x0: measure - unreliable DMA position..\n"); 2752 snd_printk(KERN_ERR "intel8x0: measure - unreliable DMA position..\n");
2753 __retry: 2753 __retry:
2754 if (attempt < 2) { 2754 if (attempt < 3) {
2755 msleep(300);
2755 attempt++; 2756 attempt++;
2756 goto __again; 2757 goto __again;
2757 } 2758 }
2758 return; 2759 goto __end;
2759 } 2760 }
2760 2761
2761 pos /= 4; 2762 pos /= 4;
@@ -2782,6 +2783,7 @@ static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
2782 else if (pos < 47500 || pos > 48500) 2783 else if (pos < 47500 || pos > 48500)
2783 /* not 48000Hz, tuning the clock.. */ 2784 /* not 48000Hz, tuning the clock.. */
2784 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos; 2785 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2786 __end:
2785 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock); 2787 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2786 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0); 2788 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
2787} 2789}
diff --git a/sound/pci/korg1212/korg1212.c b/sound/pci/korg1212/korg1212.c
index 8b79969034b..7cc38a11e99 100644
--- a/sound/pci/korg1212/korg1212.c
+++ b/sound/pci/korg1212/korg1212.c
@@ -1238,7 +1238,8 @@ static struct snd_pcm_hardware snd_korg1212_playback_info =
1238{ 1238{
1239 .info = (SNDRV_PCM_INFO_MMAP | 1239 .info = (SNDRV_PCM_INFO_MMAP |
1240 SNDRV_PCM_INFO_MMAP_VALID | 1240 SNDRV_PCM_INFO_MMAP_VALID |
1241 SNDRV_PCM_INFO_INTERLEAVED), 1241 SNDRV_PCM_INFO_INTERLEAVED |
1242 SNDRV_PCM_INFO_BATCH),
1242 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1243 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1243 .rates = (SNDRV_PCM_RATE_44100 | 1244 .rates = (SNDRV_PCM_RATE_44100 |
1244 SNDRV_PCM_RATE_48000), 1245 SNDRV_PCM_RATE_48000),
@@ -1258,7 +1259,8 @@ static struct snd_pcm_hardware snd_korg1212_capture_info =
1258{ 1259{
1259 .info = (SNDRV_PCM_INFO_MMAP | 1260 .info = (SNDRV_PCM_INFO_MMAP |
1260 SNDRV_PCM_INFO_MMAP_VALID | 1261 SNDRV_PCM_INFO_MMAP_VALID |
1261 SNDRV_PCM_INFO_INTERLEAVED), 1262 SNDRV_PCM_INFO_INTERLEAVED |
1263 SNDRV_PCM_INFO_BATCH),
1262 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1264 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1263 .rates = (SNDRV_PCM_RATE_44100 | 1265 .rates = (SNDRV_PCM_RATE_44100 |
1264 SNDRV_PCM_RATE_48000), 1266 SNDRV_PCM_RATE_48000),
diff --git a/sound/pci/lx6464es/Makefile b/sound/pci/lx6464es/Makefile
new file mode 100644
index 00000000000..eb04a6c73d8
--- /dev/null
+++ b/sound/pci/lx6464es/Makefile
@@ -0,0 +1,2 @@
1snd-lx6464es-objs := lx6464es.o lx_core.o
2obj-$(CONFIG_SND_LX6464ES) += snd-lx6464es.o
diff --git a/sound/pci/lx6464es/lx6464es.c b/sound/pci/lx6464es/lx6464es.c
new file mode 100644
index 00000000000..870bfc58c69
--- /dev/null
+++ b/sound/pci/lx6464es/lx6464es.c
@@ -0,0 +1,1152 @@
1/* -*- linux-c -*- *
2 *
3 * ALSA driver for the digigram lx6464es interface
4 *
5 * Copyright (c) 2008, 2009 Tim Blechmann <tim@klingt.org>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
21 * Boston, MA 02111-1307, USA.
22 *
23 */
24
25#include <linux/module.h>
26#include <linux/init.h>
27#include <linux/pci.h>
28#include <linux/delay.h>
29
30#include <sound/initval.h>
31#include <sound/control.h>
32#include <sound/info.h>
33
34#include "lx6464es.h"
35
36MODULE_AUTHOR("Tim Blechmann");
37MODULE_LICENSE("GPL");
38MODULE_DESCRIPTION("digigram lx6464es");
39MODULE_SUPPORTED_DEVICE("{digigram lx6464es{}}");
40
41
42static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
43static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
44static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
45
46static const char card_name[] = "LX6464ES";
47
48
49#define PCI_DEVICE_ID_PLX_LX6464ES PCI_DEVICE_ID_PLX_9056
50
51static struct pci_device_id snd_lx6464es_ids[] = {
52 { PCI_DEVICE(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_LX6464ES),
53 .subvendor = PCI_VENDOR_ID_DIGIGRAM,
54 .subdevice = PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ES_SERIAL_SUBSYSTEM
55 }, /* LX6464ES */
56 { PCI_DEVICE(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_LX6464ES),
57 .subvendor = PCI_VENDOR_ID_DIGIGRAM,
58 .subdevice = PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ES_CAE_SERIAL_SUBSYSTEM
59 }, /* LX6464ES-CAE */
60 { 0, },
61};
62
63MODULE_DEVICE_TABLE(pci, snd_lx6464es_ids);
64
65
66
67/* PGO pour USERo dans le registre pci_0x06/loc_0xEC */
68#define CHIPSC_RESET_XILINX (1L<<16)
69
70
71/* alsa callbacks */
72static struct snd_pcm_hardware lx_caps = {
73 .info = (SNDRV_PCM_INFO_MMAP |
74 SNDRV_PCM_INFO_INTERLEAVED |
75 SNDRV_PCM_INFO_MMAP_VALID |
76 SNDRV_PCM_INFO_SYNC_START),
77 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
78 SNDRV_PCM_FMTBIT_S16_BE |
79 SNDRV_PCM_FMTBIT_S24_3LE |
80 SNDRV_PCM_FMTBIT_S24_3BE),
81 .rates = (SNDRV_PCM_RATE_CONTINUOUS |
82 SNDRV_PCM_RATE_8000_192000),
83 .rate_min = 8000,
84 .rate_max = 192000,
85 .channels_min = 2,
86 .channels_max = 64,
87 .buffer_bytes_max = 64*2*3*MICROBLAZE_IBL_MAX*MAX_STREAM_BUFFER,
88 .period_bytes_min = (2*2*MICROBLAZE_IBL_MIN*2),
89 .period_bytes_max = (4*64*MICROBLAZE_IBL_MAX*MAX_STREAM_BUFFER),
90 .periods_min = 2,
91 .periods_max = MAX_STREAM_BUFFER,
92};
93
94static int lx_set_granularity(struct lx6464es *chip, u32 gran);
95
96
97static int lx_hardware_open(struct lx6464es *chip,
98 struct snd_pcm_substream *substream)
99{
100 int err = 0;
101 struct snd_pcm_runtime *runtime = substream->runtime;
102 int channels = runtime->channels;
103 int is_capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
104
105 snd_pcm_uframes_t period_size = runtime->period_size;
106
107 snd_printd(LXP "allocating pipe for %d channels\n", channels);
108 err = lx_pipe_allocate(chip, 0, is_capture, channels);
109 if (err < 0) {
110 snd_printk(KERN_ERR LXP "allocating pipe failed\n");
111 return err;
112 }
113
114 err = lx_set_granularity(chip, period_size);
115 if (err < 0) {
116 snd_printk(KERN_ERR LXP "setting granularity to %ld failed\n",
117 period_size);
118 return err;
119 }
120
121 return 0;
122}
123
124static int lx_hardware_start(struct lx6464es *chip,
125 struct snd_pcm_substream *substream)
126{
127 int err = 0;
128 struct snd_pcm_runtime *runtime = substream->runtime;
129 int is_capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
130
131 snd_printd(LXP "setting stream format\n");
132 err = lx_stream_set_format(chip, runtime, 0, is_capture);
133 if (err < 0) {
134 snd_printk(KERN_ERR LXP "setting stream format failed\n");
135 return err;
136 }
137
138 snd_printd(LXP "starting pipe\n");
139 err = lx_pipe_start(chip, 0, is_capture);
140 if (err < 0) {
141 snd_printk(KERN_ERR LXP "starting pipe failed\n");
142 return err;
143 }
144
145 snd_printd(LXP "waiting for pipe to start\n");
146 err = lx_pipe_wait_for_start(chip, 0, is_capture);
147 if (err < 0) {
148 snd_printk(KERN_ERR LXP "waiting for pipe failed\n");
149 return err;
150 }
151
152 return err;
153}
154
155
156static int lx_hardware_stop(struct lx6464es *chip,
157 struct snd_pcm_substream *substream)
158{
159 int err = 0;
160 int is_capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
161
162 snd_printd(LXP "pausing pipe\n");
163 err = lx_pipe_pause(chip, 0, is_capture);
164 if (err < 0) {
165 snd_printk(KERN_ERR LXP "pausing pipe failed\n");
166 return err;
167 }
168
169 snd_printd(LXP "waiting for pipe to become idle\n");
170 err = lx_pipe_wait_for_idle(chip, 0, is_capture);
171 if (err < 0) {
172 snd_printk(KERN_ERR LXP "waiting for pipe failed\n");
173 return err;
174 }
175
176 snd_printd(LXP "stopping pipe\n");
177 err = lx_pipe_stop(chip, 0, is_capture);
178 if (err < 0) {
179 snd_printk(LXP "stopping pipe failed\n");
180 return err;
181 }
182
183 return err;
184}
185
186
187static int lx_hardware_close(struct lx6464es *chip,
188 struct snd_pcm_substream *substream)
189{
190 int err = 0;
191 int is_capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
192
193 snd_printd(LXP "releasing pipe\n");
194 err = lx_pipe_release(chip, 0, is_capture);
195 if (err < 0) {
196 snd_printk(LXP "releasing pipe failed\n");
197 return err;
198 }
199
200 return err;
201}
202
203
204static int lx_pcm_open(struct snd_pcm_substream *substream)
205{
206 struct lx6464es *chip = snd_pcm_substream_chip(substream);
207 struct snd_pcm_runtime *runtime = substream->runtime;
208 int err = 0;
209 int board_rate;
210
211 snd_printdd("->lx_pcm_open\n");
212 mutex_lock(&chip->setup_mutex);
213
214 /* copy the struct snd_pcm_hardware struct */
215 runtime->hw = lx_caps;
216
217#if 0
218 /* buffer-size should better be multiple of period-size */
219 err = snd_pcm_hw_constraint_integer(runtime,
220 SNDRV_PCM_HW_PARAM_PERIODS);
221 if (err < 0) {
222 snd_printk(KERN_WARNING LXP "could not constrain periods\n");
223 goto exit;
224 }
225#endif
226
227 /* the clock rate cannot be changed */
228 board_rate = chip->board_sample_rate;
229 err = snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_RATE,
230 board_rate, board_rate);
231
232 if (err < 0) {
233 snd_printk(KERN_WARNING LXP "could not constrain periods\n");
234 goto exit;
235 }
236
237 /* constrain period size */
238 err = snd_pcm_hw_constraint_minmax(runtime,
239 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
240 MICROBLAZE_IBL_MIN,
241 MICROBLAZE_IBL_MAX);
242 if (err < 0) {
243 snd_printk(KERN_WARNING LXP
244 "could not constrain period size\n");
245 goto exit;
246 }
247
248 snd_pcm_hw_constraint_step(runtime, 0,
249 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 32);
250
251 snd_pcm_set_sync(substream);
252 err = 0;
253
254exit:
255 runtime->private_data = chip;
256
257 mutex_unlock(&chip->setup_mutex);
258 snd_printdd("<-lx_pcm_open, %d\n", err);
259 return err;
260}
261
262static int lx_pcm_close(struct snd_pcm_substream *substream)
263{
264 int err = 0;
265 snd_printdd("->lx_pcm_close\n");
266 return err;
267}
268
269static snd_pcm_uframes_t lx_pcm_stream_pointer(struct snd_pcm_substream
270 *substream)
271{
272 struct lx6464es *chip = snd_pcm_substream_chip(substream);
273 snd_pcm_uframes_t pos;
274 unsigned long flags;
275 int is_capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
276
277 struct lx_stream *lx_stream = is_capture ? &chip->capture_stream :
278 &chip->playback_stream;
279
280 snd_printdd("->lx_pcm_stream_pointer\n");
281
282 spin_lock_irqsave(&chip->lock, flags);
283 pos = lx_stream->frame_pos * substream->runtime->period_size;
284 spin_unlock_irqrestore(&chip->lock, flags);
285
286 snd_printdd(LXP "stream_pointer at %ld\n", pos);
287 return pos;
288}
289
290static int lx_pcm_prepare(struct snd_pcm_substream *substream)
291{
292 struct lx6464es *chip = snd_pcm_substream_chip(substream);
293 int err = 0;
294 const int is_capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
295
296 snd_printdd("->lx_pcm_prepare\n");
297
298 mutex_lock(&chip->setup_mutex);
299
300 if (chip->hardware_running[is_capture]) {
301 err = lx_hardware_stop(chip, substream);
302 if (err < 0) {
303 snd_printk(KERN_ERR LXP "failed to stop hardware. "
304 "Error code %d\n", err);
305 goto exit;
306 }
307
308 err = lx_hardware_close(chip, substream);
309 if (err < 0) {
310 snd_printk(KERN_ERR LXP "failed to close hardware. "
311 "Error code %d\n", err);
312 goto exit;
313 }
314 }
315
316 snd_printd(LXP "opening hardware\n");
317 err = lx_hardware_open(chip, substream);
318 if (err < 0) {
319 snd_printk(KERN_ERR LXP "failed to open hardware. "
320 "Error code %d\n", err);
321 goto exit;
322 }
323
324 err = lx_hardware_start(chip, substream);
325 if (err < 0) {
326 snd_printk(KERN_ERR LXP "failed to start hardware. "
327 "Error code %d\n", err);
328 goto exit;
329 }
330
331 chip->hardware_running[is_capture] = 1;
332
333 if (chip->board_sample_rate != substream->runtime->rate) {
334 if (!err)
335 chip->board_sample_rate = substream->runtime->rate;
336 }
337
338exit:
339 mutex_unlock(&chip->setup_mutex);
340 return err;
341}
342
343static int lx_pcm_hw_params(struct snd_pcm_substream *substream,
344 struct snd_pcm_hw_params *hw_params, int is_capture)
345{
346 struct lx6464es *chip = snd_pcm_substream_chip(substream);
347 int err = 0;
348
349 snd_printdd("->lx_pcm_hw_params\n");
350
351 mutex_lock(&chip->setup_mutex);
352
353 /* set dma buffer */
354 err = snd_pcm_lib_malloc_pages(substream,
355 params_buffer_bytes(hw_params));
356
357 if (is_capture)
358 chip->capture_stream.stream = substream;
359 else
360 chip->playback_stream.stream = substream;
361
362 mutex_unlock(&chip->setup_mutex);
363 return err;
364}
365
366static int lx_pcm_hw_params_playback(struct snd_pcm_substream *substream,
367 struct snd_pcm_hw_params *hw_params)
368{
369 return lx_pcm_hw_params(substream, hw_params, 0);
370}
371
372static int lx_pcm_hw_params_capture(struct snd_pcm_substream *substream,
373 struct snd_pcm_hw_params *hw_params)
374{
375 return lx_pcm_hw_params(substream, hw_params, 1);
376}
377
378static int lx_pcm_hw_free(struct snd_pcm_substream *substream)
379{
380 struct lx6464es *chip = snd_pcm_substream_chip(substream);
381 int err = 0;
382 int is_capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
383
384 snd_printdd("->lx_pcm_hw_free\n");
385 mutex_lock(&chip->setup_mutex);
386
387 if (chip->hardware_running[is_capture]) {
388 err = lx_hardware_stop(chip, substream);
389 if (err < 0) {
390 snd_printk(KERN_ERR LXP "failed to stop hardware. "
391 "Error code %d\n", err);
392 goto exit;
393 }
394
395 err = lx_hardware_close(chip, substream);
396 if (err < 0) {
397 snd_printk(KERN_ERR LXP "failed to close hardware. "
398 "Error code %d\n", err);
399 goto exit;
400 }
401
402 chip->hardware_running[is_capture] = 0;
403 }
404
405 err = snd_pcm_lib_free_pages(substream);
406
407 if (is_capture)
408 chip->capture_stream.stream = 0;
409 else
410 chip->playback_stream.stream = 0;
411
412exit:
413 mutex_unlock(&chip->setup_mutex);
414 return err;
415}
416
417static void lx_trigger_start(struct lx6464es *chip, struct lx_stream *lx_stream)
418{
419 struct snd_pcm_substream *substream = lx_stream->stream;
420 const int is_capture = lx_stream->is_capture;
421
422 int err;
423
424 const u32 channels = substream->runtime->channels;
425 const u32 bytes_per_frame = channels * 3;
426 const u32 period_size = substream->runtime->period_size;
427 const u32 periods = substream->runtime->periods;
428 const u32 period_bytes = period_size * bytes_per_frame;
429
430 dma_addr_t buf = substream->dma_buffer.addr;
431 int i;
432
433 u32 needed, freed;
434 u32 size_array[5];
435
436 for (i = 0; i != periods; ++i) {
437 u32 buffer_index = 0;
438
439 err = lx_buffer_ask(chip, 0, is_capture, &needed, &freed,
440 size_array);
441 snd_printdd(LXP "starting: needed %d, freed %d\n",
442 needed, freed);
443
444 err = lx_buffer_give(chip, 0, is_capture, period_bytes,
445 lower_32_bits(buf), upper_32_bits(buf),
446 &buffer_index);
447
448 snd_printdd(LXP "starting: buffer index %x on %p (%d bytes)\n",
449 buffer_index, (void *)buf, period_bytes);
450 buf += period_bytes;
451 }
452
453 err = lx_buffer_ask(chip, 0, is_capture, &needed, &freed, size_array);
454 snd_printdd(LXP "starting: needed %d, freed %d\n", needed, freed);
455
456 snd_printd(LXP "starting: starting stream\n");
457 err = lx_stream_start(chip, 0, is_capture);
458 if (err < 0)
459 snd_printk(KERN_ERR LXP "couldn't start stream\n");
460 else
461 lx_stream->status = LX_STREAM_STATUS_RUNNING;
462
463 lx_stream->frame_pos = 0;
464}
465
466static void lx_trigger_stop(struct lx6464es *chip, struct lx_stream *lx_stream)
467{
468 const int is_capture = lx_stream->is_capture;
469 int err;
470
471 snd_printd(LXP "stopping: stopping stream\n");
472 err = lx_stream_stop(chip, 0, is_capture);
473 if (err < 0)
474 snd_printk(KERN_ERR LXP "couldn't stop stream\n");
475 else
476 lx_stream->status = LX_STREAM_STATUS_FREE;
477
478}
479
480static void lx_trigger_tasklet_dispatch_stream(struct lx6464es *chip,
481 struct lx_stream *lx_stream)
482{
483 switch (lx_stream->status) {
484 case LX_STREAM_STATUS_SCHEDULE_RUN:
485 lx_trigger_start(chip, lx_stream);
486 break;
487
488 case LX_STREAM_STATUS_SCHEDULE_STOP:
489 lx_trigger_stop(chip, lx_stream);
490 break;
491
492 default:
493 break;
494 }
495}
496
497static void lx_trigger_tasklet(unsigned long data)
498{
499 struct lx6464es *chip = (struct lx6464es *)data;
500 unsigned long flags;
501
502 snd_printdd("->lx_trigger_tasklet\n");
503
504 spin_lock_irqsave(&chip->lock, flags);
505 lx_trigger_tasklet_dispatch_stream(chip, &chip->capture_stream);
506 lx_trigger_tasklet_dispatch_stream(chip, &chip->playback_stream);
507 spin_unlock_irqrestore(&chip->lock, flags);
508}
509
510static int lx_pcm_trigger_dispatch(struct lx6464es *chip,
511 struct lx_stream *lx_stream, int cmd)
512{
513 int err = 0;
514
515 switch (cmd) {
516 case SNDRV_PCM_TRIGGER_START:
517 lx_stream->status = LX_STREAM_STATUS_SCHEDULE_RUN;
518 break;
519
520 case SNDRV_PCM_TRIGGER_STOP:
521 lx_stream->status = LX_STREAM_STATUS_SCHEDULE_STOP;
522 break;
523
524 default:
525 err = -EINVAL;
526 goto exit;
527 }
528 tasklet_schedule(&chip->trigger_tasklet);
529
530exit:
531 return err;
532}
533
534
535static int lx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
536{
537 struct lx6464es *chip = snd_pcm_substream_chip(substream);
538 const int is_capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
539 struct lx_stream *stream = is_capture ? &chip->capture_stream :
540 &chip->playback_stream;
541
542 snd_printdd("->lx_pcm_trigger\n");
543
544 return lx_pcm_trigger_dispatch(chip, stream, cmd);
545}
546
547static int snd_lx6464es_free(struct lx6464es *chip)
548{
549 snd_printdd("->snd_lx6464es_free\n");
550
551 lx_irq_disable(chip);
552
553 if (chip->irq >= 0)
554 free_irq(chip->irq, chip);
555
556 iounmap(chip->port_dsp_bar);
557 ioport_unmap(chip->port_plx_remapped);
558
559 pci_release_regions(chip->pci);
560 pci_disable_device(chip->pci);
561
562 kfree(chip);
563
564 return 0;
565}
566
567static int snd_lx6464es_dev_free(struct snd_device *device)
568{
569 return snd_lx6464es_free(device->device_data);
570}
571
572/* reset the dsp during initialization */
573static int __devinit lx_init_xilinx_reset(struct lx6464es *chip)
574{
575 int i;
576 u32 plx_reg = lx_plx_reg_read(chip, ePLX_CHIPSC);
577
578 snd_printdd("->lx_init_xilinx_reset\n");
579
580 /* activate reset of xilinx */
581 plx_reg &= ~CHIPSC_RESET_XILINX;
582
583 lx_plx_reg_write(chip, ePLX_CHIPSC, plx_reg);
584 msleep(1);
585
586 lx_plx_reg_write(chip, ePLX_MBOX3, 0);
587 msleep(1);
588
589 plx_reg |= CHIPSC_RESET_XILINX;
590 lx_plx_reg_write(chip, ePLX_CHIPSC, plx_reg);
591
592 /* deactivate reset of xilinx */
593 for (i = 0; i != 100; ++i) {
594 u32 reg_mbox3;
595 msleep(10);
596 reg_mbox3 = lx_plx_reg_read(chip, ePLX_MBOX3);
597 if (reg_mbox3) {
598 snd_printd(LXP "xilinx reset done\n");
599 snd_printdd(LXP "xilinx took %d loops\n", i);
600 break;
601 }
602 }
603
604 /* todo: add some error handling? */
605
606 /* clear mr */
607 lx_dsp_reg_write(chip, eReg_CSM, 0);
608
609 /* le xilinx ES peut ne pas etre encore pret, on attend. */
610 msleep(600);
611
612 return 0;
613}
614
615static int __devinit lx_init_xilinx_test(struct lx6464es *chip)
616{
617 u32 reg;
618
619 snd_printdd("->lx_init_xilinx_test\n");
620
621 /* TEST if we have access to Xilinx/MicroBlaze */
622 lx_dsp_reg_write(chip, eReg_CSM, 0);
623
624 reg = lx_dsp_reg_read(chip, eReg_CSM);
625
626 if (reg) {
627 snd_printk(KERN_ERR LXP "Problem: Reg_CSM %x.\n", reg);
628
629 /* PCI9056_SPACE0_REMAP */
630 lx_plx_reg_write(chip, ePLX_PCICR, 1);
631
632 reg = lx_dsp_reg_read(chip, eReg_CSM);
633 if (reg) {
634 snd_printk(KERN_ERR LXP "Error: Reg_CSM %x.\n", reg);
635 return -EAGAIN; /* seems to be appropriate */
636 }
637 }
638
639 snd_printd(LXP "Xilinx/MicroBlaze access test successful\n");
640
641 return 0;
642}
643
644/* initialize ethersound */
645static int __devinit lx_init_ethersound_config(struct lx6464es *chip)
646{
647 int i;
648 u32 orig_conf_es = lx_dsp_reg_read(chip, eReg_CONFES);
649
650 u32 default_conf_es = (64 << IOCR_OUTPUTS_OFFSET) |
651 (64 << IOCR_INPUTS_OFFSET) |
652 (FREQ_RATIO_SINGLE_MODE << FREQ_RATIO_OFFSET);
653
654 u32 conf_es = (orig_conf_es & CONFES_READ_PART_MASK)
655 | (default_conf_es & CONFES_WRITE_PART_MASK);
656
657 snd_printdd("->lx_init_ethersound\n");
658
659 chip->freq_ratio = FREQ_RATIO_SINGLE_MODE;
660
661 /*
662 * write it to the card !
663 * this actually kicks the ES xilinx, the first time since poweron.
664 * the MAC address in the Reg_ADMACESMSB Reg_ADMACESLSB registers
665 * is not ready before this is done, and the bit 2 in Reg_CSES is set.
666 * */
667 lx_dsp_reg_write(chip, eReg_CONFES, conf_es);
668
669 for (i = 0; i != 1000; ++i) {
670 if (lx_dsp_reg_read(chip, eReg_CSES) & 4) {
671 snd_printd(LXP "ethersound initialized after %dms\n",
672 i);
673 goto ethersound_initialized;
674 }
675 msleep(1);
676 }
677 snd_printk(KERN_WARNING LXP
678 "ethersound could not be initialized after %dms\n", i);
679 return -ETIMEDOUT;
680
681 ethersound_initialized:
682 snd_printd(LXP "ethersound initialized\n");
683 return 0;
684}
685
686static int __devinit lx_init_get_version_features(struct lx6464es *chip)
687{
688 u32 dsp_version;
689
690 int err;
691
692 snd_printdd("->lx_init_get_version_features\n");
693
694 err = lx_dsp_get_version(chip, &dsp_version);
695
696 if (err == 0) {
697 u32 freq;
698
699 snd_printk(LXP "DSP version: V%02d.%02d #%d\n",
700 (dsp_version>>16) & 0xff, (dsp_version>>8) & 0xff,
701 dsp_version & 0xff);
702
703 /* later: what firmware version do we expect? */
704
705 /* retrieve Play/Rec features */
706 /* done here because we may have to handle alternate
707 * DSP files. */
708 /* later */
709
710 /* init the EtherSound sample rate */
711 err = lx_dsp_get_clock_frequency(chip, &freq);
712 if (err == 0)
713 chip->board_sample_rate = freq;
714 snd_printd(LXP "actual clock frequency %d\n", freq);
715 } else {
716 snd_printk(KERN_ERR LXP "DSP corrupted \n");
717 err = -EAGAIN;
718 }
719
720 return err;
721}
722
723static int lx_set_granularity(struct lx6464es *chip, u32 gran)
724{
725 int err = 0;
726 u32 snapped_gran = MICROBLAZE_IBL_MIN;
727
728 snd_printdd("->lx_set_granularity\n");
729
730 /* blocksize is a power of 2 */
731 while ((snapped_gran < gran) &&
732 (snapped_gran < MICROBLAZE_IBL_MAX)) {
733 snapped_gran *= 2;
734 }
735
736 if (snapped_gran == chip->pcm_granularity)
737 return 0;
738
739 err = lx_dsp_set_granularity(chip, snapped_gran);
740 if (err < 0) {
741 snd_printk(KERN_WARNING LXP "could not set granularity\n");
742 err = -EAGAIN;
743 }
744
745 if (snapped_gran != gran)
746 snd_printk(LXP "snapped blocksize to %d\n", snapped_gran);
747
748 snd_printd(LXP "set blocksize on board %d\n", snapped_gran);
749 chip->pcm_granularity = snapped_gran;
750
751 return err;
752}
753
754/* initialize and test the xilinx dsp chip */
755static int __devinit lx_init_dsp(struct lx6464es *chip)
756{
757 int err;
758 u8 mac_address[6];
759 int i;
760
761 snd_printdd("->lx_init_dsp\n");
762
763 snd_printd(LXP "initialize board\n");
764 err = lx_init_xilinx_reset(chip);
765 if (err)
766 return err;
767
768 snd_printd(LXP "testing board\n");
769 err = lx_init_xilinx_test(chip);
770 if (err)
771 return err;
772
773 snd_printd(LXP "initialize ethersound configuration\n");
774 err = lx_init_ethersound_config(chip);
775 if (err)
776 return err;
777
778 lx_irq_enable(chip);
779
780 /** \todo the mac address should be ready by not, but it isn't,
781 * so we wait for it */
782 for (i = 0; i != 1000; ++i) {
783 err = lx_dsp_get_mac(chip, mac_address);
784 if (err)
785 return err;
786 if (mac_address[0] || mac_address[1] || mac_address[2] ||
787 mac_address[3] || mac_address[4] || mac_address[5])
788 goto mac_ready;
789 msleep(1);
790 }
791 return -ETIMEDOUT;
792
793mac_ready:
794 snd_printd(LXP "mac address ready read after: %dms\n", i);
795 snd_printk(LXP "mac address: %02X.%02X.%02X.%02X.%02X.%02X\n",
796 mac_address[0], mac_address[1], mac_address[2],
797 mac_address[3], mac_address[4], mac_address[5]);
798
799 err = lx_init_get_version_features(chip);
800 if (err)
801 return err;
802
803 lx_set_granularity(chip, MICROBLAZE_IBL_DEFAULT);
804
805 chip->playback_mute = 0;
806
807 return err;
808}
809
810static struct snd_pcm_ops lx_ops_playback = {
811 .open = lx_pcm_open,
812 .close = lx_pcm_close,
813 .ioctl = snd_pcm_lib_ioctl,
814 .prepare = lx_pcm_prepare,
815 .hw_params = lx_pcm_hw_params_playback,
816 .hw_free = lx_pcm_hw_free,
817 .trigger = lx_pcm_trigger,
818 .pointer = lx_pcm_stream_pointer,
819};
820
821static struct snd_pcm_ops lx_ops_capture = {
822 .open = lx_pcm_open,
823 .close = lx_pcm_close,
824 .ioctl = snd_pcm_lib_ioctl,
825 .prepare = lx_pcm_prepare,
826 .hw_params = lx_pcm_hw_params_capture,
827 .hw_free = lx_pcm_hw_free,
828 .trigger = lx_pcm_trigger,
829 .pointer = lx_pcm_stream_pointer,
830};
831
832static int __devinit lx_pcm_create(struct lx6464es *chip)
833{
834 int err;
835 struct snd_pcm *pcm;
836
837 u32 size = 64 * /* channels */
838 3 * /* 24 bit samples */
839 MAX_STREAM_BUFFER * /* periods */
840 MICROBLAZE_IBL_MAX * /* frames per period */
841 2; /* duplex */
842
843 size = PAGE_ALIGN(size);
844
845 /* hardcoded device name & channel count */
846 err = snd_pcm_new(chip->card, (char *)card_name, 0,
847 1, 1, &pcm);
848
849 pcm->private_data = chip;
850
851 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &lx_ops_playback);
852 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &lx_ops_capture);
853
854 pcm->info_flags = 0;
855 strcpy(pcm->name, card_name);
856
857 err = snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
858 snd_dma_pci_data(chip->pci),
859 size, size);
860 if (err < 0)
861 return err;
862
863 chip->pcm = pcm;
864 chip->capture_stream.is_capture = 1;
865
866 return 0;
867}
868
869static int lx_control_playback_info(struct snd_kcontrol *kcontrol,
870 struct snd_ctl_elem_info *uinfo)
871{
872 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
873 uinfo->count = 1;
874 uinfo->value.integer.min = 0;
875 uinfo->value.integer.max = 1;
876 return 0;
877}
878
879static int lx_control_playback_get(struct snd_kcontrol *kcontrol,
880 struct snd_ctl_elem_value *ucontrol)
881{
882 struct lx6464es *chip = snd_kcontrol_chip(kcontrol);
883 ucontrol->value.integer.value[0] = chip->playback_mute;
884 return 0;
885}
886
887static int lx_control_playback_put(struct snd_kcontrol *kcontrol,
888 struct snd_ctl_elem_value *ucontrol)
889{
890 struct lx6464es *chip = snd_kcontrol_chip(kcontrol);
891 int changed = 0;
892 int current_value = chip->playback_mute;
893
894 if (current_value != ucontrol->value.integer.value[0]) {
895 lx_level_unmute(chip, 0, !current_value);
896 chip->playback_mute = !current_value;
897 changed = 1;
898 }
899 return changed;
900}
901
902static struct snd_kcontrol_new lx_control_playback_switch __devinitdata = {
903 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
904 .name = "PCM Playback Switch",
905 .index = 0,
906 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
907 .private_value = 0,
908 .info = lx_control_playback_info,
909 .get = lx_control_playback_get,
910 .put = lx_control_playback_put
911};
912
913
914
915static void lx_proc_levels_read(struct snd_info_entry *entry,
916 struct snd_info_buffer *buffer)
917{
918 u32 levels[64];
919 int err;
920 int i, j;
921 struct lx6464es *chip = entry->private_data;
922
923 snd_iprintf(buffer, "capture levels:\n");
924 err = lx_level_peaks(chip, 1, 64, levels);
925 if (err < 0)
926 return;
927
928 for (i = 0; i != 8; ++i) {
929 for (j = 0; j != 8; ++j)
930 snd_iprintf(buffer, "%08x ", levels[i*8+j]);
931 snd_iprintf(buffer, "\n");
932 }
933
934 snd_iprintf(buffer, "\nplayback levels:\n");
935
936 err = lx_level_peaks(chip, 0, 64, levels);
937 if (err < 0)
938 return;
939
940 for (i = 0; i != 8; ++i) {
941 for (j = 0; j != 8; ++j)
942 snd_iprintf(buffer, "%08x ", levels[i*8+j]);
943 snd_iprintf(buffer, "\n");
944 }
945
946 snd_iprintf(buffer, "\n");
947}
948
949static int __devinit lx_proc_create(struct snd_card *card, struct lx6464es *chip)
950{
951 struct snd_info_entry *entry;
952 int err = snd_card_proc_new(card, "levels", &entry);
953 if (err < 0)
954 return err;
955
956 snd_info_set_text_ops(entry, chip, lx_proc_levels_read);
957 return 0;
958}
959
960
961static int __devinit snd_lx6464es_create(struct snd_card *card,
962 struct pci_dev *pci,
963 struct lx6464es **rchip)
964{
965 struct lx6464es *chip;
966 int err;
967
968 static struct snd_device_ops ops = {
969 .dev_free = snd_lx6464es_dev_free,
970 };
971
972 snd_printdd("->snd_lx6464es_create\n");
973
974 *rchip = NULL;
975
976 /* enable PCI device */
977 err = pci_enable_device(pci);
978 if (err < 0)
979 return err;
980
981 pci_set_master(pci);
982
983 /* check if we can restrict PCI DMA transfers to 32 bits */
984 err = pci_set_dma_mask(pci, DMA_32BIT_MASK);
985 if (err < 0) {
986 snd_printk(KERN_ERR "architecture does not support "
987 "32bit PCI busmaster DMA\n");
988 pci_disable_device(pci);
989 return -ENXIO;
990 }
991
992 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
993 if (chip == NULL) {
994 err = -ENOMEM;
995 goto alloc_failed;
996 }
997
998 chip->card = card;
999 chip->pci = pci;
1000 chip->irq = -1;
1001
1002 /* initialize synchronization structs */
1003 spin_lock_init(&chip->lock);
1004 spin_lock_init(&chip->msg_lock);
1005 mutex_init(&chip->setup_mutex);
1006 tasklet_init(&chip->trigger_tasklet, lx_trigger_tasklet,
1007 (unsigned long)chip);
1008 tasklet_init(&chip->tasklet_capture, lx_tasklet_capture,
1009 (unsigned long)chip);
1010 tasklet_init(&chip->tasklet_playback, lx_tasklet_playback,
1011 (unsigned long)chip);
1012
1013 /* request resources */
1014 err = pci_request_regions(pci, card_name);
1015 if (err < 0)
1016 goto request_regions_failed;
1017
1018 /* plx port */
1019 chip->port_plx = pci_resource_start(pci, 1);
1020 chip->port_plx_remapped = ioport_map(chip->port_plx,
1021 pci_resource_len(pci, 1));
1022
1023 /* dsp port */
1024 chip->port_dsp_bar = pci_ioremap_bar(pci, 2);
1025
1026 err = request_irq(pci->irq, lx_interrupt, IRQF_SHARED,
1027 card_name, chip);
1028 if (err) {
1029 snd_printk(KERN_ERR LXP "unable to grab IRQ %d\n", pci->irq);
1030 goto request_irq_failed;
1031 }
1032 chip->irq = pci->irq;
1033
1034 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1035 if (err < 0)
1036 goto device_new_failed;
1037
1038 err = lx_init_dsp(chip);
1039 if (err < 0) {
1040 snd_printk(KERN_ERR LXP "error during DSP initialization\n");
1041 return err;
1042 }
1043
1044 err = lx_pcm_create(chip);
1045 if (err < 0)
1046 return err;
1047
1048 err = lx_proc_create(card, chip);
1049 if (err < 0)
1050 return err;
1051
1052 err = snd_ctl_add(card, snd_ctl_new1(&lx_control_playback_switch,
1053 chip));
1054 if (err < 0)
1055 return err;
1056
1057 snd_card_set_dev(card, &pci->dev);
1058
1059 *rchip = chip;
1060 return 0;
1061
1062device_new_failed:
1063 free_irq(pci->irq, chip);
1064
1065request_irq_failed:
1066 pci_release_regions(pci);
1067
1068request_regions_failed:
1069 kfree(chip);
1070
1071alloc_failed:
1072 pci_disable_device(pci);
1073
1074 return err;
1075}
1076
1077static int __devinit snd_lx6464es_probe(struct pci_dev *pci,
1078 const struct pci_device_id *pci_id)
1079{
1080 static int dev;
1081 struct snd_card *card;
1082 struct lx6464es *chip;
1083 int err;
1084
1085 snd_printdd("->snd_lx6464es_probe\n");
1086
1087 if (dev >= SNDRV_CARDS)
1088 return -ENODEV;
1089 if (!enable[dev]) {
1090 dev++;
1091 return -ENOENT;
1092 }
1093
1094 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
1095 if (err < 0)
1096 return err;
1097
1098 err = snd_lx6464es_create(card, pci, &chip);
1099 if (err < 0) {
1100 snd_printk(KERN_ERR LXP "error during snd_lx6464es_create\n");
1101 goto out_free;
1102 }
1103
1104 strcpy(card->driver, "lx6464es");
1105 strcpy(card->shortname, "Digigram LX6464ES");
1106 sprintf(card->longname, "%s at 0x%lx, 0x%p, irq %i",
1107 card->shortname, chip->port_plx,
1108 chip->port_dsp_bar, chip->irq);
1109
1110 err = snd_card_register(card);
1111 if (err < 0)
1112 goto out_free;
1113
1114 snd_printdd(LXP "initialization successful\n");
1115 pci_set_drvdata(pci, card);
1116 dev++;
1117 return 0;
1118
1119out_free:
1120 snd_card_free(card);
1121 return err;
1122
1123}
1124
1125static void __devexit snd_lx6464es_remove(struct pci_dev *pci)
1126{
1127 snd_card_free(pci_get_drvdata(pci));
1128 pci_set_drvdata(pci, NULL);
1129}
1130
1131
1132static struct pci_driver driver = {
1133 .name = "Digigram LX6464ES",
1134 .id_table = snd_lx6464es_ids,
1135 .probe = snd_lx6464es_probe,
1136 .remove = __devexit_p(snd_lx6464es_remove),
1137};
1138
1139
1140/* module initialization */
1141static int __init mod_init(void)
1142{
1143 return pci_register_driver(&driver);
1144}
1145
1146static void __exit mod_exit(void)
1147{
1148 pci_unregister_driver(&driver);
1149}
1150
1151module_init(mod_init);
1152module_exit(mod_exit);
diff --git a/sound/pci/lx6464es/lx6464es.h b/sound/pci/lx6464es/lx6464es.h
new file mode 100644
index 00000000000..012c010c8c8
--- /dev/null
+++ b/sound/pci/lx6464es/lx6464es.h
@@ -0,0 +1,114 @@
1/* -*- linux-c -*- *
2 *
3 * ALSA driver for the digigram lx6464es interface
4 *
5 * Copyright (c) 2009 Tim Blechmann <tim@klingt.org>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
21 * Boston, MA 02111-1307, USA.
22 *
23 */
24
25#ifndef LX6464ES_H
26#define LX6464ES_H
27
28#include <linux/spinlock.h>
29#include <asm/atomic.h>
30
31#include <sound/core.h>
32#include <sound/pcm.h>
33
34#include "lx_core.h"
35
36#define LXP "LX6464ES: "
37
38enum {
39 ES_cmd_free = 0, /* no command executing */
40 ES_cmd_processing = 1, /* execution of a read/write command */
41 ES_read_pending = 2, /* a asynchron read command is pending */
42 ES_read_finishing = 3, /* a read command has finished waiting (set by
43 * Interrupt or CancelIrp) */
44};
45
46enum lx_stream_status {
47 LX_STREAM_STATUS_FREE,
48/* LX_STREAM_STATUS_OPEN, */
49 LX_STREAM_STATUS_SCHEDULE_RUN,
50/* LX_STREAM_STATUS_STARTED, */
51 LX_STREAM_STATUS_RUNNING,
52 LX_STREAM_STATUS_SCHEDULE_STOP,
53/* LX_STREAM_STATUS_STOPPED, */
54/* LX_STREAM_STATUS_PAUSED */
55};
56
57
58struct lx_stream {
59 struct snd_pcm_substream *stream;
60 snd_pcm_uframes_t frame_pos;
61 enum lx_stream_status status; /* free, open, running, draining
62 * pause */
63 int is_capture:1;
64};
65
66
67struct lx6464es {
68 struct snd_card *card;
69 struct pci_dev *pci;
70 int irq;
71
72 spinlock_t lock; /* interrupt spinlock */
73 struct mutex setup_mutex; /* mutex used in hw_params, open
74 * and close */
75
76 struct tasklet_struct trigger_tasklet; /* trigger tasklet */
77 struct tasklet_struct tasklet_capture;
78 struct tasklet_struct tasklet_playback;
79
80 /* ports */
81 unsigned long port_plx; /* io port (size=256) */
82 void __iomem *port_plx_remapped; /* remapped plx port */
83 void __iomem *port_dsp_bar; /* memory port (32-bit,
84 * non-prefetchable,
85 * size=8K) */
86
87 /* messaging */
88 spinlock_t msg_lock; /* message spinlock */
89 atomic_t send_message_locked;
90 struct lx_rmh rmh;
91
92 /* configuration */
93 uint freq_ratio : 2;
94 uint playback_mute : 1;
95 uint hardware_running[2];
96 u32 board_sample_rate; /* sample rate read from
97 * board */
98 u32 sample_rate; /* our sample rate */
99 u16 pcm_granularity; /* board blocksize */
100
101 /* dma */
102 struct snd_dma_buffer capture_dma_buf;
103 struct snd_dma_buffer playback_dma_buf;
104
105 /* pcm */
106 struct snd_pcm *pcm;
107
108 /* streams */
109 struct lx_stream capture_stream;
110 struct lx_stream playback_stream;
111};
112
113
114#endif /* LX6464ES_H */
diff --git a/sound/pci/lx6464es/lx_core.c b/sound/pci/lx6464es/lx_core.c
new file mode 100644
index 00000000000..5812780d6e8
--- /dev/null
+++ b/sound/pci/lx6464es/lx_core.c
@@ -0,0 +1,1444 @@
1/* -*- linux-c -*- *
2 *
3 * ALSA driver for the digigram lx6464es interface
4 * low-level interface
5 *
6 * Copyright (c) 2009 Tim Blechmann <tim@klingt.org>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
21 * Boston, MA 02111-1307, USA.
22 *
23 */
24
25/* #define RMH_DEBUG 1 */
26
27#include <linux/module.h>
28#include <linux/pci.h>
29#include <linux/delay.h>
30
31#include "lx6464es.h"
32#include "lx_core.h"
33
34/* low-level register access */
35
36static const unsigned long dsp_port_offsets[] = {
37 0,
38 0x400,
39 0x401,
40 0x402,
41 0x403,
42 0x404,
43 0x405,
44 0x406,
45 0x407,
46 0x408,
47 0x409,
48 0x40a,
49 0x40b,
50 0x40c,
51
52 0x410,
53 0x411,
54 0x412,
55 0x413,
56 0x414,
57 0x415,
58 0x416,
59
60 0x420,
61 0x430,
62 0x431,
63 0x432,
64 0x433,
65 0x434,
66 0x440
67};
68
69static void __iomem *lx_dsp_register(struct lx6464es *chip, int port)
70{
71 void __iomem *base_address = chip->port_dsp_bar;
72 return base_address + dsp_port_offsets[port]*4;
73}
74
75unsigned long lx_dsp_reg_read(struct lx6464es *chip, int port)
76{
77 void __iomem *address = lx_dsp_register(chip, port);
78 return ioread32(address);
79}
80
81void lx_dsp_reg_readbuf(struct lx6464es *chip, int port, u32 *data, u32 len)
82{
83 void __iomem *address = lx_dsp_register(chip, port);
84 memcpy_fromio(data, address, len*sizeof(u32));
85}
86
87
88void lx_dsp_reg_write(struct lx6464es *chip, int port, unsigned data)
89{
90 void __iomem *address = lx_dsp_register(chip, port);
91 iowrite32(data, address);
92}
93
94void lx_dsp_reg_writebuf(struct lx6464es *chip, int port, const u32 *data,
95 u32 len)
96{
97 void __iomem *address = lx_dsp_register(chip, port);
98 memcpy_toio(address, data, len*sizeof(u32));
99}
100
101
102static const unsigned long plx_port_offsets[] = {
103 0x04,
104 0x40,
105 0x44,
106 0x48,
107 0x4c,
108 0x50,
109 0x54,
110 0x58,
111 0x5c,
112 0x64,
113 0x68,
114 0x6C
115};
116
117static void __iomem *lx_plx_register(struct lx6464es *chip, int port)
118{
119 void __iomem *base_address = chip->port_plx_remapped;
120 return base_address + plx_port_offsets[port];
121}
122
123unsigned long lx_plx_reg_read(struct lx6464es *chip, int port)
124{
125 void __iomem *address = lx_plx_register(chip, port);
126 return ioread32(address);
127}
128
129void lx_plx_reg_write(struct lx6464es *chip, int port, u32 data)
130{
131 void __iomem *address = lx_plx_register(chip, port);
132 iowrite32(data, address);
133}
134
135u32 lx_plx_mbox_read(struct lx6464es *chip, int mbox_nr)
136{
137 int index;
138
139 switch (mbox_nr) {
140 case 1:
141 index = ePLX_MBOX1; break;
142 case 2:
143 index = ePLX_MBOX2; break;
144 case 3:
145 index = ePLX_MBOX3; break;
146 case 4:
147 index = ePLX_MBOX4; break;
148 case 5:
149 index = ePLX_MBOX5; break;
150 case 6:
151 index = ePLX_MBOX6; break;
152 case 7:
153 index = ePLX_MBOX7; break;
154 case 0: /* reserved for HF flags */
155 snd_BUG();
156 default:
157 return 0xdeadbeef;
158 }
159
160 return lx_plx_reg_read(chip, index);
161}
162
163int lx_plx_mbox_write(struct lx6464es *chip, int mbox_nr, u32 value)
164{
165 int index = -1;
166
167 switch (mbox_nr) {
168 case 1:
169 index = ePLX_MBOX1; break;
170 case 3:
171 index = ePLX_MBOX3; break;
172 case 4:
173 index = ePLX_MBOX4; break;
174 case 5:
175 index = ePLX_MBOX5; break;
176 case 6:
177 index = ePLX_MBOX6; break;
178 case 7:
179 index = ePLX_MBOX7; break;
180 case 0: /* reserved for HF flags */
181 case 2: /* reserved for Pipe States
182 * the DSP keeps an image of it */
183 snd_BUG();
184 return -EBADRQC;
185 }
186
187 lx_plx_reg_write(chip, index, value);
188 return 0;
189}
190
191
192/* rmh */
193
194#ifdef CONFIG_SND_DEBUG
195#define CMD_NAME(a) a
196#else
197#define CMD_NAME(a) NULL
198#endif
199
200#define Reg_CSM_MR 0x00000002
201#define Reg_CSM_MC 0x00000001
202
203struct dsp_cmd_info {
204 u32 dcCodeOp; /* Op Code of the command (usually 1st 24-bits
205 * word).*/
206 u16 dcCmdLength; /* Command length in words of 24 bits.*/
207 u16 dcStatusType; /* Status type: 0 for fixed length, 1 for
208 * random. */
209 u16 dcStatusLength; /* Status length (if fixed).*/
210 char *dcOpName;
211};
212
213/*
214 Initialization and control data for the Microblaze interface
215 - OpCode:
216 the opcode field of the command set at the proper offset
217 - CmdLength
218 the number of command words
219 - StatusType
220 offset in the status registers: 0 means that the return value may be
221 different from 0, and must be read
222 - StatusLength
223 the number of status words (in addition to the return value)
224*/
225
226static struct dsp_cmd_info dsp_commands[] =
227{
228 { (CMD_00_INFO_DEBUG << OPCODE_OFFSET) , 1 /*custom*/
229 , 1 , 0 /**/ , CMD_NAME("INFO_DEBUG") },
230 { (CMD_01_GET_SYS_CFG << OPCODE_OFFSET) , 1 /**/
231 , 1 , 2 /**/ , CMD_NAME("GET_SYS_CFG") },
232 { (CMD_02_SET_GRANULARITY << OPCODE_OFFSET) , 1 /**/
233 , 1 , 0 /**/ , CMD_NAME("SET_GRANULARITY") },
234 { (CMD_03_SET_TIMER_IRQ << OPCODE_OFFSET) , 1 /**/
235 , 1 , 0 /**/ , CMD_NAME("SET_TIMER_IRQ") },
236 { (CMD_04_GET_EVENT << OPCODE_OFFSET) , 1 /**/
237 , 1 , 0 /*up to 10*/ , CMD_NAME("GET_EVENT") },
238 { (CMD_05_GET_PIPES << OPCODE_OFFSET) , 1 /**/
239 , 1 , 2 /*up to 4*/ , CMD_NAME("GET_PIPES") },
240 { (CMD_06_ALLOCATE_PIPE << OPCODE_OFFSET) , 1 /**/
241 , 0 , 0 /**/ , CMD_NAME("ALLOCATE_PIPE") },
242 { (CMD_07_RELEASE_PIPE << OPCODE_OFFSET) , 1 /**/
243 , 0 , 0 /**/ , CMD_NAME("RELEASE_PIPE") },
244 { (CMD_08_ASK_BUFFERS << OPCODE_OFFSET) , 1 /**/
245 , 1 , MAX_STREAM_BUFFER , CMD_NAME("ASK_BUFFERS") },
246 { (CMD_09_STOP_PIPE << OPCODE_OFFSET) , 1 /**/
247 , 0 , 0 /*up to 2*/ , CMD_NAME("STOP_PIPE") },
248 { (CMD_0A_GET_PIPE_SPL_COUNT << OPCODE_OFFSET) , 1 /**/
249 , 1 , 1 /*up to 2*/ , CMD_NAME("GET_PIPE_SPL_COUNT") },
250 { (CMD_0B_TOGGLE_PIPE_STATE << OPCODE_OFFSET) , 1 /*up to 5*/
251 , 1 , 0 /**/ , CMD_NAME("TOGGLE_PIPE_STATE") },
252 { (CMD_0C_DEF_STREAM << OPCODE_OFFSET) , 1 /*up to 4*/
253 , 1 , 0 /**/ , CMD_NAME("DEF_STREAM") },
254 { (CMD_0D_SET_MUTE << OPCODE_OFFSET) , 3 /**/
255 , 1 , 0 /**/ , CMD_NAME("SET_MUTE") },
256 { (CMD_0E_GET_STREAM_SPL_COUNT << OPCODE_OFFSET) , 1/**/
257 , 1 , 2 /**/ , CMD_NAME("GET_STREAM_SPL_COUNT") },
258 { (CMD_0F_UPDATE_BUFFER << OPCODE_OFFSET) , 3 /*up to 4*/
259 , 0 , 1 /**/ , CMD_NAME("UPDATE_BUFFER") },
260 { (CMD_10_GET_BUFFER << OPCODE_OFFSET) , 1 /**/
261 , 1 , 4 /**/ , CMD_NAME("GET_BUFFER") },
262 { (CMD_11_CANCEL_BUFFER << OPCODE_OFFSET) , 1 /**/
263 , 1 , 1 /*up to 4*/ , CMD_NAME("CANCEL_BUFFER") },
264 { (CMD_12_GET_PEAK << OPCODE_OFFSET) , 1 /**/
265 , 1 , 1 /**/ , CMD_NAME("GET_PEAK") },
266 { (CMD_13_SET_STREAM_STATE << OPCODE_OFFSET) , 1 /**/
267 , 1 , 0 /**/ , CMD_NAME("SET_STREAM_STATE") },
268};
269
270static void lx_message_init(struct lx_rmh *rmh, enum cmd_mb_opcodes cmd)
271{
272 snd_BUG_ON(cmd >= CMD_14_INVALID);
273
274 rmh->cmd[0] = dsp_commands[cmd].dcCodeOp;
275 rmh->cmd_len = dsp_commands[cmd].dcCmdLength;
276 rmh->stat_len = dsp_commands[cmd].dcStatusLength;
277 rmh->dsp_stat = dsp_commands[cmd].dcStatusType;
278 rmh->cmd_idx = cmd;
279 memset(&rmh->cmd[1], 0, (REG_CRM_NUMBER - 1) * sizeof(u32));
280
281#ifdef CONFIG_SND_DEBUG
282 memset(rmh->stat, 0, REG_CRM_NUMBER * sizeof(u32));
283#endif
284#ifdef RMH_DEBUG
285 rmh->cmd_idx = cmd;
286#endif
287}
288
289#ifdef RMH_DEBUG
290#define LXRMH "lx6464es rmh: "
291static void lx_message_dump(struct lx_rmh *rmh)
292{
293 u8 idx = rmh->cmd_idx;
294 int i;
295
296 snd_printk(LXRMH "command %s\n", dsp_commands[idx].dcOpName);
297
298 for (i = 0; i != rmh->cmd_len; ++i)
299 snd_printk(LXRMH "\tcmd[%d] %08x\n", i, rmh->cmd[i]);
300
301 for (i = 0; i != rmh->stat_len; ++i)
302 snd_printk(LXRMH "\tstat[%d]: %08x\n", i, rmh->stat[i]);
303 snd_printk("\n");
304}
305#else
306static inline void lx_message_dump(struct lx_rmh *rmh)
307{}
308#endif
309
310
311
312/* sleep 500 - 100 = 400 times 100us -> the timeout is >= 40 ms */
313#define XILINX_TIMEOUT_MS 40
314#define XILINX_POLL_NO_SLEEP 100
315#define XILINX_POLL_ITERATIONS 150
316
317#if 0 /* not used now */
318static int lx_message_send(struct lx6464es *chip, struct lx_rmh *rmh)
319{
320 u32 reg = ED_DSP_TIMED_OUT;
321 int dwloop;
322 int answer_received;
323
324 if (lx_dsp_reg_read(chip, eReg_CSM) & (Reg_CSM_MC | Reg_CSM_MR)) {
325 snd_printk(KERN_ERR LXP "PIOSendMessage eReg_CSM %x\n", reg);
326 return -EBUSY;
327 }
328
329 /* write command */
330 lx_dsp_reg_writebuf(chip, eReg_CRM1, rmh->cmd, rmh->cmd_len);
331
332 snd_BUG_ON(atomic_read(&chip->send_message_locked) != 0);
333 atomic_set(&chip->send_message_locked, 1);
334
335 /* MicoBlaze gogogo */
336 lx_dsp_reg_write(chip, eReg_CSM, Reg_CSM_MC);
337
338 /* wait for interrupt to answer */
339 for (dwloop = 0; dwloop != XILINX_TIMEOUT_MS; ++dwloop) {
340 answer_received = atomic_read(&chip->send_message_locked);
341 if (answer_received == 0)
342 break;
343 msleep(1);
344 }
345
346 if (answer_received == 0) {
347 /* in Debug mode verify Reg_CSM_MR */
348 snd_BUG_ON(!(lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR));
349
350 /* command finished, read status */
351 if (rmh->dsp_stat == 0)
352 reg = lx_dsp_reg_read(chip, eReg_CRM1);
353 else
354 reg = 0;
355 } else {
356 int i;
357 snd_printk(KERN_WARNING LXP "TIMEOUT lx_message_send! "
358 "Interrupts disabled?\n");
359
360 /* attente bit Reg_CSM_MR */
361 for (i = 0; i != XILINX_POLL_ITERATIONS; i++) {
362 if ((lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR)) {
363 if (rmh->dsp_stat == 0)
364 reg = lx_dsp_reg_read(chip, eReg_CRM1);
365 else
366 reg = 0;
367 goto polling_successful;
368 }
369
370 if (i > XILINX_POLL_NO_SLEEP)
371 msleep(1);
372 }
373 snd_printk(KERN_WARNING LXP "TIMEOUT lx_message_send! "
374 "polling failed\n");
375
376polling_successful:
377 atomic_set(&chip->send_message_locked, 0);
378 }
379
380 if ((reg & ERROR_VALUE) == 0) {
381 /* read response */
382 if (rmh->stat_len) {
383 snd_BUG_ON(rmh->stat_len >= (REG_CRM_NUMBER-1));
384
385 lx_dsp_reg_readbuf(chip, eReg_CRM2, rmh->stat,
386 rmh->stat_len);
387 }
388 } else
389 snd_printk(KERN_WARNING LXP "lx_message_send: error_value %x\n",
390 reg);
391
392 /* clear Reg_CSM_MR */
393 lx_dsp_reg_write(chip, eReg_CSM, 0);
394
395 switch (reg) {
396 case ED_DSP_TIMED_OUT:
397 snd_printk(KERN_WARNING LXP "lx_message_send: dsp timeout\n");
398 return -ETIMEDOUT;
399
400 case ED_DSP_CRASHED:
401 snd_printk(KERN_WARNING LXP "lx_message_send: dsp crashed\n");
402 return -EAGAIN;
403 }
404
405 lx_message_dump(rmh);
406 return 0;
407}
408#endif /* not used now */
409
410static int lx_message_send_atomic(struct lx6464es *chip, struct lx_rmh *rmh)
411{
412 u32 reg = ED_DSP_TIMED_OUT;
413 int dwloop;
414
415 if (lx_dsp_reg_read(chip, eReg_CSM) & (Reg_CSM_MC | Reg_CSM_MR)) {
416 snd_printk(KERN_ERR LXP "PIOSendMessage eReg_CSM %x\n", reg);
417 return -EBUSY;
418 }
419
420 /* write command */
421 lx_dsp_reg_writebuf(chip, eReg_CRM1, rmh->cmd, rmh->cmd_len);
422
423 /* MicoBlaze gogogo */
424 lx_dsp_reg_write(chip, eReg_CSM, Reg_CSM_MC);
425
426 /* wait for interrupt to answer */
427 for (dwloop = 0; dwloop != XILINX_TIMEOUT_MS * 1000; ++dwloop) {
428 if (lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR) {
429 if (rmh->dsp_stat == 0)
430 reg = lx_dsp_reg_read(chip, eReg_CRM1);
431 else
432 reg = 0;
433 goto polling_successful;
434 } else
435 udelay(1);
436 }
437 snd_printk(KERN_WARNING LXP "TIMEOUT lx_message_send_atomic! "
438 "polling failed\n");
439
440polling_successful:
441 if ((reg & ERROR_VALUE) == 0) {
442 /* read response */
443 if (rmh->stat_len) {
444 snd_BUG_ON(rmh->stat_len >= (REG_CRM_NUMBER-1));
445 lx_dsp_reg_readbuf(chip, eReg_CRM2, rmh->stat,
446 rmh->stat_len);
447 }
448 } else
449 snd_printk(LXP "rmh error: %08x\n", reg);
450
451 /* clear Reg_CSM_MR */
452 lx_dsp_reg_write(chip, eReg_CSM, 0);
453
454 switch (reg) {
455 case ED_DSP_TIMED_OUT:
456 snd_printk(KERN_WARNING LXP "lx_message_send: dsp timeout\n");
457 return -ETIMEDOUT;
458
459 case ED_DSP_CRASHED:
460 snd_printk(KERN_WARNING LXP "lx_message_send: dsp crashed\n");
461 return -EAGAIN;
462 }
463
464 lx_message_dump(rmh);
465
466 return reg;
467}
468
469
470/* low-level dsp access */
471int __devinit lx_dsp_get_version(struct lx6464es *chip, u32 *rdsp_version)
472{
473 u16 ret;
474 unsigned long flags;
475
476 spin_lock_irqsave(&chip->msg_lock, flags);
477
478 lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG);
479 ret = lx_message_send_atomic(chip, &chip->rmh);
480
481 *rdsp_version = chip->rmh.stat[1];
482 spin_unlock_irqrestore(&chip->msg_lock, flags);
483 return ret;
484}
485
486int lx_dsp_get_clock_frequency(struct lx6464es *chip, u32 *rfreq)
487{
488 u16 ret = 0;
489 unsigned long flags;
490 u32 freq_raw = 0;
491 u32 freq = 0;
492 u32 frequency = 0;
493
494 spin_lock_irqsave(&chip->msg_lock, flags);
495
496 lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG);
497 ret = lx_message_send_atomic(chip, &chip->rmh);
498
499 if (ret == 0) {
500 freq_raw = chip->rmh.stat[0] >> FREQ_FIELD_OFFSET;
501 freq = freq_raw & XES_FREQ_COUNT8_MASK;
502
503 if ((freq < XES_FREQ_COUNT8_48_MAX) ||
504 (freq > XES_FREQ_COUNT8_44_MIN))
505 frequency = 0; /* unknown */
506 else if (freq >= XES_FREQ_COUNT8_44_MAX)
507 frequency = 44100;
508 else
509 frequency = 48000;
510 }
511
512 spin_unlock_irqrestore(&chip->msg_lock, flags);
513
514 *rfreq = frequency * chip->freq_ratio;
515
516 return ret;
517}
518
519int lx_dsp_get_mac(struct lx6464es *chip, u8 *mac_address)
520{
521 u32 macmsb, maclsb;
522
523 macmsb = lx_dsp_reg_read(chip, eReg_ADMACESMSB) & 0x00FFFFFF;
524 maclsb = lx_dsp_reg_read(chip, eReg_ADMACESLSB) & 0x00FFFFFF;
525
526 /* todo: endianess handling */
527 mac_address[5] = ((u8 *)(&maclsb))[0];
528 mac_address[4] = ((u8 *)(&maclsb))[1];
529 mac_address[3] = ((u8 *)(&maclsb))[2];
530 mac_address[2] = ((u8 *)(&macmsb))[0];
531 mac_address[1] = ((u8 *)(&macmsb))[1];
532 mac_address[0] = ((u8 *)(&macmsb))[2];
533
534 return 0;
535}
536
537
538int lx_dsp_set_granularity(struct lx6464es *chip, u32 gran)
539{
540 unsigned long flags;
541 int ret;
542
543 spin_lock_irqsave(&chip->msg_lock, flags);
544
545 lx_message_init(&chip->rmh, CMD_02_SET_GRANULARITY);
546 chip->rmh.cmd[0] |= gran;
547
548 ret = lx_message_send_atomic(chip, &chip->rmh);
549 spin_unlock_irqrestore(&chip->msg_lock, flags);
550 return ret;
551}
552
553int lx_dsp_read_async_events(struct lx6464es *chip, u32 *data)
554{
555 unsigned long flags;
556 int ret;
557
558 spin_lock_irqsave(&chip->msg_lock, flags);
559
560 lx_message_init(&chip->rmh, CMD_04_GET_EVENT);
561 chip->rmh.stat_len = 9; /* we don't necessarily need the full length */
562
563 ret = lx_message_send_atomic(chip, &chip->rmh);
564
565 if (!ret)
566 memcpy(data, chip->rmh.stat, chip->rmh.stat_len * sizeof(u32));
567
568 spin_unlock_irqrestore(&chip->msg_lock, flags);
569 return ret;
570}
571
572#define CSES_TIMEOUT 100 /* microseconds */
573#define CSES_CE 0x0001
574#define CSES_BROADCAST 0x0002
575#define CSES_UPDATE_LDSV 0x0004
576
577int lx_dsp_es_check_pipeline(struct lx6464es *chip)
578{
579 int i;
580
581 for (i = 0; i != CSES_TIMEOUT; ++i) {
582 /*
583 * le bit CSES_UPDATE_LDSV est à 1 dés que le macprog
584 * est pret. il re-passe à 0 lorsque le premier read a
585 * été fait. pour l'instant on retire le test car ce bit
586 * passe a 1 environ 200 à 400 ms aprés que le registre
587 * confES à été écrit (kick du xilinx ES).
588 *
589 * On ne teste que le bit CE.
590 * */
591
592 u32 cses = lx_dsp_reg_read(chip, eReg_CSES);
593
594 if ((cses & CSES_CE) == 0)
595 return 0;
596
597 udelay(1);
598 }
599
600 return -ETIMEDOUT;
601}
602
603
604#define PIPE_INFO_TO_CMD(capture, pipe) \
605 ((u32)((u32)(pipe) | ((capture) ? ID_IS_CAPTURE : 0L)) << ID_OFFSET)
606
607
608
609/* low-level pipe handling */
610int lx_pipe_allocate(struct lx6464es *chip, u32 pipe, int is_capture,
611 int channels)
612{
613 int err;
614 unsigned long flags;
615
616 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
617
618 spin_lock_irqsave(&chip->msg_lock, flags);
619 lx_message_init(&chip->rmh, CMD_06_ALLOCATE_PIPE);
620
621 chip->rmh.cmd[0] |= pipe_cmd;
622 chip->rmh.cmd[0] |= channels;
623
624 err = lx_message_send_atomic(chip, &chip->rmh);
625 spin_unlock_irqrestore(&chip->msg_lock, flags);
626
627 if (err != 0)
628 snd_printk(KERN_ERR "lx6464es: could not allocate pipe\n");
629
630 return err;
631}
632
633int lx_pipe_release(struct lx6464es *chip, u32 pipe, int is_capture)
634{
635 int err;
636 unsigned long flags;
637
638 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
639
640 spin_lock_irqsave(&chip->msg_lock, flags);
641 lx_message_init(&chip->rmh, CMD_07_RELEASE_PIPE);
642
643 chip->rmh.cmd[0] |= pipe_cmd;
644
645 err = lx_message_send_atomic(chip, &chip->rmh);
646 spin_unlock_irqrestore(&chip->msg_lock, flags);
647
648 return err;
649}
650
651int lx_buffer_ask(struct lx6464es *chip, u32 pipe, int is_capture,
652 u32 *r_needed, u32 *r_freed, u32 *size_array)
653{
654 int err;
655 unsigned long flags;
656
657 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
658
659#ifdef CONFIG_SND_DEBUG
660 if (size_array)
661 memset(size_array, 0, sizeof(u32)*MAX_STREAM_BUFFER);
662#endif
663
664 *r_needed = 0;
665 *r_freed = 0;
666
667 spin_lock_irqsave(&chip->msg_lock, flags);
668 lx_message_init(&chip->rmh, CMD_08_ASK_BUFFERS);
669
670 chip->rmh.cmd[0] |= pipe_cmd;
671
672 err = lx_message_send_atomic(chip, &chip->rmh);
673
674 if (!err) {
675 int i;
676 for (i = 0; i < MAX_STREAM_BUFFER; ++i) {
677 u32 stat = chip->rmh.stat[i];
678 if (stat & (BF_EOB << BUFF_FLAGS_OFFSET)) {
679 /* finished */
680 *r_freed += 1;
681 if (size_array)
682 size_array[i] = stat & MASK_DATA_SIZE;
683 } else if ((stat & (BF_VALID << BUFF_FLAGS_OFFSET))
684 == 0)
685 /* free */
686 *r_needed += 1;
687 }
688
689#if 0
690 snd_printdd(LXP "CMD_08_ASK_BUFFERS: needed %d, freed %d\n",
691 *r_needed, *r_freed);
692 for (i = 0; i < MAX_STREAM_BUFFER; ++i) {
693 for (i = 0; i != chip->rmh.stat_len; ++i)
694 snd_printdd(" stat[%d]: %x, %x\n", i,
695 chip->rmh.stat[i],
696 chip->rmh.stat[i] & MASK_DATA_SIZE);
697 }
698#endif
699 }
700
701 spin_unlock_irqrestore(&chip->msg_lock, flags);
702 return err;
703}
704
705
706int lx_pipe_stop(struct lx6464es *chip, u32 pipe, int is_capture)
707{
708 int err;
709 unsigned long flags;
710
711 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
712
713 spin_lock_irqsave(&chip->msg_lock, flags);
714 lx_message_init(&chip->rmh, CMD_09_STOP_PIPE);
715
716 chip->rmh.cmd[0] |= pipe_cmd;
717
718 err = lx_message_send_atomic(chip, &chip->rmh);
719
720 spin_unlock_irqrestore(&chip->msg_lock, flags);
721 return err;
722}
723
724static int lx_pipe_toggle_state(struct lx6464es *chip, u32 pipe, int is_capture)
725{
726 int err;
727 unsigned long flags;
728
729 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
730
731 spin_lock_irqsave(&chip->msg_lock, flags);
732 lx_message_init(&chip->rmh, CMD_0B_TOGGLE_PIPE_STATE);
733
734 chip->rmh.cmd[0] |= pipe_cmd;
735
736 err = lx_message_send_atomic(chip, &chip->rmh);
737
738 spin_unlock_irqrestore(&chip->msg_lock, flags);
739 return err;
740}
741
742
743int lx_pipe_start(struct lx6464es *chip, u32 pipe, int is_capture)
744{
745 int err;
746
747 err = lx_pipe_wait_for_idle(chip, pipe, is_capture);
748 if (err < 0)
749 return err;
750
751 err = lx_pipe_toggle_state(chip, pipe, is_capture);
752
753 return err;
754}
755
756int lx_pipe_pause(struct lx6464es *chip, u32 pipe, int is_capture)
757{
758 int err = 0;
759
760 err = lx_pipe_wait_for_start(chip, pipe, is_capture);
761 if (err < 0)
762 return err;
763
764 err = lx_pipe_toggle_state(chip, pipe, is_capture);
765
766 return err;
767}
768
769
770int lx_pipe_sample_count(struct lx6464es *chip, u32 pipe, int is_capture,
771 u64 *rsample_count)
772{
773 int err;
774 unsigned long flags;
775
776 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
777
778 spin_lock_irqsave(&chip->msg_lock, flags);
779 lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT);
780
781 chip->rmh.cmd[0] |= pipe_cmd;
782 chip->rmh.stat_len = 2; /* need all words here! */
783
784 err = lx_message_send_atomic(chip, &chip->rmh); /* don't sleep! */
785
786 if (err != 0)
787 snd_printk(KERN_ERR
788 "lx6464es: could not query pipe's sample count\n");
789 else {
790 *rsample_count = ((u64)(chip->rmh.stat[0] & MASK_SPL_COUNT_HI)
791 << 24) /* hi part */
792 + chip->rmh.stat[1]; /* lo part */
793 }
794
795 spin_unlock_irqrestore(&chip->msg_lock, flags);
796 return err;
797}
798
799int lx_pipe_state(struct lx6464es *chip, u32 pipe, int is_capture, u16 *rstate)
800{
801 int err;
802 unsigned long flags;
803
804 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
805
806 spin_lock_irqsave(&chip->msg_lock, flags);
807 lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT);
808
809 chip->rmh.cmd[0] |= pipe_cmd;
810
811 err = lx_message_send_atomic(chip, &chip->rmh);
812
813 if (err != 0)
814 snd_printk(KERN_ERR "lx6464es: could not query pipe's state\n");
815 else
816 *rstate = (chip->rmh.stat[0] >> PSTATE_OFFSET) & 0x0F;
817
818 spin_unlock_irqrestore(&chip->msg_lock, flags);
819 return err;
820}
821
822static int lx_pipe_wait_for_state(struct lx6464es *chip, u32 pipe,
823 int is_capture, u16 state)
824{
825 int i;
826
827 /* max 2*PCMOnlyGranularity = 2*1024 at 44100 = < 50 ms:
828 * timeout 50 ms */
829 for (i = 0; i != 50; ++i) {
830 u16 current_state;
831 int err = lx_pipe_state(chip, pipe, is_capture, &current_state);
832
833 if (err < 0)
834 return err;
835
836 if (current_state == state)
837 return 0;
838
839 mdelay(1);
840 }
841
842 return -ETIMEDOUT;
843}
844
845int lx_pipe_wait_for_start(struct lx6464es *chip, u32 pipe, int is_capture)
846{
847 return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_RUN);
848}
849
850int lx_pipe_wait_for_idle(struct lx6464es *chip, u32 pipe, int is_capture)
851{
852 return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_IDLE);
853}
854
855/* low-level stream handling */
856int lx_stream_set_state(struct lx6464es *chip, u32 pipe,
857 int is_capture, enum stream_state_t state)
858{
859 int err;
860 unsigned long flags;
861
862 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
863
864 spin_lock_irqsave(&chip->msg_lock, flags);
865 lx_message_init(&chip->rmh, CMD_13_SET_STREAM_STATE);
866
867 chip->rmh.cmd[0] |= pipe_cmd;
868 chip->rmh.cmd[0] |= state;
869
870 err = lx_message_send_atomic(chip, &chip->rmh);
871 spin_unlock_irqrestore(&chip->msg_lock, flags);
872
873 return err;
874}
875
876int lx_stream_set_format(struct lx6464es *chip, struct snd_pcm_runtime *runtime,
877 u32 pipe, int is_capture)
878{
879 int err;
880 unsigned long flags;
881
882 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
883
884 u32 channels = runtime->channels;
885
886 if (runtime->channels != channels)
887 snd_printk(KERN_ERR LXP "channel count mismatch: %d vs %d",
888 runtime->channels, channels);
889
890 spin_lock_irqsave(&chip->msg_lock, flags);
891 lx_message_init(&chip->rmh, CMD_0C_DEF_STREAM);
892
893 chip->rmh.cmd[0] |= pipe_cmd;
894
895 if (runtime->sample_bits == 16)
896 /* 16 bit format */
897 chip->rmh.cmd[0] |= (STREAM_FMT_16b << STREAM_FMT_OFFSET);
898
899 if (snd_pcm_format_little_endian(runtime->format))
900 /* little endian/intel format */
901 chip->rmh.cmd[0] |= (STREAM_FMT_intel << STREAM_FMT_OFFSET);
902
903 chip->rmh.cmd[0] |= channels-1;
904
905 err = lx_message_send_atomic(chip, &chip->rmh);
906 spin_unlock_irqrestore(&chip->msg_lock, flags);
907
908 return err;
909}
910
911int lx_stream_state(struct lx6464es *chip, u32 pipe, int is_capture,
912 int *rstate)
913{
914 int err;
915 unsigned long flags;
916
917 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
918
919 spin_lock_irqsave(&chip->msg_lock, flags);
920 lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT);
921
922 chip->rmh.cmd[0] |= pipe_cmd;
923
924 err = lx_message_send_atomic(chip, &chip->rmh);
925
926 *rstate = (chip->rmh.stat[0] & SF_START) ? START_STATE : PAUSE_STATE;
927
928 spin_unlock_irqrestore(&chip->msg_lock, flags);
929 return err;
930}
931
932int lx_stream_sample_position(struct lx6464es *chip, u32 pipe, int is_capture,
933 u64 *r_bytepos)
934{
935 int err;
936 unsigned long flags;
937
938 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
939
940 spin_lock_irqsave(&chip->msg_lock, flags);
941 lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT);
942
943 chip->rmh.cmd[0] |= pipe_cmd;
944
945 err = lx_message_send_atomic(chip, &chip->rmh);
946
947 *r_bytepos = ((u64) (chip->rmh.stat[0] & MASK_SPL_COUNT_HI)
948 << 32) /* hi part */
949 + chip->rmh.stat[1]; /* lo part */
950
951 spin_unlock_irqrestore(&chip->msg_lock, flags);
952 return err;
953}
954
955/* low-level buffer handling */
956int lx_buffer_give(struct lx6464es *chip, u32 pipe, int is_capture,
957 u32 buffer_size, u32 buf_address_lo, u32 buf_address_hi,
958 u32 *r_buffer_index)
959{
960 int err;
961 unsigned long flags;
962
963 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
964
965 spin_lock_irqsave(&chip->msg_lock, flags);
966 lx_message_init(&chip->rmh, CMD_0F_UPDATE_BUFFER);
967
968 chip->rmh.cmd[0] |= pipe_cmd;
969 chip->rmh.cmd[0] |= BF_NOTIFY_EOB; /* request interrupt notification */
970
971 /* todo: pause request, circular buffer */
972
973 chip->rmh.cmd[1] = buffer_size & MASK_DATA_SIZE;
974 chip->rmh.cmd[2] = buf_address_lo;
975
976 if (buf_address_hi) {
977 chip->rmh.cmd_len = 4;
978 chip->rmh.cmd[3] = buf_address_hi;
979 chip->rmh.cmd[0] |= BF_64BITS_ADR;
980 }
981
982 err = lx_message_send_atomic(chip, &chip->rmh);
983
984 if (err == 0) {
985 *r_buffer_index = chip->rmh.stat[0];
986 goto done;
987 }
988
989 if (err == EB_RBUFFERS_TABLE_OVERFLOW)
990 snd_printk(LXP "lx_buffer_give EB_RBUFFERS_TABLE_OVERFLOW\n");
991
992 if (err == EB_INVALID_STREAM)
993 snd_printk(LXP "lx_buffer_give EB_INVALID_STREAM\n");
994
995 if (err == EB_CMD_REFUSED)
996 snd_printk(LXP "lx_buffer_give EB_CMD_REFUSED\n");
997
998 done:
999 spin_unlock_irqrestore(&chip->msg_lock, flags);
1000 return err;
1001}
1002
1003int lx_buffer_free(struct lx6464es *chip, u32 pipe, int is_capture,
1004 u32 *r_buffer_size)
1005{
1006 int err;
1007 unsigned long flags;
1008
1009 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
1010
1011 spin_lock_irqsave(&chip->msg_lock, flags);
1012 lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER);
1013
1014 chip->rmh.cmd[0] |= pipe_cmd;
1015 chip->rmh.cmd[0] |= MASK_BUFFER_ID; /* ask for the current buffer: the
1016 * microblaze will seek for it */
1017
1018 err = lx_message_send_atomic(chip, &chip->rmh);
1019
1020 if (err == 0)
1021 *r_buffer_size = chip->rmh.stat[0] & MASK_DATA_SIZE;
1022
1023 spin_unlock_irqrestore(&chip->msg_lock, flags);
1024 return err;
1025}
1026
1027int lx_buffer_cancel(struct lx6464es *chip, u32 pipe, int is_capture,
1028 u32 buffer_index)
1029{
1030 int err;
1031 unsigned long flags;
1032
1033 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
1034
1035 spin_lock_irqsave(&chip->msg_lock, flags);
1036 lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER);
1037
1038 chip->rmh.cmd[0] |= pipe_cmd;
1039 chip->rmh.cmd[0] |= buffer_index;
1040
1041 err = lx_message_send_atomic(chip, &chip->rmh);
1042
1043 spin_unlock_irqrestore(&chip->msg_lock, flags);
1044 return err;
1045}
1046
1047
1048/* low-level gain/peak handling
1049 *
1050 * \todo: can we unmute capture/playback channels independently?
1051 *
1052 * */
1053int lx_level_unmute(struct lx6464es *chip, int is_capture, int unmute)
1054{
1055 int err;
1056 unsigned long flags;
1057
1058 /* bit set to 1: channel muted */
1059 u64 mute_mask = unmute ? 0 : 0xFFFFFFFFFFFFFFFFLLU;
1060
1061 spin_lock_irqsave(&chip->msg_lock, flags);
1062 lx_message_init(&chip->rmh, CMD_0D_SET_MUTE);
1063
1064 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, 0);
1065
1066 chip->rmh.cmd[1] = (u32)(mute_mask >> (u64)32); /* hi part */
1067 chip->rmh.cmd[2] = (u32)(mute_mask & (u64)0xFFFFFFFF); /* lo part */
1068
1069 snd_printk("mute %x %x %x\n", chip->rmh.cmd[0], chip->rmh.cmd[1],
1070 chip->rmh.cmd[2]);
1071
1072 err = lx_message_send_atomic(chip, &chip->rmh);
1073
1074 spin_unlock_irqrestore(&chip->msg_lock, flags);
1075 return err;
1076}
1077
1078static u32 peak_map[] = {
1079 0x00000109, /* -90.308dB */
1080 0x0000083B, /* -72.247dB */
1081 0x000020C4, /* -60.205dB */
1082 0x00008273, /* -48.030dB */
1083 0x00020756, /* -36.005dB */
1084 0x00040C37, /* -30.001dB */
1085 0x00081385, /* -24.002dB */
1086 0x00101D3F, /* -18.000dB */
1087 0x0016C310, /* -15.000dB */
1088 0x002026F2, /* -12.001dB */
1089 0x002D6A86, /* -9.000dB */
1090 0x004026E6, /* -6.004dB */
1091 0x005A9DF6, /* -3.000dB */
1092 0x0065AC8B, /* -2.000dB */
1093 0x00721481, /* -1.000dB */
1094 0x007FFFFF, /* FS */
1095};
1096
1097int lx_level_peaks(struct lx6464es *chip, int is_capture, int channels,
1098 u32 *r_levels)
1099{
1100 int err = 0;
1101 unsigned long flags;
1102 int i;
1103 spin_lock_irqsave(&chip->msg_lock, flags);
1104
1105 for (i = 0; i < channels; i += 4) {
1106 u32 s0, s1, s2, s3;
1107
1108 lx_message_init(&chip->rmh, CMD_12_GET_PEAK);
1109 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, i);
1110
1111 err = lx_message_send_atomic(chip, &chip->rmh);
1112
1113 if (err == 0) {
1114 s0 = peak_map[chip->rmh.stat[0] & 0x0F];
1115 s1 = peak_map[(chip->rmh.stat[0] >> 4) & 0xf];
1116 s2 = peak_map[(chip->rmh.stat[0] >> 8) & 0xf];
1117 s3 = peak_map[(chip->rmh.stat[0] >> 12) & 0xf];
1118 } else
1119 s0 = s1 = s2 = s3 = 0;
1120
1121 r_levels[0] = s0;
1122 r_levels[1] = s1;
1123 r_levels[2] = s2;
1124 r_levels[3] = s3;
1125
1126 r_levels += 4;
1127 }
1128
1129 spin_unlock_irqrestore(&chip->msg_lock, flags);
1130 return err;
1131}
1132
1133/* interrupt handling */
1134#define PCX_IRQ_NONE 0
1135#define IRQCS_ACTIVE_PCIDB 0x00002000L /* Bit nø 13 */
1136#define IRQCS_ENABLE_PCIIRQ 0x00000100L /* Bit nø 08 */
1137#define IRQCS_ENABLE_PCIDB 0x00000200L /* Bit nø 09 */
1138
1139static u32 lx_interrupt_test_ack(struct lx6464es *chip)
1140{
1141 u32 irqcs = lx_plx_reg_read(chip, ePLX_IRQCS);
1142
1143 /* Test if PCI Doorbell interrupt is active */
1144 if (irqcs & IRQCS_ACTIVE_PCIDB) {
1145 u32 temp;
1146 irqcs = PCX_IRQ_NONE;
1147
1148 while ((temp = lx_plx_reg_read(chip, ePLX_L2PCIDB))) {
1149 /* RAZ interrupt */
1150 irqcs |= temp;
1151 lx_plx_reg_write(chip, ePLX_L2PCIDB, temp);
1152 }
1153
1154 return irqcs;
1155 }
1156 return PCX_IRQ_NONE;
1157}
1158
1159static int lx_interrupt_ack(struct lx6464es *chip, u32 *r_irqsrc,
1160 int *r_async_pending, int *r_async_escmd)
1161{
1162 u32 irq_async;
1163 u32 irqsrc = lx_interrupt_test_ack(chip);
1164
1165 if (irqsrc == PCX_IRQ_NONE)
1166 return 0;
1167
1168 *r_irqsrc = irqsrc;
1169
1170 irq_async = irqsrc & MASK_SYS_ASYNC_EVENTS; /* + EtherSound response
1171 * (set by xilinx) + EOB */
1172
1173 if (irq_async & MASK_SYS_STATUS_ESA) {
1174 irq_async &= ~MASK_SYS_STATUS_ESA;
1175 *r_async_escmd = 1;
1176 }
1177
1178 if (irqsrc & MASK_SYS_STATUS_CMD_DONE)
1179 /* xilinx command notification */
1180 atomic_set(&chip->send_message_locked, 0);
1181
1182 if (irq_async) {
1183 /* snd_printd("interrupt: async event pending\n"); */
1184 *r_async_pending = 1;
1185 }
1186
1187 return 1;
1188}
1189
1190static int lx_interrupt_handle_async_events(struct lx6464es *chip, u32 irqsrc,
1191 int *r_freq_changed,
1192 u64 *r_notified_in_pipe_mask,
1193 u64 *r_notified_out_pipe_mask)
1194{
1195 int err;
1196 u32 stat[9]; /* answer from CMD_04_GET_EVENT */
1197
1198 /* On peut optimiser pour ne pas lire les evenements vides
1199 * les mots de réponse sont dans l'ordre suivant :
1200 * Stat[0] mot de status général
1201 * Stat[1] fin de buffer OUT pF
1202 * Stat[2] fin de buffer OUT pf
1203 * Stat[3] fin de buffer IN pF
1204 * Stat[4] fin de buffer IN pf
1205 * Stat[5] underrun poid fort
1206 * Stat[6] underrun poid faible
1207 * Stat[7] overrun poid fort
1208 * Stat[8] overrun poid faible
1209 * */
1210
1211 u64 orun_mask;
1212 u64 urun_mask;
1213#if 0
1214 int has_underrun = (irqsrc & MASK_SYS_STATUS_URUN) ? 1 : 0;
1215 int has_overrun = (irqsrc & MASK_SYS_STATUS_ORUN) ? 1 : 0;
1216#endif
1217 int eb_pending_out = (irqsrc & MASK_SYS_STATUS_EOBO) ? 1 : 0;
1218 int eb_pending_in = (irqsrc & MASK_SYS_STATUS_EOBI) ? 1 : 0;
1219
1220 *r_freq_changed = (irqsrc & MASK_SYS_STATUS_FREQ) ? 1 : 0;
1221
1222 err = lx_dsp_read_async_events(chip, stat);
1223 if (err < 0)
1224 return err;
1225
1226 if (eb_pending_in) {
1227 *r_notified_in_pipe_mask = ((u64)stat[3] << 32)
1228 + stat[4];
1229 snd_printdd(LXP "interrupt: EOBI pending %llx\n",
1230 *r_notified_in_pipe_mask);
1231 }
1232 if (eb_pending_out) {
1233 *r_notified_out_pipe_mask = ((u64)stat[1] << 32)
1234 + stat[2];
1235 snd_printdd(LXP "interrupt: EOBO pending %llx\n",
1236 *r_notified_out_pipe_mask);
1237 }
1238
1239 orun_mask = ((u64)stat[7] << 32) + stat[8];
1240 urun_mask = ((u64)stat[5] << 32) + stat[6];
1241
1242 /* todo: handle xrun notification */
1243
1244 return err;
1245}
1246
1247static int lx_interrupt_request_new_buffer(struct lx6464es *chip,
1248 struct lx_stream *lx_stream)
1249{
1250 struct snd_pcm_substream *substream = lx_stream->stream;
1251 int is_capture = lx_stream->is_capture;
1252 int err;
1253 unsigned long flags;
1254
1255 const u32 channels = substream->runtime->channels;
1256 const u32 bytes_per_frame = channels * 3;
1257 const u32 period_size = substream->runtime->period_size;
1258 const u32 period_bytes = period_size * bytes_per_frame;
1259 const u32 pos = lx_stream->frame_pos;
1260 const u32 next_pos = ((pos+1) == substream->runtime->periods) ?
1261 0 : pos + 1;
1262
1263 dma_addr_t buf = substream->dma_buffer.addr + pos * period_bytes;
1264 u32 buf_hi = 0;
1265 u32 buf_lo = 0;
1266 u32 buffer_index = 0;
1267
1268 u32 needed, freed;
1269 u32 size_array[MAX_STREAM_BUFFER];
1270
1271 snd_printdd("->lx_interrupt_request_new_buffer\n");
1272
1273 spin_lock_irqsave(&chip->lock, flags);
1274
1275 err = lx_buffer_ask(chip, 0, is_capture, &needed, &freed, size_array);
1276 snd_printdd(LXP "interrupt: needed %d, freed %d\n", needed, freed);
1277
1278 unpack_pointer(buf, &buf_lo, &buf_hi);
1279 err = lx_buffer_give(chip, 0, is_capture, period_bytes, buf_lo, buf_hi,
1280 &buffer_index);
1281 snd_printdd(LXP "interrupt: gave buffer index %x on %p (%d bytes)\n",
1282 buffer_index, (void *)buf, period_bytes);
1283
1284 lx_stream->frame_pos = next_pos;
1285 spin_unlock_irqrestore(&chip->lock, flags);
1286
1287 return err;
1288}
1289
1290void lx_tasklet_playback(unsigned long data)
1291{
1292 struct lx6464es *chip = (struct lx6464es *)data;
1293 struct lx_stream *lx_stream = &chip->playback_stream;
1294 int err;
1295
1296 snd_printdd("->lx_tasklet_playback\n");
1297
1298 err = lx_interrupt_request_new_buffer(chip, lx_stream);
1299 if (err < 0)
1300 snd_printk(KERN_ERR LXP
1301 "cannot request new buffer for playback\n");
1302
1303 snd_pcm_period_elapsed(lx_stream->stream);
1304}
1305
1306void lx_tasklet_capture(unsigned long data)
1307{
1308 struct lx6464es *chip = (struct lx6464es *)data;
1309 struct lx_stream *lx_stream = &chip->capture_stream;
1310 int err;
1311
1312 snd_printdd("->lx_tasklet_capture\n");
1313 err = lx_interrupt_request_new_buffer(chip, lx_stream);
1314 if (err < 0)
1315 snd_printk(KERN_ERR LXP
1316 "cannot request new buffer for capture\n");
1317
1318 snd_pcm_period_elapsed(lx_stream->stream);
1319}
1320
1321
1322
1323static int lx_interrupt_handle_audio_transfer(struct lx6464es *chip,
1324 u64 notified_in_pipe_mask,
1325 u64 notified_out_pipe_mask)
1326{
1327 int err = 0;
1328
1329 if (notified_in_pipe_mask) {
1330 snd_printdd(LXP "requesting audio transfer for capture\n");
1331 tasklet_hi_schedule(&chip->tasklet_capture);
1332 }
1333
1334 if (notified_out_pipe_mask) {
1335 snd_printdd(LXP "requesting audio transfer for playback\n");
1336 tasklet_hi_schedule(&chip->tasklet_playback);
1337 }
1338
1339 return err;
1340}
1341
1342
1343irqreturn_t lx_interrupt(int irq, void *dev_id)
1344{
1345 struct lx6464es *chip = dev_id;
1346 int async_pending, async_escmd;
1347 u32 irqsrc;
1348
1349 spin_lock(&chip->lock);
1350
1351 snd_printdd("**************************************************\n");
1352
1353 if (!lx_interrupt_ack(chip, &irqsrc, &async_pending, &async_escmd)) {
1354 spin_unlock(&chip->lock);
1355 snd_printdd("IRQ_NONE\n");
1356 return IRQ_NONE; /* this device did not cause the interrupt */
1357 }
1358
1359 if (irqsrc & MASK_SYS_STATUS_CMD_DONE)
1360 goto exit;
1361
1362#if 0
1363 if (irqsrc & MASK_SYS_STATUS_EOBI)
1364 snd_printdd(LXP "interrupt: EOBI\n");
1365
1366 if (irqsrc & MASK_SYS_STATUS_EOBO)
1367 snd_printdd(LXP "interrupt: EOBO\n");
1368
1369 if (irqsrc & MASK_SYS_STATUS_URUN)
1370 snd_printdd(LXP "interrupt: URUN\n");
1371
1372 if (irqsrc & MASK_SYS_STATUS_ORUN)
1373 snd_printdd(LXP "interrupt: ORUN\n");
1374#endif
1375
1376 if (async_pending) {
1377 u64 notified_in_pipe_mask = 0;
1378 u64 notified_out_pipe_mask = 0;
1379 int freq_changed;
1380 int err;
1381
1382 /* handle async events */
1383 err = lx_interrupt_handle_async_events(chip, irqsrc,
1384 &freq_changed,
1385 &notified_in_pipe_mask,
1386 &notified_out_pipe_mask);
1387 if (err)
1388 snd_printk(KERN_ERR LXP
1389 "error handling async events\n");
1390
1391 err = lx_interrupt_handle_audio_transfer(chip,
1392 notified_in_pipe_mask,
1393 notified_out_pipe_mask
1394 );
1395 if (err)
1396 snd_printk(KERN_ERR LXP
1397 "error during audio transfer\n");
1398 }
1399
1400 if (async_escmd) {
1401#if 0
1402 /* backdoor for ethersound commands
1403 *
1404 * for now, we do not need this
1405 *
1406 * */
1407
1408 snd_printdd("lx6464es: interrupt requests escmd handling\n");
1409#endif
1410 }
1411
1412exit:
1413 spin_unlock(&chip->lock);
1414 return IRQ_HANDLED; /* this device caused the interrupt */
1415}
1416
1417
1418static void lx_irq_set(struct lx6464es *chip, int enable)
1419{
1420 u32 reg = lx_plx_reg_read(chip, ePLX_IRQCS);
1421
1422 /* enable/disable interrupts
1423 *
1424 * Set the Doorbell and PCI interrupt enable bits
1425 *
1426 * */
1427 if (enable)
1428 reg |= (IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB);
1429 else
1430 reg &= ~(IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB);
1431 lx_plx_reg_write(chip, ePLX_IRQCS, reg);
1432}
1433
1434void lx_irq_enable(struct lx6464es *chip)
1435{
1436 snd_printdd("->lx_irq_enable\n");
1437 lx_irq_set(chip, 1);
1438}
1439
1440void lx_irq_disable(struct lx6464es *chip)
1441{
1442 snd_printdd("->lx_irq_disable\n");
1443 lx_irq_set(chip, 0);
1444}
diff --git a/sound/pci/lx6464es/lx_core.h b/sound/pci/lx6464es/lx_core.h
new file mode 100644
index 00000000000..6bd9cbbbc68
--- /dev/null
+++ b/sound/pci/lx6464es/lx_core.h
@@ -0,0 +1,242 @@
1/* -*- linux-c -*- *
2 *
3 * ALSA driver for the digigram lx6464es interface
4 * low-level interface
5 *
6 * Copyright (c) 2009 Tim Blechmann <tim@klingt.org>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
21 * Boston, MA 02111-1307, USA.
22 *
23 */
24
25#ifndef LX_CORE_H
26#define LX_CORE_H
27
28#include <linux/interrupt.h>
29
30#include "lx_defs.h"
31
32#define REG_CRM_NUMBER 12
33
34struct lx6464es;
35
36/* low-level register access */
37
38/* dsp register access */
39enum {
40 eReg_BASE,
41 eReg_CSM,
42 eReg_CRM1,
43 eReg_CRM2,
44 eReg_CRM3,
45 eReg_CRM4,
46 eReg_CRM5,
47 eReg_CRM6,
48 eReg_CRM7,
49 eReg_CRM8,
50 eReg_CRM9,
51 eReg_CRM10,
52 eReg_CRM11,
53 eReg_CRM12,
54
55 eReg_ICR,
56 eReg_CVR,
57 eReg_ISR,
58 eReg_RXHTXH,
59 eReg_RXMTXM,
60 eReg_RHLTXL,
61 eReg_RESETDSP,
62
63 eReg_CSUF,
64 eReg_CSES,
65 eReg_CRESMSB,
66 eReg_CRESLSB,
67 eReg_ADMACESMSB,
68 eReg_ADMACESLSB,
69 eReg_CONFES,
70
71 eMaxPortLx
72};
73
74unsigned long lx_dsp_reg_read(struct lx6464es *chip, int port);
75void lx_dsp_reg_readbuf(struct lx6464es *chip, int port, u32 *data, u32 len);
76void lx_dsp_reg_write(struct lx6464es *chip, int port, unsigned data);
77void lx_dsp_reg_writebuf(struct lx6464es *chip, int port, const u32 *data,
78 u32 len);
79
80/* plx register access */
81enum {
82 ePLX_PCICR,
83
84 ePLX_MBOX0,
85 ePLX_MBOX1,
86 ePLX_MBOX2,
87 ePLX_MBOX3,
88 ePLX_MBOX4,
89 ePLX_MBOX5,
90 ePLX_MBOX6,
91 ePLX_MBOX7,
92
93 ePLX_L2PCIDB,
94 ePLX_IRQCS,
95 ePLX_CHIPSC,
96
97 eMaxPort
98};
99
100unsigned long lx_plx_reg_read(struct lx6464es *chip, int port);
101void lx_plx_reg_write(struct lx6464es *chip, int port, u32 data);
102
103/* rhm */
104struct lx_rmh {
105 u16 cmd_len; /* length of the command to send (WORDs) */
106 u16 stat_len; /* length of the status received (WORDs) */
107 u16 dsp_stat; /* status type, RMP_SSIZE_XXX */
108 u16 cmd_idx; /* index of the command */
109 u32 cmd[REG_CRM_NUMBER];
110 u32 stat[REG_CRM_NUMBER];
111};
112
113
114/* low-level dsp access */
115int __devinit lx_dsp_get_version(struct lx6464es *chip, u32 *rdsp_version);
116int lx_dsp_get_clock_frequency(struct lx6464es *chip, u32 *rfreq);
117int lx_dsp_set_granularity(struct lx6464es *chip, u32 gran);
118int lx_dsp_read_async_events(struct lx6464es *chip, u32 *data);
119int lx_dsp_get_mac(struct lx6464es *chip, u8 *mac_address);
120
121
122/* low-level pipe handling */
123int lx_pipe_allocate(struct lx6464es *chip, u32 pipe, int is_capture,
124 int channels);
125int lx_pipe_release(struct lx6464es *chip, u32 pipe, int is_capture);
126int lx_pipe_sample_count(struct lx6464es *chip, u32 pipe, int is_capture,
127 u64 *rsample_count);
128int lx_pipe_state(struct lx6464es *chip, u32 pipe, int is_capture, u16 *rstate);
129int lx_pipe_stop(struct lx6464es *chip, u32 pipe, int is_capture);
130int lx_pipe_start(struct lx6464es *chip, u32 pipe, int is_capture);
131int lx_pipe_pause(struct lx6464es *chip, u32 pipe, int is_capture);
132
133int lx_pipe_wait_for_start(struct lx6464es *chip, u32 pipe, int is_capture);
134int lx_pipe_wait_for_idle(struct lx6464es *chip, u32 pipe, int is_capture);
135
136/* low-level stream handling */
137int lx_stream_set_format(struct lx6464es *chip, struct snd_pcm_runtime *runtime,
138 u32 pipe, int is_capture);
139int lx_stream_state(struct lx6464es *chip, u32 pipe, int is_capture,
140 int *rstate);
141int lx_stream_sample_position(struct lx6464es *chip, u32 pipe, int is_capture,
142 u64 *r_bytepos);
143
144int lx_stream_set_state(struct lx6464es *chip, u32 pipe,
145 int is_capture, enum stream_state_t state);
146
147static inline int lx_stream_start(struct lx6464es *chip, u32 pipe,
148 int is_capture)
149{
150 snd_printdd("->lx_stream_start\n");
151 return lx_stream_set_state(chip, pipe, is_capture, SSTATE_RUN);
152}
153
154static inline int lx_stream_pause(struct lx6464es *chip, u32 pipe,
155 int is_capture)
156{
157 snd_printdd("->lx_stream_pause\n");
158 return lx_stream_set_state(chip, pipe, is_capture, SSTATE_PAUSE);
159}
160
161static inline int lx_stream_stop(struct lx6464es *chip, u32 pipe,
162 int is_capture)
163{
164 snd_printdd("->lx_stream_stop\n");
165 return lx_stream_set_state(chip, pipe, is_capture, SSTATE_STOP);
166}
167
168/* low-level buffer handling */
169int lx_buffer_ask(struct lx6464es *chip, u32 pipe, int is_capture,
170 u32 *r_needed, u32 *r_freed, u32 *size_array);
171int lx_buffer_give(struct lx6464es *chip, u32 pipe, int is_capture,
172 u32 buffer_size, u32 buf_address_lo, u32 buf_address_hi,
173 u32 *r_buffer_index);
174int lx_buffer_free(struct lx6464es *chip, u32 pipe, int is_capture,
175 u32 *r_buffer_size);
176int lx_buffer_cancel(struct lx6464es *chip, u32 pipe, int is_capture,
177 u32 buffer_index);
178
179/* low-level gain/peak handling */
180int lx_level_unmute(struct lx6464es *chip, int is_capture, int unmute);
181int lx_level_peaks(struct lx6464es *chip, int is_capture, int channels,
182 u32 *r_levels);
183
184
185/* interrupt handling */
186irqreturn_t lx_interrupt(int irq, void *dev_id);
187void lx_irq_enable(struct lx6464es *chip);
188void lx_irq_disable(struct lx6464es *chip);
189
190void lx_tasklet_capture(unsigned long data);
191void lx_tasklet_playback(unsigned long data);
192
193
194/* Stream Format Header Defines (for LIN and IEEE754) */
195#define HEADER_FMT_BASE HEADER_FMT_BASE_LIN
196#define HEADER_FMT_BASE_LIN 0xFED00000
197#define HEADER_FMT_BASE_FLOAT 0xFAD00000
198#define HEADER_FMT_MONO 0x00000080 /* bit 23 in header_lo. WARNING: old
199 * bit 22 is ignored in float
200 * format */
201#define HEADER_FMT_INTEL 0x00008000
202#define HEADER_FMT_16BITS 0x00002000
203#define HEADER_FMT_24BITS 0x00004000
204#define HEADER_FMT_UPTO11 0x00000200 /* frequency is less or equ. to 11k.
205 * */
206#define HEADER_FMT_UPTO32 0x00000100 /* frequency is over 11k and less
207 * then 32k.*/
208
209
210#define BIT_FMP_HEADER 23
211#define BIT_FMP_SD 22
212#define BIT_FMP_MULTICHANNEL 19
213
214#define START_STATE 1
215#define PAUSE_STATE 0
216
217
218
219
220
221/* from PcxAll_e.h */
222/* Start/Pause condition for pipes (PCXStartPipe, PCXPausePipe) */
223#define START_PAUSE_IMMEDIATE 0
224#define START_PAUSE_ON_SYNCHRO 1
225#define START_PAUSE_ON_TIME_CODE 2
226
227
228/* Pipe / Stream state */
229#define START_STATE 1
230#define PAUSE_STATE 0
231
232static inline void unpack_pointer(dma_addr_t ptr, u32 *r_low, u32 *r_high)
233{
234 *r_low = (u32)(ptr & 0xffffffff);
235#if BITS_PER_LONG == 32
236 *r_high = 0;
237#else
238 *r_high = (u32)((u64)ptr>>32);
239#endif
240}
241
242#endif /* LX_CORE_H */
diff --git a/sound/pci/lx6464es/lx_defs.h b/sound/pci/lx6464es/lx_defs.h
new file mode 100644
index 00000000000..49d36bdd512
--- /dev/null
+++ b/sound/pci/lx6464es/lx_defs.h
@@ -0,0 +1,376 @@
1/* -*- linux-c -*- *
2 *
3 * ALSA driver for the digigram lx6464es interface
4 * adapted upstream headers
5 *
6 * Copyright (c) 2009 Tim Blechmann <tim@klingt.org>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
21 * Boston, MA 02111-1307, USA.
22 *
23 */
24
25#ifndef LX_DEFS_H
26#define LX_DEFS_H
27
28/* code adapted from ethersound.h */
29#define XES_FREQ_COUNT8_MASK 0x00001FFF /* compteur 25MHz entre 8 ech. */
30#define XES_FREQ_COUNT8_44_MIN 0x00001288 /* 25M /
31 * [ 44k - ( 44.1k + 48k ) / 2 ]
32 * * 8 */
33#define XES_FREQ_COUNT8_44_MAX 0x000010F0 /* 25M / [ ( 44.1k + 48k ) / 2 ]
34 * * 8 */
35#define XES_FREQ_COUNT8_48_MAX 0x00000F08 /* 25M /
36 * [ 48k + ( 44.1k + 48k ) / 2 ]
37 * * 8 */
38
39/* code adapted from LXES_registers.h */
40
41#define IOCR_OUTPUTS_OFFSET 0 /* (rw) offset for the number of OUTs in the
42 * ConfES register. */
43#define IOCR_INPUTS_OFFSET 8 /* (rw) offset for the number of INs in the
44 * ConfES register. */
45#define FREQ_RATIO_OFFSET 19 /* (rw) offset for frequency ratio in the
46 * ConfES register. */
47#define FREQ_RATIO_SINGLE_MODE 0x01 /* value for single mode frequency ratio:
48 * sample rate = frequency rate. */
49
50#define CONFES_READ_PART_MASK 0x00070000
51#define CONFES_WRITE_PART_MASK 0x00F80000
52
53/* code adapted from if_drv_mb.h */
54
55#define MASK_SYS_STATUS_ERROR (1L << 31) /* events that lead to a PCI irq if
56 * not yet pending */
57#define MASK_SYS_STATUS_URUN (1L << 30)
58#define MASK_SYS_STATUS_ORUN (1L << 29)
59#define MASK_SYS_STATUS_EOBO (1L << 28)
60#define MASK_SYS_STATUS_EOBI (1L << 27)
61#define MASK_SYS_STATUS_FREQ (1L << 26)
62#define MASK_SYS_STATUS_ESA (1L << 25) /* reserved, this is set by the
63 * XES */
64#define MASK_SYS_STATUS_TIMER (1L << 24)
65
66#define MASK_SYS_ASYNC_EVENTS (MASK_SYS_STATUS_ERROR | \
67 MASK_SYS_STATUS_URUN | \
68 MASK_SYS_STATUS_ORUN | \
69 MASK_SYS_STATUS_EOBO | \
70 MASK_SYS_STATUS_EOBI | \
71 MASK_SYS_STATUS_FREQ | \
72 MASK_SYS_STATUS_ESA)
73
74#define MASK_SYS_PCI_EVENTS (MASK_SYS_ASYNC_EVENTS | \
75 MASK_SYS_STATUS_TIMER)
76
77#define MASK_SYS_TIMER_COUNT 0x0000FFFF
78
79#define MASK_SYS_STATUS_EOT_PLX (1L << 22) /* event that remains
80 * internal: reserved fo end
81 * of plx dma */
82#define MASK_SYS_STATUS_XES (1L << 21) /* event that remains
83 * internal: pending XES
84 * IRQ */
85#define MASK_SYS_STATUS_CMD_DONE (1L << 20) /* alternate command
86 * management: notify driver
87 * instead of polling */
88
89
90#define MAX_STREAM_BUFFER 5 /* max amount of stream buffers. */
91
92#define MICROBLAZE_IBL_MIN 32
93#define MICROBLAZE_IBL_DEFAULT 128
94#define MICROBLAZE_IBL_MAX 512
95/* #define MASK_GRANULARITY (2*MICROBLAZE_IBL_MAX-1) */
96
97
98
99/* command opcodes, see reference for details */
100
101/*
102 the capture bit position in the object_id field in driver commands
103 depends upon the number of managed channels. For now, 64 IN + 64 OUT are
104 supported. HOwever, the communication protocol forsees 1024 channels, hence
105 bit 10 indicates a capture (input) object).
106*/
107#define ID_IS_CAPTURE (1L << 10)
108#define ID_OFFSET 13 /* object ID is at the 13th bit in the
109 * 1st command word.*/
110#define ID_CH_MASK 0x3F
111#define OPCODE_OFFSET 24 /* offset of the command opcode in the first
112 * command word.*/
113
114enum cmd_mb_opcodes {
115 CMD_00_INFO_DEBUG = 0x00,
116 CMD_01_GET_SYS_CFG = 0x01,
117 CMD_02_SET_GRANULARITY = 0x02,
118 CMD_03_SET_TIMER_IRQ = 0x03,
119 CMD_04_GET_EVENT = 0x04,
120 CMD_05_GET_PIPES = 0x05,
121
122 CMD_06_ALLOCATE_PIPE = 0x06,
123 CMD_07_RELEASE_PIPE = 0x07,
124 CMD_08_ASK_BUFFERS = 0x08,
125 CMD_09_STOP_PIPE = 0x09,
126 CMD_0A_GET_PIPE_SPL_COUNT = 0x0a,
127 CMD_0B_TOGGLE_PIPE_STATE = 0x0b,
128
129 CMD_0C_DEF_STREAM = 0x0c,
130 CMD_0D_SET_MUTE = 0x0d,
131 CMD_0E_GET_STREAM_SPL_COUNT = 0x0e,
132 CMD_0F_UPDATE_BUFFER = 0x0f,
133 CMD_10_GET_BUFFER = 0x10,
134 CMD_11_CANCEL_BUFFER = 0x11,
135 CMD_12_GET_PEAK = 0x12,
136 CMD_13_SET_STREAM_STATE = 0x13,
137 CMD_14_INVALID = 0x14,
138};
139
140/* pipe states */
141enum pipe_state_t {
142 PSTATE_IDLE = 0, /* the pipe is not processed in the XES_IRQ
143 * (free or stopped, or paused). */
144 PSTATE_RUN = 1, /* sustained play/record state. */
145 PSTATE_PURGE = 2, /* the ES channels are now off, render pipes do
146 * not DMA, record pipe do a last DMA. */
147 PSTATE_ACQUIRE = 3, /* the ES channels are now on, render pipes do
148 * not yet increase their sample count, record
149 * pipes do not DMA. */
150 PSTATE_CLOSING = 4, /* the pipe is releasing, and may not yet
151 * receive an "alloc" command. */
152};
153
154/* stream states */
155enum stream_state_t {
156 SSTATE_STOP = 0x00, /* setting to stop resets the stream spl
157 * count.*/
158 SSTATE_RUN = (0x01 << 0), /* start DMA and spl count handling. */
159 SSTATE_PAUSE = (0x01 << 1), /* pause DMA and spl count handling. */
160};
161
162/* buffer flags */
163enum buffer_flags {
164 BF_VALID = 0x80, /* set if the buffer is valid, clear if free.*/
165 BF_CURRENT = 0x40, /* set if this is the current buffer (there is
166 * always a current buffer).*/
167 BF_NOTIFY_EOB = 0x20, /* set if this buffer must cause a PCI event
168 * when finished.*/
169 BF_CIRCULAR = 0x10, /* set if buffer[1] must be copied to buffer[0]
170 * by the end of this buffer.*/
171 BF_64BITS_ADR = 0x08, /* set if the hi part of the address is valid.*/
172 BF_xx = 0x04, /* future extension.*/
173 BF_EOB = 0x02, /* set if finished, but not yet free.*/
174 BF_PAUSE = 0x01, /* pause stream at buffer end.*/
175 BF_ZERO = 0x00, /* no flags (init).*/
176};
177
178/**
179* Stream Flags definitions
180*/
181enum stream_flags {
182 SF_ZERO = 0x00000000, /* no flags (stream invalid). */
183 SF_VALID = 0x10000000, /* the stream has a valid DMA_conf
184 * info (setstreamformat). */
185 SF_XRUN = 0x20000000, /* the stream is un x-run state. */
186 SF_START = 0x40000000, /* the DMA is running.*/
187 SF_ASIO = 0x80000000, /* ASIO.*/
188};
189
190
191#define MASK_SPL_COUNT_HI 0x00FFFFFF /* 4 MSBits are status bits */
192#define PSTATE_OFFSET 28 /* 4 MSBits are status bits */
193
194
195#define MASK_STREAM_HAS_MAPPING (1L << 12)
196#define MASK_STREAM_IS_ASIO (1L << 9)
197#define STREAM_FMT_OFFSET 10 /* the stream fmt bits start at the 10th
198 * bit in the command word. */
199
200#define STREAM_FMT_16b 0x02
201#define STREAM_FMT_intel 0x01
202
203#define FREQ_FIELD_OFFSET 15 /* offset of the freq field in the response
204 * word */
205
206#define BUFF_FLAGS_OFFSET 24 /* offset of the buffer flags in the
207 * response word. */
208#define MASK_DATA_SIZE 0x00FFFFFF /* this must match the field size of
209 * datasize in the buffer_t structure. */
210
211#define MASK_BUFFER_ID 0xFF /* the cancel command awaits a buffer ID,
212 * may be 0xFF for "current". */
213
214
215/* code adapted from PcxErr_e.h */
216
217/* Bits masks */
218
219#define ERROR_MASK 0x8000
220
221#define SOURCE_MASK 0x7800
222
223#define E_SOURCE_BOARD 0x4000 /* 8 >> 1 */
224#define E_SOURCE_DRV 0x2000 /* 4 >> 1 */
225#define E_SOURCE_API 0x1000 /* 2 >> 1 */
226/* Error tools */
227#define E_SOURCE_TOOLS 0x0800 /* 1 >> 1 */
228/* Error pcxaudio */
229#define E_SOURCE_AUDIO 0x1800 /* 3 >> 1 */
230/* Error virtual pcx */
231#define E_SOURCE_VPCX 0x2800 /* 5 >> 1 */
232/* Error dispatcher */
233#define E_SOURCE_DISPATCHER 0x3000 /* 6 >> 1 */
234/* Error from CobraNet firmware */
235#define E_SOURCE_COBRANET 0x3800 /* 7 >> 1 */
236
237#define E_SOURCE_USER 0x7800
238
239#define CLASS_MASK 0x0700
240
241#define CODE_MASK 0x00FF
242
243/* Bits values */
244
245/* Values for the error/warning bit */
246#define ERROR_VALUE 0x8000
247#define WARNING_VALUE 0x0000
248
249/* Class values */
250#define E_CLASS_GENERAL 0x0000
251#define E_CLASS_INVALID_CMD 0x0100
252#define E_CLASS_INVALID_STD_OBJECT 0x0200
253#define E_CLASS_RSRC_IMPOSSIBLE 0x0300
254#define E_CLASS_WRONG_CONTEXT 0x0400
255#define E_CLASS_BAD_SPECIFIC_PARAMETER 0x0500
256#define E_CLASS_REAL_TIME_ERROR 0x0600
257#define E_CLASS_DIRECTSHOW 0x0700
258#define E_CLASS_FREE 0x0700
259
260
261/* Complete DRV error code for the general class */
262#define ED_GN (ERROR_VALUE | E_SOURCE_DRV | E_CLASS_GENERAL)
263#define ED_CONCURRENCY (ED_GN | 0x01)
264#define ED_DSP_CRASHED (ED_GN | 0x02)
265#define ED_UNKNOWN_BOARD (ED_GN | 0x03)
266#define ED_NOT_INSTALLED (ED_GN | 0x04)
267#define ED_CANNOT_OPEN_SVC_MANAGER (ED_GN | 0x05)
268#define ED_CANNOT_READ_REGISTRY (ED_GN | 0x06)
269#define ED_DSP_VERSION_MISMATCH (ED_GN | 0x07)
270#define ED_UNAVAILABLE_FEATURE (ED_GN | 0x08)
271#define ED_CANCELLED (ED_GN | 0x09)
272#define ED_NO_RESPONSE_AT_IRQA (ED_GN | 0x10)
273#define ED_INVALID_ADDRESS (ED_GN | 0x11)
274#define ED_DSP_CORRUPTED (ED_GN | 0x12)
275#define ED_PENDING_OPERATION (ED_GN | 0x13)
276#define ED_NET_ALLOCATE_MEMORY_IMPOSSIBLE (ED_GN | 0x14)
277#define ED_NET_REGISTER_ERROR (ED_GN | 0x15)
278#define ED_NET_THREAD_ERROR (ED_GN | 0x16)
279#define ED_NET_OPEN_ERROR (ED_GN | 0x17)
280#define ED_NET_CLOSE_ERROR (ED_GN | 0x18)
281#define ED_NET_NO_MORE_PACKET (ED_GN | 0x19)
282#define ED_NET_NO_MORE_BUFFER (ED_GN | 0x1A)
283#define ED_NET_SEND_ERROR (ED_GN | 0x1B)
284#define ED_NET_RECEIVE_ERROR (ED_GN | 0x1C)
285#define ED_NET_WRONG_MSG_SIZE (ED_GN | 0x1D)
286#define ED_NET_WAIT_ERROR (ED_GN | 0x1E)
287#define ED_NET_EEPROM_ERROR (ED_GN | 0x1F)
288#define ED_INVALID_RS232_COM_NUMBER (ED_GN | 0x20)
289#define ED_INVALID_RS232_INIT (ED_GN | 0x21)
290#define ED_FILE_ERROR (ED_GN | 0x22)
291#define ED_INVALID_GPIO_CMD (ED_GN | 0x23)
292#define ED_RS232_ALREADY_OPENED (ED_GN | 0x24)
293#define ED_RS232_NOT_OPENED (ED_GN | 0x25)
294#define ED_GPIO_ALREADY_OPENED (ED_GN | 0x26)
295#define ED_GPIO_NOT_OPENED (ED_GN | 0x27)
296#define ED_REGISTRY_ERROR (ED_GN | 0x28) /* <- NCX */
297#define ED_INVALID_SERVICE (ED_GN | 0x29) /* <- NCX */
298
299#define ED_READ_FILE_ALREADY_OPENED (ED_GN | 0x2a) /* <- Decalage
300 * pour RCX
301 * (old 0x28)
302 * */
303#define ED_READ_FILE_INVALID_COMMAND (ED_GN | 0x2b) /* ~ */
304#define ED_READ_FILE_INVALID_PARAMETER (ED_GN | 0x2c) /* ~ */
305#define ED_READ_FILE_ALREADY_CLOSED (ED_GN | 0x2d) /* ~ */
306#define ED_READ_FILE_NO_INFORMATION (ED_GN | 0x2e) /* ~ */
307#define ED_READ_FILE_INVALID_HANDLE (ED_GN | 0x2f) /* ~ */
308#define ED_READ_FILE_END_OF_FILE (ED_GN | 0x30) /* ~ */
309#define ED_READ_FILE_ERROR (ED_GN | 0x31) /* ~ */
310
311#define ED_DSP_CRASHED_EXC_DSPSTACK_OVERFLOW (ED_GN | 0x32) /* <- Decalage pour
312 * PCX (old 0x14) */
313#define ED_DSP_CRASHED_EXC_SYSSTACK_OVERFLOW (ED_GN | 0x33) /* ~ */
314#define ED_DSP_CRASHED_EXC_ILLEGAL (ED_GN | 0x34) /* ~ */
315#define ED_DSP_CRASHED_EXC_TIMER_REENTRY (ED_GN | 0x35) /* ~ */
316#define ED_DSP_CRASHED_EXC_FATAL_ERROR (ED_GN | 0x36) /* ~ */
317
318#define ED_FLASH_PCCARD_NOT_PRESENT (ED_GN | 0x37)
319
320#define ED_NO_CURRENT_CLOCK (ED_GN | 0x38)
321
322/* Complete DRV error code for real time class */
323#define ED_RT (ERROR_VALUE | E_SOURCE_DRV | E_CLASS_REAL_TIME_ERROR)
324#define ED_DSP_TIMED_OUT (ED_RT | 0x01)
325#define ED_DSP_CHK_TIMED_OUT (ED_RT | 0x02)
326#define ED_STREAM_OVERRUN (ED_RT | 0x03)
327#define ED_DSP_BUSY (ED_RT | 0x04)
328#define ED_DSP_SEMAPHORE_TIME_OUT (ED_RT | 0x05)
329#define ED_BOARD_TIME_OUT (ED_RT | 0x06)
330#define ED_XILINX_ERROR (ED_RT | 0x07)
331#define ED_COBRANET_ITF_NOT_RESPONDING (ED_RT | 0x08)
332
333/* Complete BOARD error code for the invaid standard object class */
334#define EB_ISO (ERROR_VALUE | E_SOURCE_BOARD | \
335 E_CLASS_INVALID_STD_OBJECT)
336#define EB_INVALID_EFFECT (EB_ISO | 0x00)
337#define EB_INVALID_PIPE (EB_ISO | 0x40)
338#define EB_INVALID_STREAM (EB_ISO | 0x80)
339#define EB_INVALID_AUDIO (EB_ISO | 0xC0)
340
341/* Complete BOARD error code for impossible resource allocation class */
342#define EB_RI (ERROR_VALUE | E_SOURCE_BOARD | E_CLASS_RSRC_IMPOSSIBLE)
343#define EB_ALLOCATE_ALL_STREAM_TRANSFERT_BUFFERS_IMPOSSIBLE (EB_RI | 0x01)
344#define EB_ALLOCATE_PIPE_SAMPLE_BUFFER_IMPOSSIBLE (EB_RI | 0x02)
345
346#define EB_ALLOCATE_MEM_STREAM_IMPOSSIBLE \
347 EB_ALLOCATE_ALL_STREAM_TRANSFERT_BUFFERS_IMPOSSIBLE
348#define EB_ALLOCATE_MEM_PIPE_IMPOSSIBLE \
349 EB_ALLOCATE_PIPE_SAMPLE_BUFFER_IMPOSSIBLE
350
351#define EB_ALLOCATE_DIFFERED_CMD_IMPOSSIBLE (EB_RI | 0x03)
352#define EB_TOO_MANY_DIFFERED_CMD (EB_RI | 0x04)
353#define EB_RBUFFERS_TABLE_OVERFLOW (EB_RI | 0x05)
354#define EB_ALLOCATE_EFFECTS_IMPOSSIBLE (EB_RI | 0x08)
355#define EB_ALLOCATE_EFFECT_POS_IMPOSSIBLE (EB_RI | 0x09)
356#define EB_RBUFFER_NOT_AVAILABLE (EB_RI | 0x0A)
357#define EB_ALLOCATE_CONTEXT_LIII_IMPOSSIBLE (EB_RI | 0x0B)
358#define EB_STATUS_DIALOG_IMPOSSIBLE (EB_RI | 0x1D)
359#define EB_CONTROL_CMD_IMPOSSIBLE (EB_RI | 0x1E)
360#define EB_STATUS_SEND_IMPOSSIBLE (EB_RI | 0x1F)
361#define EB_ALLOCATE_PIPE_IMPOSSIBLE (EB_RI | 0x40)
362#define EB_ALLOCATE_STREAM_IMPOSSIBLE (EB_RI | 0x80)
363#define EB_ALLOCATE_AUDIO_IMPOSSIBLE (EB_RI | 0xC0)
364
365/* Complete BOARD error code for wrong call context class */
366#define EB_WCC (ERROR_VALUE | E_SOURCE_BOARD | E_CLASS_WRONG_CONTEXT)
367#define EB_CMD_REFUSED (EB_WCC | 0x00)
368#define EB_START_STREAM_REFUSED (EB_WCC | 0xFC)
369#define EB_SPC_REFUSED (EB_WCC | 0xFD)
370#define EB_CSN_REFUSED (EB_WCC | 0xFE)
371#define EB_CSE_REFUSED (EB_WCC | 0xFF)
372
373
374
375
376#endif /* LX_DEFS_H */
diff --git a/sound/pci/oxygen/oxygen_pcm.c b/sound/pci/oxygen/oxygen_pcm.c
index c262049961e..3b5ca70c9d4 100644
--- a/sound/pci/oxygen/oxygen_pcm.c
+++ b/sound/pci/oxygen/oxygen_pcm.c
@@ -487,10 +487,14 @@ static int oxygen_hw_free(struct snd_pcm_substream *substream)
487{ 487{
488 struct oxygen *chip = snd_pcm_substream_chip(substream); 488 struct oxygen *chip = snd_pcm_substream_chip(substream);
489 unsigned int channel = oxygen_substream_channel(substream); 489 unsigned int channel = oxygen_substream_channel(substream);
490 unsigned int channel_mask = 1 << channel;
490 491
491 spin_lock_irq(&chip->reg_lock); 492 spin_lock_irq(&chip->reg_lock);
492 chip->interrupt_mask &= ~(1 << channel); 493 chip->interrupt_mask &= ~channel_mask;
493 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask); 494 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
495
496 oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
497 oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
494 spin_unlock_irq(&chip->reg_lock); 498 spin_unlock_irq(&chip->reg_lock);
495 499
496 return snd_pcm_lib_free_pages(substream); 500 return snd_pcm_lib_free_pages(substream);
diff --git a/sound/pci/oxygen/virtuoso.c b/sound/pci/oxygen/virtuoso.c
index bc5ce11c8b1..bf971f7cfdc 100644
--- a/sound/pci/oxygen/virtuoso.c
+++ b/sound/pci/oxygen/virtuoso.c
@@ -113,8 +113,8 @@
113 */ 113 */
114 114
115/* 115/*
116 * Xonar Essence STX 116 * Xonar Essence ST (Deluxe)/STX
117 * ----------------- 117 * -----------------------------
118 * 118 *
119 * CMI8788: 119 * CMI8788:
120 * 120 *
@@ -180,6 +180,8 @@ enum {
180 MODEL_DX, 180 MODEL_DX,
181 MODEL_HDAV, /* without daughterboard */ 181 MODEL_HDAV, /* without daughterboard */
182 MODEL_HDAV_H6, /* with H6 daughterboard */ 182 MODEL_HDAV_H6, /* with H6 daughterboard */
183 MODEL_ST,
184 MODEL_ST_H6,
183 MODEL_STX, 185 MODEL_STX,
184}; 186};
185 187
@@ -188,8 +190,10 @@ static struct pci_device_id xonar_ids[] __devinitdata = {
188 { OXYGEN_PCI_SUBID(0x1043, 0x8275), .driver_data = MODEL_DX }, 190 { OXYGEN_PCI_SUBID(0x1043, 0x8275), .driver_data = MODEL_DX },
189 { OXYGEN_PCI_SUBID(0x1043, 0x82b7), .driver_data = MODEL_D2X }, 191 { OXYGEN_PCI_SUBID(0x1043, 0x82b7), .driver_data = MODEL_D2X },
190 { OXYGEN_PCI_SUBID(0x1043, 0x8314), .driver_data = MODEL_HDAV }, 192 { OXYGEN_PCI_SUBID(0x1043, 0x8314), .driver_data = MODEL_HDAV },
193 { OXYGEN_PCI_SUBID(0x1043, 0x8327), .driver_data = MODEL_DX },
191 { OXYGEN_PCI_SUBID(0x1043, 0x834f), .driver_data = MODEL_D1 }, 194 { OXYGEN_PCI_SUBID(0x1043, 0x834f), .driver_data = MODEL_D1 },
192 { OXYGEN_PCI_SUBID(0x1043, 0x835c), .driver_data = MODEL_STX }, 195 { OXYGEN_PCI_SUBID(0x1043, 0x835c), .driver_data = MODEL_STX },
196 { OXYGEN_PCI_SUBID(0x1043, 0x835d), .driver_data = MODEL_ST },
193 { OXYGEN_PCI_SUBID_BROKEN_EEPROM }, 197 { OXYGEN_PCI_SUBID_BROKEN_EEPROM },
194 { } 198 { }
195}; 199};
@@ -210,9 +214,9 @@ MODULE_DEVICE_TABLE(pci, xonar_ids);
210#define GPIO_DX_FRONT_PANEL 0x0002 214#define GPIO_DX_FRONT_PANEL 0x0002
211#define GPIO_DX_INPUT_ROUTE 0x0100 215#define GPIO_DX_INPUT_ROUTE 0x0100
212 216
213#define GPIO_HDAV_DB_MASK 0x0030 217#define GPIO_DB_MASK 0x0030
214#define GPIO_HDAV_DB_H6 0x0000 218#define GPIO_DB_H6 0x0000
215#define GPIO_HDAV_DB_XX 0x0020 219#define GPIO_DB_XX 0x0020
216 220
217#define GPIO_ST_HP_REAR 0x0002 221#define GPIO_ST_HP_REAR 0x0002
218#define GPIO_ST_HP 0x0080 222#define GPIO_ST_HP 0x0080
@@ -530,7 +534,7 @@ static void xonar_hdav_init(struct oxygen *chip)
530 snd_component_add(chip->card, "CS5381"); 534 snd_component_add(chip->card, "CS5381");
531} 535}
532 536
533static void xonar_stx_init(struct oxygen *chip) 537static void xonar_st_init(struct oxygen *chip)
534{ 538{
535 struct xonar_data *data = chip->model_data; 539 struct xonar_data *data = chip->model_data;
536 540
@@ -539,12 +543,11 @@ static void xonar_stx_init(struct oxygen *chip)
539 OXYGEN_2WIRE_INTERRUPT_MASK | 543 OXYGEN_2WIRE_INTERRUPT_MASK |
540 OXYGEN_2WIRE_SPEED_FAST); 544 OXYGEN_2WIRE_SPEED_FAST);
541 545
546 if (chip->model.private_data == MODEL_ST_H6)
547 chip->model.dac_channels = 8;
542 data->anti_pop_delay = 100; 548 data->anti_pop_delay = 100;
543 data->dacs = 1; 549 data->dacs = chip->model.private_data == MODEL_ST_H6 ? 4 : 1;
544 data->output_enable_bit = GPIO_DX_OUTPUT_ENABLE; 550 data->output_enable_bit = GPIO_DX_OUTPUT_ENABLE;
545 data->ext_power_reg = OXYGEN_GPI_DATA;
546 data->ext_power_int_reg = OXYGEN_GPI_INTERRUPT_MASK;
547 data->ext_power_bit = GPI_DX_EXT_POWER;
548 data->pcm1796_oversampling = PCM1796_OS_64; 551 data->pcm1796_oversampling = PCM1796_OS_64;
549 552
550 pcm1796_init(chip); 553 pcm1796_init(chip);
@@ -560,6 +563,17 @@ static void xonar_stx_init(struct oxygen *chip)
560 snd_component_add(chip->card, "CS5381"); 563 snd_component_add(chip->card, "CS5381");
561} 564}
562 565
566static void xonar_stx_init(struct oxygen *chip)
567{
568 struct xonar_data *data = chip->model_data;
569
570 data->ext_power_reg = OXYGEN_GPI_DATA;
571 data->ext_power_int_reg = OXYGEN_GPI_INTERRUPT_MASK;
572 data->ext_power_bit = GPI_DX_EXT_POWER;
573
574 xonar_st_init(chip);
575}
576
563static void xonar_disable_output(struct oxygen *chip) 577static void xonar_disable_output(struct oxygen *chip)
564{ 578{
565 struct xonar_data *data = chip->model_data; 579 struct xonar_data *data = chip->model_data;
@@ -1021,7 +1035,8 @@ static const struct oxygen_model model_xonar_hdav = {
1021 .model_data_size = sizeof(struct xonar_data), 1035 .model_data_size = sizeof(struct xonar_data),
1022 .device_config = PLAYBACK_0_TO_I2S | 1036 .device_config = PLAYBACK_0_TO_I2S |
1023 PLAYBACK_1_TO_SPDIF | 1037 PLAYBACK_1_TO_SPDIF |
1024 CAPTURE_0_FROM_I2S_2, 1038 CAPTURE_0_FROM_I2S_2 |
1039 CAPTURE_1_FROM_SPDIF,
1025 .dac_channels = 8, 1040 .dac_channels = 8,
1026 .dac_volume_min = 255 - 2*60, 1041 .dac_volume_min = 255 - 2*60,
1027 .dac_volume_max = 255, 1042 .dac_volume_max = 255,
@@ -1034,7 +1049,7 @@ static const struct oxygen_model model_xonar_hdav = {
1034static const struct oxygen_model model_xonar_st = { 1049static const struct oxygen_model model_xonar_st = {
1035 .longname = "Asus Virtuoso 100", 1050 .longname = "Asus Virtuoso 100",
1036 .chip = "AV200", 1051 .chip = "AV200",
1037 .init = xonar_stx_init, 1052 .init = xonar_st_init,
1038 .control_filter = xonar_st_control_filter, 1053 .control_filter = xonar_st_control_filter,
1039 .mixer_init = xonar_st_mixer_init, 1054 .mixer_init = xonar_st_mixer_init,
1040 .cleanup = xonar_st_cleanup, 1055 .cleanup = xonar_st_cleanup,
@@ -1067,6 +1082,7 @@ static int __devinit get_xonar_model(struct oxygen *chip,
1067 [MODEL_D2] = &model_xonar_d2, 1082 [MODEL_D2] = &model_xonar_d2,
1068 [MODEL_D2X] = &model_xonar_d2, 1083 [MODEL_D2X] = &model_xonar_d2,
1069 [MODEL_HDAV] = &model_xonar_hdav, 1084 [MODEL_HDAV] = &model_xonar_hdav,
1085 [MODEL_ST] = &model_xonar_st,
1070 [MODEL_STX] = &model_xonar_st, 1086 [MODEL_STX] = &model_xonar_st,
1071 }; 1087 };
1072 static const char *const names[] = { 1088 static const char *const names[] = {
@@ -1076,6 +1092,8 @@ static int __devinit get_xonar_model(struct oxygen *chip,
1076 [MODEL_D2X] = "Xonar D2X", 1092 [MODEL_D2X] = "Xonar D2X",
1077 [MODEL_HDAV] = "Xonar HDAV1.3", 1093 [MODEL_HDAV] = "Xonar HDAV1.3",
1078 [MODEL_HDAV_H6] = "Xonar HDAV1.3+H6", 1094 [MODEL_HDAV_H6] = "Xonar HDAV1.3+H6",
1095 [MODEL_ST] = "Xonar Essence ST",
1096 [MODEL_ST_H6] = "Xonar Essence ST+H6",
1079 [MODEL_STX] = "Xonar Essence STX", 1097 [MODEL_STX] = "Xonar Essence STX",
1080 }; 1098 };
1081 unsigned int model = id->driver_data; 1099 unsigned int model = id->driver_data;
@@ -1092,21 +1110,27 @@ static int __devinit get_xonar_model(struct oxygen *chip,
1092 chip->model.init = xonar_dx_init; 1110 chip->model.init = xonar_dx_init;
1093 break; 1111 break;
1094 case MODEL_HDAV: 1112 case MODEL_HDAV:
1095 oxygen_clear_bits16(chip, OXYGEN_GPIO_CONTROL, 1113 oxygen_clear_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_DB_MASK);
1096 GPIO_HDAV_DB_MASK); 1114 switch (oxygen_read16(chip, OXYGEN_GPIO_DATA) & GPIO_DB_MASK) {
1097 switch (oxygen_read16(chip, OXYGEN_GPIO_DATA) & 1115 case GPIO_DB_H6:
1098 GPIO_HDAV_DB_MASK) {
1099 case GPIO_HDAV_DB_H6:
1100 model = MODEL_HDAV_H6; 1116 model = MODEL_HDAV_H6;
1101 break; 1117 break;
1102 case GPIO_HDAV_DB_XX: 1118 case GPIO_DB_XX:
1103 snd_printk(KERN_ERR "unknown daughterboard\n"); 1119 snd_printk(KERN_ERR "unknown daughterboard\n");
1104 return -ENODEV; 1120 return -ENODEV;
1105 } 1121 }
1106 break; 1122 break;
1123 case MODEL_ST:
1124 oxygen_clear_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_DB_MASK);
1125 switch (oxygen_read16(chip, OXYGEN_GPIO_DATA) & GPIO_DB_MASK) {
1126 case GPIO_DB_H6:
1127 model = MODEL_ST_H6;
1128 break;
1129 }
1130 break;
1107 case MODEL_STX: 1131 case MODEL_STX:
1108 oxygen_clear_bits16(chip, OXYGEN_GPIO_CONTROL, 1132 chip->model.init = xonar_stx_init;
1109 GPIO_HDAV_DB_MASK); 1133 oxygen_clear_bits16(chip, OXYGEN_GPIO_CONTROL, GPIO_DB_MASK);
1110 break; 1134 break;
1111 } 1135 }
1112 1136
diff --git a/sound/pci/riptide/riptide.c b/sound/pci/riptide/riptide.c
index 6f1034417a0..235a71e5ac8 100644
--- a/sound/pci/riptide/riptide.c
+++ b/sound/pci/riptide/riptide.c
@@ -507,41 +507,19 @@ static int riptide_reset(struct cmdif *cif, struct snd_riptide *chip);
507 */ 507 */
508 508
509static struct pci_device_id snd_riptide_ids[] = { 509static struct pci_device_id snd_riptide_ids[] = {
510 { 510 { PCI_DEVICE(0x127a, 0x4310) },
511 .vendor = 0x127a,.device = 0x4310, 511 { PCI_DEVICE(0x127a, 0x4320) },
512 .subvendor = PCI_ANY_ID,.subdevice = PCI_ANY_ID, 512 { PCI_DEVICE(0x127a, 0x4330) },
513 }, 513 { PCI_DEVICE(0x127a, 0x4340) },
514 {
515 .vendor = 0x127a,.device = 0x4320,
516 .subvendor = PCI_ANY_ID,.subdevice = PCI_ANY_ID,
517 },
518 {
519 .vendor = 0x127a,.device = 0x4330,
520 .subvendor = PCI_ANY_ID,.subdevice = PCI_ANY_ID,
521 },
522 {
523 .vendor = 0x127a,.device = 0x4340,
524 .subvendor = PCI_ANY_ID,.subdevice = PCI_ANY_ID,
525 },
526 {0,}, 514 {0,},
527}; 515};
528 516
529#ifdef SUPPORT_JOYSTICK 517#ifdef SUPPORT_JOYSTICK
530static struct pci_device_id snd_riptide_joystick_ids[] __devinitdata = { 518static struct pci_device_id snd_riptide_joystick_ids[] __devinitdata = {
531 { 519 { PCI_DEVICE(0x127a, 0x4312) },
532 .vendor = 0x127a,.device = 0x4312, 520 { PCI_DEVICE(0x127a, 0x4322) },
533 .subvendor = PCI_ANY_ID,.subdevice = PCI_ANY_ID, 521 { PCI_DEVICE(0x127a, 0x4332) },
534 }, 522 { PCI_DEVICE(0x127a, 0x4342) },
535 {
536 .vendor = 0x127a,.device = 0x4322,
537 .subvendor = PCI_ANY_ID,.subdevice = PCI_ANY_ID,
538 },
539 {.vendor = 0x127a,.device = 0x4332,
540 .subvendor = PCI_ANY_ID,.subdevice = PCI_ANY_ID,
541 },
542 {.vendor = 0x127a,.device = 0x4342,
543 .subvendor = PCI_ANY_ID,.subdevice = PCI_ANY_ID,
544 },
545 {0,}, 523 {0,},
546}; 524};
547#endif 525#endif
@@ -889,7 +867,7 @@ static int sendcmd(struct cmdif *cif, u32 flags, u32 cmd, u32 parm,
889 spin_lock_irqsave(&cif->lock, irqflags); 867 spin_lock_irqsave(&cif->lock, irqflags);
890 while (i++ < CMDIF_TIMEOUT && !IS_READY(cif->hwport)) 868 while (i++ < CMDIF_TIMEOUT && !IS_READY(cif->hwport))
891 udelay(10); 869 udelay(10);
892 if (i >= CMDIF_TIMEOUT) { 870 if (i > CMDIF_TIMEOUT) {
893 err = -EBUSY; 871 err = -EBUSY;
894 goto errout; 872 goto errout;
895 } 873 }
@@ -907,8 +885,10 @@ static int sendcmd(struct cmdif *cif, u32 flags, u32 cmd, u32 parm,
907 WRITE_PORT_ULONG(cmdport->data1, cmd); /* write cmd */ 885 WRITE_PORT_ULONG(cmdport->data1, cmd); /* write cmd */
908 if ((flags & RESP) && ret) { 886 if ((flags & RESP) && ret) {
909 while (!IS_DATF(cmdport) && 887 while (!IS_DATF(cmdport) &&
910 time++ < CMDIF_TIMEOUT) 888 time < CMDIF_TIMEOUT) {
911 udelay(10); 889 udelay(10);
890 time++;
891 }
912 if (time < CMDIF_TIMEOUT) { /* read response */ 892 if (time < CMDIF_TIMEOUT) { /* read response */
913 ret->retlongs[0] = 893 ret->retlongs[0] =
914 READ_PORT_ULONG(cmdport->data1); 894 READ_PORT_ULONG(cmdport->data1);
@@ -1207,12 +1187,79 @@ static int riptide_resume(struct pci_dev *pci)
1207} 1187}
1208#endif 1188#endif
1209 1189
1190static int try_to_load_firmware(struct cmdif *cif, struct snd_riptide *chip)
1191{
1192 union firmware_version firmware = { .ret = CMDRET_ZERO };
1193 int i, timeout, err;
1194
1195 for (i = 0; i < 2; i++) {
1196 WRITE_PORT_ULONG(cif->hwport->port[i].data1, 0);
1197 WRITE_PORT_ULONG(cif->hwport->port[i].data2, 0);
1198 }
1199 SET_GRESET(cif->hwport);
1200 udelay(100);
1201 UNSET_GRESET(cif->hwport);
1202 udelay(100);
1203
1204 for (timeout = 100000; --timeout; udelay(10)) {
1205 if (IS_READY(cif->hwport) && !IS_GERR(cif->hwport))
1206 break;
1207 }
1208 if (!timeout) {
1209 snd_printk(KERN_ERR
1210 "Riptide: device not ready, audio status: 0x%x "
1211 "ready: %d gerr: %d\n",
1212 READ_AUDIO_STATUS(cif->hwport),
1213 IS_READY(cif->hwport), IS_GERR(cif->hwport));
1214 return -EIO;
1215 } else {
1216 snd_printdd
1217 ("Riptide: audio status: 0x%x ready: %d gerr: %d\n",
1218 READ_AUDIO_STATUS(cif->hwport),
1219 IS_READY(cif->hwport), IS_GERR(cif->hwport));
1220 }
1221
1222 SEND_GETV(cif, &firmware.ret);
1223 snd_printdd("Firmware version: ASIC: %d CODEC %d AUXDSP %d PROG %d\n",
1224 firmware.firmware.ASIC, firmware.firmware.CODEC,
1225 firmware.firmware.AUXDSP, firmware.firmware.PROG);
1226
1227 for (i = 0; i < FIRMWARE_VERSIONS; i++) {
1228 if (!memcmp(&firmware_versions[i], &firmware, sizeof(firmware)))
1229 break;
1230 }
1231 if (i >= FIRMWARE_VERSIONS)
1232 return 0; /* no match */
1233
1234 if (!chip)
1235 return 1; /* OK */
1236
1237 snd_printdd("Writing Firmware\n");
1238 if (!chip->fw_entry) {
1239 err = request_firmware(&chip->fw_entry, "riptide.hex",
1240 &chip->pci->dev);
1241 if (err) {
1242 snd_printk(KERN_ERR
1243 "Riptide: Firmware not available %d\n", err);
1244 return -EIO;
1245 }
1246 }
1247 err = loadfirmware(cif, chip->fw_entry->data, chip->fw_entry->size);
1248 if (err) {
1249 snd_printk(KERN_ERR
1250 "Riptide: Could not load firmware %d\n", err);
1251 return err;
1252 }
1253
1254 chip->firmware = firmware;
1255
1256 return 1; /* OK */
1257}
1258
1210static int riptide_reset(struct cmdif *cif, struct snd_riptide *chip) 1259static int riptide_reset(struct cmdif *cif, struct snd_riptide *chip)
1211{ 1260{
1212 int timeout, tries;
1213 union cmdret rptr = CMDRET_ZERO; 1261 union cmdret rptr = CMDRET_ZERO;
1214 union firmware_version firmware; 1262 int err, tries;
1215 int i, j, err, has_firmware;
1216 1263
1217 if (!cif) 1264 if (!cif)
1218 return -EINVAL; 1265 return -EINVAL;
@@ -1225,75 +1272,11 @@ static int riptide_reset(struct cmdif *cif, struct snd_riptide *chip)
1225 cif->is_reset = 0; 1272 cif->is_reset = 0;
1226 1273
1227 tries = RESET_TRIES; 1274 tries = RESET_TRIES;
1228 has_firmware = 0; 1275 do {
1229 while (has_firmware == 0 && tries-- > 0) { 1276 err = try_to_load_firmware(cif, chip);
1230 for (i = 0; i < 2; i++) { 1277 if (err < 0)
1231 WRITE_PORT_ULONG(cif->hwport->port[i].data1, 0); 1278 return err;
1232 WRITE_PORT_ULONG(cif->hwport->port[i].data2, 0); 1279 } while (!err && --tries);
1233 }
1234 SET_GRESET(cif->hwport);
1235 udelay(100);
1236 UNSET_GRESET(cif->hwport);
1237 udelay(100);
1238
1239 for (timeout = 100000; --timeout; udelay(10)) {
1240 if (IS_READY(cif->hwport) && !IS_GERR(cif->hwport))
1241 break;
1242 }
1243 if (timeout == 0) {
1244 snd_printk(KERN_ERR
1245 "Riptide: device not ready, audio status: 0x%x ready: %d gerr: %d\n",
1246 READ_AUDIO_STATUS(cif->hwport),
1247 IS_READY(cif->hwport), IS_GERR(cif->hwport));
1248 return -EIO;
1249 } else {
1250 snd_printdd
1251 ("Riptide: audio status: 0x%x ready: %d gerr: %d\n",
1252 READ_AUDIO_STATUS(cif->hwport),
1253 IS_READY(cif->hwport), IS_GERR(cif->hwport));
1254 }
1255
1256 SEND_GETV(cif, &rptr);
1257 for (i = 0; i < 4; i++)
1258 firmware.ret.retwords[i] = rptr.retwords[i];
1259
1260 snd_printdd
1261 ("Firmware version: ASIC: %d CODEC %d AUXDSP %d PROG %d\n",
1262 firmware.firmware.ASIC, firmware.firmware.CODEC,
1263 firmware.firmware.AUXDSP, firmware.firmware.PROG);
1264
1265 for (j = 0; j < FIRMWARE_VERSIONS; j++) {
1266 has_firmware = 1;
1267 for (i = 0; i < 4; i++) {
1268 if (firmware_versions[j].ret.retwords[i] !=
1269 firmware.ret.retwords[i])
1270 has_firmware = 0;
1271 }
1272 if (has_firmware)
1273 break;
1274 }
1275
1276 if (chip != NULL && has_firmware == 0) {
1277 snd_printdd("Writing Firmware\n");
1278 if (!chip->fw_entry) {
1279 if ((err =
1280 request_firmware(&chip->fw_entry,
1281 "riptide.hex",
1282 &chip->pci->dev)) != 0) {
1283 snd_printk(KERN_ERR
1284 "Riptide: Firmware not available %d\n",
1285 err);
1286 return -EIO;
1287 }
1288 }
1289 err = loadfirmware(cif, chip->fw_entry->data,
1290 chip->fw_entry->size);
1291 if (err)
1292 snd_printk(KERN_ERR
1293 "Riptide: Could not load firmware %d\n",
1294 err);
1295 }
1296 }
1297 1280
1298 SEND_SACR(cif, 0, AC97_RESET); 1281 SEND_SACR(cif, 0, AC97_RESET);
1299 SEND_RACR(cif, AC97_RESET, &rptr); 1282 SEND_RACR(cif, AC97_RESET, &rptr);
@@ -1335,11 +1318,6 @@ static int riptide_reset(struct cmdif *cif, struct snd_riptide *chip)
1335 SET_AIE(cif->hwport); 1318 SET_AIE(cif->hwport);
1336 SET_AIACK(cif->hwport); 1319 SET_AIACK(cif->hwport);
1337 cif->is_reset = 1; 1320 cif->is_reset = 1;
1338 if (chip) {
1339 for (i = 0; i < 4; i++)
1340 chip->firmware.ret.retwords[i] =
1341 firmware.ret.retwords[i];
1342 }
1343 1321
1344 return 0; 1322 return 0;
1345} 1323}
@@ -1454,7 +1432,7 @@ static int snd_riptide_trigger(struct snd_pcm_substream *substream, int cmd)
1454 SEND_GPOS(cif, 0, data->id, &rptr); 1432 SEND_GPOS(cif, 0, data->id, &rptr);
1455 udelay(1); 1433 udelay(1);
1456 } while (i != rptr.retlongs[1] && j++ < MAX_WRITE_RETRY); 1434 } while (i != rptr.retlongs[1] && j++ < MAX_WRITE_RETRY);
1457 if (j >= MAX_WRITE_RETRY) 1435 if (j > MAX_WRITE_RETRY)
1458 snd_printk(KERN_ERR "Riptide: Could not stop stream!"); 1436 snd_printk(KERN_ERR "Riptide: Could not stop stream!");
1459 break; 1437 break;
1460 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1438 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
@@ -1783,7 +1761,7 @@ snd_riptide_codec_write(struct snd_ac97 *ac97, unsigned short reg,
1783 SEND_SACR(cif, val, reg); 1761 SEND_SACR(cif, val, reg);
1784 SEND_RACR(cif, reg, &rptr); 1762 SEND_RACR(cif, reg, &rptr);
1785 } while (rptr.retwords[1] != val && i++ < MAX_WRITE_RETRY); 1763 } while (rptr.retwords[1] != val && i++ < MAX_WRITE_RETRY);
1786 if (i == MAX_WRITE_RETRY) 1764 if (i > MAX_WRITE_RETRY)
1787 snd_printdd("Write AC97 reg failed\n"); 1765 snd_printdd("Write AC97 reg failed\n");
1788} 1766}
1789 1767
@@ -2036,14 +2014,12 @@ static int __devinit snd_riptide_mixer(struct snd_riptide *chip)
2036} 2014}
2037 2015
2038#ifdef SUPPORT_JOYSTICK 2016#ifdef SUPPORT_JOYSTICK
2039static int have_joystick;
2040static struct pci_dev *riptide_gameport_pci;
2041static struct gameport *riptide_gameport;
2042 2017
2043static int __devinit 2018static int __devinit
2044snd_riptide_joystick_probe(struct pci_dev *pci, const struct pci_device_id *id) 2019snd_riptide_joystick_probe(struct pci_dev *pci, const struct pci_device_id *id)
2045{ 2020{
2046 static int dev; 2021 static int dev;
2022 struct gameport *gameport;
2047 2023
2048 if (dev >= SNDRV_CARDS) 2024 if (dev >= SNDRV_CARDS)
2049 return -ENODEV; 2025 return -ENODEV;
@@ -2052,36 +2028,33 @@ snd_riptide_joystick_probe(struct pci_dev *pci, const struct pci_device_id *id)
2052 return -ENOENT; 2028 return -ENOENT;
2053 } 2029 }
2054 2030
2055 if (joystick_port[dev]) { 2031 if (!joystick_port[dev++])
2056 riptide_gameport = gameport_allocate_port(); 2032 return 0;
2057 if (riptide_gameport) { 2033
2058 if (!request_region 2034 gameport = gameport_allocate_port();
2059 (joystick_port[dev], 8, "Riptide gameport")) { 2035 if (!gameport)
2060 snd_printk(KERN_WARNING 2036 return -ENOMEM;
2061 "Riptide: cannot grab gameport 0x%x\n", 2037 if (!request_region(joystick_port[dev], 8, "Riptide gameport")) {
2062 joystick_port[dev]); 2038 snd_printk(KERN_WARNING
2063 gameport_free_port(riptide_gameport); 2039 "Riptide: cannot grab gameport 0x%x\n",
2064 riptide_gameport = NULL; 2040 joystick_port[dev]);
2065 } else { 2041 gameport_free_port(gameport);
2066 riptide_gameport_pci = pci; 2042 return -EBUSY;
2067 riptide_gameport->io = joystick_port[dev];
2068 gameport_register_port(riptide_gameport);
2069 }
2070 }
2071 } 2043 }
2072 dev++; 2044
2045 gameport->io = joystick_port[dev];
2046 gameport_register_port(gameport);
2047 pci_set_drvdata(pci, gameport);
2073 return 0; 2048 return 0;
2074} 2049}
2075 2050
2076static void __devexit snd_riptide_joystick_remove(struct pci_dev *pci) 2051static void __devexit snd_riptide_joystick_remove(struct pci_dev *pci)
2077{ 2052{
2078 if (riptide_gameport) { 2053 struct gameport *gameport = pci_get_drvdata(pci);
2079 if (riptide_gameport_pci == pci) { 2054 if (gameport) {
2080 release_region(riptide_gameport->io, 8); 2055 release_region(gameport->io, 8);
2081 riptide_gameport_pci = NULL; 2056 gameport_unregister_port(gameport);
2082 gameport_unregister_port(riptide_gameport); 2057 pci_set_drvdata(pci, NULL);
2083 riptide_gameport = NULL;
2084 }
2085 } 2058 }
2086} 2059}
2087#endif 2060#endif
@@ -2092,8 +2065,8 @@ snd_card_riptide_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2092 static int dev; 2065 static int dev;
2093 struct snd_card *card; 2066 struct snd_card *card;
2094 struct snd_riptide *chip; 2067 struct snd_riptide *chip;
2095 unsigned short addr; 2068 unsigned short val;
2096 int err = 0; 2069 int err;
2097 2070
2098 if (dev >= SNDRV_CARDS) 2071 if (dev >= SNDRV_CARDS)
2099 return -ENODEV; 2072 return -ENODEV;
@@ -2105,60 +2078,63 @@ snd_card_riptide_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2105 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card); 2078 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2106 if (err < 0) 2079 if (err < 0)
2107 return err; 2080 return err;
2108 if ((err = snd_riptide_create(card, pci, &chip)) < 0) { 2081 err = snd_riptide_create(card, pci, &chip);
2109 snd_card_free(card); 2082 if (err < 0)
2110 return err; 2083 goto error;
2111 }
2112 card->private_data = chip; 2084 card->private_data = chip;
2113 if ((err = snd_riptide_pcm(chip, 0, NULL)) < 0) { 2085 err = snd_riptide_pcm(chip, 0, NULL);
2114 snd_card_free(card); 2086 if (err < 0)
2115 return err; 2087 goto error;
2116 } 2088 err = snd_riptide_mixer(chip);
2117 if ((err = snd_riptide_mixer(chip)) < 0) { 2089 if (err < 0)
2118 snd_card_free(card); 2090 goto error;
2119 return err; 2091
2120 } 2092 val = LEGACY_ENABLE_ALL;
2121 pci_write_config_word(chip->pci, PCI_EXT_Legacy_Mask, LEGACY_ENABLE_ALL 2093 if (opl3_port[dev])
2122 | (opl3_port[dev] ? LEGACY_ENABLE_FM : 0) 2094 val |= LEGACY_ENABLE_FM;
2123#ifdef SUPPORT_JOYSTICK 2095#ifdef SUPPORT_JOYSTICK
2124 | (joystick_port[dev] ? LEGACY_ENABLE_GAMEPORT : 2096 if (joystick_port[dev])
2125 0) 2097 val |= LEGACY_ENABLE_GAMEPORT;
2126#endif 2098#endif
2127 | (mpu_port[dev] 2099 if (mpu_port[dev])
2128 ? (LEGACY_ENABLE_MPU_INT | LEGACY_ENABLE_MPU) : 2100 val |= LEGACY_ENABLE_MPU_INT | LEGACY_ENABLE_MPU;
2129 0) 2101 val |= (chip->irq << 4) & 0xf0;
2130 | ((chip->irq << 4) & 0xF0)); 2102 pci_write_config_word(chip->pci, PCI_EXT_Legacy_Mask, val);
2131 if ((addr = mpu_port[dev]) != 0) { 2103 if (mpu_port[dev]) {
2132 pci_write_config_word(chip->pci, PCI_EXT_MPU_Base, addr); 2104 val = mpu_port[dev];
2133 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_RIPTIDE, 2105 pci_write_config_word(chip->pci, PCI_EXT_MPU_Base, val);
2134 addr, 0, chip->irq, 0, 2106 err = snd_mpu401_uart_new(card, 0, MPU401_HW_RIPTIDE,
2135 &chip->rmidi)) < 0) 2107 val, 0, chip->irq, 0,
2108 &chip->rmidi);
2109 if (err < 0)
2136 snd_printk(KERN_WARNING 2110 snd_printk(KERN_WARNING
2137 "Riptide: Can't Allocate MPU at 0x%x\n", 2111 "Riptide: Can't Allocate MPU at 0x%x\n",
2138 addr); 2112 val);
2139 else 2113 else
2140 chip->mpuaddr = addr; 2114 chip->mpuaddr = val;
2141 } 2115 }
2142 if ((addr = opl3_port[dev]) != 0) { 2116 if (opl3_port[dev]) {
2143 pci_write_config_word(chip->pci, PCI_EXT_FM_Base, addr); 2117 val = opl3_port[dev];
2144 if ((err = snd_opl3_create(card, addr, addr + 2, 2118 pci_write_config_word(chip->pci, PCI_EXT_FM_Base, val);
2145 OPL3_HW_RIPTIDE, 0, 2119 err = snd_opl3_create(card, val, val + 2,
2146 &chip->opl3)) < 0) 2120 OPL3_HW_RIPTIDE, 0, &chip->opl3);
2121 if (err < 0)
2147 snd_printk(KERN_WARNING 2122 snd_printk(KERN_WARNING
2148 "Riptide: Can't Allocate OPL3 at 0x%x\n", 2123 "Riptide: Can't Allocate OPL3 at 0x%x\n",
2149 addr); 2124 val);
2150 else { 2125 else {
2151 chip->opladdr = addr; 2126 chip->opladdr = val;
2152 if ((err = 2127 err = snd_opl3_hwdep_new(chip->opl3, 0, 1, NULL);
2153 snd_opl3_hwdep_new(chip->opl3, 0, 1, NULL)) < 0) 2128 if (err < 0)
2154 snd_printk(KERN_WARNING 2129 snd_printk(KERN_WARNING
2155 "Riptide: Can't Allocate OPL3-HWDEP\n"); 2130 "Riptide: Can't Allocate OPL3-HWDEP\n");
2156 } 2131 }
2157 } 2132 }
2158#ifdef SUPPORT_JOYSTICK 2133#ifdef SUPPORT_JOYSTICK
2159 if ((addr = joystick_port[dev]) != 0) { 2134 if (joystick_port[dev]) {
2160 pci_write_config_word(chip->pci, PCI_EXT_Game_Base, addr); 2135 val = joystick_port[dev];
2161 chip->gameaddr = addr; 2136 pci_write_config_word(chip->pci, PCI_EXT_Game_Base, val);
2137 chip->gameaddr = val;
2162 } 2138 }
2163#endif 2139#endif
2164 2140
@@ -2176,13 +2152,16 @@ snd_card_riptide_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2176 chip->opladdr); 2152 chip->opladdr);
2177#endif 2153#endif
2178 snd_riptide_proc_init(chip); 2154 snd_riptide_proc_init(chip);
2179 if ((err = snd_card_register(card)) < 0) { 2155 err = snd_card_register(card);
2180 snd_card_free(card); 2156 if (err < 0)
2181 return err; 2157 goto error;
2182 }
2183 pci_set_drvdata(pci, card); 2158 pci_set_drvdata(pci, card);
2184 dev++; 2159 dev++;
2185 return 0; 2160 return 0;
2161
2162 error:
2163 snd_card_free(card);
2164 return err;
2186} 2165}
2187 2166
2188static void __devexit snd_card_riptide_remove(struct pci_dev *pci) 2167static void __devexit snd_card_riptide_remove(struct pci_dev *pci)
@@ -2214,14 +2193,11 @@ static struct pci_driver joystick_driver = {
2214static int __init alsa_card_riptide_init(void) 2193static int __init alsa_card_riptide_init(void)
2215{ 2194{
2216 int err; 2195 int err;
2217 if ((err = pci_register_driver(&driver)) < 0) 2196 err = pci_register_driver(&driver);
2197 if (err < 0)
2218 return err; 2198 return err;
2219#if defined(SUPPORT_JOYSTICK) 2199#if defined(SUPPORT_JOYSTICK)
2220 if (pci_register_driver(&joystick_driver) < 0) { 2200 pci_register_driver(&joystick_driver);
2221 have_joystick = 0;
2222 snd_printk(KERN_INFO "no joystick found\n");
2223 } else
2224 have_joystick = 1;
2225#endif 2201#endif
2226 return 0; 2202 return 0;
2227} 2203}
@@ -2230,8 +2206,7 @@ static void __exit alsa_card_riptide_exit(void)
2230{ 2206{
2231 pci_unregister_driver(&driver); 2207 pci_unregister_driver(&driver);
2232#if defined(SUPPORT_JOYSTICK) 2208#if defined(SUPPORT_JOYSTICK)
2233 if (have_joystick) 2209 pci_unregister_driver(&joystick_driver);
2234 pci_unregister_driver(&joystick_driver);
2235#endif 2210#endif
2236} 2211}
2237 2212
diff --git a/sound/pci/rme9652/hdsp.c b/sound/pci/rme9652/hdsp.c
index 314e73531bd..3da5c029f93 100644
--- a/sound/pci/rme9652/hdsp.c
+++ b/sound/pci/rme9652/hdsp.c
@@ -28,6 +28,7 @@
28#include <linux/pci.h> 28#include <linux/pci.h>
29#include <linux/firmware.h> 29#include <linux/firmware.h>
30#include <linux/moduleparam.h> 30#include <linux/moduleparam.h>
31#include <linux/math64.h>
31 32
32#include <sound/core.h> 33#include <sound/core.h>
33#include <sound/control.h> 34#include <sound/control.h>
@@ -402,9 +403,9 @@ MODULE_FIRMWARE("digiface_firmware_rev11.bin");
402#define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES) 403#define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
403#define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024) 404#define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
404 405
405/* use hotplug firmeare loader? */ 406/* use hotplug firmware loader? */
406#if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE) 407#if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE)
407#if !defined(HDSP_USE_HWDEP_LOADER) && !defined(CONFIG_SND_HDSP) 408#if !defined(HDSP_USE_HWDEP_LOADER)
408#define HDSP_FW_LOADER 409#define HDSP_FW_LOADER
409#endif 410#endif
410#endif 411#endif
@@ -1047,7 +1048,6 @@ static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1047static void hdsp_set_dds_value(struct hdsp *hdsp, int rate) 1048static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1048{ 1049{
1049 u64 n; 1050 u64 n;
1050 u32 r;
1051 1051
1052 if (rate >= 112000) 1052 if (rate >= 112000)
1053 rate /= 4; 1053 rate /= 4;
@@ -1055,7 +1055,7 @@ static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1055 rate /= 2; 1055 rate /= 2;
1056 1056
1057 n = DDS_NUMERATOR; 1057 n = DDS_NUMERATOR;
1058 div64_32(&n, rate, &r); 1058 n = div_u64(n, rate);
1059 /* n should be less than 2^32 for being written to FREQ register */ 1059 /* n should be less than 2^32 for being written to FREQ register */
1060 snd_BUG_ON(n >> 32); 1060 snd_BUG_ON(n >> 32);
1061 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS 1061 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
@@ -3097,7 +3097,6 @@ static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct sn
3097static int hdsp_dds_offset(struct hdsp *hdsp) 3097static int hdsp_dds_offset(struct hdsp *hdsp)
3098{ 3098{
3099 u64 n; 3099 u64 n;
3100 u32 r;
3101 unsigned int dds_value = hdsp->dds_value; 3100 unsigned int dds_value = hdsp->dds_value;
3102 int system_sample_rate = hdsp->system_sample_rate; 3101 int system_sample_rate = hdsp->system_sample_rate;
3103 3102
@@ -3109,7 +3108,7 @@ static int hdsp_dds_offset(struct hdsp *hdsp)
3109 * dds_value = n / rate 3108 * dds_value = n / rate
3110 * rate = n / dds_value 3109 * rate = n / dds_value
3111 */ 3110 */
3112 div64_32(&n, dds_value, &r); 3111 n = div_u64(n, dds_value);
3113 if (system_sample_rate >= 112000) 3112 if (system_sample_rate >= 112000)
3114 n *= 4; 3113 n *= 4;
3115 else if (system_sample_rate >= 56000) 3114 else if (system_sample_rate >= 56000)
diff --git a/sound/pci/rme9652/hdspm.c b/sound/pci/rme9652/hdspm.c
index bac2dc0c5d8..0dce331a2a3 100644
--- a/sound/pci/rme9652/hdspm.c
+++ b/sound/pci/rme9652/hdspm.c
@@ -29,6 +29,7 @@
29#include <linux/moduleparam.h> 29#include <linux/moduleparam.h>
30#include <linux/slab.h> 30#include <linux/slab.h>
31#include <linux/pci.h> 31#include <linux/pci.h>
32#include <linux/math64.h>
32#include <asm/io.h> 33#include <asm/io.h>
33 34
34#include <sound/core.h> 35#include <sound/core.h>
@@ -831,7 +832,6 @@ static int hdspm_set_interrupt_interval(struct hdspm * s, unsigned int frames)
831static void hdspm_set_dds_value(struct hdspm *hdspm, int rate) 832static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
832{ 833{
833 u64 n; 834 u64 n;
834 u32 r;
835 835
836 if (rate >= 112000) 836 if (rate >= 112000)
837 rate /= 4; 837 rate /= 4;
@@ -844,7 +844,7 @@ static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
844 */ 844 */
845 /* n = 104857600000000ULL; */ /* = 2^20 * 10^8 */ 845 /* n = 104857600000000ULL; */ /* = 2^20 * 10^8 */
846 n = 110100480000000ULL; /* Value checked for AES32 and MADI */ 846 n = 110100480000000ULL; /* Value checked for AES32 and MADI */
847 div64_32(&n, rate, &r); 847 n = div_u64(n, rate);
848 /* n should be less than 2^32 for being written to FREQ register */ 848 /* n should be less than 2^32 for being written to FREQ register */
849 snd_BUG_ON(n >> 32); 849 snd_BUG_ON(n >> 32);
850 hdspm_write(hdspm, HDSPM_freqReg, (u32)n); 850 hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
diff --git a/sound/pci/via82xx.c b/sound/pci/via82xx.c
index 809b233dd4a..1ef58c51c21 100644
--- a/sound/pci/via82xx.c
+++ b/sound/pci/via82xx.c
@@ -1687,7 +1687,7 @@ static int snd_via8233_pcmdxs_volume_put(struct snd_kcontrol *kcontrol,
1687 return change; 1687 return change;
1688} 1688}
1689 1689
1690static const DECLARE_TLV_DB_SCALE(db_scale_dxs, -9450, 150, 1); 1690static const DECLARE_TLV_DB_SCALE(db_scale_dxs, -4650, 150, 1);
1691 1691
1692static struct snd_kcontrol_new snd_via8233_pcmdxs_volume_control __devinitdata = { 1692static struct snd_kcontrol_new snd_via8233_pcmdxs_volume_control __devinitdata = {
1693 .name = "PCM Playback Volume", 1693 .name = "PCM Playback Volume",
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-20 18:47:39 -0400