diff options
Diffstat (limited to 'include/linux/mtd/sh_flctl.h')
-rw-r--r-- | include/linux/mtd/sh_flctl.h | 23 |
1 files changed, 16 insertions, 7 deletions
diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h index a38e1fa8af0..01e4b15b280 100644 --- a/include/linux/mtd/sh_flctl.h +++ b/include/linux/mtd/sh_flctl.h | |||
@@ -49,7 +49,6 @@ | |||
49 | #define FLERRADR(f) (f->reg + 0x98) | 49 | #define FLERRADR(f) (f->reg + 0x98) |
50 | 50 | ||
51 | /* FLCMNCR control bits */ | 51 | /* FLCMNCR control bits */ |
52 | #define ECCPOS2 (0x1 << 25) | ||
53 | #define _4ECCCNTEN (0x1 << 24) | 52 | #define _4ECCCNTEN (0x1 << 24) |
54 | #define _4ECCEN (0x1 << 23) | 53 | #define _4ECCEN (0x1 << 23) |
55 | #define _4ECCCORRECT (0x1 << 22) | 54 | #define _4ECCCORRECT (0x1 << 22) |
@@ -59,9 +58,6 @@ | |||
59 | #define QTSEL_E (0x1 << 17) | 58 | #define QTSEL_E (0x1 << 17) |
60 | #define ENDIAN (0x1 << 16) /* 1 = little endian */ | 59 | #define ENDIAN (0x1 << 16) /* 1 = little endian */ |
61 | #define FCKSEL_E (0x1 << 15) | 60 | #define FCKSEL_E (0x1 << 15) |
62 | #define ECCPOS_00 (0x00 << 12) | ||
63 | #define ECCPOS_01 (0x01 << 12) | ||
64 | #define ECCPOS_02 (0x02 << 12) | ||
65 | #define ACM_SACCES_MODE (0x01 << 10) | 61 | #define ACM_SACCES_MODE (0x01 << 10) |
66 | #define NANWF_E (0x1 << 9) | 62 | #define NANWF_E (0x1 << 9) |
67 | #define SE_D (0x1 << 8) /* Spare area disable */ | 63 | #define SE_D (0x1 << 8) /* Spare area disable */ |
@@ -107,6 +103,14 @@ | |||
107 | #define DOCMD2_E (0x1 << 17) /* 2nd cmd stage execute */ | 103 | #define DOCMD2_E (0x1 << 17) /* 2nd cmd stage execute */ |
108 | #define DOCMD1_E (0x1 << 16) /* 1st cmd stage execute */ | 104 | #define DOCMD1_E (0x1 << 16) /* 1st cmd stage execute */ |
109 | 105 | ||
106 | /* FLINTDMACR control bits */ | ||
107 | #define ESTERINTE (0x1 << 24) /* ECC error interrupt enable */ | ||
108 | #define AC1CLR (0x1 << 19) /* ECC FIFO clear */ | ||
109 | #define AC0CLR (0x1 << 18) /* Data FIFO clear */ | ||
110 | #define ECERB (0x1 << 9) /* ECC error */ | ||
111 | #define STERB (0x1 << 8) /* Status error */ | ||
112 | #define STERINTE (0x1 << 4) /* Status error enable */ | ||
113 | |||
110 | /* FLTRCR control bits */ | 114 | /* FLTRCR control bits */ |
111 | #define TRSTRT (0x1 << 0) /* translation start */ | 115 | #define TRSTRT (0x1 << 0) /* translation start */ |
112 | #define TREND (0x1 << 1) /* translation end */ | 116 | #define TREND (0x1 << 1) /* translation end */ |
@@ -125,9 +129,15 @@ | |||
125 | #define _4ECCEND (0x1 << 1) /* 4 symbols end */ | 129 | #define _4ECCEND (0x1 << 1) /* 4 symbols end */ |
126 | #define _4ECCEXST (0x1 << 0) /* 4 symbols exist */ | 130 | #define _4ECCEXST (0x1 << 0) /* 4 symbols exist */ |
127 | 131 | ||
128 | #define INIT_FL4ECCRESULT_VAL 0x03FF03FF | ||
129 | #define LOOP_TIMEOUT_MAX 0x00010000 | 132 | #define LOOP_TIMEOUT_MAX 0x00010000 |
130 | 133 | ||
134 | enum flctl_ecc_res_t { | ||
135 | FL_SUCCESS, | ||
136 | FL_REPAIRABLE, | ||
137 | FL_ERROR, | ||
138 | FL_TIMEOUT | ||
139 | }; | ||
140 | |||
131 | struct sh_flctl { | 141 | struct sh_flctl { |
132 | struct mtd_info mtd; | 142 | struct mtd_info mtd; |
133 | struct nand_chip chip; | 143 | struct nand_chip chip; |
@@ -145,8 +155,7 @@ struct sh_flctl { | |||
145 | uint32_t erase_ADRCNT; /* bits of FLCMDCR in ERASE1 cmd */ | 155 | uint32_t erase_ADRCNT; /* bits of FLCMDCR in ERASE1 cmd */ |
146 | uint32_t rw_ADRCNT; /* bits of FLCMDCR in READ WRITE cmd */ | 156 | uint32_t rw_ADRCNT; /* bits of FLCMDCR in READ WRITE cmd */ |
147 | uint32_t flcmncr_base; /* base value of FLCMNCR */ | 157 | uint32_t flcmncr_base; /* base value of FLCMNCR */ |
148 | 158 | uint32_t flintdmacr_base; /* irq enable bits */ | |
149 | int hwecc_cant_correct[4]; | ||
150 | 159 | ||
151 | unsigned page_size:1; /* NAND page size (0 = 512, 1 = 2048) */ | 160 | unsigned page_size:1; /* NAND page size (0 = 512, 1 = 2048) */ |
152 | unsigned hwecc:1; /* Hardware ECC (0 = disabled, 1 = enabled) */ | 161 | unsigned hwecc:1; /* Hardware ECC (0 = disabled, 1 = enabled) */ |