1 files changed, 43 insertions, 36 deletions

diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index 6a68c4eb4e4..5ee48390dec 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -8,8 +8,8 @@
  * the Free Software Foundation; either version 2 of the License, or (at
  * your option) any later version.
  */
-#ifndef __SDHCI_H
-#define __SDHCI_H
+#ifndef LINUX_MMC_SDHCI_H
+#define LINUX_MMC_SDHCI_H
 
 #include <linux/scatterlist.h>
 #include <linux/compiler.h>
@@ -21,72 +21,78 @@ struct sdhci_host {
         /* Data set by hardware interface driver */
         const char *hw_name;    /* Hardware bus name */
 
-        unsigned int quirks;    /* Deviations from spec. */
+        u64 quirks;     /* Deviations from spec. */
 
 /* Controller doesn't honor resets unless we touch the clock register */
-#define SDHCI_QUIRK_CLOCK_BEFORE_RESET                  (1<<0)
+#define SDHCI_QUIRK_CLOCK_BEFORE_RESET                  (1ULL<<0)
 /* Controller has bad caps bits, but really supports DMA */
-#define SDHCI_QUIRK_FORCE_DMA                           (1<<1)
+#define SDHCI_QUIRK_FORCE_DMA                           (1ULL<<1)
 /* Controller doesn't like to be reset when there is no card inserted. */
-#define SDHCI_QUIRK_NO_CARD_NO_RESET                    (1<<2)
+#define SDHCI_QUIRK_NO_CARD_NO_RESET                    (1ULL<<2)
 /* Controller doesn't like clearing the power reg before a change */
-#define SDHCI_QUIRK_SINGLE_POWER_WRITE                  (1<<3)
+#define SDHCI_QUIRK_SINGLE_POWER_WRITE                  (1ULL<<3)
 /* Controller has flaky internal state so reset it on each ios change */
-#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS               (1<<4)
+#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS               (1ULL<<4)
 /* Controller has an unusable DMA engine */
-#define SDHCI_QUIRK_BROKEN_DMA                          (1<<5)
+#define SDHCI_QUIRK_BROKEN_DMA                          (1ULL<<5)
 /* Controller has an unusable ADMA engine */
-#define SDHCI_QUIRK_BROKEN_ADMA                         (1<<6)
+#define SDHCI_QUIRK_BROKEN_ADMA                         (1ULL<<6)
 /* Controller can only DMA from 32-bit aligned addresses */
-#define SDHCI_QUIRK_32BIT_DMA_ADDR                      (1<<7)
+#define SDHCI_QUIRK_32BIT_DMA_ADDR                      (1ULL<<7)
 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
-#define SDHCI_QUIRK_32BIT_DMA_SIZE                      (1<<8)
+#define SDHCI_QUIRK_32BIT_DMA_SIZE                      (1ULL<<8)
 /* Controller can only ADMA chunks that are a multiple of 32 bits */
-#define SDHCI_QUIRK_32BIT_ADMA_SIZE                     (1<<9)
+#define SDHCI_QUIRK_32BIT_ADMA_SIZE                     (1ULL<<9)
 /* Controller needs to be reset after each request to stay stable */
-#define SDHCI_QUIRK_RESET_AFTER_REQUEST                 (1<<10)
+#define SDHCI_QUIRK_RESET_AFTER_REQUEST                 (1ULL<<10)
 /* Controller needs voltage and power writes to happen separately */
-#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER             (1<<11)
+#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER             (1ULL<<11)
 /* Controller provides an incorrect timeout value for transfers */
-#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL                  (1<<12)
+#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL                  (1ULL<<12)
 /* Controller has an issue with buffer bits for small transfers */
-#define SDHCI_QUIRK_BROKEN_SMALL_PIO                    (1<<13)
+#define SDHCI_QUIRK_BROKEN_SMALL_PIO                    (1ULL<<13)
 /* Controller does not provide transfer-complete interrupt when not busy */
-#define SDHCI_QUIRK_NO_BUSY_IRQ                         (1<<14)
+#define SDHCI_QUIRK_NO_BUSY_IRQ                         (1ULL<<14)
 /* Controller has unreliable card detection */
-#define SDHCI_QUIRK_BROKEN_CARD_DETECTION               (1<<15)
+#define SDHCI_QUIRK_BROKEN_CARD_DETECTION               (1ULL<<15)
 /* Controller reports inverted write-protect state */
-#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT              (1<<16)
+#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT              (1ULL<<16)
 /* Controller has nonstandard clock management */
-#define SDHCI_QUIRK_NONSTANDARD_CLOCK                   (1<<17)
+#define SDHCI_QUIRK_NONSTANDARD_CLOCK                   (1ULL<<17)
 /* Controller does not like fast PIO transfers */
-#define SDHCI_QUIRK_PIO_NEEDS_DELAY                     (1<<18)
+#define SDHCI_QUIRK_PIO_NEEDS_DELAY                     (1ULL<<18)
 /* Controller losing signal/interrupt enable states after reset */
-#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET            (1<<19)
+#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET            (1ULL<<19)
 /* Controller has to be forced to use block size of 2048 bytes */
-#define SDHCI_QUIRK_FORCE_BLK_SZ_2048                   (1<<20)
+#define SDHCI_QUIRK_FORCE_BLK_SZ_2048                   (1ULL<<20)
 /* Controller cannot do multi-block transfers */
-#define SDHCI_QUIRK_NO_MULTIBLOCK                       (1<<21)
+#define SDHCI_QUIRK_NO_MULTIBLOCK                       (1ULL<<21)
 /* Controller can only handle 1-bit data transfers */
-#define SDHCI_QUIRK_FORCE_1_BIT_DATA                    (1<<22)
+#define SDHCI_QUIRK_FORCE_1_BIT_DATA                    (1ULL<<22)
 /* Controller needs 10ms delay between applying power and clock */
-#define SDHCI_QUIRK_DELAY_AFTER_POWER                   (1<<23)
+#define SDHCI_QUIRK_DELAY_AFTER_POWER                   (1ULL<<23)
 /* Controller uses SDCLK instead of TMCLK for data timeouts */
-#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK             (1<<24)
+#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK             (1ULL<<24)
 /* Controller reports wrong base clock capability */
-#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN               (1<<25)
+#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN               (1ULL<<25)
 /* Controller cannot support End Attribute in NOP ADMA descriptor */
-#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC               (1<<26)
+#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC               (1ULL<<26)
 /* Controller is missing device caps. Use caps provided by host */
-#define SDHCI_QUIRK_MISSING_CAPS                        (1<<27)
+#define SDHCI_QUIRK_MISSING_CAPS                        (1ULL<<27)
 /* Controller uses Auto CMD12 command to stop the transfer */
-#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12              (1<<28)
+#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12              (1ULL<<28)
 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
-#define SDHCI_QUIRK_NO_HISPD_BIT                        (1<<29)
+#define SDHCI_QUIRK_NO_HISPD_BIT                        (1ULL<<29)
 /* Controller treats ADMA descriptors with length 0000h incorrectly */
-#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC            (1<<30)
+#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC            (1ULL<<30)
 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
-#define SDHCI_QUIRK_UNSTABLE_RO_DETECT                  (1<<31)
+#define SDHCI_QUIRK_UNSTABLE_RO_DETECT                  (1ULL<<31)
+/* Controller cannot report the line status in present state register */
+#define SDHCI_QUIRK_NON_STD_VOLTAGE_SWITCHING           (1ULL<<32)
+/* Controller doesn't follow the standard frequency tuning procedure */
+#define SDHCI_QUIRK_NON_STANDARD_TUNING                 (1ULL<<33)
+/* Controller doesn't calculate max_discard_to */
+#define SDHCI_QUIRK_NO_CALC_MAX_DISCARD_TO              (1ULL<<34)
 
         int irq;                /* Device IRQ */
         void __iomem *ioaddr;   /* Mapped address */
@@ -145,6 +151,7 @@ struct sdhci_host {
         struct tasklet_struct finish_tasklet;
 
         struct timer_list timer;        /* Timer for timeouts */
+        unsigned int card_int_set;      /* card int status */
 
         unsigned int caps;      /* Alternative capabilities */
 
@@ -162,4 +169,4 @@ struct sdhci_host {
 
         unsigned long private[0] ____cacheline_aligned;
 };
-#endif /* __SDHCI_H */
+#endif /* LINUX_MMC_SDHCI_H */