aboutsummaryrefslogtreecommitdiffstats
path: root/include/linux/mfd
diff options
context:
space:
mode:
Diffstat (limited to 'include/linux/mfd')
-rw-r--r--include/linux/mfd/da903x.h4
-rw-r--r--include/linux/mfd/mcp.h69
-rw-r--r--include/linux/mfd/twl4030-codec.h272
-rw-r--r--include/linux/mfd/ucb1x00.h258
-rw-r--r--include/linux/mfd/wm831x/regulator.h4
5 files changed, 605 insertions, 2 deletions
diff --git a/include/linux/mfd/da903x.h b/include/linux/mfd/da903x.h
index c63b65c9442..0aa3a1a49ee 100644
--- a/include/linux/mfd/da903x.h
+++ b/include/linux/mfd/da903x.h
@@ -96,6 +96,10 @@ struct da9034_touch_pdata {
96 int y_inverted; 96 int y_inverted;
97}; 97};
98 98
99struct da9034_backlight_pdata {
100 int output_current; /* output current of WLED, from 0-31 (in mA) */
101};
102
99/* DA9030 battery charger data */ 103/* DA9030 battery charger data */
100struct power_supply_info; 104struct power_supply_info;
101 105
diff --git a/include/linux/mfd/mcp.h b/include/linux/mfd/mcp.h
new file mode 100644
index 00000000000..ee496708e38
--- /dev/null
+++ b/include/linux/mfd/mcp.h
@@ -0,0 +1,69 @@
1/*
2 * linux/drivers/mfd/mcp.h
3 *
4 * Copyright (C) 2001 Russell King, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
9 */
10#ifndef MCP_H
11#define MCP_H
12
13#include <mach/dma.h>
14
15struct mcp_ops;
16
17struct mcp {
18 struct module *owner;
19 struct mcp_ops *ops;
20 spinlock_t lock;
21 int use_count;
22 unsigned int sclk_rate;
23 unsigned int rw_timeout;
24 dma_device_t dma_audio_rd;
25 dma_device_t dma_audio_wr;
26 dma_device_t dma_telco_rd;
27 dma_device_t dma_telco_wr;
28 struct device attached_device;
29 int gpio_base;
30};
31
32struct mcp_ops {
33 void (*set_telecom_divisor)(struct mcp *, unsigned int);
34 void (*set_audio_divisor)(struct mcp *, unsigned int);
35 void (*reg_write)(struct mcp *, unsigned int, unsigned int);
36 unsigned int (*reg_read)(struct mcp *, unsigned int);
37 void (*enable)(struct mcp *);
38 void (*disable)(struct mcp *);
39};
40
41void mcp_set_telecom_divisor(struct mcp *, unsigned int);
42void mcp_set_audio_divisor(struct mcp *, unsigned int);
43void mcp_reg_write(struct mcp *, unsigned int, unsigned int);
44unsigned int mcp_reg_read(struct mcp *, unsigned int);
45void mcp_enable(struct mcp *);
46void mcp_disable(struct mcp *);
47#define mcp_get_sclk_rate(mcp) ((mcp)->sclk_rate)
48
49struct mcp *mcp_host_alloc(struct device *, size_t);
50int mcp_host_register(struct mcp *);
51void mcp_host_unregister(struct mcp *);
52
53struct mcp_driver {
54 struct device_driver drv;
55 int (*probe)(struct mcp *);
56 void (*remove)(struct mcp *);
57 int (*suspend)(struct mcp *, pm_message_t);
58 int (*resume)(struct mcp *);
59};
60
61int mcp_driver_register(struct mcp_driver *);
62void mcp_driver_unregister(struct mcp_driver *);
63
64#define mcp_get_drvdata(mcp) dev_get_drvdata(&(mcp)->attached_device)
65#define mcp_set_drvdata(mcp,d) dev_set_drvdata(&(mcp)->attached_device, d)
66
67#define mcp_priv(mcp) ((void *)((mcp)+1))
68
69#endif
diff --git a/include/linux/mfd/twl4030-codec.h b/include/linux/mfd/twl4030-codec.h
new file mode 100644
index 00000000000..2ec317c68e5
--- /dev/null
+++ b/include/linux/mfd/twl4030-codec.h
@@ -0,0 +1,272 @@
1/*
2 * MFD driver for twl4030 codec submodule
3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#ifndef __TWL4030_CODEC_H__
25#define __TWL4030_CODEC_H__
26
27/* Codec registers */
28#define TWL4030_REG_CODEC_MODE 0x01
29#define TWL4030_REG_OPTION 0x02
30#define TWL4030_REG_UNKNOWN 0x03
31#define TWL4030_REG_MICBIAS_CTL 0x04
32#define TWL4030_REG_ANAMICL 0x05
33#define TWL4030_REG_ANAMICR 0x06
34#define TWL4030_REG_AVADC_CTL 0x07
35#define TWL4030_REG_ADCMICSEL 0x08
36#define TWL4030_REG_DIGMIXING 0x09
37#define TWL4030_REG_ATXL1PGA 0x0A
38#define TWL4030_REG_ATXR1PGA 0x0B
39#define TWL4030_REG_AVTXL2PGA 0x0C
40#define TWL4030_REG_AVTXR2PGA 0x0D
41#define TWL4030_REG_AUDIO_IF 0x0E
42#define TWL4030_REG_VOICE_IF 0x0F
43#define TWL4030_REG_ARXR1PGA 0x10
44#define TWL4030_REG_ARXL1PGA 0x11
45#define TWL4030_REG_ARXR2PGA 0x12
46#define TWL4030_REG_ARXL2PGA 0x13
47#define TWL4030_REG_VRXPGA 0x14
48#define TWL4030_REG_VSTPGA 0x15
49#define TWL4030_REG_VRX2ARXPGA 0x16
50#define TWL4030_REG_AVDAC_CTL 0x17
51#define TWL4030_REG_ARX2VTXPGA 0x18
52#define TWL4030_REG_ARXL1_APGA_CTL 0x19
53#define TWL4030_REG_ARXR1_APGA_CTL 0x1A
54#define TWL4030_REG_ARXL2_APGA_CTL 0x1B
55#define TWL4030_REG_ARXR2_APGA_CTL 0x1C
56#define TWL4030_REG_ATX2ARXPGA 0x1D
57#define TWL4030_REG_BT_IF 0x1E
58#define TWL4030_REG_BTPGA 0x1F
59#define TWL4030_REG_BTSTPGA 0x20
60#define TWL4030_REG_EAR_CTL 0x21
61#define TWL4030_REG_HS_SEL 0x22
62#define TWL4030_REG_HS_GAIN_SET 0x23
63#define TWL4030_REG_HS_POPN_SET 0x24
64#define TWL4030_REG_PREDL_CTL 0x25
65#define TWL4030_REG_PREDR_CTL 0x26
66#define TWL4030_REG_PRECKL_CTL 0x27
67#define TWL4030_REG_PRECKR_CTL 0x28
68#define TWL4030_REG_HFL_CTL 0x29
69#define TWL4030_REG_HFR_CTL 0x2A
70#define TWL4030_REG_ALC_CTL 0x2B
71#define TWL4030_REG_ALC_SET1 0x2C
72#define TWL4030_REG_ALC_SET2 0x2D
73#define TWL4030_REG_BOOST_CTL 0x2E
74#define TWL4030_REG_SOFTVOL_CTL 0x2F
75#define TWL4030_REG_DTMF_FREQSEL 0x30
76#define TWL4030_REG_DTMF_TONEXT1H 0x31
77#define TWL4030_REG_DTMF_TONEXT1L 0x32
78#define TWL4030_REG_DTMF_TONEXT2H 0x33
79#define TWL4030_REG_DTMF_TONEXT2L 0x34
80#define TWL4030_REG_DTMF_TONOFF 0x35
81#define TWL4030_REG_DTMF_WANONOFF 0x36
82#define TWL4030_REG_I2S_RX_SCRAMBLE_H 0x37
83#define TWL4030_REG_I2S_RX_SCRAMBLE_M 0x38
84#define TWL4030_REG_I2S_RX_SCRAMBLE_L 0x39
85#define TWL4030_REG_APLL_CTL 0x3A
86#define TWL4030_REG_DTMF_CTL 0x3B
87#define TWL4030_REG_DTMF_PGA_CTL2 0x3C
88#define TWL4030_REG_DTMF_PGA_CTL1 0x3D
89#define TWL4030_REG_MISC_SET_1 0x3E
90#define TWL4030_REG_PCMBTMUX 0x3F
91#define TWL4030_REG_RX_PATH_SEL 0x43
92#define TWL4030_REG_VDL_APGA_CTL 0x44
93#define TWL4030_REG_VIBRA_CTL 0x45
94#define TWL4030_REG_VIBRA_SET 0x46
95#define TWL4030_REG_VIBRA_PWM_SET 0x47
96#define TWL4030_REG_ANAMIC_GAIN 0x48
97#define TWL4030_REG_MISC_SET_2 0x49
98
99/* Bitfield Definitions */
100
101/* TWL4030_CODEC_MODE (0x01) Fields */
102#define TWL4030_APLL_RATE 0xF0
103#define TWL4030_APLL_RATE_8000 0x00
104#define TWL4030_APLL_RATE_11025 0x10
105#define TWL4030_APLL_RATE_12000 0x20
106#define TWL4030_APLL_RATE_16000 0x40
107#define TWL4030_APLL_RATE_22050 0x50
108#define TWL4030_APLL_RATE_24000 0x60
109#define TWL4030_APLL_RATE_32000 0x80
110#define TWL4030_APLL_RATE_44100 0x90
111#define TWL4030_APLL_RATE_48000 0xA0
112#define TWL4030_APLL_RATE_96000 0xE0
113#define TWL4030_SEL_16K 0x08
114#define TWL4030_CODECPDZ 0x02
115#define TWL4030_OPT_MODE 0x01
116#define TWL4030_OPTION_1 (1 << 0)
117#define TWL4030_OPTION_2 (0 << 0)
118
119/* TWL4030_OPTION (0x02) Fields */
120#define TWL4030_ATXL1_EN (1 << 0)
121#define TWL4030_ATXR1_EN (1 << 1)
122#define TWL4030_ATXL2_VTXL_EN (1 << 2)
123#define TWL4030_ATXR2_VTXR_EN (1 << 3)
124#define TWL4030_ARXL1_VRX_EN (1 << 4)
125#define TWL4030_ARXR1_EN (1 << 5)
126#define TWL4030_ARXL2_EN (1 << 6)
127#define TWL4030_ARXR2_EN (1 << 7)
128
129/* TWL4030_REG_MICBIAS_CTL (0x04) Fields */
130#define TWL4030_MICBIAS2_CTL 0x40
131#define TWL4030_MICBIAS1_CTL 0x20
132#define TWL4030_HSMICBIAS_EN 0x04
133#define TWL4030_MICBIAS2_EN 0x02
134#define TWL4030_MICBIAS1_EN 0x01
135
136/* ANAMICL (0x05) Fields */
137#define TWL4030_CNCL_OFFSET_START 0x80
138#define TWL4030_OFFSET_CNCL_SEL 0x60
139#define TWL4030_OFFSET_CNCL_SEL_ARX1 0x00
140#define TWL4030_OFFSET_CNCL_SEL_ARX2 0x20
141#define TWL4030_OFFSET_CNCL_SEL_VRX 0x40
142#define TWL4030_OFFSET_CNCL_SEL_ALL 0x60
143#define TWL4030_MICAMPL_EN 0x10
144#define TWL4030_CKMIC_EN 0x08
145#define TWL4030_AUXL_EN 0x04
146#define TWL4030_HSMIC_EN 0x02
147#define TWL4030_MAINMIC_EN 0x01
148
149/* ANAMICR (0x06) Fields */
150#define TWL4030_MICAMPR_EN 0x10
151#define TWL4030_AUXR_EN 0x04
152#define TWL4030_SUBMIC_EN 0x01
153
154/* AVADC_CTL (0x07) Fields */
155#define TWL4030_ADCL_EN 0x08
156#define TWL4030_AVADC_CLK_PRIORITY 0x04
157#define TWL4030_ADCR_EN 0x02
158
159/* TWL4030_REG_ADCMICSEL (0x08) Fields */
160#define TWL4030_DIGMIC1_EN 0x08
161#define TWL4030_TX2IN_SEL 0x04
162#define TWL4030_DIGMIC0_EN 0x02
163#define TWL4030_TX1IN_SEL 0x01
164
165/* AUDIO_IF (0x0E) Fields */
166#define TWL4030_AIF_SLAVE_EN 0x80
167#define TWL4030_DATA_WIDTH 0x60
168#define TWL4030_DATA_WIDTH_16S_16W 0x00
169#define TWL4030_DATA_WIDTH_32S_16W 0x40
170#define TWL4030_DATA_WIDTH_32S_24W 0x60
171#define TWL4030_AIF_FORMAT 0x18
172#define TWL4030_AIF_FORMAT_CODEC 0x00
173#define TWL4030_AIF_FORMAT_LEFT 0x08
174#define TWL4030_AIF_FORMAT_RIGHT 0x10
175#define TWL4030_AIF_FORMAT_TDM 0x18
176#define TWL4030_AIF_TRI_EN 0x04
177#define TWL4030_CLK256FS_EN 0x02
178#define TWL4030_AIF_EN 0x01
179
180/* VOICE_IF (0x0F) Fields */
181#define TWL4030_VIF_SLAVE_EN 0x80
182#define TWL4030_VIF_DIN_EN 0x40
183#define TWL4030_VIF_DOUT_EN 0x20
184#define TWL4030_VIF_SWAP 0x10
185#define TWL4030_VIF_FORMAT 0x08
186#define TWL4030_VIF_TRI_EN 0x04
187#define TWL4030_VIF_SUB_EN 0x02
188#define TWL4030_VIF_EN 0x01
189
190/* EAR_CTL (0x21) */
191#define TWL4030_EAR_GAIN 0x30
192
193/* HS_GAIN_SET (0x23) Fields */
194#define TWL4030_HSR_GAIN 0x0C
195#define TWL4030_HSR_GAIN_PWR_DOWN 0x00
196#define TWL4030_HSR_GAIN_PLUS_6DB 0x04
197#define TWL4030_HSR_GAIN_0DB 0x08
198#define TWL4030_HSR_GAIN_MINUS_6DB 0x0C
199#define TWL4030_HSL_GAIN 0x03
200#define TWL4030_HSL_GAIN_PWR_DOWN 0x00
201#define TWL4030_HSL_GAIN_PLUS_6DB 0x01
202#define TWL4030_HSL_GAIN_0DB 0x02
203#define TWL4030_HSL_GAIN_MINUS_6DB 0x03
204
205/* HS_POPN_SET (0x24) Fields */
206#define TWL4030_VMID_EN 0x40
207#define TWL4030_EXTMUTE 0x20
208#define TWL4030_RAMP_DELAY 0x1C
209#define TWL4030_RAMP_DELAY_20MS 0x00
210#define TWL4030_RAMP_DELAY_40MS 0x04
211#define TWL4030_RAMP_DELAY_81MS 0x08
212#define TWL4030_RAMP_DELAY_161MS 0x0C
213#define TWL4030_RAMP_DELAY_323MS 0x10
214#define TWL4030_RAMP_DELAY_645MS 0x14
215#define TWL4030_RAMP_DELAY_1291MS 0x18
216#define TWL4030_RAMP_DELAY_2581MS 0x1C
217#define TWL4030_RAMP_EN 0x02
218
219/* PREDL_CTL (0x25) */
220#define TWL4030_PREDL_GAIN 0x30
221
222/* PREDR_CTL (0x26) */
223#define TWL4030_PREDR_GAIN 0x30
224
225/* PRECKL_CTL (0x27) */
226#define TWL4030_PRECKL_GAIN 0x30
227
228/* PRECKR_CTL (0x28) */
229#define TWL4030_PRECKR_GAIN 0x30
230
231/* HFL_CTL (0x29, 0x2A) Fields */
232#define TWL4030_HF_CTL_HB_EN 0x04
233#define TWL4030_HF_CTL_LOOP_EN 0x08
234#define TWL4030_HF_CTL_RAMP_EN 0x10
235#define TWL4030_HF_CTL_REF_EN 0x20
236
237/* APLL_CTL (0x3A) Fields */
238#define TWL4030_APLL_EN 0x10
239#define TWL4030_APLL_INFREQ 0x0F
240#define TWL4030_APLL_INFREQ_19200KHZ 0x05
241#define TWL4030_APLL_INFREQ_26000KHZ 0x06
242#define TWL4030_APLL_INFREQ_38400KHZ 0x0F
243
244/* REG_MISC_SET_1 (0x3E) Fields */
245#define TWL4030_CLK64_EN 0x80
246#define TWL4030_SCRAMBLE_EN 0x40
247#define TWL4030_FMLOOP_EN 0x20
248#define TWL4030_SMOOTH_ANAVOL_EN 0x02
249#define TWL4030_DIGMIC_LR_SWAP_EN 0x01
250
251/* VIBRA_CTL (0x45) */
252#define TWL4030_VIBRA_EN 0x01
253#define TWL4030_VIBRA_DIR 0x02
254#define TWL4030_VIBRA_AUDIO_SEL_L1 (0x00 << 2)
255#define TWL4030_VIBRA_AUDIO_SEL_R1 (0x01 << 2)
256#define TWL4030_VIBRA_AUDIO_SEL_L2 (0x02 << 2)
257#define TWL4030_VIBRA_AUDIO_SEL_R2 (0x03 << 2)
258#define TWL4030_VIBRA_SEL 0x10
259#define TWL4030_VIBRA_DIR_SEL 0x20
260
261/* TWL4030 codec resource IDs */
262enum twl4030_codec_res {
263 TWL4030_CODEC_RES_POWER = 0,
264 TWL4030_CODEC_RES_APLL,
265 TWL4030_CODEC_RES_MAX,
266};
267
268int twl4030_codec_disable_resource(enum twl4030_codec_res id);
269int twl4030_codec_enable_resource(enum twl4030_codec_res id);
270unsigned int twl4030_codec_get_mclk(void);
271
272#endif /* End of __TWL4030_CODEC_H__ */
diff --git a/include/linux/mfd/ucb1x00.h b/include/linux/mfd/ucb1x00.h
new file mode 100644
index 00000000000..aa9c3789bed
--- /dev/null
+++ b/include/linux/mfd/ucb1x00.h
@@ -0,0 +1,258 @@
1/*
2 * linux/include/mfd/ucb1x00.h
3 *
4 * Copyright (C) 2001 Russell King, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
9 */
10#ifndef UCB1200_H
11#define UCB1200_H
12
13#include <linux/mfd/mcp.h>
14#include <linux/gpio.h>
15
16#define UCB_IO_DATA 0x00
17#define UCB_IO_DIR 0x01
18
19#define UCB_IO_0 (1 << 0)
20#define UCB_IO_1 (1 << 1)
21#define UCB_IO_2 (1 << 2)
22#define UCB_IO_3 (1 << 3)
23#define UCB_IO_4 (1 << 4)
24#define UCB_IO_5 (1 << 5)
25#define UCB_IO_6 (1 << 6)
26#define UCB_IO_7 (1 << 7)
27#define UCB_IO_8 (1 << 8)
28#define UCB_IO_9 (1 << 9)
29
30#define UCB_IE_RIS 0x02
31#define UCB_IE_FAL 0x03
32#define UCB_IE_STATUS 0x04
33#define UCB_IE_CLEAR 0x04
34#define UCB_IE_ADC (1 << 11)
35#define UCB_IE_TSPX (1 << 12)
36#define UCB_IE_TSMX (1 << 13)
37#define UCB_IE_TCLIP (1 << 14)
38#define UCB_IE_ACLIP (1 << 15)
39
40#define UCB_IRQ_TSPX 12
41
42#define UCB_TC_A 0x05
43#define UCB_TC_A_LOOP (1 << 7) /* UCB1200 */
44#define UCB_TC_A_AMPL (1 << 7) /* UCB1300 */
45
46#define UCB_TC_B 0x06
47#define UCB_TC_B_VOICE_ENA (1 << 3)
48#define UCB_TC_B_CLIP (1 << 4)
49#define UCB_TC_B_ATT (1 << 6)
50#define UCB_TC_B_SIDE_ENA (1 << 11)
51#define UCB_TC_B_MUTE (1 << 13)
52#define UCB_TC_B_IN_ENA (1 << 14)
53#define UCB_TC_B_OUT_ENA (1 << 15)
54
55#define UCB_AC_A 0x07
56#define UCB_AC_B 0x08
57#define UCB_AC_B_LOOP (1 << 8)
58#define UCB_AC_B_MUTE (1 << 13)
59#define UCB_AC_B_IN_ENA (1 << 14)
60#define UCB_AC_B_OUT_ENA (1 << 15)
61
62#define UCB_TS_CR 0x09
63#define UCB_TS_CR_TSMX_POW (1 << 0)
64#define UCB_TS_CR_TSPX_POW (1 << 1)
65#define UCB_TS_CR_TSMY_POW (1 << 2)
66#define UCB_TS_CR_TSPY_POW (1 << 3)
67#define UCB_TS_CR_TSMX_GND (1 << 4)
68#define UCB_TS_CR_TSPX_GND (1 << 5)
69#define UCB_TS_CR_TSMY_GND (1 << 6)
70#define UCB_TS_CR_TSPY_GND (1 << 7)
71#define UCB_TS_CR_MODE_INT (0 << 8)
72#define UCB_TS_CR_MODE_PRES (1 << 8)
73#define UCB_TS_CR_MODE_POS (2 << 8)
74#define UCB_TS_CR_BIAS_ENA (1 << 11)
75#define UCB_TS_CR_TSPX_LOW (1 << 12)
76#define UCB_TS_CR_TSMX_LOW (1 << 13)
77
78#define UCB_ADC_CR 0x0a
79#define UCB_ADC_SYNC_ENA (1 << 0)
80#define UCB_ADC_VREFBYP_CON (1 << 1)
81#define UCB_ADC_INP_TSPX (0 << 2)
82#define UCB_ADC_INP_TSMX (1 << 2)
83#define UCB_ADC_INP_TSPY (2 << 2)
84#define UCB_ADC_INP_TSMY (3 << 2)
85#define UCB_ADC_INP_AD0 (4 << 2)
86#define UCB_ADC_INP_AD1 (5 << 2)
87#define UCB_ADC_INP_AD2 (6 << 2)
88#define UCB_ADC_INP_AD3 (7 << 2)
89#define UCB_ADC_EXT_REF (1 << 5)
90#define UCB_ADC_START (1 << 7)
91#define UCB_ADC_ENA (1 << 15)
92
93#define UCB_ADC_DATA 0x0b
94#define UCB_ADC_DAT_VAL (1 << 15)
95#define UCB_ADC_DAT(x) (((x) & 0x7fe0) >> 5)
96
97#define UCB_ID 0x0c
98#define UCB_ID_1200 0x1004
99#define UCB_ID_1300 0x1005
100#define UCB_ID_TC35143 0x9712
101
102#define UCB_MODE 0x0d
103#define UCB_MODE_DYN_VFLAG_ENA (1 << 12)
104#define UCB_MODE_AUD_OFF_CAN (1 << 13)
105
106
107struct ucb1x00_irq {
108 void *devid;
109 void (*fn)(int, void *);
110};
111
112struct ucb1x00 {
113 spinlock_t lock;
114 struct mcp *mcp;
115 unsigned int irq;
116 struct semaphore adc_sem;
117 spinlock_t io_lock;
118 u16 id;
119 u16 io_dir;
120 u16 io_out;
121 u16 adc_cr;
122 u16 irq_fal_enbl;
123 u16 irq_ris_enbl;
124 struct ucb1x00_irq irq_handler[16];
125 struct device dev;
126 struct list_head node;
127 struct list_head devs;
128 struct gpio_chip gpio;
129};
130
131struct ucb1x00_driver;
132
133struct ucb1x00_dev {
134 struct list_head dev_node;
135 struct list_head drv_node;
136 struct ucb1x00 *ucb;
137 struct ucb1x00_driver *drv;
138 void *priv;
139};
140
141struct ucb1x00_driver {
142 struct list_head node;
143 struct list_head devs;
144 int (*add)(struct ucb1x00_dev *dev);
145 void (*remove)(struct ucb1x00_dev *dev);
146 int (*suspend)(struct ucb1x00_dev *dev, pm_message_t state);
147 int (*resume)(struct ucb1x00_dev *dev);
148};
149
150#define classdev_to_ucb1x00(cd) container_of(cd, struct ucb1x00, dev)
151
152int ucb1x00_register_driver(struct ucb1x00_driver *);
153void ucb1x00_unregister_driver(struct ucb1x00_driver *);
154
155/**
156 * ucb1x00_clkrate - return the UCB1x00 SIB clock rate
157 * @ucb: UCB1x00 structure describing chip
158 *
159 * Return the SIB clock rate in Hz.
160 */
161static inline unsigned int ucb1x00_clkrate(struct ucb1x00 *ucb)
162{
163 return mcp_get_sclk_rate(ucb->mcp);
164}
165
166/**
167 * ucb1x00_enable - enable the UCB1x00 SIB clock
168 * @ucb: UCB1x00 structure describing chip
169 *
170 * Enable the SIB clock. This can be called multiple times.
171 */
172static inline void ucb1x00_enable(struct ucb1x00 *ucb)
173{
174 mcp_enable(ucb->mcp);
175}
176
177/**
178 * ucb1x00_disable - disable the UCB1x00 SIB clock
179 * @ucb: UCB1x00 structure describing chip
180 *
181 * Disable the SIB clock. The SIB clock will only be disabled
182 * when the number of ucb1x00_enable calls match the number of
183 * ucb1x00_disable calls.
184 */
185static inline void ucb1x00_disable(struct ucb1x00 *ucb)
186{
187 mcp_disable(ucb->mcp);
188}
189
190/**
191 * ucb1x00_reg_write - write a UCB1x00 register
192 * @ucb: UCB1x00 structure describing chip
193 * @reg: UCB1x00 4-bit register index to write
194 * @val: UCB1x00 16-bit value to write
195 *
196 * Write the UCB1x00 register @reg with value @val. The SIB
197 * clock must be running for this function to return.
198 */
199static inline void ucb1x00_reg_write(struct ucb1x00 *ucb, unsigned int reg, unsigned int val)
200{
201 mcp_reg_write(ucb->mcp, reg, val);
202}
203
204/**
205 * ucb1x00_reg_read - read a UCB1x00 register
206 * @ucb: UCB1x00 structure describing chip
207 * @reg: UCB1x00 4-bit register index to write
208 *
209 * Read the UCB1x00 register @reg and return its value. The SIB
210 * clock must be running for this function to return.
211 */
212static inline unsigned int ucb1x00_reg_read(struct ucb1x00 *ucb, unsigned int reg)
213{
214 return mcp_reg_read(ucb->mcp, reg);
215}
216/**
217 * ucb1x00_set_audio_divisor -
218 * @ucb: UCB1x00 structure describing chip
219 * @div: SIB clock divisor
220 */
221static inline void ucb1x00_set_audio_divisor(struct ucb1x00 *ucb, unsigned int div)
222{
223 mcp_set_audio_divisor(ucb->mcp, div);
224}
225
226/**
227 * ucb1x00_set_telecom_divisor -
228 * @ucb: UCB1x00 structure describing chip
229 * @div: SIB clock divisor
230 */
231static inline void ucb1x00_set_telecom_divisor(struct ucb1x00 *ucb, unsigned int div)
232{
233 mcp_set_telecom_divisor(ucb->mcp, div);
234}
235
236void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int, unsigned int);
237void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int, unsigned int);
238unsigned int ucb1x00_io_read(struct ucb1x00 *ucb);
239
240#define UCB_NOSYNC (0)
241#define UCB_SYNC (1)
242
243unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync);
244void ucb1x00_adc_enable(struct ucb1x00 *ucb);
245void ucb1x00_adc_disable(struct ucb1x00 *ucb);
246
247/*
248 * Which edges of the IRQ do you want to control today?
249 */
250#define UCB_RISING (1 << 0)
251#define UCB_FALLING (1 << 1)
252
253int ucb1x00_hook_irq(struct ucb1x00 *ucb, unsigned int idx, void (*fn)(int, void *), void *devid);
254void ucb1x00_enable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges);
255void ucb1x00_disable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges);
256int ucb1x00_free_irq(struct ucb1x00 *ucb, unsigned int idx, void *devid);
257
258#endif
diff --git a/include/linux/mfd/wm831x/regulator.h b/include/linux/mfd/wm831x/regulator.h
index f95466343fb..955d30fc6a2 100644
--- a/include/linux/mfd/wm831x/regulator.h
+++ b/include/linux/mfd/wm831x/regulator.h
@@ -1212,7 +1212,7 @@
1212#define WM831X_LDO1_OK_SHIFT 0 /* LDO1_OK */ 1212#define WM831X_LDO1_OK_SHIFT 0 /* LDO1_OK */
1213#define WM831X_LDO1_OK_WIDTH 1 /* LDO1_OK */ 1213#define WM831X_LDO1_OK_WIDTH 1 /* LDO1_OK */
1214 1214
1215#define WM831X_ISINK_MAX_ISEL 56 1215#define WM831X_ISINK_MAX_ISEL 55
1216extern int wm831x_isinkv_values[WM831X_ISINK_MAX_ISEL]; 1216extern int wm831x_isinkv_values[WM831X_ISINK_MAX_ISEL + 1];
1217 1217
1218#endif 1218#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-22 07:35:16 -0400