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-rw-r--r--include/linux/mfd/aat2870.h181
-rw-r--r--include/linux/mfd/ab8500.h8
-rw-r--r--include/linux/mfd/max77663-core.h178
-rw-r--r--include/linux/mfd/max8907c.h259
-rw-r--r--include/linux/mfd/max8997.h7
-rw-r--r--include/linux/mfd/max8998.h12
-rw-r--r--include/linux/mfd/pm8xxx/rtc.h25
-rw-r--r--include/linux/mfd/rc5t583.h295
-rw-r--r--include/linux/mfd/ricoh583.h164
-rw-r--r--include/linux/mfd/stmpe.h3
-rw-r--r--include/linux/mfd/tmio.h8
-rw-r--r--include/linux/mfd/tps65090.h53
-rw-r--r--include/linux/mfd/tps6586x.h54
-rw-r--r--include/linux/mfd/tps65910.h52
-rw-r--r--include/linux/mfd/tps65912.h327
-rw-r--r--include/linux/mfd/tps6591x.h124
-rw-r--r--include/linux/mfd/tps80031.h203
-rw-r--r--include/linux/mfd/twl4030-audio.h (renamed from include/linux/mfd/twl4030-codec.h)16
-rw-r--r--include/linux/mfd/twl6040.h228
-rw-r--r--include/linux/mfd/wm831x/core.h131
-rw-r--r--include/linux/mfd/wm831x/pdata.h6
-rw-r--r--include/linux/mfd/wm8400-private.h7
-rw-r--r--include/linux/mfd/wm8994/core.h9
-rw-r--r--include/linux/mfd/wm8994/pdata.h2
24 files changed, 2314 insertions, 38 deletions
diff --git a/include/linux/mfd/aat2870.h b/include/linux/mfd/aat2870.h
new file mode 100644
index 00000000000..f7316c29bde
--- /dev/null
+++ b/include/linux/mfd/aat2870.h
@@ -0,0 +1,181 @@
1/*
2 * linux/include/linux/mfd/aat2870.h
3 *
4 * Copyright (c) 2011, NVIDIA Corporation.
5 * Author: Jin Park <jinyoungp@nvidia.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 */
21
22#ifndef __LINUX_MFD_AAT2870_H
23#define __LINUX_MFD_AAT2870_H
24
25#include <linux/debugfs.h>
26#include <linux/i2c.h>
27
28/* Register offsets */
29#define AAT2870_BL_CH_EN 0x00
30#define AAT2870_BLM 0x01
31#define AAT2870_BLS 0x02
32#define AAT2870_BL1 0x03
33#define AAT2870_BL2 0x04
34#define AAT2870_BL3 0x05
35#define AAT2870_BL4 0x06
36#define AAT2870_BL5 0x07
37#define AAT2870_BL6 0x08
38#define AAT2870_BL7 0x09
39#define AAT2870_BL8 0x0A
40#define AAT2870_FLR 0x0B
41#define AAT2870_FM 0x0C
42#define AAT2870_FS 0x0D
43#define AAT2870_ALS_CFG0 0x0E
44#define AAT2870_ALS_CFG1 0x0F
45#define AAT2870_ALS_CFG2 0x10
46#define AAT2870_AMB 0x11
47#define AAT2870_ALS0 0x12
48#define AAT2870_ALS1 0x13
49#define AAT2870_ALS2 0x14
50#define AAT2870_ALS3 0x15
51#define AAT2870_ALS4 0x16
52#define AAT2870_ALS5 0x17
53#define AAT2870_ALS6 0x18
54#define AAT2870_ALS7 0x19
55#define AAT2870_ALS8 0x1A
56#define AAT2870_ALS9 0x1B
57#define AAT2870_ALSA 0x1C
58#define AAT2870_ALSB 0x1D
59#define AAT2870_ALSC 0x1E
60#define AAT2870_ALSD 0x1F
61#define AAT2870_ALSE 0x20
62#define AAT2870_ALSF 0x21
63#define AAT2870_SUB_SET 0x22
64#define AAT2870_SUB_CTRL 0x23
65#define AAT2870_LDO_AB 0x24
66#define AAT2870_LDO_CD 0x25
67#define AAT2870_LDO_EN 0x26
68#define AAT2870_REG_NUM 0x27
69
70/* Device IDs */
71enum aat2870_id {
72 AAT2870_ID_BL,
73 AAT2870_ID_LDOA,
74 AAT2870_ID_LDOB,
75 AAT2870_ID_LDOC,
76 AAT2870_ID_LDOD
77};
78
79/* Backlight channels */
80#define AAT2870_BL_CH1 0x01
81#define AAT2870_BL_CH2 0x02
82#define AAT2870_BL_CH3 0x04
83#define AAT2870_BL_CH4 0x08
84#define AAT2870_BL_CH5 0x10
85#define AAT2870_BL_CH6 0x20
86#define AAT2870_BL_CH7 0x40
87#define AAT2870_BL_CH8 0x80
88#define AAT2870_BL_CH_ALL 0xFF
89
90/* Backlight current magnitude (mA) */
91enum aat2870_current {
92 AAT2870_CURRENT_0_45 = 1,
93 AAT2870_CURRENT_0_90,
94 AAT2870_CURRENT_1_80,
95 AAT2870_CURRENT_2_70,
96 AAT2870_CURRENT_3_60,
97 AAT2870_CURRENT_4_50,
98 AAT2870_CURRENT_5_40,
99 AAT2870_CURRENT_6_30,
100 AAT2870_CURRENT_7_20,
101 AAT2870_CURRENT_8_10,
102 AAT2870_CURRENT_9_00,
103 AAT2870_CURRENT_9_90,
104 AAT2870_CURRENT_10_8,
105 AAT2870_CURRENT_11_7,
106 AAT2870_CURRENT_12_6,
107 AAT2870_CURRENT_13_5,
108 AAT2870_CURRENT_14_4,
109 AAT2870_CURRENT_15_3,
110 AAT2870_CURRENT_16_2,
111 AAT2870_CURRENT_17_1,
112 AAT2870_CURRENT_18_0,
113 AAT2870_CURRENT_18_9,
114 AAT2870_CURRENT_19_8,
115 AAT2870_CURRENT_20_7,
116 AAT2870_CURRENT_21_6,
117 AAT2870_CURRENT_22_5,
118 AAT2870_CURRENT_23_4,
119 AAT2870_CURRENT_24_3,
120 AAT2870_CURRENT_25_2,
121 AAT2870_CURRENT_26_1,
122 AAT2870_CURRENT_27_0,
123 AAT2870_CURRENT_27_9
124};
125
126struct aat2870_register {
127 bool readable;
128 bool writeable;
129 u8 value;
130};
131
132struct aat2870_data {
133 struct device *dev;
134 struct i2c_client *client;
135
136 struct mutex io_lock;
137 struct aat2870_register *reg_cache; /* register cache */
138 int en_pin; /* enable GPIO pin (if < 0, ignore this value) */
139 bool is_enable;
140
141 /* init and uninit for platform specified */
142 int (*init)(struct aat2870_data *aat2870);
143 void (*uninit)(struct aat2870_data *aat2870);
144
145 /* i2c io funcntions */
146 int (*read)(struct aat2870_data *aat2870, u8 addr, u8 *val);
147 int (*write)(struct aat2870_data *aat2870, u8 addr, u8 val);
148 int (*update)(struct aat2870_data *aat2870, u8 addr, u8 mask, u8 val);
149
150 /* for debugfs */
151 struct dentry *dentry_root;
152 struct dentry *dentry_reg;
153};
154
155struct aat2870_subdev_info {
156 int id;
157 const char *name;
158 void *platform_data;
159};
160
161struct aat2870_platform_data {
162 int en_pin; /* enable GPIO pin (if < 0, ignore this value) */
163
164 struct aat2870_subdev_info *subdevs;
165 int num_subdevs;
166
167 /* init and uninit for platform specified */
168 int (*init)(struct aat2870_data *aat2870);
169 void (*uninit)(struct aat2870_data *aat2870);
170};
171
172struct aat2870_bl_platform_data {
173 /* backlight channels, default is AAT2870_BL_CH_ALL */
174 int channels;
175 /* backlight current magnitude, default is AAT2870_CURRENT_27_9 */
176 int max_current;
177 /* maximum brightness, default is 255 */
178 int max_brightness;
179};
180
181#endif /* __LINUX_MFD_AAT2870_H */
diff --git a/include/linux/mfd/ab8500.h b/include/linux/mfd/ab8500.h
index b3184307519..838c6b487cc 100644
--- a/include/linux/mfd/ab8500.h
+++ b/include/linux/mfd/ab8500.h
@@ -28,6 +28,7 @@
28#define AB8500_INTERRUPT 0xE 28#define AB8500_INTERRUPT 0xE
29#define AB8500_RTC 0xF 29#define AB8500_RTC 0xF
30#define AB8500_MISC 0x10 30#define AB8500_MISC 0x10
31#define AB8500_DEVELOPMENT 0x11
31#define AB8500_DEBUG 0x12 32#define AB8500_DEBUG 0x12
32#define AB8500_PROD_TEST 0x13 33#define AB8500_PROD_TEST 0x13
33#define AB8500_OTP_EMUL 0x15 34#define AB8500_OTP_EMUL 0x15
@@ -74,13 +75,6 @@
74#define AB8500_INT_ACC_DETECT_21DB_F 37 75#define AB8500_INT_ACC_DETECT_21DB_F 37
75#define AB8500_INT_ACC_DETECT_21DB_R 38 76#define AB8500_INT_ACC_DETECT_21DB_R 38
76#define AB8500_INT_GP_SW_ADC_CONV_END 39 77#define AB8500_INT_GP_SW_ADC_CONV_END 39
77#define AB8500_INT_ACC_DETECT_1DB_F 33
78#define AB8500_INT_ACC_DETECT_1DB_R 34
79#define AB8500_INT_ACC_DETECT_22DB_F 35
80#define AB8500_INT_ACC_DETECT_22DB_R 36
81#define AB8500_INT_ACC_DETECT_21DB_F 37
82#define AB8500_INT_ACC_DETECT_21DB_R 38
83#define AB8500_INT_GP_SW_ADC_CONV_END 39
84#define AB8500_INT_GPIO6R 40 78#define AB8500_INT_GPIO6R 40
85#define AB8500_INT_GPIO7R 41 79#define AB8500_INT_GPIO7R 41
86#define AB8500_INT_GPIO8R 42 80#define AB8500_INT_GPIO8R 42
diff --git a/include/linux/mfd/max77663-core.h b/include/linux/mfd/max77663-core.h
new file mode 100644
index 00000000000..acfe22aac53
--- /dev/null
+++ b/include/linux/mfd/max77663-core.h
@@ -0,0 +1,178 @@
1/*
2 * include/linux/mfd/max77663-core.h
3 *
4 * Copyright 2011 Maxim Integrated Products, Inc.
5 * Copyright (C) 2011-2012 NVIDIA Corporation
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
11 *
12 */
13
14#ifndef __LINUX_MFD_MAX77663_CORE_H__
15#define __LINUX_MFD_MAX77663_CORE_H__
16
17#include <linux/irq.h>
18#include <linux/mfd/core.h>
19
20/*
21 * Interrupts
22 */
23enum {
24 MAX77663_IRQ_LBT_LB, /* Low-Battery */
25 MAX77663_IRQ_LBT_THERM_ALRM1, /* Thermal alarm status, > 120C */
26 MAX77663_IRQ_LBT_THERM_ALRM2, /* Thermal alarm status, > 140C */
27
28 MAX77663_IRQ_GPIO0, /* GPIO0 edge detection */
29 MAX77663_IRQ_GPIO1, /* GPIO1 edge detection */
30 MAX77663_IRQ_GPIO2, /* GPIO2 edge detection */
31 MAX77663_IRQ_GPIO3, /* GPIO3 edge detection */
32 MAX77663_IRQ_GPIO4, /* GPIO4 edge detection */
33 MAX77663_IRQ_GPIO5, /* GPIO5 edge detection */
34 MAX77663_IRQ_GPIO6, /* GPIO6 edge detection */
35 MAX77663_IRQ_GPIO7, /* GPIO7 edge detection */
36
37 MAX77663_IRQ_ONOFF_HRDPOWRN, /* Hard power off warnning */
38 MAX77663_IRQ_ONOFF_EN0_1SEC, /* EN0 active for 1s */
39 MAX77663_IRQ_ONOFF_EN0_FALLING, /* EN0 falling */
40 MAX77663_IRQ_ONOFF_EN0_RISING, /* EN0 rising */
41 MAX77663_IRQ_ONOFF_LID_FALLING, /* LID falling */
42 MAX77663_IRQ_ONOFF_LID_RISING, /* LID rising */
43 MAX77663_IRQ_ONOFF_ACOK_FALLING,/* ACOK falling */
44 MAX77663_IRQ_ONOFF_ACOK_RISING, /* ACOK rising */
45
46 MAX77663_IRQ_RTC, /* RTC */
47 MAX77663_IRQ_SD_PF, /* SD power fail */
48 MAX77663_IRQ_LDO_PF, /* LDO power fail */
49 MAX77663_IRQ_32K, /* 32kHz oscillator */
50 MAX77663_IRQ_NVER, /* Non-Volatile Event Recorder */
51
52 MAX77663_IRQ_NR,
53};
54
55/*
56 *GPIOs
57 */
58enum {
59 MAX77663_GPIO0,
60 MAX77663_GPIO1,
61 MAX77663_GPIO2,
62 MAX77663_GPIO3,
63 MAX77663_GPIO4,
64 MAX77663_GPIO5,
65 MAX77663_GPIO6,
66 MAX77663_GPIO7,
67
68 MAX77663_GPIO_NR,
69};
70
71/* Direction */
72enum max77663_gpio_dir {
73 GPIO_DIR_DEF,
74 GPIO_DIR_IN,
75 GPIO_DIR_OUT,
76};
77
78/* Data output */
79enum max77663_gpio_data_out {
80 GPIO_DOUT_DEF,
81 GPIO_DOUT_HIGH,
82 GPIO_DOUT_LOW,
83};
84
85/* Output drive */
86enum max77663_gpio_out_drv {
87 GPIO_OUT_DRV_DEF,
88 GPIO_OUT_DRV_PUSH_PULL,
89 GPIO_OUT_DRV_OPEN_DRAIN,
90};
91
92/* Pull-up */
93enum max77663_gpio_pull_up {
94 GPIO_PU_DEF,
95 GPIO_PU_ENABLE,
96 GPIO_PU_DISABLE,
97};
98
99/* Pull-down */
100enum max77663_gpio_pull_down {
101 GPIO_PD_DEF,
102 GPIO_PD_ENABLE,
103 GPIO_PD_DISABLE,
104};
105
106/* Alternate */
107enum max77663_gpio_alt {
108 GPIO_ALT_DEF,
109 GPIO_ALT_ENABLE,
110 GPIO_ALT_DISABLE,
111};
112
113/*
114 * Flags
115 */
116#define SLP_LPM_ENABLE 0x01
117
118struct max77663_gpio_config {
119 int gpio; /* gpio number */
120 enum max77663_gpio_dir dir;
121 enum max77663_gpio_data_out dout;
122 enum max77663_gpio_out_drv out_drv;
123 enum max77663_gpio_pull_up pull_up;
124 enum max77663_gpio_pull_down pull_down;
125 enum max77663_gpio_alt alternate;
126};
127
128struct max77663_platform_data {
129 int irq_base;
130 int gpio_base;
131
132 int num_gpio_cfgs;
133 struct max77663_gpio_config *gpio_cfgs;
134
135 int num_subdevs;
136 struct mfd_cell *sub_devices;
137
138 unsigned int flags;
139
140 unsigned char rtc_i2c_addr;
141
142 bool use_power_off;
143};
144
145#if defined(CONFIG_MFD_MAX77663)
146int max77663_read(struct device *dev, u8 addr, void *values, u32 len,
147 bool is_rtc);
148int max77663_write(struct device *dev, u8 addr, void *values, u32 len,
149 bool is_rtc);
150int max77663_set_bits(struct device *dev, u8 addr, u8 mask, u8 value,
151 bool is_rtc);
152int max77663_gpio_set_alternate(int gpio, int alternate);
153#else
154static inline int max77663_read(struct device *dev, u8 addr, void *values,
155 u32 len, bool is_rtc)
156{
157 return 0;
158}
159
160static inline int max77663_write(struct device *dev, u8 addr, void *values,
161 u32 len, bool is_rtc)
162{
163 return 0;
164}
165
166static inline int max77663_set_bits(struct device *dev, u8 addr, u8 mask,
167 u8 value, bool is_rtc)
168{
169 return 0;
170}
171
172static inline int max77663_gpio_set_alternate(int gpio, int alternate)
173{
174 return 0;
175}
176#endif /* defined(CONFIG_MFD_MAX77663) */
177
178#endif /* __LINUX_MFD_MAX77663_CORE_H__ */
diff --git a/include/linux/mfd/max8907c.h b/include/linux/mfd/max8907c.h
new file mode 100644
index 00000000000..48014b0485c
--- /dev/null
+++ b/include/linux/mfd/max8907c.h
@@ -0,0 +1,259 @@
1/* linux/mfd/max8907c.h
2 *
3 * Functions to access MAX8907C power management chip.
4 *
5 * Copyright (C) 2010 Gyungoh Yoo <jack.yoo@maxim-ic.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __LINUX_MFD_MAX8907C_H
13#define __LINUX_MFD_MAX8907C_H
14
15/* MAX8907C register map */
16#define MAX8907C_REG_SYSENSEL 0x00
17#define MAX8907C_REG_ON_OFF_IRQ1 0x01
18#define MAX8907C_REG_ON_OFF_IRQ1_MASK 0x02
19#define MAX8907C_REG_ON_OFF_STAT 0x03
20#define MAX8907C_REG_SDCTL1 0x04
21#define MAX8907C_REG_SDSEQCNT1 0x05
22#define MAX8907C_REG_SDV1 0x06
23#define MAX8907C_REG_SDCTL2 0x07
24#define MAX8907C_REG_SDSEQCNT2 0x08
25#define MAX8907C_REG_SDV2 0x09
26#define MAX8907C_REG_SDCTL3 0x0A
27#define MAX8907C_REG_SDSEQCNT3 0x0B
28#define MAX8907C_REG_SDV3 0x0C
29#define MAX8907C_REG_ON_OFF_IRQ2 0x0D
30#define MAX8907C_REG_ON_OFF_IRQ2_MASK 0x0E
31#define MAX8907C_REG_RESET_CNFG 0x0F
32#define MAX8907C_REG_LDOCTL16 0x10
33#define MAX8907C_REG_LDOSEQCNT16 0x11
34#define MAX8907C_REG_LDO16VOUT 0x12
35#define MAX8907C_REG_SDBYSEQCNT 0x13
36#define MAX8907C_REG_LDOCTL17 0x14
37#define MAX8907C_REG_LDOSEQCNT17 0x15
38#define MAX8907C_REG_LDO17VOUT 0x16
39#define MAX8907C_REG_LDOCTL1 0x18
40#define MAX8907C_REG_LDOSEQCNT1 0x19
41#define MAX8907C_REG_LDO1VOUT 0x1A
42#define MAX8907C_REG_LDOCTL2 0x1C
43#define MAX8907C_REG_LDOSEQCNT2 0x1D
44#define MAX8907C_REG_LDO2VOUT 0x1E
45#define MAX8907C_REG_LDOCTL3 0x20
46#define MAX8907C_REG_LDOSEQCNT3 0x21
47#define MAX8907C_REG_LDO3VOUT 0x22
48#define MAX8907C_REG_LDOCTL4 0x24
49#define MAX8907C_REG_LDOSEQCNT4 0x25
50#define MAX8907C_REG_LDO4VOUT 0x26
51#define MAX8907C_REG_LDOCTL5 0x28
52#define MAX8907C_REG_LDOSEQCNT5 0x29
53#define MAX8907C_REG_LDO5VOUT 0x2A
54#define MAX8907C_REG_LDOCTL6 0x2C
55#define MAX8907C_REG_LDOSEQCNT6 0x2D
56#define MAX8907C_REG_LDO6VOUT 0x2E
57#define MAX8907C_REG_LDOCTL7 0x30
58#define MAX8907C_REG_LDOSEQCNT7 0x31
59#define MAX8907C_REG_LDO7VOUT 0x32
60#define MAX8907C_REG_LDOCTL8 0x34
61#define MAX8907C_REG_LDOSEQCNT8 0x35
62#define MAX8907C_REG_LDO8VOUT 0x36
63#define MAX8907C_REG_LDOCTL9 0x38
64#define MAX8907C_REG_LDOSEQCNT9 0x39
65#define MAX8907C_REG_LDO9VOUT 0x3A
66#define MAX8907C_REG_LDOCTL10 0x3C
67#define MAX8907C_REG_LDOSEQCNT10 0x3D
68#define MAX8907C_REG_LDO10VOUT 0x3E
69#define MAX8907C_REG_LDOCTL11 0x40
70#define MAX8907C_REG_LDOSEQCNT11 0x41
71#define MAX8907C_REG_LDO11VOUT 0x42
72#define MAX8907C_REG_LDOCTL12 0x44
73#define MAX8907C_REG_LDOSEQCNT12 0x45
74#define MAX8907C_REG_LDO12VOUT 0x46
75#define MAX8907C_REG_LDOCTL13 0x48
76#define MAX8907C_REG_LDOSEQCNT13 0x49
77#define MAX8907C_REG_LDO13VOUT 0x4A
78#define MAX8907C_REG_LDOCTL14 0x4C
79#define MAX8907C_REG_LDOSEQCNT14 0x4D
80#define MAX8907C_REG_LDO14VOUT 0x4E
81#define MAX8907C_REG_LDOCTL15 0x50
82#define MAX8907C_REG_LDOSEQCNT15 0x51
83#define MAX8907C_REG_LDO15VOUT 0x52
84#define MAX8907C_REG_OUT5VEN 0x54
85#define MAX8907C_REG_OUT5VSEQ 0x55
86#define MAX8907C_REG_OUT33VEN 0x58
87#define MAX8907C_REG_OUT33VSEQ 0x59
88#define MAX8907C_REG_LDOCTL19 0x5C
89#define MAX8907C_REG_LDOSEQCNT19 0x5D
90#define MAX8907C_REG_LDO19VOUT 0x5E
91#define MAX8907C_REG_LBCNFG 0x60
92#define MAX8907C_REG_SEQ1CNFG 0x64
93#define MAX8907C_REG_SEQ2CNFG 0x65
94#define MAX8907C_REG_SEQ3CNFG 0x66
95#define MAX8907C_REG_SEQ4CNFG 0x67
96#define MAX8907C_REG_SEQ5CNFG 0x68
97#define MAX8907C_REG_SEQ6CNFG 0x69
98#define MAX8907C_REG_SEQ7CNFG 0x6A
99#define MAX8907C_REG_LDOCTL18 0x72
100#define MAX8907C_REG_LDOSEQCNT18 0x73
101#define MAX8907C_REG_LDO18VOUT 0x74
102#define MAX8907C_REG_BBAT_CNFG 0x78
103#define MAX8907C_REG_CHG_CNTL1 0x7C
104#define MAX8907C_REG_CHG_CNTL2 0x7D
105#define MAX8907C_REG_CHG_IRQ1 0x7E
106#define MAX8907C_REG_CHG_IRQ2 0x7F
107#define MAX8907C_REG_CHG_IRQ1_MASK 0x80
108#define MAX8907C_REG_CHG_IRQ2_MASK 0x81
109#define MAX8907C_REG_CHG_STAT 0x82
110#define MAX8907C_REG_WLED_MODE_CNTL 0x84
111#define MAX8907C_REG_ILED_CNTL 0x84
112#define MAX8907C_REG_II1RR 0x8E
113#define MAX8907C_REG_II2RR 0x8F
114#define MAX8907C_REG_LDOCTL20 0x9C
115#define MAX8907C_REG_LDOSEQCNT20 0x9D
116#define MAX8907C_REG_LDO20VOUT 0x9E
117
118/* RTC register */
119#define MAX8907C_REG_RTC_SEC 0x00
120#define MAX8907C_REG_RTC_MIN 0x01
121#define MAX8907C_REG_RTC_HOURS 0x02
122#define MAX8907C_REG_RTC_WEEKDAY 0x03
123#define MAX8907C_REG_RTC_DATE 0x04
124#define MAX8907C_REG_RTC_MONTH 0x05
125#define MAX8907C_REG_RTC_YEAR1 0x06
126#define MAX8907C_REG_RTC_YEAR2 0x07
127#define MAX8907C_REG_ALARM0_SEC 0x08
128#define MAX8907C_REG_ALARM0_MIN 0x09
129#define MAX8907C_REG_ALARM0_HOURS 0x0A
130#define MAX8907C_REG_ALARM0_WEEKDAY 0x0B
131#define MAX8907C_REG_ALARM0_DATE 0x0C
132#define MAX8907C_REG_ALARM0_MONTH 0x0D
133#define MAX8907C_REG_ALARM0_YEAR1 0x0E
134#define MAX8907C_REG_ALARM0_YEAR2 0x0F
135#define MAX8907C_REG_ALARM1_SEC 0x10
136#define MAX8907C_REG_ALARM1_MIN 0x11
137#define MAX8907C_REG_ALARM1_HOURS 0x12
138#define MAX8907C_REG_ALARM1_WEEKDAY 0x13
139#define MAX8907C_REG_ALARM1_DATE 0x14
140#define MAX8907C_REG_ALARM1_MONTH 0x15
141#define MAX8907C_REG_ALARM1_YEAR1 0x16
142#define MAX8907C_REG_ALARM1_YEAR2 0x17
143#define MAX8907C_REG_ALARM0_CNTL 0x18
144#define MAX8907C_REG_ALARM1_CNTL 0x19
145#define MAX8907C_REG_RTC_STATUS 0x1A
146#define MAX8907C_REG_RTC_CNTL 0x1B
147#define MAX8907C_REG_RTC_IRQ 0x1C
148#define MAX8907C_REG_RTC_IRQ_MASK 0x1D
149#define MAX8907C_REG_MPL_CNTL 0x1E
150
151/* ADC and Touch Screen Controller register map */
152
153#define MAX8907C_CTL 0
154#define MAX8907C_SEQCNT 1
155#define MAX8907C_VOUT 2
156
157/* mask bit fields */
158#define MAX8907C_MASK_LDO_SEQ 0x1C
159#define MAX8907C_MASK_LDO_EN 0x01
160#define MAX8907C_MASK_VBBATTCV 0x03
161#define MAX8907C_MASK_OUT5V_VINEN 0x10
162#define MAX8907C_MASK_OUT5V_ENSRC 0x0E
163#define MAX8907C_MASK_OUT5V_EN 0x01
164
165/* Power off bit in RESET_CNFG reg */
166#define MAX8907C_MASK_POWER_OFF 0x40
167
168#define MAX8907C_MASK_PWR_EN 0x80
169#define MAX8907C_MASK_CTL_SEQ 0x1C
170
171#define MAX8907C_PWR_EN 0x80
172#define MAX8907C_CTL_SEQ 0x04
173
174#define MAX8907C_SD_SEQ1 0x02
175#define MAX8907C_SD_SEQ2 0x06
176
177#define MAX8907C_DELAY_CNT0 0x00
178
179#define MAX8907C_POWER_UP_DELAY_CNT1 0x10
180#define MAX8907C_POWER_UP_DELAY_CNT12 0xC0
181
182#define MAX8907C_POWER_DOWN_DELAY_CNT12 0x0C
183
184#define RTC_I2C_ADDR 0x68
185
186/*
187 * MAX8907B revision requires s/w WAR to connect PWREN input to
188 * sequencer 2 because of the bug in the silicon.
189 */
190#define MAX8907B_II2RR_PWREN_WAR (0x12)
191
192/* Defines common for all supplies PWREN sequencer selection */
193#define MAX8907B_SEQSEL_PWREN_LXX 1 /* SEQ2 (PWREN) */
194
195/* IRQ definitions */
196enum {
197 MAX8907C_IRQ_VCHG_DC_OVP,
198 MAX8907C_IRQ_VCHG_DC_F,
199 MAX8907C_IRQ_VCHG_DC_R,
200 MAX8907C_IRQ_VCHG_THM_OK_R,
201 MAX8907C_IRQ_VCHG_THM_OK_F,
202 MAX8907C_IRQ_VCHG_MBATTLOW_F,
203 MAX8907C_IRQ_VCHG_MBATTLOW_R,
204 MAX8907C_IRQ_VCHG_RST,
205 MAX8907C_IRQ_VCHG_DONE,
206 MAX8907C_IRQ_VCHG_TOPOFF,
207 MAX8907C_IRQ_VCHG_TMR_FAULT,
208 MAX8907C_IRQ_GPM_RSTIN,
209 MAX8907C_IRQ_GPM_MPL,
210 MAX8907C_IRQ_GPM_SW_3SEC,
211 MAX8907C_IRQ_GPM_EXTON_F,
212 MAX8907C_IRQ_GPM_EXTON_R,
213 MAX8907C_IRQ_GPM_SW_1SEC,
214 MAX8907C_IRQ_GPM_SW_F,
215 MAX8907C_IRQ_GPM_SW_R,
216 MAX8907C_IRQ_GPM_SYSCKEN_F,
217 MAX8907C_IRQ_GPM_SYSCKEN_R,
218 MAX8907C_IRQ_RTC_ALARM1,
219 MAX8907C_IRQ_RTC_ALARM0,
220 MAX8907C_NR_IRQS,
221};
222
223struct max8907c {
224 struct device *dev;
225 struct mutex io_lock;
226 struct mutex irq_lock;
227 struct i2c_client *i2c_power;
228 struct i2c_client *i2c_rtc;
229 int irq_base;
230 int core_irq;
231
232 unsigned char cache_chg[2];
233 unsigned char cache_on[2];
234 unsigned char cache_rtc;
235
236};
237
238struct max8907c_platform_data {
239 int num_subdevs;
240 struct platform_device **subdevs;
241 int irq_base;
242 int (*max8907c_setup)(void);
243 bool use_power_off;
244};
245
246int max8907c_reg_read(struct i2c_client *i2c, u8 reg);
247int max8907c_reg_bulk_read(struct i2c_client *i2c, u8 reg, u8 count, u8 *val);
248int max8907c_reg_write(struct i2c_client *i2c, u8 reg, u8 val);
249int max8907c_reg_bulk_write(struct i2c_client *i2c, u8 reg, u8 count, u8 *val);
250int max8907c_set_bits(struct i2c_client *i2c, u8 reg, u8 mask, u8 val);
251
252int max8907c_irq_init(struct max8907c *chip, int irq, int irq_base);
253void max8907c_irq_free(struct max8907c *chip);
254int max8907c_suspend(struct i2c_client *i2c, pm_message_t state);
255int max8907c_resume(struct i2c_client *i2c);
256void max8907c_deep_sleep(int enter);
257int max8907c_pwr_en_config(void);
258int max8907c_pwr_en_attach(void);
259#endif
diff --git a/include/linux/mfd/max8997.h b/include/linux/mfd/max8997.h
index 60931d08942..0bbd13dbe33 100644
--- a/include/linux/mfd/max8997.h
+++ b/include/linux/mfd/max8997.h
@@ -107,11 +107,16 @@ struct max8997_platform_data {
107 unsigned int buck5_voltage[8]; 107 unsigned int buck5_voltage[8];
108 bool buck5_gpiodvs; 108 bool buck5_gpiodvs;
109 109
110 /* ---- Charger control ---- */
111 /* eoc stands for 'end of charge' */
112 int eoc_mA; /* 50 ~ 200mA by 10mA step */
113 /* charge Full Timeout */
114 int timeout; /* 0 (no timeout), 5, 6, 7 hours */
115
110 /* MUIC: Not implemented */ 116 /* MUIC: Not implemented */
111 /* HAPTIC: Not implemented */ 117 /* HAPTIC: Not implemented */
112 /* RTC: Not implemented */ 118 /* RTC: Not implemented */
113 /* Flash: Not implemented */ 119 /* Flash: Not implemented */
114 /* Charger control: Not implemented */
115}; 120};
116 121
117#endif /* __LINUX_MFD_MAX8998_H */ 122#endif /* __LINUX_MFD_MAX8998_H */
diff --git a/include/linux/mfd/max8998.h b/include/linux/mfd/max8998.h
index 61daa167b57..f4f0dfa4698 100644
--- a/include/linux/mfd/max8998.h
+++ b/include/linux/mfd/max8998.h
@@ -87,6 +87,15 @@ struct max8998_regulator_data {
87 * @wakeup: Allow to wake up from suspend 87 * @wakeup: Allow to wake up from suspend
88 * @rtc_delay: LP3974 RTC chip bug that requires delay after a register 88 * @rtc_delay: LP3974 RTC chip bug that requires delay after a register
89 * write before reading it. 89 * write before reading it.
90 * @eoc: End of Charge Level in percent: 10% ~ 45% by 5% step
91 * If it equals 0, leave it unchanged.
92 * Otherwise, it is a invalid value.
93 * @restart: Restart Level in mV: 100, 150, 200, and -1 for disable.
94 * If it equals 0, leave it unchanged.
95 * Otherwise, it is a invalid value.
96 * @timeout: Full Timeout in hours: 5, 6, 7, and -1 for disable.
97 * If it equals 0, leave it unchanged.
98 * Otherwise, leave it unchanged.
90 */ 99 */
91struct max8998_platform_data { 100struct max8998_platform_data {
92 struct max8998_regulator_data *regulators; 101 struct max8998_regulator_data *regulators;
@@ -107,6 +116,9 @@ struct max8998_platform_data {
107 int buck2_default_idx; 116 int buck2_default_idx;
108 bool wakeup; 117 bool wakeup;
109 bool rtc_delay; 118 bool rtc_delay;
119 int eoc;
120 int restart;
121 int timeout;
110}; 122};
111 123
112#endif /* __LINUX_MFD_MAX8998_H */ 124#endif /* __LINUX_MFD_MAX8998_H */
diff --git a/include/linux/mfd/pm8xxx/rtc.h b/include/linux/mfd/pm8xxx/rtc.h
new file mode 100644
index 00000000000..14f1983eaec
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/rtc.h
@@ -0,0 +1,25 @@
1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __RTC_PM8XXX_H__
14#define __RTC_PM8XXX_H__
15
16#define PM8XXX_RTC_DEV_NAME "rtc-pm8xxx"
17/**
18 * struct pm8xxx_rtc_pdata - RTC driver platform data
19 * @rtc_write_enable: variable stating RTC write capability
20 */
21struct pm8xxx_rtc_platform_data {
22 bool rtc_write_enable;
23};
24
25#endif /* __RTC_PM8XXX_H__ */
diff --git a/include/linux/mfd/rc5t583.h b/include/linux/mfd/rc5t583.h
new file mode 100644
index 00000000000..a2c61609d21
--- /dev/null
+++ b/include/linux/mfd/rc5t583.h
@@ -0,0 +1,295 @@
1/*
2 * Core driver interface to access RICOH_RC5T583 power management chip.
3 *
4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
5 * Author: Laxman dewangan <ldewangan@nvidia.com>
6 *
7 * Based on code
8 * Copyright (C) 2011 RICOH COMPANY,LTD
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2, as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 */
23
24#ifndef __LINUX_MFD_RC5T583_H
25#define __LINUX_MFD_RC5T583_H
26
27#include <linux/mutex.h>
28#include <linux/types.h>
29
30#define RC5T583_MAX_REGS 0xF8
31
32/* Maximum number of main interrupts */
33#define MAX_MAIN_INTERRUPT 5
34#define RC5T583_MAX_GPEDGE_REG 2
35#define RC5T583_MAX_INTERRUPT_MASK_REGS 9
36
37/* Interrupt enable register */
38#define RC5T583_INT_EN_SYS1 0x19
39#define RC5T583_INT_EN_SYS2 0x1D
40#define RC5T583_INT_EN_DCDC 0x41
41#define RC5T583_INT_EN_RTC 0xED
42#define RC5T583_INT_EN_ADC1 0x90
43#define RC5T583_INT_EN_ADC2 0x91
44#define RC5T583_INT_EN_ADC3 0x92
45
46/* Interrupt status registers (monitor regs in Ricoh)*/
47#define RC5T583_INTC_INTPOL 0xAD
48#define RC5T583_INTC_INTEN 0xAE
49#define RC5T583_INTC_INTMON 0xAF
50
51#define RC5T583_INT_MON_GRP 0xAF
52#define RC5T583_INT_MON_SYS1 0x1B
53#define RC5T583_INT_MON_SYS2 0x1F
54#define RC5T583_INT_MON_DCDC 0x43
55#define RC5T583_INT_MON_RTC 0xEE
56
57/* Interrupt clearing registers */
58#define RC5T583_INT_IR_SYS1 0x1A
59#define RC5T583_INT_IR_SYS2 0x1E
60#define RC5T583_INT_IR_DCDC 0x42
61#define RC5T583_INT_IR_RTC 0xEE
62#define RC5T583_INT_IR_ADCL 0x94
63#define RC5T583_INT_IR_ADCH 0x95
64#define RC5T583_INT_IR_ADCEND 0x96
65#define RC5T583_INT_IR_GPIOR 0xA9
66#define RC5T583_INT_IR_GPIOF 0xAA
67
68/* Sleep sequence registers */
69#define RC5T583_SLPSEQ1 0x21
70#define RC5T583_SLPSEQ2 0x22
71#define RC5T583_SLPSEQ3 0x23
72#define RC5T583_SLPSEQ4 0x24
73#define RC5T583_SLPSEQ5 0x25
74#define RC5T583_SLPSEQ6 0x26
75#define RC5T583_SLPSEQ7 0x27
76#define RC5T583_SLPSEQ8 0x28
77#define RC5T583_SLPSEQ9 0x29
78#define RC5T583_SLPSEQ10 0x2A
79#define RC5T583_SLPSEQ11 0x2B
80
81/* Regulator registers */
82#define RC5T583_REG_DC0CTL 0x30
83#define RC5T583_REG_DC0DAC 0x31
84#define RC5T583_REG_DC0LATCTL 0x32
85#define RC5T583_REG_SR0CTL 0x33
86
87#define RC5T583_REG_DC1CTL 0x34
88#define RC5T583_REG_DC1DAC 0x35
89#define RC5T583_REG_DC1LATCTL 0x36
90#define RC5T583_REG_SR1CTL 0x37
91
92#define RC5T583_REG_DC2CTL 0x38
93#define RC5T583_REG_DC2DAC 0x39
94#define RC5T583_REG_DC2LATCTL 0x3A
95#define RC5T583_REG_SR2CTL 0x3B
96
97#define RC5T583_REG_DC3CTL 0x3C
98#define RC5T583_REG_DC3DAC 0x3D
99#define RC5T583_REG_DC3LATCTL 0x3E
100#define RC5T583_REG_SR3CTL 0x3F
101
102
103#define RC5T583_REG_LDOEN1 0x50
104#define RC5T583_REG_LDOEN2 0x51
105#define RC5T583_REG_LDODIS1 0x52
106#define RC5T583_REG_LDODIS2 0x53
107
108#define RC5T583_REG_LDO0DAC 0x54
109#define RC5T583_REG_LDO1DAC 0x55
110#define RC5T583_REG_LDO2DAC 0x56
111#define RC5T583_REG_LDO3DAC 0x57
112#define RC5T583_REG_LDO4DAC 0x58
113#define RC5T583_REG_LDO5DAC 0x59
114#define RC5T583_REG_LDO6DAC 0x5A
115#define RC5T583_REG_LDO7DAC 0x5B
116#define RC5T583_REG_LDO8DAC 0x5C
117#define RC5T583_REG_LDO9DAC 0x5D
118
119#define RC5T583_REG_DC0DAC_DS 0x60
120#define RC5T583_REG_DC1DAC_DS 0x61
121#define RC5T583_REG_DC2DAC_DS 0x62
122#define RC5T583_REG_DC3DAC_DS 0x63
123
124#define RC5T583_REG_LDO0DAC_DS 0x64
125#define RC5T583_REG_LDO1DAC_DS 0x65
126#define RC5T583_REG_LDO2DAC_DS 0x66
127#define RC5T583_REG_LDO3DAC_DS 0x67
128#define RC5T583_REG_LDO4DAC_DS 0x68
129#define RC5T583_REG_LDO5DAC_DS 0x69
130#define RC5T583_REG_LDO6DAC_DS 0x6A
131#define RC5T583_REG_LDO7DAC_DS 0x6B
132#define RC5T583_REG_LDO8DAC_DS 0x6C
133#define RC5T583_REG_LDO9DAC_DS 0x6D
134
135/* GPIO register base address */
136#define RC5T583_GPIO_IOSEL 0xA0
137#define RC5T583_GPIO_PDEN 0xA1
138#define RC5T583_GPIO_IOOUT 0xA2
139#define RC5T583_GPIO_PGSEL 0xA3
140#define RC5T583_GPIO_GPINV 0xA4
141#define RC5T583_GPIO_GPDEB 0xA5
142#define RC5T583_GPIO_GPEDGE1 0xA6
143#define RC5T583_GPIO_GPEDGE2 0xA7
144#define RC5T583_GPIO_EN_INT 0xA8
145#define RC5T583_GPIO_MON_IOIN 0xAB
146#define RC5T583_GPIO_GPOFUNC 0xAC
147
148/* RICOH_RC5T583 IRQ definitions */
149enum {
150 RC5T583_IRQ_ONKEY,
151 RC5T583_IRQ_ACOK,
152 RC5T583_IRQ_LIDOPEN,
153 RC5T583_IRQ_PREOT,
154 RC5T583_IRQ_CLKSTP,
155 RC5T583_IRQ_ONKEY_OFF,
156 RC5T583_IRQ_WD,
157 RC5T583_IRQ_EN_PWRREQ1,
158 RC5T583_IRQ_EN_PWRREQ2,
159 RC5T583_IRQ_PRE_VINDET,
160
161 RC5T583_IRQ_DC0LIM,
162 RC5T583_IRQ_DC1LIM,
163 RC5T583_IRQ_DC2LIM,
164 RC5T583_IRQ_DC3LIM,
165
166 RC5T583_IRQ_CTC,
167 RC5T583_IRQ_YALE,
168 RC5T583_IRQ_DALE,
169 RC5T583_IRQ_WALE,
170
171 RC5T583_IRQ_AIN1L,
172 RC5T583_IRQ_AIN2L,
173 RC5T583_IRQ_AIN3L,
174 RC5T583_IRQ_VBATL,
175 RC5T583_IRQ_VIN3L,
176 RC5T583_IRQ_VIN8L,
177 RC5T583_IRQ_AIN1H,
178 RC5T583_IRQ_AIN2H,
179 RC5T583_IRQ_AIN3H,
180 RC5T583_IRQ_VBATH,
181 RC5T583_IRQ_VIN3H,
182 RC5T583_IRQ_VIN8H,
183 RC5T583_IRQ_ADCEND,
184
185 RC5T583_IRQ_GPIO0,
186 RC5T583_IRQ_GPIO1,
187 RC5T583_IRQ_GPIO2,
188 RC5T583_IRQ_GPIO3,
189 RC5T583_IRQ_GPIO4,
190 RC5T583_IRQ_GPIO5,
191 RC5T583_IRQ_GPIO6,
192 RC5T583_IRQ_GPIO7,
193
194 /* Should be last entry */
195 RC5T583_MAX_IRQS,
196};
197
198/* Ricoh583 gpio definitions */
199enum {
200 RC5T583_GPIO0,
201 RC5T583_GPIO1,
202 RC5T583_GPIO2,
203 RC5T583_GPIO3,
204 RC5T583_GPIO4,
205 RC5T583_GPIO5,
206 RC5T583_GPIO6,
207 RC5T583_GPIO7,
208
209 /* Should be last entry */
210 RC5T583_MAX_GPIO,
211};
212
213enum {
214 RC5T583_DS_NONE,
215 RC5T583_DS_DC0,
216 RC5T583_DS_DC1,
217 RC5T583_DS_DC2,
218 RC5T583_DS_DC3,
219 RC5T583_DS_LDO0,
220 RC5T583_DS_LDO1,
221 RC5T583_DS_LDO2,
222 RC5T583_DS_LDO3,
223 RC5T583_DS_LDO4,
224 RC5T583_DS_LDO5,
225 RC5T583_DS_LDO6,
226 RC5T583_DS_LDO7,
227 RC5T583_DS_LDO8,
228 RC5T583_DS_LDO9,
229 RC5T583_DS_PSO0,
230 RC5T583_DS_PSO1,
231 RC5T583_DS_PSO2,
232 RC5T583_DS_PSO3,
233 RC5T583_DS_PSO4,
234 RC5T583_DS_PSO5,
235 RC5T583_DS_PSO6,
236 RC5T583_DS_PSO7,
237
238 /* Should be last entry */
239 RC5T583_DS_MAX,
240};
241
242/*
243 * Ricoh pmic RC5T583 supports sleep through two external controls.
244 * The output of gpios and regulator can be enable/disable through
245 * this external signals.
246 */
247enum {
248 RC5T583_EXT_PWRREQ1_CONTROL = 0x1,
249 RC5T583_EXT_PWRREQ2_CONTROL = 0x2,
250};
251
252struct rc5t583 {
253 struct device *dev;
254 struct regmap *regmap;
255 int chip_irq;
256 int irq_base;
257 struct mutex irq_lock;
258 unsigned long group_irq_en[MAX_MAIN_INTERRUPT];
259
260 /* For main interrupt bits in INTC */
261 uint8_t intc_inten_reg;
262
263 /* For group interrupt bits and address */
264 uint8_t irq_en_reg[RC5T583_MAX_INTERRUPT_MASK_REGS];
265
266 /* For gpio edge */
267 uint8_t gpedge_reg[RC5T583_MAX_GPEDGE_REG];
268};
269
270/*
271 * rc5t583_platform_data: Platform data for ricoh rc5t583 pmu.
272 * The board specific data is provided through this structure.
273 * @irq_base: Irq base number on which this device registers their interrupts.
274 * @enable_shutdown: Enable shutdown through the input pin "shutdown".
275 */
276
277struct rc5t583_platform_data {
278 int irq_base;
279 bool enable_shutdown;
280};
281
282int rc5t583_write(struct device *dev, u8 reg, uint8_t val);
283int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val);
284int rc5t583_set_bits(struct device *dev, unsigned int reg,
285 unsigned int bit_mask);
286int rc5t583_clear_bits(struct device *dev, unsigned int reg,
287 unsigned int bit_mask);
288int rc5t583_update(struct device *dev, unsigned int reg,
289 unsigned int val, unsigned int mask);
290int rc5t583_ext_power_req_config(struct device *dev, int deepsleep_id,
291 int ext_pwr_req, int deepsleep_slot_nr);
292int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base);
293int rc5t583_irq_exit(struct rc5t583 *rc5t583);
294
295#endif
diff --git a/include/linux/mfd/ricoh583.h b/include/linux/mfd/ricoh583.h
new file mode 100644
index 00000000000..4e38cded0fa
--- /dev/null
+++ b/include/linux/mfd/ricoh583.h
@@ -0,0 +1,164 @@
1/* include/linux/mfd/ricoh583.h
2 *
3 * Core driver interface to access RICOH583 power management chip.
4 *
5 * Copyright (C) 2011 NVIDIA Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 *
21 */
22
23#ifndef __LINUX_MFD_RICOH583_H
24#define __LINUX_MFD_RICOH583_H
25
26#include <linux/rtc.h>
27/* RICOH583 IRQ definitions */
28enum {
29 RICOH583_IRQ_ONKEY,
30 RICOH583_IRQ_ACOK,
31 RICOH583_IRQ_LIDOPEN,
32 RICOH583_IRQ_PREOT,
33 RICOH583_IRQ_CLKSTP,
34 RICOH583_IRQ_ONKEY_OFF,
35 RICOH583_IRQ_WD,
36 RICOH583_IRQ_EN_PWRREQ1,
37 RICOH583_IRQ_EN_PWRREQ2,
38 RICOH583_IRQ_PRE_VINDET,
39
40 RICOH583_IRQ_DC0LIM,
41 RICOH583_IRQ_DC1LIM,
42 RICOH583_IRQ_DC2LIM,
43 RICOH583_IRQ_DC3LIM,
44
45 RICOH583_IRQ_CTC,
46 RICOH583_IRQ_YALE,
47 RICOH583_IRQ_DALE,
48 RICOH583_IRQ_WALE,
49
50 RICOH583_IRQ_AIN1L,
51 RICOH583_IRQ_AIN2L,
52 RICOH583_IRQ_AIN3L,
53 RICOH583_IRQ_VBATL,
54 RICOH583_IRQ_VIN3L,
55 RICOH583_IRQ_VIN8L,
56 RICOH583_IRQ_AIN1H,
57 RICOH583_IRQ_AIN2H,
58 RICOH583_IRQ_AIN3H,
59 RICOH583_IRQ_VBATH,
60 RICOH583_IRQ_VIN3H,
61 RICOH583_IRQ_VIN8H,
62 RICOH583_IRQ_ADCEND,
63
64 RICOH583_IRQ_GPIO0,
65 RICOH583_IRQ_GPIO1,
66 RICOH583_IRQ_GPIO2,
67 RICOH583_IRQ_GPIO3,
68 RICOH583_IRQ_GPIO4,
69 RICOH583_IRQ_GPIO5,
70 RICOH583_IRQ_GPIO6,
71 RICOH583_IRQ_GPIO7,
72 RICOH583_NR_IRQS,
73};
74
75/* Ricoh583 gpio definitions */
76enum {
77 RICOH583_GPIO0,
78 RICOH583_GPIO1,
79 RICOH583_GPIO2,
80 RICOH583_GPIO3,
81 RICOH583_GPIO4,
82 RICOH583_GPIO5,
83 RICOH583_GPIO6,
84 RICOH583_GPIO7,
85
86 RICOH583_NR_GPIO,
87};
88
89enum ricoh583_deepsleep_control_id {
90 RICOH583_DS_NONE,
91 RICOH583_DS_DC0,
92 RICOH583_DS_DC1,
93 RICOH583_DS_DC2,
94 RICOH583_DS_DC3,
95 RICOH583_DS_LDO0,
96 RICOH583_DS_LDO1,
97 RICOH583_DS_LDO2,
98 RICOH583_DS_LDO3,
99 RICOH583_DS_LDO4,
100 RICOH583_DS_LDO5,
101 RICOH583_DS_LDO6,
102 RICOH583_DS_LDO7,
103 RICOH583_DS_LDO8,
104 RICOH583_DS_LDO9,
105 RICOH583_DS_PSO0,
106 RICOH583_DS_PSO1,
107 RICOH583_DS_PSO2,
108 RICOH583_DS_PSO3,
109 RICOH583_DS_PSO4,
110 RICOH583_DS_PSO5,
111 RICOH583_DS_PSO6,
112 RICOH583_DS_PSO7,
113};
114enum ricoh583_ext_pwrreq_control {
115 RICOH583_EXT_PWRREQ1_CONTROL = 0x1,
116 RICOH583_EXT_PWRREQ2_CONTROL = 0x2,
117};
118
119struct ricoh583_subdev_info {
120 int id;
121 const char *name;
122 void *platform_data;
123};
124
125struct ricoh583_rtc_platform_data {
126 int irq;
127 struct rtc_time time;
128};
129
130struct ricoh583_gpio_init_data {
131 unsigned pulldn_en:1; /* Enable pull down */
132 unsigned output_mode_en:1; /* Enable output mode during init */
133 unsigned output_val:1; /* Output value if it is in output mode */
134 unsigned init_apply:1; /* Apply init data on configuring gpios*/
135};
136
137struct ricoh583_platform_data {
138 int num_subdevs;
139 struct ricoh583_subdev_info *subdevs;
140 int gpio_base;
141 int irq_base;
142
143 struct ricoh583_gpio_init_data *gpio_init_data;
144 int num_gpioinit_data;
145 bool enable_shutdown_pin;
146};
147
148extern int ricoh583_read(struct device *dev, uint8_t reg, uint8_t *val);
149extern int ricoh583_bulk_reads(struct device *dev, u8 reg, u8 count,
150 uint8_t *val);
151extern int ricoh583_write(struct device *dev, u8 reg, uint8_t val);
152extern int ricoh583_bulk_writes(struct device *dev, u8 reg, u8 count,
153 uint8_t *val);
154extern int ricoh583_set_bits(struct device *dev, u8 reg, uint8_t bit_mask);
155extern int ricoh583_clr_bits(struct device *dev, u8 reg, uint8_t bit_mask);
156extern int ricoh583_update(struct device *dev, u8 reg, uint8_t val,
157 uint8_t mask);
158extern int ricoh583_ext_power_req_config(struct device *dev,
159 enum ricoh583_deepsleep_control_id control_id,
160 enum ricoh583_ext_pwrreq_control ext_pwr_req,
161 int deepsleep_slot_nr);
162extern int ricoh583_power_off(void);
163
164#endif
diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h
index e762c270d8d..be1af7c42e5 100644
--- a/include/linux/mfd/stmpe.h
+++ b/include/linux/mfd/stmpe.h
@@ -57,6 +57,7 @@ struct stmpe_variant_info;
57 * @irq_lock: IRQ bus lock 57 * @irq_lock: IRQ bus lock
58 * @dev: device, mostly for dev_dbg() 58 * @dev: device, mostly for dev_dbg()
59 * @i2c: i2c client 59 * @i2c: i2c client
60 * @partnum: part number
60 * @variant: the detected STMPE model number 61 * @variant: the detected STMPE model number
61 * @regs: list of addresses of registers which are at different addresses on 62 * @regs: list of addresses of registers which are at different addresses on
62 * different variants. Indexed by one of STMPE_IDX_*. 63 * different variants. Indexed by one of STMPE_IDX_*.
@@ -121,6 +122,8 @@ struct stmpe_keypad_platform_data {
121 * @norequest_mask: bitmask specifying which GPIOs should _not_ be 122 * @norequest_mask: bitmask specifying which GPIOs should _not_ be
122 * requestable due to different usage (e.g. touch, keypad) 123 * requestable due to different usage (e.g. touch, keypad)
123 * STMPE_GPIO_NOREQ_* macros can be used here. 124 * STMPE_GPIO_NOREQ_* macros can be used here.
125 * @setup: board specific setup callback.
126 * @remove: board specific remove callback
124 */ 127 */
125struct stmpe_gpio_platform_data { 128struct stmpe_gpio_platform_data {
126 int gpio_base; 129 int gpio_base;
diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
index 5a90266c3a5..0dc98044d8b 100644
--- a/include/linux/mfd/tmio.h
+++ b/include/linux/mfd/tmio.h
@@ -68,6 +68,11 @@
68 * controller and report the event to the driver. 68 * controller and report the event to the driver.
69 */ 69 */
70#define TMIO_MMC_HAS_COLD_CD (1 << 3) 70#define TMIO_MMC_HAS_COLD_CD (1 << 3)
71/*
72 * Some controllers require waiting for the SD bus to become
73 * idle before writing to some registers.
74 */
75#define TMIO_MMC_HAS_IDLE_WAIT (1 << 4)
71 76
72int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base); 77int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
73int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base); 78int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
@@ -80,6 +85,8 @@ struct tmio_mmc_dma {
80 int alignment_shift; 85 int alignment_shift;
81}; 86};
82 87
88struct tmio_mmc_host;
89
83/* 90/*
84 * data for the MMC controller 91 * data for the MMC controller
85 */ 92 */
@@ -94,6 +101,7 @@ struct tmio_mmc_data {
94 void (*set_pwr)(struct platform_device *host, int state); 101 void (*set_pwr)(struct platform_device *host, int state);
95 void (*set_clk_div)(struct platform_device *host, int state); 102 void (*set_clk_div)(struct platform_device *host, int state);
96 int (*get_cd)(struct platform_device *host); 103 int (*get_cd)(struct platform_device *host);
104 int (*write16_hook)(struct tmio_mmc_host *host, int addr);
97}; 105};
98 106
99static inline void tmio_mmc_cd_wakeup(struct tmio_mmc_data *pdata) 107static inline void tmio_mmc_cd_wakeup(struct tmio_mmc_data *pdata)
diff --git a/include/linux/mfd/tps65090.h b/include/linux/mfd/tps65090.h
new file mode 100644
index 00000000000..511ced59ef1
--- /dev/null
+++ b/include/linux/mfd/tps65090.h
@@ -0,0 +1,53 @@
1/*
2 * include/linux/mfd/tps65090.h
3 * Core driver interface for TI TPS65090 PMIC family
4 *
5 * Copyright (C) 2012 NVIDIA Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 *
21 */
22
23#ifndef __LINUX_MFD_TPS65090_H
24#define __LINUX_MFD_TPS65090_H
25
26#include <linux/rtc.h>
27
28struct tps65090_subdev_info {
29 int id;
30 const char *name;
31 void *platform_data;
32};
33
34struct tps65090_platform_data {
35 int irq_base;
36 int num_subdevs;
37 struct tps65090_subdev_info *subdevs;
38};
39
40/*
41 * NOTE: the functions below are not intended for use outside
42 * of the TPS65090 sub-device drivers
43 */
44extern int tps65090_write(struct device *dev, int reg, uint8_t val);
45extern int tps65090_writes(struct device *dev, int reg, int len, uint8_t *val);
46extern int tps65090_read(struct device *dev, int reg, uint8_t *val);
47extern int tps65090_reads(struct device *dev, int reg, int len, uint8_t *val);
48extern int tps65090_set_bits(struct device *dev, int reg, uint8_t bit_num);
49extern int tps65090_clr_bits(struct device *dev, int reg, uint8_t bit_num);
50extern int tps65090_update(struct device *dev, int reg, uint8_t val,
51 uint8_t bit_num);
52
53#endif /*__LINUX_MFD_TPS65090_H */
diff --git a/include/linux/mfd/tps6586x.h b/include/linux/mfd/tps6586x.h
index b6bab1b04e2..702cee59cc7 100644
--- a/include/linux/mfd/tps6586x.h
+++ b/include/linux/mfd/tps6586x.h
@@ -1,6 +1,10 @@
1#ifndef __LINUX_MFD_TPS6586X_H 1#ifndef __LINUX_MFD_TPS6586X_H
2#define __LINUX_MFD_TPS6586X_H 2#define __LINUX_MFD_TPS6586X_H
3 3
4#define SM0_PWM_BIT 0
5#define SM1_PWM_BIT 1
6#define SM2_PWM_BIT 2
7
4enum { 8enum {
5 TPS6586X_ID_SM_0, 9 TPS6586X_ID_SM_0,
6 TPS6586X_ID_SM_1, 10 TPS6586X_ID_SM_1,
@@ -48,18 +52,68 @@ enum {
48 TPS6586X_INT_RTC_ALM2, 52 TPS6586X_INT_RTC_ALM2,
49}; 53};
50 54
55enum pwm_pfm_mode {
56 PWM_ONLY,
57 AUTO_PWM_PFM,
58 PWM_DEFAULT_VALUE,
59
60};
61
62enum slew_rate_settings {
63 SLEW_RATE_INSTANTLY = 0,
64 SLEW_RATE_0110UV_PER_SEC = 0x1,
65 SLEW_RATE_0220UV_PER_SEC = 0x2,
66 SLEW_RATE_0440UV_PER_SEC = 0x3,
67 SLEW_RATE_0880UV_PER_SEC = 0x4,
68 SLEW_RATE_1760UV_PER_SEC = 0x5,
69 SLEW_RATE_3520UV_PER_SEC = 0x6,
70 SLEW_RATE_7040UV_PER_SEC = 0x7,
71 SLEW_RATE_DEFAULT_VALUE,
72};
73
74struct tps6586x_settings {
75 /* SM0, SM1 and SM2 have PWM-only and auto PWM/PFM mode */
76 enum pwm_pfm_mode sm_pwm_mode;
77 /* SM0 and SM1 have slew rate settings */
78 enum slew_rate_settings slew_rate;
79};
80
81enum {
82 TPS6586X_RTC_CL_SEL_1_5PF = 0x0,
83 TPS6586X_RTC_CL_SEL_6_5PF = 0x1,
84 TPS6586X_RTC_CL_SEL_7_5PF = 0x2,
85 TPS6586X_RTC_CL_SEL_12_5PF = 0x3,
86};
87
51struct tps6586x_subdev_info { 88struct tps6586x_subdev_info {
52 int id; 89 int id;
53 const char *name; 90 const char *name;
54 void *platform_data; 91 void *platform_data;
55}; 92};
56 93
94struct tps6586x_epoch_start {
95 int year;
96 int month;
97 int day;
98 int hour;
99 int min;
100 int sec;
101};
102
103struct tps6586x_rtc_platform_data {
104 int irq;
105 struct tps6586x_epoch_start start;
106 int cl_sel; /* internal XTAL capacitance, see TPS6586X_RTC_CL_SEL* */
107};
108
57struct tps6586x_platform_data { 109struct tps6586x_platform_data {
58 int num_subdevs; 110 int num_subdevs;
59 struct tps6586x_subdev_info *subdevs; 111 struct tps6586x_subdev_info *subdevs;
60 112
61 int gpio_base; 113 int gpio_base;
62 int irq_base; 114 int irq_base;
115
116 bool use_power_off;
63}; 117};
64 118
65/* 119/*
diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h
index 8bb85b930c0..f6021cc9d91 100644
--- a/include/linux/mfd/tps65910.h
+++ b/include/linux/mfd/tps65910.h
@@ -243,7 +243,8 @@
243 243
244 244
245/*Registers VDD1, VDD2 voltage values definitions */ 245/*Registers VDD1, VDD2 voltage values definitions */
246#define VDD1_2_NUM_VOLTS 73 246#define VDD1_2_NUM_VOLT_FINE 73
247#define VDD1_2_NUM_VOLT_COARSE 3
247#define VDD1_2_MIN_VOLT 6000 248#define VDD1_2_MIN_VOLT 6000
248#define VDD1_2_OFFSET 125 249#define VDD1_2_OFFSET 125
249 250
@@ -269,7 +270,7 @@
269#define LDO1_SEL_MASK 0xFC 270#define LDO1_SEL_MASK 0xFC
270#define LDO3_SEL_MASK 0x7C 271#define LDO3_SEL_MASK 0x7C
271#define LDO_MIN_VOLT 1000 272#define LDO_MIN_VOLT 1000
272#define LDO_MAX_VOLT 3300; 273#define LDO_MAX_VOLT 3300
273 274
274 275
275/*Register VDIG1 (0x80) register.RegisterDescription */ 276/*Register VDIG1 (0x80) register.RegisterDescription */
@@ -656,6 +657,8 @@
656 657
657 658
658/*Register GPIO (0x80) register.RegisterDescription */ 659/*Register GPIO (0x80) register.RegisterDescription */
660#define GPIO_SLEEP_MASK 0x80
661#define GPIO_SLEEP_SHIFT 7
659#define GPIO_DEB_MASK 0x10 662#define GPIO_DEB_MASK 0x10
660#define GPIO_DEB_SHIFT 4 663#define GPIO_DEB_SHIFT 4
661#define GPIO_PUEN_MASK 0x08 664#define GPIO_PUEN_MASK 0x08
@@ -739,6 +742,45 @@
739#define TPS65910_GPIO_STS BIT(1) 742#define TPS65910_GPIO_STS BIT(1)
740#define TPS65910_GPIO_SET BIT(0) 743#define TPS65910_GPIO_SET BIT(0)
741 744
745/* Max number of TPS65910/11 GPIOs */
746#define TPS65910_NUM_GPIO 6
747#define TPS65911_NUM_GPIO 9
748#define TPS6591X_MAX_NUM_GPIO 9
749
750/* Regulator Index Definitions */
751#define TPS65910_REG_VRTC 0
752#define TPS65910_REG_VIO 1
753#define TPS65910_REG_VDD1 2
754#define TPS65910_REG_VDD2 3
755#define TPS65910_REG_VDD3 4
756#define TPS65910_REG_VDIG1 5
757#define TPS65910_REG_VDIG2 6
758#define TPS65910_REG_VPLL 7
759#define TPS65910_REG_VDAC 8
760#define TPS65910_REG_VAUX1 9
761#define TPS65910_REG_VAUX2 10
762#define TPS65910_REG_VAUX33 11
763#define TPS65910_REG_VMMC 12
764
765#define TPS65911_REG_VDDCTRL 4
766#define TPS65911_REG_LDO1 5
767#define TPS65911_REG_LDO2 6
768#define TPS65911_REG_LDO3 7
769#define TPS65911_REG_LDO4 8
770#define TPS65911_REG_LDO5 9
771#define TPS65911_REG_LDO6 10
772#define TPS65911_REG_LDO7 11
773#define TPS65911_REG_LDO8 12
774
775/* Max number of TPS65910/11 regulators */
776#define TPS65910_NUM_REGS 13
777
778/* External sleep controls through EN1/EN2/EN3/SLEEP inputs */
779#define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 0x1
780#define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 0x2
781#define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 0x4
782#define TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP 0x8
783
742/** 784/**
743 * struct tps65910_board 785 * struct tps65910_board
744 * Board platform data may be used to initialize regulators. 786 * Board platform data may be used to initialize regulators.
@@ -750,7 +792,9 @@ struct tps65910_board {
750 int irq_base; 792 int irq_base;
751 int vmbch_threshold; 793 int vmbch_threshold;
752 int vmbch2_threshold; 794 int vmbch2_threshold;
753 struct regulator_init_data *tps65910_pmic_init_data; 795 unsigned long regulator_ext_sleep_control[TPS65910_NUM_REGS];
796 bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO];
797 struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS];
754}; 798};
755 799
756/** 800/**
@@ -760,6 +804,7 @@ struct tps65910_board {
760struct tps65910 { 804struct tps65910 {
761 struct device *dev; 805 struct device *dev;
762 struct i2c_client *i2c_client; 806 struct i2c_client *i2c_client;
807 struct regmap *regmap;
763 struct mutex io_mutex; 808 struct mutex io_mutex;
764 unsigned int id; 809 unsigned int id;
765 int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest); 810 int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest);
@@ -791,6 +836,7 @@ int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
791void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base); 836void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base);
792int tps65910_irq_init(struct tps65910 *tps65910, int irq, 837int tps65910_irq_init(struct tps65910 *tps65910, int irq,
793 struct tps65910_platform_data *pdata); 838 struct tps65910_platform_data *pdata);
839int tps65910_irq_exit(struct tps65910 *tps65910);
794 840
795static inline int tps65910_chip_id(struct tps65910 *tps65910) 841static inline int tps65910_chip_id(struct tps65910 *tps65910)
796{ 842{
diff --git a/include/linux/mfd/tps65912.h b/include/linux/mfd/tps65912.h
new file mode 100644
index 00000000000..aaceab402ec
--- /dev/null
+++ b/include/linux/mfd/tps65912.h
@@ -0,0 +1,327 @@
1/*
2 * tps65912.h -- TI TPS6591x
3 *
4 * Copyright 2011 Texas Instruments Inc.
5 *
6 * Author: Margarita Olaya <magi@slimlogic.co.uk>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __LINUX_MFD_TPS65912_H
16#define __LINUX_MFD_TPS65912_H
17
18/* TPS regulator type list */
19#define REGULATOR_LDO 0
20#define REGULATOR_DCDC 1
21
22/*
23 * List of registers for TPS65912
24 */
25
26#define TPS65912_DCDC1_CTRL 0x00
27#define TPS65912_DCDC2_CTRL 0x01
28#define TPS65912_DCDC3_CTRL 0x02
29#define TPS65912_DCDC4_CTRL 0x03
30#define TPS65912_DCDC1_OP 0x04
31#define TPS65912_DCDC1_AVS 0x05
32#define TPS65912_DCDC1_LIMIT 0x06
33#define TPS65912_DCDC2_OP 0x07
34#define TPS65912_DCDC2_AVS 0x08
35#define TPS65912_DCDC2_LIMIT 0x09
36#define TPS65912_DCDC3_OP 0x0A
37#define TPS65912_DCDC3_AVS 0x0B
38#define TPS65912_DCDC3_LIMIT 0x0C
39#define TPS65912_DCDC4_OP 0x0D
40#define TPS65912_DCDC4_AVS 0x0E
41#define TPS65912_DCDC4_LIMIT 0x0F
42#define TPS65912_LDO1_OP 0x10
43#define TPS65912_LDO1_AVS 0x11
44#define TPS65912_LDO1_LIMIT 0x12
45#define TPS65912_LDO2_OP 0x13
46#define TPS65912_LDO2_AVS 0x14
47#define TPS65912_LDO2_LIMIT 0x15
48#define TPS65912_LDO3_OP 0x16
49#define TPS65912_LDO3_AVS 0x17
50#define TPS65912_LDO3_LIMIT 0x18
51#define TPS65912_LDO4_OP 0x19
52#define TPS65912_LDO4_AVS 0x1A
53#define TPS65912_LDO4_LIMIT 0x1B
54#define TPS65912_LDO5 0x1C
55#define TPS65912_LDO6 0x1D
56#define TPS65912_LDO7 0x1E
57#define TPS65912_LDO8 0x1F
58#define TPS65912_LDO9 0x20
59#define TPS65912_LDO10 0x21
60#define TPS65912_THRM 0x22
61#define TPS65912_CLK32OUT 0x23
62#define TPS65912_DEVCTRL 0x24
63#define TPS65912_DEVCTRL2 0x25
64#define TPS65912_I2C_SPI_CFG 0x26
65#define TPS65912_KEEP_ON 0x27
66#define TPS65912_KEEP_ON2 0x28
67#define TPS65912_SET_OFF1 0x29
68#define TPS65912_SET_OFF2 0x2A
69#define TPS65912_DEF_VOLT 0x2B
70#define TPS65912_DEF_VOLT_MAPPING 0x2C
71#define TPS65912_DISCHARGE 0x2D
72#define TPS65912_DISCHARGE2 0x2E
73#define TPS65912_EN1_SET1 0x2F
74#define TPS65912_EN1_SET2 0x30
75#define TPS65912_EN2_SET1 0x31
76#define TPS65912_EN2_SET2 0x32
77#define TPS65912_EN3_SET1 0x33
78#define TPS65912_EN3_SET2 0x34
79#define TPS65912_EN4_SET1 0x35
80#define TPS65912_EN4_SET2 0x36
81#define TPS65912_PGOOD 0x37
82#define TPS65912_PGOOD2 0x38
83#define TPS65912_INT_STS 0x39
84#define TPS65912_INT_MSK 0x3A
85#define TPS65912_INT_STS2 0x3B
86#define TPS65912_INT_MSK2 0x3C
87#define TPS65912_INT_STS3 0x3D
88#define TPS65912_INT_MSK3 0x3E
89#define TPS65912_INT_STS4 0x3F
90#define TPS65912_INT_MSK4 0x40
91#define TPS65912_GPIO1 0x41
92#define TPS65912_GPIO2 0x42
93#define TPS65912_GPIO3 0x43
94#define TPS65912_GPIO4 0x44
95#define TPS65912_GPIO5 0x45
96#define TPS65912_VMON 0x46
97#define TPS65912_LEDA_CTRL1 0x47
98#define TPS65912_LEDA_CTRL2 0x48
99#define TPS65912_LEDA_CTRL3 0x49
100#define TPS65912_LEDA_CTRL4 0x4A
101#define TPS65912_LEDA_CTRL5 0x4B
102#define TPS65912_LEDA_CTRL6 0x4C
103#define TPS65912_LEDA_CTRL7 0x4D
104#define TPS65912_LEDA_CTRL8 0x4E
105#define TPS65912_LEDB_CTRL1 0x4F
106#define TPS65912_LEDB_CTRL2 0x50
107#define TPS65912_LEDB_CTRL3 0x51
108#define TPS65912_LEDB_CTRL4 0x52
109#define TPS65912_LEDB_CTRL5 0x53
110#define TPS65912_LEDB_CTRL6 0x54
111#define TPS65912_LEDB_CTRL7 0x55
112#define TPS65912_LEDB_CTRL8 0x56
113#define TPS65912_LEDC_CTRL1 0x57
114#define TPS65912_LEDC_CTRL2 0x58
115#define TPS65912_LEDC_CTRL3 0x59
116#define TPS65912_LEDC_CTRL4 0x5A
117#define TPS65912_LEDC_CTRL5 0x5B
118#define TPS65912_LEDC_CTRL6 0x5C
119#define TPS65912_LEDC_CTRL7 0x5D
120#define TPS65912_LEDC_CTRL8 0x5E
121#define TPS65912_LED_RAMP_UP_TIME 0x5F
122#define TPS65912_LED_RAMP_DOWN_TIME 0x60
123#define TPS65912_LED_SEQ_EN 0x61
124#define TPS65912_LOADSWITCH 0x62
125#define TPS65912_SPARE 0x63
126#define TPS65912_VERNUM 0x64
127#define TPS6591X_MAX_REGISTER 0x64
128
129/* IRQ Definitions */
130#define TPS65912_IRQ_PWRHOLD_F 0
131#define TPS65912_IRQ_VMON 1
132#define TPS65912_IRQ_PWRON 2
133#define TPS65912_IRQ_PWRON_LP 3
134#define TPS65912_IRQ_PWRHOLD_R 4
135#define TPS65912_IRQ_HOTDIE 5
136#define TPS65912_IRQ_GPIO1_R 6
137#define TPS65912_IRQ_GPIO1_F 7
138#define TPS65912_IRQ_GPIO2_R 8
139#define TPS65912_IRQ_GPIO2_F 9
140#define TPS65912_IRQ_GPIO3_R 10
141#define TPS65912_IRQ_GPIO3_F 11
142#define TPS65912_IRQ_GPIO4_R 12
143#define TPS65912_IRQ_GPIO4_F 13
144#define TPS65912_IRQ_GPIO5_R 14
145#define TPS65912_IRQ_GPIO5_F 15
146#define TPS65912_IRQ_PGOOD_DCDC1 16
147#define TPS65912_IRQ_PGOOD_DCDC2 17
148#define TPS65912_IRQ_PGOOD_DCDC3 18
149#define TPS65912_IRQ_PGOOD_DCDC4 19
150#define TPS65912_IRQ_PGOOD_LDO1 20
151#define TPS65912_IRQ_PGOOD_LDO2 21
152#define TPS65912_IRQ_PGOOD_LDO3 22
153#define TPS65912_IRQ_PGOOD_LDO4 23
154#define TPS65912_IRQ_PGOOD_LDO5 24
155#define TPS65912_IRQ_PGOOD_LDO6 25
156#define TPS65912_IRQ_PGOOD_LDO7 26
157#define TPS65912_IRQ_PGOOD_LD08 27
158#define TPS65912_IRQ_PGOOD_LDO9 28
159#define TPS65912_IRQ_PGOOD_LDO10 29
160
161#define TPS65912_NUM_IRQ 30
162
163/* GPIO 1 and 2 Register Definitions */
164#define GPIO_SLEEP_MASK 0x80
165#define GPIO_SLEEP_SHIFT 7
166#define GPIO_DEB_MASK 0x10
167#define GPIO_DEB_SHIFT 4
168#define GPIO_CFG_MASK 0x04
169#define GPIO_CFG_SHIFT 2
170#define GPIO_STS_MASK 0x02
171#define GPIO_STS_SHIFT 1
172#define GPIO_SET_MASK 0x01
173#define GPIO_SET_SHIFT 0
174
175/* GPIO 3 Register Definitions */
176#define GPIO3_SLEEP_MASK 0x80
177#define GPIO3_SLEEP_SHIFT 7
178#define GPIO3_SEL_MASK 0x40
179#define GPIO3_SEL_SHIFT 6
180#define GPIO3_ODEN_MASK 0x20
181#define GPIO3_ODEN_SHIFT 5
182#define GPIO3_DEB_MASK 0x10
183#define GPIO3_DEB_SHIFT 4
184#define GPIO3_PDEN_MASK 0x08
185#define GPIO3_PDEN_SHIFT 3
186#define GPIO3_CFG_MASK 0x04
187#define GPIO3_CFG_SHIFT 2
188#define GPIO3_STS_MASK 0x02
189#define GPIO3_STS_SHIFT 1
190#define GPIO3_SET_MASK 0x01
191#define GPIO3_SET_SHIFT 0
192
193/* GPIO 4 Register Definitions */
194#define GPIO4_SLEEP_MASK 0x80
195#define GPIO4_SLEEP_SHIFT 7
196#define GPIO4_SEL_MASK 0x40
197#define GPIO4_SEL_SHIFT 6
198#define GPIO4_ODEN_MASK 0x20
199#define GPIO4_ODEN_SHIFT 5
200#define GPIO4_DEB_MASK 0x10
201#define GPIO4_DEB_SHIFT 4
202#define GPIO4_PDEN_MASK 0x08
203#define GPIO4_PDEN_SHIFT 3
204#define GPIO4_CFG_MASK 0x04
205#define GPIO4_CFG_SHIFT 2
206#define GPIO4_STS_MASK 0x02
207#define GPIO4_STS_SHIFT 1
208#define GPIO4_SET_MASK 0x01
209#define GPIO4_SET_SHIFT 0
210
211/* Register THERM (0x80) register.RegisterDescription */
212#define THERM_THERM_HD_MASK 0x20
213#define THERM_THERM_HD_SHIFT 5
214#define THERM_THERM_TS_MASK 0x10
215#define THERM_THERM_TS_SHIFT 4
216#define THERM_THERM_HDSEL_MASK 0x0C
217#define THERM_THERM_HDSEL_SHIFT 2
218#define THERM_RSVD1_MASK 0x02
219#define THERM_RSVD1_SHIFT 1
220#define THERM_THERM_STATE_MASK 0x01
221#define THERM_THERM_STATE_SHIFT 0
222
223/* Register DCDCCTRL1 register.RegisterDescription */
224#define DCDCCTRL_VCON_ENABLE_MASK 0x80
225#define DCDCCTRL_VCON_ENABLE_SHIFT 7
226#define DCDCCTRL_VCON_RANGE1_MASK 0x40
227#define DCDCCTRL_VCON_RANGE1_SHIFT 6
228#define DCDCCTRL_VCON_RANGE0_MASK 0x20
229#define DCDCCTRL_VCON_RANGE0_SHIFT 5
230#define DCDCCTRL_TSTEP2_MASK 0x10
231#define DCDCCTRL_TSTEP2_SHIFT 4
232#define DCDCCTRL_TSTEP1_MASK 0x08
233#define DCDCCTRL_TSTEP1_SHIFT 3
234#define DCDCCTRL_TSTEP0_MASK 0x04
235#define DCDCCTRL_TSTEP0_SHIFT 2
236#define DCDCCTRL_DCDC1_MODE_MASK 0x02
237#define DCDCCTRL_DCDC1_MODE_SHIFT 1
238
239/* Register DCDCCTRL2 and DCDCCTRL3 register.RegisterDescription */
240#define DCDCCTRL_TSTEP2_MASK 0x10
241#define DCDCCTRL_TSTEP2_SHIFT 4
242#define DCDCCTRL_TSTEP1_MASK 0x08
243#define DCDCCTRL_TSTEP1_SHIFT 3
244#define DCDCCTRL_TSTEP0_MASK 0x04
245#define DCDCCTRL_TSTEP0_SHIFT 2
246#define DCDCCTRL_DCDC_MODE_MASK 0x02
247#define DCDCCTRL_DCDC_MODE_SHIFT 1
248#define DCDCCTRL_RSVD0_MASK 0x01
249#define DCDCCTRL_RSVD0_SHIFT 0
250
251/* Register DCDCCTRL4 register.RegisterDescription */
252#define DCDCCTRL_RAMP_TIME_MASK 0x01
253#define DCDCCTRL_RAMP_TIME_SHIFT 0
254
255/* Register DCDCx_AVS */
256#define DCDC_AVS_ENABLE_MASK 0x80
257#define DCDC_AVS_ENABLE_SHIFT 7
258#define DCDC_AVS_ECO_MASK 0x40
259#define DCDC_AVS_ECO_SHIFT 6
260
261/* Register DCDCx_LIMIT */
262#define DCDC_LIMIT_RANGE_MASK 0xC0
263#define DCDC_LIMIT_RANGE_SHIFT 6
264#define DCDC_LIMIT_MAX_SEL_MASK 0x3F
265#define DCDC_LIMIT_MAX_SEL_SHIFT 0
266
267/**
268 * struct tps65912_board
269 * Board platform dat may be used to initialize regulators.
270 */
271struct tps65912_board {
272 int is_dcdc1_avs;
273 int is_dcdc2_avs;
274 int is_dcdc3_avs;
275 int is_dcdc4_avs;
276 int irq;
277 int irq_base;
278 int gpio_base;
279 struct regulator_init_data *tps65912_pmic_init_data;
280};
281
282/**
283 * struct tps65912 - tps65912 sub-driver chip access routines
284 */
285
286struct tps65912 {
287 struct device *dev;
288 /* for read/write acces */
289 struct mutex io_mutex;
290
291 /* For device IO interfaces: I2C or SPI */
292 void *control_data;
293
294 int (*read)(struct tps65912 *tps65912, u8 reg, int size, void *dest);
295 int (*write)(struct tps65912 *tps65912, u8 reg, int size, void *src);
296
297 /* Client devices */
298 struct tps65912_pmic *pmic;
299
300 /* GPIO Handling */
301 struct gpio_chip gpio;
302
303 /* IRQ Handling */
304 struct mutex irq_lock;
305 int chip_irq;
306 int irq_base;
307 int irq_num;
308 u32 irq_mask;
309};
310
311struct tps65912_platform_data {
312 int irq;
313 int irq_base;
314};
315
316unsigned int tps_chip(void);
317
318int tps65912_set_bits(struct tps65912 *tps65912, u8 reg, u8 mask);
319int tps65912_clear_bits(struct tps65912 *tps65912, u8 reg, u8 mask);
320int tps65912_reg_read(struct tps65912 *tps65912, u8 reg);
321int tps65912_reg_write(struct tps65912 *tps65912, u8 reg, u8 val);
322int tps65912_device_init(struct tps65912 *tps65912);
323void tps65912_device_exit(struct tps65912 *tps65912);
324int tps65912_irq_init(struct tps65912 *tps65912, int irq,
325 struct tps65912_platform_data *pdata);
326
327#endif /* __LINUX_MFD_TPS65912_H */
diff --git a/include/linux/mfd/tps6591x.h b/include/linux/mfd/tps6591x.h
new file mode 100644
index 00000000000..d0d829fc8ab
--- /dev/null
+++ b/include/linux/mfd/tps6591x.h
@@ -0,0 +1,124 @@
1/*
2 * include/linux/mfd/tps6591x.c
3 * Core driver interface for TI TPS6591x PMIC family
4 *
5 * Copyright (C) 2011 NVIDIA Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 *
21 */
22
23#ifndef __LINUX_MFD_TPS6591X_H
24#define __LINUX_MFD_TPS6591X_H
25
26#include <linux/rtc.h>
27
28enum {
29 TPS6591X_INT_PWRHOLD_F,
30 TPS6591X_INT_VMBHI,
31 TPS6591X_INT_PWRON,
32 TPS6591X_INT_PWRON_LP,
33 TPS6591X_INT_PWRHOLD_R,
34 TPS6591X_INT_HOTDIE,
35 TPS6591X_INT_RTC_ALARM,
36 TPS6591X_INT_RTC_PERIOD,
37 TPS6591X_INT_GPIO0,
38 TPS6591X_INT_GPIO1,
39 TPS6591X_INT_GPIO2,
40 TPS6591X_INT_GPIO3,
41 TPS6591X_INT_GPIO4,
42 TPS6591X_INT_GPIO5,
43 TPS6591X_INT_WTCHDG,
44 TPS6591X_INT_VMBCH2_H,
45 TPS6591X_INT_VMBCH2_L,
46 TPS6591X_INT_PWRDN,
47
48 /* Last entry */
49 TPS6591X_INT_NR,
50};
51
52/* Gpio definitions */
53enum {
54 TPS6591X_GPIO_GP0 = 0,
55 TPS6591X_GPIO_GP1 = 1,
56 TPS6591X_GPIO_GP2 = 2,
57 TPS6591X_GPIO_GP3 = 3,
58 TPS6591X_GPIO_GP4 = 4,
59 TPS6591X_GPIO_GP5 = 5,
60 TPS6591X_GPIO_GP6 = 6,
61 TPS6591X_GPIO_GP7 = 7,
62 TPS6591X_GPIO_GP8 = 8,
63
64 /* Last entry */
65 TPS6591X_GPIO_NR,
66};
67
68struct tps6591x_subdev_info {
69 int id;
70 const char *name;
71 void *platform_data;
72};
73
74struct tps6591x_rtc_platform_data {
75 int irq;
76 struct rtc_time time;
77};
78
79struct tps6591x_sleep_keepon_data {
80 /* set 1 to maintain the following on sleep mode */
81 unsigned therm_keepon:1; /* themal monitoring */
82 unsigned clkout32k_keepon:1; /* CLK32KOUT */
83 unsigned vrtc_keepon:1; /* LD0 full load capability */
84 unsigned i2chs_keepon:1; /* high speed internal clock */
85};
86
87struct tps6591x_gpio_init_data {
88 unsigned sleep_en:1; /* Enable sleep mode */
89 unsigned pulldn_en:1; /* Enable pull down */
90 unsigned output_mode_en:1; /* Enable output mode during init */
91 unsigned output_val:1; /* Output value if it is in output mode */
92 unsigned init_apply:1; /* Apply init data on configuring gpios*/
93};
94
95struct tps6591x_platform_data {
96 int gpio_base;
97 int irq_base;
98
99 int num_subdevs;
100 struct tps6591x_subdev_info *subdevs;
101
102 bool dev_slp_en;
103 struct tps6591x_sleep_keepon_data *slp_keepon;
104
105 struct tps6591x_gpio_init_data *gpio_init_data;
106 int num_gpioinit_data;
107
108 bool use_power_off;
109};
110
111/*
112 * NOTE: the functions below are not intended for use outside
113 * of the TPS6591X sub-device drivers
114 */
115extern int tps6591x_write(struct device *dev, int reg, uint8_t val);
116extern int tps6591x_writes(struct device *dev, int reg, int len, uint8_t *val);
117extern int tps6591x_read(struct device *dev, int reg, uint8_t *val);
118extern int tps6591x_reads(struct device *dev, int reg, int len, uint8_t *val);
119extern int tps6591x_set_bits(struct device *dev, int reg, uint8_t bit_mask);
120extern int tps6591x_clr_bits(struct device *dev, int reg, uint8_t bit_mask);
121extern int tps6591x_update(struct device *dev, int reg, uint8_t val,
122 uint8_t mask);
123
124#endif /*__LINUX_MFD_TPS6591X_H */
diff --git a/include/linux/mfd/tps80031.h b/include/linux/mfd/tps80031.h
new file mode 100644
index 00000000000..1802dfefef0
--- /dev/null
+++ b/include/linux/mfd/tps80031.h
@@ -0,0 +1,203 @@
1/*
2 * include/linux/mfd/tps80031.c
3 *
4 * Core driver interface for TI TPS80031 PMIC
5 *
6 * Copyright (C) 2011 NVIDIA Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 *
22 */
23
24#ifndef __LINUX_MFD_TPS80031_H
25#define __LINUX_MFD_TPS80031_H
26
27#include <linux/rtc.h>
28
29/* Supported chips */
30enum chips {
31 TPS80031 = 0x00000001,
32 TPS80032 = 0x00000002,
33};
34
35enum {
36 TPS80031_INT_PWRON,
37 TPS80031_INT_RPWRON,
38 TPS80031_INT_SYS_VLOW,
39 TPS80031_INT_RTC_ALARM,
40 TPS80031_INT_RTC_PERIOD,
41 TPS80031_INT_HOT_DIE,
42 TPS80031_INT_VXX_SHORT,
43 TPS80031_INT_SPDURATION,
44 TPS80031_INT_WATCHDOG,
45 TPS80031_INT_BAT,
46 TPS80031_INT_SIM,
47 TPS80031_INT_MMC,
48 TPS80031_INT_RES,
49 TPS80031_INT_GPADC_RT,
50 TPS80031_INT_GPADC_SW2_EOC,
51 TPS80031_INT_CC_AUTOCAL,
52 TPS80031_INT_ID_WKUP,
53 TPS80031_INT_VBUSS_WKUP,
54 TPS80031_INT_ID,
55 TPS80031_INT_VBUS,
56 TPS80031_INT_CHRG_CTRL,
57 TPS80031_INT_EXT_CHRG,
58 TPS80031_INT_INT_CHRG,
59 TPS80031_INT_RES2,
60 TPS80031_INT_BAT_TEMP_OVRANGE,
61 TPS80031_INT_BAT_REMOVED,
62 TPS80031_INT_VBUS_DET,
63 TPS80031_INT_VAC_DET,
64 TPS80031_INT_FAULT_WDG,
65 TPS80031_INT_LINCH_GATED,
66
67 /* Last interrupt id to get the end number */
68 TPS80031_INT_NR,
69};
70
71enum adc_channel {
72 BATTERY_TYPE = 0, /* External ADC */
73 BATTERY_TEMPERATURE = 1, /* External ADC */
74 AUDIO_ACCESSORY = 2, /* External ADC */
75 TEMPERATURE_EXTERNAL_DIODE = 3, /* External ADC */
76 TEMPERATURE_MEASUREMENT = 4, /* External ADC */
77 GENERAL_PURPOSE_1 = 5, /* External ADC */
78 GENERAL_PURPOSE_2 = 6, /* External ADC */
79 SYSTEM_SUPPLY = 7, /* Internal ADC */
80 BACKUP_BATTERY = 8, /* Internal ADC */
81 EXTERNAL_CHARGER_INPUT = 9, /* Internal ADC */
82 VBUS = 10, /* Internal ADC */
83 VBUS_DCDC_OUTPUT_CURRENT = 11, /* Internal ADC */
84 DIE_TEMPERATURE_1 = 12, /* Internal ADC */
85 DIE_TEMPERATURE_2 = 13, /* Internal ADC */
86 USB_ID_LINE = 14, /* Internal ADC */
87 TEST_NETWORK_1 = 15, /* Internal ADC */
88 TEST_NETWORK_2 = 16, /* Internal ADC */
89 BATTERY_CHARGING_CURRENT = 17, /* Internal ADC */
90 BATTERY_VOLTAGE = 18, /* Internal ADC */
91};
92
93enum TPS80031_GPIO {
94 TPS80031_GPIO_REGEN1,
95 TPS80031_GPIO_REGEN2,
96 TPS80031_GPIO_SYSEN,
97
98 /* Last entry */
99 TPS80031_GPIO_NR,
100};
101
102enum TPS80031_CLOCK32K {
103 TPS80031_CLOCK32K_AO,
104 TPS80031_CLOCK32K_G,
105 TPS80031_CLOCK32K_AUDIO,
106
107 /* Last entry */
108 TPS80031_CLOCK32K_NR,
109};
110
111enum {
112 SLAVE_ID0 = 0,
113 SLAVE_ID1 = 1,
114 SLAVE_ID2 = 2,
115 SLAVE_ID3 = 3,
116};
117
118enum {
119 I2C_ID0_ADDR = 0x12,
120 I2C_ID1_ADDR = 0x48,
121 I2C_ID2_ADDR = 0x49,
122 I2C_ID3_ADDR = 0x4A,
123};
124
125/* External controls requests */
126enum tps80031_ext_control {
127 PWR_REQ_INPUT_NONE = 0x00000000,
128 PWR_REQ_INPUT_PREQ1 = 0x00000001,
129 PWR_REQ_INPUT_PREQ2 = 0x00000002,
130 PWR_REQ_INPUT_PREQ3 = 0x00000004,
131 PWR_OFF_ON_SLEEP = 0x00000008,
132 PWR_ON_ON_SLEEP = 0x00000010,
133};
134
135struct tps80031_subdev_info {
136 int id;
137 const char *name;
138 void *platform_data;
139};
140
141struct tps80031_rtc_platform_data {
142 int irq;
143 struct rtc_time time;
144};
145
146struct tps80031_clk32k_init_data {
147 int clk32k_nr;
148 bool enable;
149 unsigned long ext_ctrl_flag;
150};
151
152struct tps80031_gpio_init_data {
153 int gpio_nr;
154 unsigned long ext_ctrl_flag;
155};
156
157struct tps80031_platform_data {
158 int num_subdevs;
159 struct tps80031_subdev_info *subdevs;
160 int gpio_base;
161 int irq_base;
162 struct tps80031_32kclock_plat_data *clk32k_pdata;
163 struct tps80031_gpio_init_data *gpio_init_data;
164 int gpio_init_data_size;
165 struct tps80031_clk32k_init_data *clk32k_init_data;
166 int clk32k_init_data_size;
167 bool use_power_off;
168};
169
170struct tps80031_bg_platform_data {
171 int irq_base;
172 int battery_present;
173};
174
175/*
176 * NOTE: the functions below are not intended for use outside
177 * of the TPS80031 sub-device drivers
178 */
179extern int tps80031_write(struct device *dev, int sid, int reg, uint8_t val);
180extern int tps80031_writes(struct device *dev, int sid, int reg, int len,
181 uint8_t *val);
182extern int tps80031_read(struct device *dev, int sid, int reg, uint8_t *val);
183extern int tps80031_reads(struct device *dev, int sid, int reg, int len,
184 uint8_t *val);
185extern int tps80031_set_bits(struct device *dev, int sid, int reg,
186 uint8_t bit_mask);
187extern int tps80031_clr_bits(struct device *dev, int sid, int reg,
188 uint8_t bit_mask);
189extern int tps80031_update(struct device *dev, int sid, int reg, uint8_t val,
190 uint8_t mask);
191extern int tps80031_force_update(struct device *dev, int sid, int reg,
192 uint8_t val, uint8_t mask);
193extern int tps80031_ext_power_req_config(struct device *dev,
194 unsigned long ext_ctrl_flag, int preq_bit,
195 int state_reg_add, int trans_reg_add);
196
197extern unsigned long tps80031_get_chip_info(struct device *dev);
198
199extern int tps80031_gpadc_conversion(int channle_no);
200
201extern int tps80031_get_pmu_version(struct device *dev);
202
203#endif /*__LINUX_MFD_TPS80031_H */
diff --git a/include/linux/mfd/twl4030-codec.h b/include/linux/mfd/twl4030-audio.h
index 5cc16bbd1da..3d22b72df07 100644
--- a/include/linux/mfd/twl4030-codec.h
+++ b/include/linux/mfd/twl4030-audio.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * MFD driver for twl4030 codec submodule 2 * MFD driver for twl4030 audio submodule
3 * 3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> 4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
5 * 5 *
@@ -259,14 +259,14 @@
259#define TWL4030_VIBRA_DIR_SEL 0x20 259#define TWL4030_VIBRA_DIR_SEL 0x20
260 260
261/* TWL4030 codec resource IDs */ 261/* TWL4030 codec resource IDs */
262enum twl4030_codec_res { 262enum twl4030_audio_res {
263 TWL4030_CODEC_RES_POWER = 0, 263 TWL4030_AUDIO_RES_POWER = 0,
264 TWL4030_CODEC_RES_APLL, 264 TWL4030_AUDIO_RES_APLL,
265 TWL4030_CODEC_RES_MAX, 265 TWL4030_AUDIO_RES_MAX,
266}; 266};
267 267
268int twl4030_codec_disable_resource(enum twl4030_codec_res id); 268int twl4030_audio_disable_resource(enum twl4030_audio_res id);
269int twl4030_codec_enable_resource(enum twl4030_codec_res id); 269int twl4030_audio_enable_resource(enum twl4030_audio_res id);
270unsigned int twl4030_codec_get_mclk(void); 270unsigned int twl4030_audio_get_mclk(void);
271 271
272#endif /* End of __TWL4030_CODEC_H__ */ 272#endif /* End of __TWL4030_CODEC_H__ */
diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h
new file mode 100644
index 00000000000..4c806f6d663
--- /dev/null
+++ b/include/linux/mfd/twl6040.h
@@ -0,0 +1,228 @@
1/*
2 * MFD driver for twl6040
3 *
4 * Authors: Jorge Eduardo Candelaria <jorge.candelaria@ti.com>
5 * Misael Lopez Cruz <misael.lopez@ti.com>
6 *
7 * Copyright: (C) 2011 Texas Instruments, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25#ifndef __TWL6040_CODEC_H__
26#define __TWL6040_CODEC_H__
27
28#include <linux/interrupt.h>
29#include <linux/mfd/core.h>
30
31#define TWL6040_REG_ASICID 0x01
32#define TWL6040_REG_ASICREV 0x02
33#define TWL6040_REG_INTID 0x03
34#define TWL6040_REG_INTMR 0x04
35#define TWL6040_REG_NCPCTL 0x05
36#define TWL6040_REG_LDOCTL 0x06
37#define TWL6040_REG_HPPLLCTL 0x07
38#define TWL6040_REG_LPPLLCTL 0x08
39#define TWL6040_REG_LPPLLDIV 0x09
40#define TWL6040_REG_AMICBCTL 0x0A
41#define TWL6040_REG_DMICBCTL 0x0B
42#define TWL6040_REG_MICLCTL 0x0C
43#define TWL6040_REG_MICRCTL 0x0D
44#define TWL6040_REG_MICGAIN 0x0E
45#define TWL6040_REG_LINEGAIN 0x0F
46#define TWL6040_REG_HSLCTL 0x10
47#define TWL6040_REG_HSRCTL 0x11
48#define TWL6040_REG_HSGAIN 0x12
49#define TWL6040_REG_EARCTL 0x13
50#define TWL6040_REG_HFLCTL 0x14
51#define TWL6040_REG_HFLGAIN 0x15
52#define TWL6040_REG_HFRCTL 0x16
53#define TWL6040_REG_HFRGAIN 0x17
54#define TWL6040_REG_VIBCTLL 0x18
55#define TWL6040_REG_VIBDATL 0x19
56#define TWL6040_REG_VIBCTLR 0x1A
57#define TWL6040_REG_VIBDATR 0x1B
58#define TWL6040_REG_HKCTL1 0x1C
59#define TWL6040_REG_HKCTL2 0x1D
60#define TWL6040_REG_GPOCTL 0x1E
61#define TWL6040_REG_ALB 0x1F
62#define TWL6040_REG_DLB 0x20
63#define TWL6040_REG_TRIM1 0x28
64#define TWL6040_REG_TRIM2 0x29
65#define TWL6040_REG_TRIM3 0x2A
66#define TWL6040_REG_HSOTRIM 0x2B
67#define TWL6040_REG_HFOTRIM 0x2C
68#define TWL6040_REG_ACCCTL 0x2D
69#define TWL6040_REG_STATUS 0x2E
70
71#define TWL6040_CACHEREGNUM (TWL6040_REG_STATUS + 1)
72
73#define TWL6040_VIOREGNUM 18
74#define TWL6040_VDDREGNUM 21
75
76/* INTID (0x03) fields */
77
78#define TWL6040_THINT 0x01
79#define TWL6040_PLUGINT 0x02
80#define TWL6040_UNPLUGINT 0x04
81#define TWL6040_HOOKINT 0x08
82#define TWL6040_HFINT 0x10
83#define TWL6040_VIBINT 0x20
84#define TWL6040_READYINT 0x40
85
86/* INTMR (0x04) fields */
87
88#define TWL6040_THMSK 0x01
89#define TWL6040_PLUGMSK 0x02
90#define TWL6040_HOOKMSK 0x08
91#define TWL6040_HFMSK 0x10
92#define TWL6040_VIBMSK 0x20
93#define TWL6040_READYMSK 0x40
94#define TWL6040_ALLINT_MSK 0x7B
95
96/* NCPCTL (0x05) fields */
97
98#define TWL6040_NCPENA 0x01
99#define TWL6040_NCPOPEN 0x40
100
101/* LDOCTL (0x06) fields */
102
103#define TWL6040_LSLDOENA 0x01
104#define TWL6040_HSLDOENA 0x04
105#define TWL6040_REFENA 0x40
106#define TWL6040_OSCENA 0x80
107
108/* HPPLLCTL (0x07) fields */
109
110#define TWL6040_HPLLENA 0x01
111#define TWL6040_HPLLRST 0x02
112#define TWL6040_HPLLBP 0x04
113#define TWL6040_HPLLSQRENA 0x08
114#define TWL6040_MCLK_12000KHZ (0 << 5)
115#define TWL6040_MCLK_19200KHZ (1 << 5)
116#define TWL6040_MCLK_26000KHZ (2 << 5)
117#define TWL6040_MCLK_38400KHZ (3 << 5)
118#define TWL6040_MCLK_MSK 0x60
119
120/* LPPLLCTL (0x08) fields */
121
122#define TWL6040_LPLLENA 0x01
123#define TWL6040_LPLLRST 0x02
124#define TWL6040_LPLLSEL 0x04
125#define TWL6040_LPLLFIN 0x08
126#define TWL6040_HPLLSEL 0x10
127
128/* HSLCTL (0x10) fields */
129
130#define TWL6040_HSDACMODEL 0x02
131#define TWL6040_HSDRVMODEL 0x08
132
133/* HSRCTL (0x11) fields */
134
135#define TWL6040_HSDACMODER 0x02
136#define TWL6040_HSDRVMODER 0x08
137
138/* VIBCTLL (0x18) fields */
139
140#define TWL6040_VIBENAL 0x01
141#define TWL6040_VIBCTRLL 0x04
142#define TWL6040_VIBCTRLLP 0x08
143#define TWL6040_VIBCTRLLN 0x10
144
145/* VIBDATL (0x19) fields */
146
147#define TWL6040_VIBDAT_MAX 0x64
148
149/* VIBCTLR (0x1A) fields */
150
151#define TWL6040_VIBENAR 0x01
152#define TWL6040_VIBCTRLR 0x04
153#define TWL6040_VIBCTRLRP 0x08
154#define TWL6040_VIBCTRLRN 0x10
155
156/* GPOCTL (0x1E) fields */
157
158#define TWL6040_GPO1 0x01
159#define TWL6040_GPO2 0x02
160#define TWL6040_GPO3 0x03
161
162/* ACCCTL (0x2D) fields */
163
164#define TWL6040_I2CSEL 0x01
165#define TWL6040_RESETSPLIT 0x04
166#define TWL6040_INTCLRMODE 0x08
167
168/* STATUS (0x2E) fields */
169
170#define TWL6040_PLUGCOMP 0x02
171#define TWL6040_VIBLOCDET 0x10
172#define TWL6040_VIBROCDET 0x20
173#define TWL6040_TSHUTDET 0x40
174
175#define TWL6040_CELLS 2
176
177#define TWL6040_REV_ES1_0 0x00
178#define TWL6040_REV_ES1_1 0x01
179#define TWL6040_REV_ES1_2 0x02
180
181#define TWL6040_IRQ_TH 0
182#define TWL6040_IRQ_PLUG 1
183#define TWL6040_IRQ_HOOK 2
184#define TWL6040_IRQ_HF 3
185#define TWL6040_IRQ_VIB 4
186#define TWL6040_IRQ_READY 5
187
188/* PLL selection */
189#define TWL6040_SYSCLK_SEL_LPPLL 0
190#define TWL6040_SYSCLK_SEL_HPPLL 1
191
192struct twl6040 {
193 struct device *dev;
194 struct mutex mutex;
195 struct mutex io_mutex;
196 struct mutex irq_mutex;
197 struct mfd_cell cells[TWL6040_CELLS];
198 struct completion ready;
199
200 int audpwron;
201 int power_count;
202 int rev;
203
204 int pll;
205 unsigned int sysclk;
206
207 unsigned int irq;
208 unsigned int irq_base;
209 u8 irq_masks_cur;
210 u8 irq_masks_cache;
211};
212
213int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg);
214int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg,
215 u8 val);
216int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg,
217 u8 mask);
218int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg,
219 u8 mask);
220int twl6040_power(struct twl6040 *twl6040, int on);
221int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
222 unsigned int freq_in, unsigned int freq_out);
223int twl6040_get_pll(struct twl6040 *twl6040);
224unsigned int twl6040_get_sysclk(struct twl6040 *twl6040);
225int twl6040_irq_init(struct twl6040 *twl6040);
226void twl6040_irq_exit(struct twl6040 *twl6040);
227
228#endif /* End of __TWL6040_CODEC_H__ */
diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h
index 0d515ee1c24..ed8fe0d0409 100644
--- a/include/linux/mfd/wm831x/core.h
+++ b/include/linux/mfd/wm831x/core.h
@@ -17,6 +17,8 @@
17 17
18#include <linux/completion.h> 18#include <linux/completion.h>
19#include <linux/interrupt.h> 19#include <linux/interrupt.h>
20#include <linux/list.h>
21#include <linux/regmap.h>
20 22
21/* 23/*
22 * Register values. 24 * Register values.
@@ -234,9 +236,111 @@
234#define WM831X_ON_PIN_TO_SHIFT 0 /* ON_PIN_TO - [1:0] */ 236#define WM831X_ON_PIN_TO_SHIFT 0 /* ON_PIN_TO - [1:0] */
235#define WM831X_ON_PIN_TO_WIDTH 2 /* ON_PIN_TO - [1:0] */ 237#define WM831X_ON_PIN_TO_WIDTH 2 /* ON_PIN_TO - [1:0] */
236 238
239/*
240 * R16528 (0x4090) - Clock Control 1
241 */
242#define WM831X_CLKOUT_ENA 0x8000 /* CLKOUT_ENA */
243#define WM831X_CLKOUT_ENA_MASK 0x8000 /* CLKOUT_ENA */
244#define WM831X_CLKOUT_ENA_SHIFT 15 /* CLKOUT_ENA */
245#define WM831X_CLKOUT_ENA_WIDTH 1 /* CLKOUT_ENA */
246#define WM831X_CLKOUT_OD 0x2000 /* CLKOUT_OD */
247#define WM831X_CLKOUT_OD_MASK 0x2000 /* CLKOUT_OD */
248#define WM831X_CLKOUT_OD_SHIFT 13 /* CLKOUT_OD */
249#define WM831X_CLKOUT_OD_WIDTH 1 /* CLKOUT_OD */
250#define WM831X_CLKOUT_SLOT_MASK 0x0700 /* CLKOUT_SLOT - [10:8] */
251#define WM831X_CLKOUT_SLOT_SHIFT 8 /* CLKOUT_SLOT - [10:8] */
252#define WM831X_CLKOUT_SLOT_WIDTH 3 /* CLKOUT_SLOT - [10:8] */
253#define WM831X_CLKOUT_SLPSLOT_MASK 0x0070 /* CLKOUT_SLPSLOT - [6:4] */
254#define WM831X_CLKOUT_SLPSLOT_SHIFT 4 /* CLKOUT_SLPSLOT - [6:4] */
255#define WM831X_CLKOUT_SLPSLOT_WIDTH 3 /* CLKOUT_SLPSLOT - [6:4] */
256#define WM831X_CLKOUT_SRC 0x0001 /* CLKOUT_SRC */
257#define WM831X_CLKOUT_SRC_MASK 0x0001 /* CLKOUT_SRC */
258#define WM831X_CLKOUT_SRC_SHIFT 0 /* CLKOUT_SRC */
259#define WM831X_CLKOUT_SRC_WIDTH 1 /* CLKOUT_SRC */
260
261/*
262 * R16529 (0x4091) - Clock Control 2
263 */
264#define WM831X_XTAL_INH 0x8000 /* XTAL_INH */
265#define WM831X_XTAL_INH_MASK 0x8000 /* XTAL_INH */
266#define WM831X_XTAL_INH_SHIFT 15 /* XTAL_INH */
267#define WM831X_XTAL_INH_WIDTH 1 /* XTAL_INH */
268#define WM831X_XTAL_ENA 0x2000 /* XTAL_ENA */
269#define WM831X_XTAL_ENA_MASK 0x2000 /* XTAL_ENA */
270#define WM831X_XTAL_ENA_SHIFT 13 /* XTAL_ENA */
271#define WM831X_XTAL_ENA_WIDTH 1 /* XTAL_ENA */
272#define WM831X_XTAL_BKUPENA 0x1000 /* XTAL_BKUPENA */
273#define WM831X_XTAL_BKUPENA_MASK 0x1000 /* XTAL_BKUPENA */
274#define WM831X_XTAL_BKUPENA_SHIFT 12 /* XTAL_BKUPENA */
275#define WM831X_XTAL_BKUPENA_WIDTH 1 /* XTAL_BKUPENA */
276#define WM831X_FLL_AUTO 0x0080 /* FLL_AUTO */
277#define WM831X_FLL_AUTO_MASK 0x0080 /* FLL_AUTO */
278#define WM831X_FLL_AUTO_SHIFT 7 /* FLL_AUTO */
279#define WM831X_FLL_AUTO_WIDTH 1 /* FLL_AUTO */
280#define WM831X_FLL_AUTO_FREQ_MASK 0x0007 /* FLL_AUTO_FREQ - [2:0] */
281#define WM831X_FLL_AUTO_FREQ_SHIFT 0 /* FLL_AUTO_FREQ - [2:0] */
282#define WM831X_FLL_AUTO_FREQ_WIDTH 3 /* FLL_AUTO_FREQ - [2:0] */
283
284/*
285 * R16530 (0x4092) - FLL Control 1
286 */
287#define WM831X_FLL_FRAC 0x0004 /* FLL_FRAC */
288#define WM831X_FLL_FRAC_MASK 0x0004 /* FLL_FRAC */
289#define WM831X_FLL_FRAC_SHIFT 2 /* FLL_FRAC */
290#define WM831X_FLL_FRAC_WIDTH 1 /* FLL_FRAC */
291#define WM831X_FLL_OSC_ENA 0x0002 /* FLL_OSC_ENA */
292#define WM831X_FLL_OSC_ENA_MASK 0x0002 /* FLL_OSC_ENA */
293#define WM831X_FLL_OSC_ENA_SHIFT 1 /* FLL_OSC_ENA */
294#define WM831X_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */
295#define WM831X_FLL_ENA 0x0001 /* FLL_ENA */
296#define WM831X_FLL_ENA_MASK 0x0001 /* FLL_ENA */
297#define WM831X_FLL_ENA_SHIFT 0 /* FLL_ENA */
298#define WM831X_FLL_ENA_WIDTH 1 /* FLL_ENA */
299
300/*
301 * R16531 (0x4093) - FLL Control 2
302 */
303#define WM831X_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */
304#define WM831X_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */
305#define WM831X_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */
306#define WM831X_FLL_CTRL_RATE_MASK 0x0070 /* FLL_CTRL_RATE - [6:4] */
307#define WM831X_FLL_CTRL_RATE_SHIFT 4 /* FLL_CTRL_RATE - [6:4] */
308#define WM831X_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [6:4] */
309#define WM831X_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */
310#define WM831X_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */
311#define WM831X_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */
312
313/*
314 * R16532 (0x4094) - FLL Control 3
315 */
316#define WM831X_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */
317#define WM831X_FLL_K_SHIFT 0 /* FLL_K - [15:0] */
318#define WM831X_FLL_K_WIDTH 16 /* FLL_K - [15:0] */
319
320/*
321 * R16533 (0x4095) - FLL Control 4
322 */
323#define WM831X_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */
324#define WM831X_FLL_N_SHIFT 5 /* FLL_N - [14:5] */
325#define WM831X_FLL_N_WIDTH 10 /* FLL_N - [14:5] */
326#define WM831X_FLL_GAIN_MASK 0x000F /* FLL_GAIN - [3:0] */
327#define WM831X_FLL_GAIN_SHIFT 0 /* FLL_GAIN - [3:0] */
328#define WM831X_FLL_GAIN_WIDTH 4 /* FLL_GAIN - [3:0] */
329
330/*
331 * R16534 (0x4096) - FLL Control 5
332 */
333#define WM831X_FLL_CLK_REF_DIV_MASK 0x0018 /* FLL_CLK_REF_DIV - [4:3] */
334#define WM831X_FLL_CLK_REF_DIV_SHIFT 3 /* FLL_CLK_REF_DIV - [4:3] */
335#define WM831X_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [4:3] */
336#define WM831X_FLL_CLK_SRC_MASK 0x0003 /* FLL_CLK_SRC - [1:0] */
337#define WM831X_FLL_CLK_SRC_SHIFT 0 /* FLL_CLK_SRC - [1:0] */
338#define WM831X_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [1:0] */
339
237struct regulator_dev; 340struct regulator_dev;
238 341
239#define WM831X_NUM_IRQ_REGS 5 342#define WM831X_NUM_IRQ_REGS 5
343#define WM831X_NUM_GPIO_REGS 16
240 344
241enum wm831x_parent { 345enum wm831x_parent {
242 WM8310 = 0x8310, 346 WM8310 = 0x8310,
@@ -248,23 +352,27 @@ enum wm831x_parent {
248 WM8326 = 0x8326, 352 WM8326 = 0x8326,
249}; 353};
250 354
355struct wm831x;
356enum wm831x_auxadc;
357
358typedef int (*wm831x_auxadc_read_fn)(struct wm831x *wm831x,
359 enum wm831x_auxadc input);
360
251struct wm831x { 361struct wm831x {
252 struct mutex io_lock; 362 struct mutex io_lock;
253 363
254 struct device *dev; 364 struct device *dev;
255 int (*read_dev)(struct wm831x *wm831x, unsigned short reg,
256 int bytes, void *dest);
257 int (*write_dev)(struct wm831x *wm831x, unsigned short reg,
258 int bytes, void *src);
259 365
260 void *control_data; 366 struct regmap *regmap;
261 367
262 int irq; /* Our chip IRQ */ 368 int irq; /* Our chip IRQ */
263 struct mutex irq_lock; 369 struct mutex irq_lock;
264 unsigned int irq_base; 370 int irq_base;
265 int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */ 371 int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */
266 int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */ 372 int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */
267 373
374 bool soft_shutdown;
375
268 /* Chip revision based flags */ 376 /* Chip revision based flags */
269 unsigned has_gpio_ena:1; /* Has GPIO enable bit */ 377 unsigned has_gpio_ena:1; /* Has GPIO enable bit */
270 unsigned has_cs_sts:1; /* Has current sink status bit */ 378 unsigned has_cs_sts:1; /* Has current sink status bit */
@@ -272,8 +380,13 @@ struct wm831x {
272 380
273 int num_gpio; 381 int num_gpio;
274 382
383 /* Used by the interrupt controller code to post writes */
384 int gpio_update[WM831X_NUM_GPIO_REGS];
385
275 struct mutex auxadc_lock; 386 struct mutex auxadc_lock;
276 struct completion auxadc_done; 387 struct list_head auxadc_pending;
388 u16 auxadc_active;
389 wm831x_auxadc_read_fn auxadc_read;
277 390
278 /* The WM831x has a security key blocking access to certain 391 /* The WM831x has a security key blocking access to certain
279 * registers. The mutex is taken by the accessors for locking 392 * registers. The mutex is taken by the accessors for locking
@@ -298,7 +411,11 @@ int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg,
298int wm831x_device_init(struct wm831x *wm831x, unsigned long id, int irq); 411int wm831x_device_init(struct wm831x *wm831x, unsigned long id, int irq);
299void wm831x_device_exit(struct wm831x *wm831x); 412void wm831x_device_exit(struct wm831x *wm831x);
300int wm831x_device_suspend(struct wm831x *wm831x); 413int wm831x_device_suspend(struct wm831x *wm831x);
414void wm831x_device_shutdown(struct wm831x *wm831x);
301int wm831x_irq_init(struct wm831x *wm831x, int irq); 415int wm831x_irq_init(struct wm831x *wm831x, int irq);
302void wm831x_irq_exit(struct wm831x *wm831x); 416void wm831x_irq_exit(struct wm831x *wm831x);
417void wm831x_auxadc_init(struct wm831x *wm831x);
418
419extern struct regmap_config wm831x_regmap_config;
303 420
304#endif 421#endif
diff --git a/include/linux/mfd/wm831x/pdata.h b/include/linux/mfd/wm831x/pdata.h
index ff42d700293..1d7a3f7b3b5 100644
--- a/include/linux/mfd/wm831x/pdata.h
+++ b/include/linux/mfd/wm831x/pdata.h
@@ -120,6 +120,12 @@ struct wm831x_pdata {
120 /** Put the /IRQ line into CMOS mode */ 120 /** Put the /IRQ line into CMOS mode */
121 bool irq_cmos; 121 bool irq_cmos;
122 122
123 /** Disable the touchscreen */
124 bool disable_touch;
125
126 /** The driver should initiate a power off sequence during shutdown */
127 bool soft_shutdown;
128
123 int irq_base; 129 int irq_base;
124 int gpio_base; 130 int gpio_base;
125 int gpio_defaults[WM831X_GPIO_NUM]; 131 int gpio_defaults[WM831X_GPIO_NUM];
diff --git a/include/linux/mfd/wm8400-private.h b/include/linux/mfd/wm8400-private.h
index 2aab4e93a5c..0147b696851 100644
--- a/include/linux/mfd/wm8400-private.h
+++ b/include/linux/mfd/wm8400-private.h
@@ -25,16 +25,15 @@
25#include <linux/mutex.h> 25#include <linux/mutex.h>
26#include <linux/platform_device.h> 26#include <linux/platform_device.h>
27 27
28struct regmap;
29
28#define WM8400_REGISTER_COUNT 0x55 30#define WM8400_REGISTER_COUNT 0x55
29 31
30struct wm8400 { 32struct wm8400 {
31 struct device *dev; 33 struct device *dev;
32 34
33 int (*read_dev)(void *data, char reg, int count, u16 *dst);
34 int (*write_dev)(void *data, char reg, int count, const u16 *src);
35
36 struct mutex io_lock; 35 struct mutex io_lock;
37 void *io_data; 36 struct regmap *regmap;
38 37
39 u16 reg_cache[WM8400_REGISTER_COUNT]; 38 u16 reg_cache[WM8400_REGISTER_COUNT];
40 39
diff --git a/include/linux/mfd/wm8994/core.h b/include/linux/mfd/wm8994/core.h
index f0b69cdae41..45df450d869 100644
--- a/include/linux/mfd/wm8994/core.h
+++ b/include/linux/mfd/wm8994/core.h
@@ -24,6 +24,7 @@ enum wm8994_type {
24 24
25struct regulator_dev; 25struct regulator_dev;
26struct regulator_bulk_data; 26struct regulator_bulk_data;
27struct regmap;
27 28
28#define WM8994_NUM_GPIO_REGS 11 29#define WM8994_NUM_GPIO_REGS 11
29#define WM8994_NUM_LDO_REGS 2 30#define WM8994_NUM_LDO_REGS 2
@@ -50,18 +51,12 @@ struct regulator_bulk_data;
50#define WM8994_IRQ_GPIO(x) (x + WM8994_IRQ_TEMP_WARN) 51#define WM8994_IRQ_GPIO(x) (x + WM8994_IRQ_TEMP_WARN)
51 52
52struct wm8994 { 53struct wm8994 {
53 struct mutex io_lock;
54 struct mutex irq_lock; 54 struct mutex irq_lock;
55 55
56 enum wm8994_type type; 56 enum wm8994_type type;
57 57
58 struct device *dev; 58 struct device *dev;
59 int (*read_dev)(struct wm8994 *wm8994, unsigned short reg, 59 struct regmap *regmap;
60 int bytes, void *dest);
61 int (*write_dev)(struct wm8994 *wm8994, unsigned short reg,
62 int bytes, const void *src);
63
64 void *control_data;
65 60
66 int gpio_base; 61 int gpio_base;
67 int irq_base; 62 int irq_base;
diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h
index d12f8d635a8..97cf4f27d64 100644
--- a/include/linux/mfd/wm8994/pdata.h
+++ b/include/linux/mfd/wm8994/pdata.h
@@ -26,7 +26,7 @@ struct wm8994_ldo_pdata {
26 struct regulator_init_data *init_data; 26 struct regulator_init_data *init_data;
27}; 27};
28 28
29#define WM8994_CONFIGURE_GPIO 0x8000 29#define WM8994_CONFIGURE_GPIO 0x10000
30 30
31#define WM8994_DRC_REGS 5 31#define WM8994_DRC_REGS 5
32#define WM8994_EQ_REGS 20 32#define WM8994_EQ_REGS 20
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-02 04:45:28 -0400