aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-mips
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/addrspace.h36
-rw-r--r--include/asm-mips/apm.h65
-rw-r--r--include/asm-mips/asmmacro-32.h4
-rw-r--r--include/asm-mips/asmmacro-64.h19
-rw-r--r--include/asm-mips/bootinfo.h13
-rw-r--r--include/asm-mips/cpu.h6
-rw-r--r--include/asm-mips/ddb5074.h11
-rw-r--r--include/asm-mips/ddb5xxx/ddb5074.h38
-rw-r--r--include/asm-mips/ddb5xxx/ddb5476.h157
-rw-r--r--include/asm-mips/ddb5xxx/ddb5xxx.h11
-rw-r--r--include/asm-mips/delay.h22
-rw-r--r--include/asm-mips/emma2rh/emma2rh.h330
-rw-r--r--include/asm-mips/emma2rh/markeins.h76
-rw-r--r--include/asm-mips/fpu.h3
-rw-r--r--include/asm-mips/fpu_emulator.h4
-rw-r--r--include/asm-mips/futex.h153
-rw-r--r--include/asm-mips/inst.h33
-rw-r--r--include/asm-mips/mach-ddb5074/mc146818rtc.h31
-rw-r--r--include/asm-mips/mach-dec/param.h18
-rw-r--r--include/asm-mips/mach-emma2rh/irq.h (renamed from include/asm-mips/mach-mips/param.h)8
-rw-r--r--include/asm-mips/mach-excite/cpu-feature-overrides.h40
-rw-r--r--include/asm-mips/mach-excite/excite.h155
-rw-r--r--include/asm-mips/mach-excite/excite_nandflash.h7
-rw-r--r--include/asm-mips/mach-excite/rm9k_eth.h23
-rw-r--r--include/asm-mips/mach-excite/rm9k_wdt.h12
-rw-r--r--include/asm-mips/mach-excite/rm9k_xicap.h16
-rw-r--r--include/asm-mips/mach-generic/param.h13
-rw-r--r--include/asm-mips/mach-ip22/cpu-feature-overrides.h2
-rw-r--r--include/asm-mips/mach-ip27/cpu-feature-overrides.h3
-rw-r--r--include/asm-mips/mach-ip32/cpu-feature-overrides.h2
-rw-r--r--include/asm-mips/mach-jazz/param.h16
-rw-r--r--include/asm-mips/mach-mips/cpu-feature-overrides.h4
-rw-r--r--include/asm-mips/mach-qemu/param.h13
-rw-r--r--include/asm-mips/mach-rm200/cpu-feature-overrides.h4
-rw-r--r--include/asm-mips/mach-sim/cpu-feature-overrides.h4
-rw-r--r--include/asm-mips/mach-wrppmc/mach-gt64120.h84
-rw-r--r--include/asm-mips/mipsregs.h6
-rw-r--r--include/asm-mips/mmzone.h11
-rw-r--r--include/asm-mips/page.h21
-rw-r--r--include/asm-mips/param.h2
-rw-r--r--include/asm-mips/pci/bridge.h3
-rw-r--r--include/asm-mips/pgtable-32.h61
-rw-r--r--include/asm-mips/pgtable-64.h13
-rw-r--r--include/asm-mips/pgtable.h105
-rw-r--r--include/asm-mips/processor.h16
-rw-r--r--include/asm-mips/qemu.h6
-rw-r--r--include/asm-mips/rm9k-ocd.h56
-rw-r--r--include/asm-mips/sigcontext.h10
-rw-r--r--include/asm-mips/smp.h5
-rw-r--r--include/asm-mips/sn/addrs.h27
-rw-r--r--include/asm-mips/sn/fru.h (renamed from include/asm-mips/sn/sn0/sn0_fru.h)8
-rw-r--r--include/asm-mips/sn/klconfig.h89
-rw-r--r--include/asm-mips/sn/kldir.h34
-rw-r--r--include/asm-mips/sn/sn0/addrs.h87
-rw-r--r--include/asm-mips/sn/sn0/arch.h17
-rw-r--r--include/asm-mips/sn/sn0/hub.h4
-rw-r--r--include/asm-mips/sn/sn0/hubio.h16
-rw-r--r--include/asm-mips/sn/sn0/hubmd.h2
-rw-r--r--include/asm-mips/sn/sn0/hubpi.h18
-rw-r--r--include/asm-mips/sn/sn0/ip27.h9
-rw-r--r--include/asm-mips/sni.h7
-rw-r--r--include/asm-mips/sparsemem.h14
-rw-r--r--include/asm-mips/war.h5
63 files changed, 1267 insertions, 821 deletions
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index a7d0d26e93c..45c706e34df 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -128,60 +128,26 @@
128#if defined (CONFIG_CPU_R4300) \ 128#if defined (CONFIG_CPU_R4300) \
129 || defined (CONFIG_CPU_R4X00) \ 129 || defined (CONFIG_CPU_R4X00) \
130 || defined (CONFIG_CPU_R5000) \ 130 || defined (CONFIG_CPU_R5000) \
131 || defined (CONFIG_CPU_RM7000) \
131 || defined (CONFIG_CPU_NEVADA) \ 132 || defined (CONFIG_CPU_NEVADA) \
132 || defined (CONFIG_CPU_TX49XX) \ 133 || defined (CONFIG_CPU_TX49XX) \
133 || defined (CONFIG_CPU_MIPS64) 134 || defined (CONFIG_CPU_MIPS64)
134#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
135#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */
136#define K0SIZE _LLCONST_(0x0000001000000000) /* 2^^36 */
137#define K1SIZE _LLCONST_(0x0000001000000000) /* 2^^36 */
138#define K2SIZE _LLCONST_(0x000000ff80000000)
139#define KSEGSIZE _LLCONST_(0x000000ff80000000) /* max syssegsz */
140#define TO_PHYS_MASK _LLCONST_(0x0000000fffffffff) /* 2^^36 - 1 */ 135#define TO_PHYS_MASK _LLCONST_(0x0000000fffffffff) /* 2^^36 - 1 */
141#endif 136#endif
142 137
143#if defined (CONFIG_CPU_R8000) 138#if defined (CONFIG_CPU_R8000)
144/* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */ 139/* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */
145#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
146#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */
147#define K0SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
148#define K1SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
149#define K2SIZE _LLCONST_(0x0001000000000000)
150#define KSEGSIZE _LLCONST_(0x0000010000000000) /* max syssegsz */
151#define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff) /* 2^^40 - 1 */ 140#define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff) /* 2^^40 - 1 */
152#endif 141#endif
153 142
154#if defined (CONFIG_CPU_R10000) 143#if defined (CONFIG_CPU_R10000)
155#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
156#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */
157#define K0SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
158#define K1SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
159#define K2SIZE _LLCONST_(0x00000fff80000000)
160#define KSEGSIZE _LLCONST_(0x00000fff80000000) /* max syssegsz */
161#define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff) /* 2^^40 - 1 */ 144#define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff) /* 2^^40 - 1 */
162#endif 145#endif
163 146
164#if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A) 147#if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A)
165#define KUSIZE _LLCONST_(0x0000100000000000) /* 2^^44 */
166#define KUSIZE_64 _LLCONST_(0x0000100000000000) /* 2^^44 */
167#define K0SIZE _LLCONST_(0x0000100000000000) /* 2^^44 */
168#define K1SIZE _LLCONST_(0x0000100000000000) /* 2^^44 */
169#define K2SIZE _LLCONST_(0x0000ffff80000000)
170#define KSEGSIZE _LLCONST_(0x0000ffff80000000) /* max syssegsz */
171#define TO_PHYS_MASK _LLCONST_(0x00000fffffffffff) /* 2^^44 - 1 */ 148#define TO_PHYS_MASK _LLCONST_(0x00000fffffffffff) /* 2^^44 - 1 */
172#endif 149#endif
173 150
174/*
175 * Further names for SGI source compatibility. These are stolen from
176 * IRIX's <sys/mips_addrspace.h>.
177 */
178#define KUBASE _LLCONST_(0)
179#define KUSIZE_32 _LLCONST_(0x0000000080000000) /* KUSIZE
180 for a 32 bit proc */
181#define K0BASE_EXL_WR _LLCONST_(0xa800000000000000) /* exclusive on write */
182#define K0BASE_NONCOH _LLCONST_(0x9800000000000000) /* noncoherent */
183#define K0BASE_EXL _LLCONST_(0xa000000000000000) /* exclusive */
184
185#ifndef CONFIG_CPU_R8000 151#ifndef CONFIG_CPU_R8000
186 152
187/* 153/*
diff --git a/include/asm-mips/apm.h b/include/asm-mips/apm.h
new file mode 100644
index 00000000000..e8c69208f63
--- /dev/null
+++ b/include/asm-mips/apm.h
@@ -0,0 +1,65 @@
1/* -*- linux-c -*-
2 *
3 * (C) 2003 zecke@handhelds.org
4 *
5 * GPL version 2
6 *
7 * based on arch/arm/kernel/apm.c
8 * factor out the information needed by architectures to provide
9 * apm status
10 *
11 *
12 */
13#ifndef MIPS_ASM_SA1100_APM_H
14#define MIPS_ASM_SA1100_APM_H
15
16#include <linux/config.h>
17#include <linux/apm_bios.h>
18
19/*
20 * This structure gets filled in by the machine specific 'get_power_status'
21 * implementation. Any fields which are not set default to a safe value.
22 */
23struct apm_power_info {
24 unsigned char ac_line_status;
25#define APM_AC_OFFLINE 0
26#define APM_AC_ONLINE 1
27#define APM_AC_BACKUP 2
28#define APM_AC_UNKNOWN 0xff
29
30 unsigned char battery_status;
31#define APM_BATTERY_STATUS_HIGH 0
32#define APM_BATTERY_STATUS_LOW 1
33#define APM_BATTERY_STATUS_CRITICAL 2
34#define APM_BATTERY_STATUS_CHARGING 3
35#define APM_BATTERY_STATUS_NOT_PRESENT 4
36#define APM_BATTERY_STATUS_UNKNOWN 0xff
37
38 unsigned char battery_flag;
39#define APM_BATTERY_FLAG_HIGH (1 << 0)
40#define APM_BATTERY_FLAG_LOW (1 << 1)
41#define APM_BATTERY_FLAG_CRITICAL (1 << 2)
42#define APM_BATTERY_FLAG_CHARGING (1 << 3)
43#define APM_BATTERY_FLAG_NOT_PRESENT (1 << 7)
44#define APM_BATTERY_FLAG_UNKNOWN 0xff
45
46 int battery_life;
47 int time;
48 int units;
49#define APM_UNITS_MINS 0
50#define APM_UNITS_SECS 1
51#define APM_UNITS_UNKNOWN -1
52
53};
54
55/*
56 * This allows machines to provide their own "apm get power status" function.
57 */
58extern void (*apm_get_power_status)(struct apm_power_info *);
59
60/*
61 * Queue an event (APM_SYS_SUSPEND or APM_CRITICAL_SUSPEND)
62 */
63void apm_queue_event(apm_event_t event);
64
65#endif
diff --git a/include/asm-mips/asmmacro-32.h b/include/asm-mips/asmmacro-32.h
index 11daf5ceb7b..5de3963f511 100644
--- a/include/asm-mips/asmmacro-32.h
+++ b/include/asm-mips/asmmacro-32.h
@@ -12,7 +12,7 @@
12#include <asm/fpregdef.h> 12#include <asm/fpregdef.h>
13#include <asm/mipsregs.h> 13#include <asm/mipsregs.h>
14 14
15 .macro fpu_save_double thread status tmp1=t0 tmp2 15 .macro fpu_save_double thread status tmp1=t0
16 cfc1 \tmp1, fcr31 16 cfc1 \tmp1, fcr31
17 sdc1 $f0, THREAD_FPR0(\thread) 17 sdc1 $f0, THREAD_FPR0(\thread)
18 sdc1 $f2, THREAD_FPR2(\thread) 18 sdc1 $f2, THREAD_FPR2(\thread)
@@ -70,7 +70,7 @@
70 sw \tmp, THREAD_FCR31(\thread) 70 sw \tmp, THREAD_FCR31(\thread)
71 .endm 71 .endm
72 72
73 .macro fpu_restore_double thread tmp=t0 73 .macro fpu_restore_double thread status tmp=t0
74 lw \tmp, THREAD_FCR31(\thread) 74 lw \tmp, THREAD_FCR31(\thread)
75 ldc1 $f0, THREAD_FPR0(\thread) 75 ldc1 $f0, THREAD_FPR0(\thread)
76 ldc1 $f2, THREAD_FPR2(\thread) 76 ldc1 $f2, THREAD_FPR2(\thread)
diff --git a/include/asm-mips/asmmacro-64.h b/include/asm-mips/asmmacro-64.h
index 559c355b9b8..225feefcb25 100644
--- a/include/asm-mips/asmmacro-64.h
+++ b/include/asm-mips/asmmacro-64.h
@@ -53,12 +53,12 @@
53 sdc1 $f31, THREAD_FPR31(\thread) 53 sdc1 $f31, THREAD_FPR31(\thread)
54 .endm 54 .endm
55 55
56 .macro fpu_save_double thread status tmp1 tmp2 56 .macro fpu_save_double thread status tmp
57 sll \tmp2, \tmp1, 5 57 sll \tmp, \status, 5
58 bgez \tmp2, 2f 58 bgez \tmp, 2f
59 fpu_save_16odd \thread 59 fpu_save_16odd \thread
602: 602:
61 fpu_save_16even \thread \tmp1 # clobbers t1 61 fpu_save_16even \thread \tmp
62 .endm 62 .endm
63 63
64 .macro fpu_restore_16even thread tmp=t0 64 .macro fpu_restore_16even thread tmp=t0
@@ -101,13 +101,12 @@
101 ldc1 $f31, THREAD_FPR31(\thread) 101 ldc1 $f31, THREAD_FPR31(\thread)
102 .endm 102 .endm
103 103
104 .macro fpu_restore_double thread tmp 104 .macro fpu_restore_double thread status tmp
105 mfc0 t0, CP0_STATUS 105 sll \tmp, \status, 5
106 sll t1, t0, 5 106 bgez \tmp, 1f # 16 register mode?
107 bgez t1, 1f # 16 register mode?
108 107
109 fpu_restore_16odd a0 108 fpu_restore_16odd \thread
1101: fpu_restore_16even a0, t0 # clobbers t0 1091: fpu_restore_16even \thread \tmp
111 .endm 110 .endm
112 111
113 .macro cpu_save_nonscratch thread 112 .macro cpu_save_nonscratch thread
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index 14fc88f2722..3b745e76f42 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -217,6 +217,13 @@
217 */ 217 */
218#define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */ 218#define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
219#define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */ 219#define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
220#define MACH_TITAN_EXCITE 2 /* Basler eXcite */
221
222/*
223 * Valid machtype for group NEC EMMA2RH
224 */
225#define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */
226#define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */
220 227
221#define CL_SIZE COMMAND_LINE_SIZE 228#define CL_SIZE COMMAND_LINE_SIZE
222 229
@@ -258,4 +265,10 @@ extern char arcs_cmdline[CL_SIZE];
258 * Registers a0, a1, a3 and a4 as passed to the kenrel entry by firmware 265 * Registers a0, a1, a3 and a4 as passed to the kenrel entry by firmware
259 */ 266 */
260extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3; 267extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
268
269/*
270 * Platform memory detection hook called by setup_arch
271 */
272extern void plat_mem_setup(void);
273
261#endif /* _ASM_BOOTINFO_H */ 274#endif /* _ASM_BOOTINFO_H */
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 818b9a97e21..dff2a0a52f8 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -51,6 +51,7 @@
51#define PRID_IMP_R4300 0x0b00 51#define PRID_IMP_R4300 0x0b00
52#define PRID_IMP_VR41XX 0x0c00 52#define PRID_IMP_VR41XX 0x0c00
53#define PRID_IMP_R12000 0x0e00 53#define PRID_IMP_R12000 0x0e00
54#define PRID_IMP_R14000 0x0f00
54#define PRID_IMP_R8000 0x1000 55#define PRID_IMP_R8000 0x1000
55#define PRID_IMP_PR4450 0x1200 56#define PRID_IMP_PR4450 0x1200
56#define PRID_IMP_R4600 0x2000 57#define PRID_IMP_R4600 0x2000
@@ -87,6 +88,7 @@
87#define PRID_IMP_24K 0x9300 88#define PRID_IMP_24K 0x9300
88#define PRID_IMP_34K 0x9500 89#define PRID_IMP_34K 0x9500
89#define PRID_IMP_24KE 0x9600 90#define PRID_IMP_24KE 0x9600
91#define PRID_IMP_74K 0x9700
90 92
91/* 93/*
92 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE 94 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -196,7 +198,9 @@
196#define CPU_34K 60 198#define CPU_34K 60
197#define CPU_PR4450 61 199#define CPU_PR4450 61
198#define CPU_SB1A 62 200#define CPU_SB1A 62
199#define CPU_LAST 62 201#define CPU_74K 63
202#define CPU_R14000 64
203#define CPU_LAST 64
200 204
201/* 205/*
202 * ISA Level encodings 206 * ISA Level encodings
diff --git a/include/asm-mips/ddb5074.h b/include/asm-mips/ddb5074.h
deleted file mode 100644
index 0d09ac27f9a..00000000000
--- a/include/asm-mips/ddb5074.h
+++ /dev/null
@@ -1,11 +0,0 @@
1/*
2 * include/asm-mips/ddb5074.h -- NEC DDB Vrc-5074 definitions
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 */
7
8extern void ddb5074_led_hex(int hex);
9extern void ddb5074_led_d2(int on);
10extern void ddb5074_led_d3(int on);
11
diff --git a/include/asm-mips/ddb5xxx/ddb5074.h b/include/asm-mips/ddb5xxx/ddb5074.h
deleted file mode 100644
index 58d88306af6..00000000000
--- a/include/asm-mips/ddb5xxx/ddb5074.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * include/asm-mips/ddb5074.h -- NEC DDB Vrc-5074 definitions
3 *
4 * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
5 * Sony Software Development Center Europe (SDCE), Brussels
6 */
7
8#ifndef _ASM_DDB5XXX_DDB5074_H
9#define _ASM_DDB5XXX_DDB5074_H
10
11#include <asm/nile4.h>
12
13#define DDB_SDRAM_SIZE 0x04000000 /* 64MB */
14
15#define DDB_PCI_IO_BASE 0x06000000
16#define DDB_PCI_IO_SIZE 0x02000000 /* 32 MB */
17
18#define DDB_PCI_MEM_BASE 0x08000000
19#define DDB_PCI_MEM_SIZE 0x08000000 /* 128 MB */
20
21#define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
22#define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE
23
24#define NILE4_PCI_IO_BASE 0xa6000000
25#define NILE4_PCI_MEM_BASE 0xa8000000
26#define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE
27#define DDB_PCI_IACK_BASE NILE4_PCI_IO_BASE
28
29#define NILE4_IRQ_BASE NUM_I8259_INTERRUPTS
30#define CPU_IRQ_BASE (NUM_NILE4_INTERRUPTS + NILE4_IRQ_BASE)
31#define CPU_NILE4_CASCADE 2
32
33extern void ddb5074_led_hex(int hex);
34extern void ddb5074_led_d2(int on);
35extern void ddb5074_led_d3(int on);
36
37extern void nile4_irq_setup(u32 base);
38#endif
diff --git a/include/asm-mips/ddb5xxx/ddb5476.h b/include/asm-mips/ddb5xxx/ddb5476.h
deleted file mode 100644
index 4c23390d935..00000000000
--- a/include/asm-mips/ddb5xxx/ddb5476.h
+++ /dev/null
@@ -1,157 +0,0 @@
1/*
2 * header file specific for ddb5476
3 *
4 * Copyright (C) 2001 MontaVista Software Inc.
5 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14/*
15 * Memory map (physical address)
16 *
17 * Note most of the following address must be properly aligned by the
18 * corresponding size. For example, if PCI_IO_SIZE is 16MB, then
19 * PCI_IO_BASE must be aligned along 16MB boundary.
20 */
21#define DDB_SDRAM_BASE 0x00000000
22#define DDB_SDRAM_SIZE 0x04000000 /* 64MB */
23
24#define DDB_DCS3_BASE 0x04000000 /* flash 1 */
25#define DDB_DCS3_SIZE 0x01000000 /* 16MB */
26
27#define DDB_DCS2_BASE 0x05000000 /* flash 2 */
28#define DDB_DCS2_SIZE 0x01000000 /* 16MB */
29
30#define DDB_PCI_IO_BASE 0x06000000
31#define DDB_PCI_IO_SIZE 0x02000000 /* 32 MB */
32
33#define DDB_PCI_MEM_BASE 0x08000000
34#define DDB_PCI_MEM_SIZE 0x08000000 /* 128 MB */
35
36#define DDB_DCS5_BASE 0x13000000 /* DDB status regs */
37#define DDB_DCS5_SIZE 0x00200000 /* 2MB, 8-bit */
38
39#define DDB_DCS4_BASE 0x14000000 /* DDB control regs */
40#define DDB_DCS4_SIZE 0x00200000 /* 2MB, 8-bit */
41
42#define DDB_INTCS_BASE 0x1fa00000 /* VRC5476 control regs */
43#define DDB_INTCS_SIZE 0x00200000 /* 2MB */
44
45#define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */
46#define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */
47
48
49/* aliases */
50#define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
51#define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE
52
53/* PCI intr ack share PCIW0 with PCI IO */
54#define DDB_PCI_IACK_BASE DDB_PCI_IO_BASE
55
56/*
57 * Interrupt mapping
58 *
59 * We have three interrupt controllers:
60 *
61 * . CPU itself - 8 sources
62 * . i8259 - 16 sources
63 * . vrc5476 - 16 sources
64 *
65 * They connected as follows:
66 * all vrc5476 interrupts are routed to cpu IP2 (by software setting)
67 * all i2869 are routed to INTC in vrc5476 (by hardware connection)
68 *
69 * All VRC5476 PCI interrupts are level-triggered (no ack needed).
70 * All PCI irq but INTC are active low.
71 */
72
73/*
74 * irq number block assignment
75 */
76
77#define NUM_CPU_IRQ 8
78#define NUM_I8259_IRQ 16
79#define NUM_VRC5476_IRQ 16
80
81#define DDB_IRQ_BASE 0
82
83#define I8259_IRQ_BASE DDB_IRQ_BASE
84#define VRC5476_IRQ_BASE (I8259_IRQ_BASE + NUM_I8259_IRQ)
85#define CPU_IRQ_BASE (VRC5476_IRQ_BASE + NUM_VRC5476_IRQ)
86
87/*
88 * vrc5476 irq defs, see page 52-64 of Vrc5074 system controller manual
89 */
90
91#define VRC5476_IRQ_CPCE 0 /* cpu parity error */
92#define VRC5476_IRQ_CNTD 1 /* cpu no target */
93#define VRC5476_IRQ_MCE 2 /* memory check error */
94#define VRC5476_IRQ_DMA 3 /* DMA */
95#define VRC5476_IRQ_UART 4 /* vrc5476 builtin UART, not used */
96#define VRC5476_IRQ_WDOG 5 /* watchdog timer */
97#define VRC5476_IRQ_GPT 6 /* general purpose timer */
98#define VRC5476_IRQ_LBRT 7 /* local bus read timeout */
99#define VRC5476_IRQ_INTA 8 /* PCI INT #A */
100#define VRC5476_IRQ_INTB 9 /* PCI INT #B */
101#define VRC5476_IRQ_INTC 10 /* PCI INT #C */
102#define VRC5476_IRQ_INTD 11 /* PCI INT #D */
103#define VRC5476_IRQ_INTE 12 /* PCI INT #E */
104#define VRC5476_IRQ_RESERVED_13 13 /* reserved */
105#define VRC5476_IRQ_PCIS 14 /* PCI SERR # */
106#define VRC5476_IRQ_PCI 15 /* PCI internal error */
107
108/*
109 * i2859 irq assignment
110 */
111#define I8259_IRQ_RESERVED_0 0
112#define I8259_IRQ_KEYBOARD 1 /* M1543 default */
113#define I8259_IRQ_CASCADE 2
114#define I8259_IRQ_UART_B 3 /* M1543 default, may conflict with RTC according to schematic diagram */
115#define I8259_IRQ_UART_A 4 /* M1543 default */
116#define I8259_IRQ_PARALLEL 5 /* M1543 default */
117#define I8259_IRQ_RESERVED_6 6
118#define I8259_IRQ_RESERVED_7 7
119#define I8259_IRQ_RTC 8 /* who set this? */
120#define I8259_IRQ_USB 9 /* ddb_setup */
121#define I8259_IRQ_PMU 10 /* ddb_setup */
122#define I8259_IRQ_RESERVED_11 11
123#define I8259_IRQ_RESERVED_12 12 /* m1543_irq_setup */
124#define I8259_IRQ_RESERVED_13 13
125#define I8259_IRQ_HDC1 14 /* default and ddb_setup */
126#define I8259_IRQ_HDC2 15 /* default */
127
128
129/*
130 * misc
131 */
132#define VRC5476_I8259_CASCADE VRC5476_IRQ_INTC
133#define CPU_VRC5476_CASCADE 2
134
135#define is_i8259_irq(irq) ((irq) < NUM_I8259_IRQ)
136#define nile4_to_irq(n) ((n)+NUM_I8259_IRQ)
137#define irq_to_nile4(n) ((n)-NUM_I8259_IRQ)
138
139/*
140 * low-level irq functions
141 */
142#ifndef __ASSEMBLY__
143extern void nile4_map_irq(int nile4_irq, int cpu_irq);
144extern void nile4_map_irq_all(int cpu_irq);
145extern void nile4_enable_irq(int nile4_irq);
146extern void nile4_disable_irq(int nile4_irq);
147extern void nile4_disable_irq_all(void);
148extern u16 nile4_get_irq_stat(int cpu_irq);
149extern void nile4_enable_irq_output(int cpu_irq);
150extern void nile4_disable_irq_output(int cpu_irq);
151extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
152extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
153extern void nile4_clear_irq(int nile4_irq);
154extern void nile4_clear_irq_mask(u32 mask);
155extern u8 nile4_i8259_iack(void);
156extern void nile4_dump_irq_status(void); /* Debug */
157#endif /* !__ASSEMBLY__ */
diff --git a/include/asm-mips/ddb5xxx/ddb5xxx.h b/include/asm-mips/ddb5xxx/ddb5xxx.h
index 42c27487162..e97fcc8d548 100644
--- a/include/asm-mips/ddb5xxx/ddb5xxx.h
+++ b/include/asm-mips/ddb5xxx/ddb5xxx.h
@@ -173,13 +173,8 @@
173 173
174static inline void ddb_sync(void) 174static inline void ddb_sync(void)
175{ 175{
176/* The DDB5074 doesn't seem to like these accesses. They kill the board on
177 * interrupt load
178 */
179#ifndef CONFIG_DDB5074
180 volatile u32 *p = (volatile u32 *)0xbfc00000; 176 volatile u32 *p = (volatile u32 *)0xbfc00000;
181 (void)(*p); 177 (void)(*p);
182#endif
183} 178}
184 179
185static inline void ddb_out32(u32 offset, u32 val) 180static inline void ddb_out32(u32 offset, u32 val)
@@ -259,11 +254,7 @@ extern void ddb_pci_reset_bus(void);
259/* 254/*
260 * include the board dependent part 255 * include the board dependent part
261 */ 256 */
262#if defined(CONFIG_DDB5074) 257#if defined(CONFIG_DDB5477)
263#include <asm/ddb5xxx/ddb5074.h>
264#elif defined(CONFIG_DDB5476)
265#include <asm/ddb5xxx/ddb5476.h>
266#elif defined(CONFIG_DDB5477)
267#include <asm/ddb5xxx/ddb5477.h> 258#include <asm/ddb5xxx/ddb5477.h>
268#else 259#else
269#error "Unknown DDB board!" 260#error "Unknown DDB board!"
diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h
index b2c9ed47508..ea77050f8e3 100644
--- a/include/asm-mips/delay.h
+++ b/include/asm-mips/delay.h
@@ -18,20 +18,22 @@ static inline void __delay(unsigned long loops)
18{ 18{
19 if (sizeof(long) == 4) 19 if (sizeof(long) == 4)
20 __asm__ __volatile__ ( 20 __asm__ __volatile__ (
21 ".set\tnoreorder\n" 21 " .set noreorder \n"
22 "1:\tbnez\t%0,1b\n\t" 22 " .align 3 \n"
23 "subu\t%0,1\n\t" 23 "1: bnez %0, 1b \n"
24 ".set\treorder" 24 " subu %0, 1 \n"
25 " .set reorder \n"
25 : "=r" (loops) 26 : "=r" (loops)
26 : "0" (loops)); 27 : "0" (loops));
27 else if (sizeof(long) == 8) 28 else if (sizeof(long) == 8)
28 __asm__ __volatile__ ( 29 __asm__ __volatile__ (
29 ".set\tnoreorder\n" 30 " .set noreorder \n"
30 "1:\tbnez\t%0,1b\n\t" 31 " .align 3 \n"
31 "dsubu\t%0,1\n\t" 32 "1: bnez %0, 1b \n"
32 ".set\treorder" 33 " dsubu %0, 1 \n"
33 :"=r" (loops) 34 " .set reorder \n"
34 :"0" (loops)); 35 : "=r" (loops)
36 : "0" (loops));
35} 37}
36 38
37 39
diff --git a/include/asm-mips/emma2rh/emma2rh.h b/include/asm-mips/emma2rh/emma2rh.h
new file mode 100644
index 00000000000..4fb8df71caa
--- /dev/null
+++ b/include/asm-mips/emma2rh/emma2rh.h
@@ -0,0 +1,330 @@
1/*
2 * include/asm-mips/emma2rh/emma2rh.h
3 * This file is EMMA2RH common header.
4 *
5 * Copyright (C) NEC Electronics Corporation 2005-2006
6 *
7 * This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
8 * Copyright 2001 MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24#ifndef __ASM_EMMA2RH_EMMA2RH_H
25#define __ASM_EMMA2RH_EMMA2RH_H
26
27/*
28 * EMMA2RH registers
29 */
30#define REGBASE 0x10000000
31
32#define EMMA2RH_BHIF_STRAP_0 (0x000010+REGBASE)
33#define EMMA2RH_BHIF_INT_ST_0 (0x000030+REGBASE)
34#define EMMA2RH_BHIF_INT_ST_1 (0x000034+REGBASE)
35#define EMMA2RH_BHIF_INT_ST_2 (0x000038+REGBASE)
36#define EMMA2RH_BHIF_INT_EN_0 (0x000040+REGBASE)
37#define EMMA2RH_BHIF_INT_EN_1 (0x000044+REGBASE)
38#define EMMA2RH_BHIF_INT_EN_2 (0x000048+REGBASE)
39#define EMMA2RH_BHIF_INT1_EN_0 (0x000050+REGBASE)
40#define EMMA2RH_BHIF_INT1_EN_1 (0x000054+REGBASE)
41#define EMMA2RH_BHIF_INT1_EN_2 (0x000058+REGBASE)
42#define EMMA2RH_BHIF_SW_INT (0x000070+REGBASE)
43#define EMMA2RH_BHIF_SW_INT_EN (0x000080+REGBASE)
44#define EMMA2RH_BHIF_SW_INT_CLR (0x000090+REGBASE)
45#define EMMA2RH_BHIF_MAIN_CTRL (0x0000b4+REGBASE)
46#define EMMA2RH_BHIF_EXCEPT_VECT_BASE_ADDRESS (0x0000c0+REGBASE)
47#define EMMA2RH_GPIO_DIR (0x110d20+REGBASE)
48#define EMMA2RH_GPIO_INT_ST (0x110d30+REGBASE)
49#define EMMA2RH_GPIO_INT_MASK (0x110d3c+REGBASE)
50#define EMMA2RH_GPIO_INT_MODE (0x110d48+REGBASE)
51#define EMMA2RH_GPIO_INT_CND_A (0x110d54+REGBASE)
52#define EMMA2RH_GPIO_INT_CND_B (0x110d60+REGBASE)
53#define EMMA2RH_PBRD_INT_EN (0x100010+REGBASE)
54#define EMMA2RH_PBRD_CLKSEL (0x100028+REGBASE)
55#define EMMA2RH_PFUR0_BASE (0x101000+REGBASE)
56#define EMMA2RH_PFUR1_BASE (0x102000+REGBASE)
57#define EMMA2RH_PFUR2_BASE (0x103000+REGBASE)
58#define EMMA2RH_PIIC0_BASE (0x107000+REGBASE)
59#define EMMA2RH_PIIC1_BASE (0x108000+REGBASE)
60#define EMMA2RH_PIIC2_BASE (0x109000+REGBASE)
61#define EMMA2RH_PCI_CONTROL (0x200000+REGBASE)
62#define EMMA2RH_PCI_ARBIT_CTR (0x200004+REGBASE)
63#define EMMA2RH_PCI_IWIN0_CTR (0x200010+REGBASE)
64#define EMMA2RH_PCI_IWIN1_CTR (0x200014+REGBASE)
65#define EMMA2RH_PCI_INIT_ESWP (0x200018+REGBASE)
66#define EMMA2RH_PCI_INT (0x200020+REGBASE)
67#define EMMA2RH_PCI_INT_EN (0x200024+REGBASE)
68#define EMMA2RH_PCI_TWIN_CTR (0x200030+REGBASE)
69#define EMMA2RH_PCI_TWIN_BADR (0x200034+REGBASE)
70#define EMMA2RH_PCI_TWIN0_DADR (0x200038+REGBASE)
71#define EMMA2RH_PCI_TWIN1_DADR (0x20003c+REGBASE)
72
73/*
74 * Memory map (physical address)
75 *
76 * Note most of the following address must be properly aligned by the
77 * corresponding size. For example, if PCI_IO_SIZE is 16MB, then
78 * PCI_IO_BASE must be aligned along 16MB boundary.
79 */
80
81/* the actual ram size is detected at run-time */
82#define EMMA2RH_RAM_BASE 0x00000000
83#define EMMA2RH_RAM_SIZE 0x10000000 /* less than 256MB */
84
85#define EMMA2RH_IO_BASE 0x10000000
86#define EMMA2RH_IO_SIZE 0x01000000 /* 16 MB */
87
88#define EMMA2RH_GENERALIO_BASE 0x11000000
89#define EMMA2RH_GENERALIO_SIZE 0x01000000 /* 16 MB */
90
91#define EMMA2RH_PCI_IO_BASE 0x12000000
92#define EMMA2RH_PCI_IO_SIZE 0x02000000 /* 32 MB */
93
94#define EMMA2RH_PCI_MEM_BASE 0x14000000
95#define EMMA2RH_PCI_MEM_SIZE 0x08000000 /* 128 MB */
96
97#define EMMA2RH_ROM_BASE 0x1c000000
98#define EMMA2RH_ROM_SIZE 0x04000000 /* 64 MB */
99
100#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE
101#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE
102
103#define NUM_CPU_IRQ 8
104#define NUM_EMMA2RH_IRQ 96
105
106#define CPU_EMMA2RH_CASCADE 2
107#define EMMA2RH_IRQ_BASE 0
108
109/*
110 * emma2rh irq defs
111 */
112
113#define EMMA2RH_IRQ_INT0 (0 + EMMA2RH_IRQ_BASE)
114#define EMMA2RH_IRQ_INT1 (1 + EMMA2RH_IRQ_BASE)
115#define EMMA2RH_IRQ_INT2 (2 + EMMA2RH_IRQ_BASE)
116#define EMMA2RH_IRQ_INT3 (3 + EMMA2RH_IRQ_BASE)
117#define EMMA2RH_IRQ_INT4 (4 + EMMA2RH_IRQ_BASE)
118#define EMMA2RH_IRQ_INT5 (5 + EMMA2RH_IRQ_BASE)
119#define EMMA2RH_IRQ_INT6 (6 + EMMA2RH_IRQ_BASE)
120#define EMMA2RH_IRQ_INT7 (7 + EMMA2RH_IRQ_BASE)
121#define EMMA2RH_IRQ_INT8 (8 + EMMA2RH_IRQ_BASE)
122#define EMMA2RH_IRQ_INT9 (9 + EMMA2RH_IRQ_BASE)
123#define EMMA2RH_IRQ_INT10 (10 + EMMA2RH_IRQ_BASE)
124#define EMMA2RH_IRQ_INT11 (11 + EMMA2RH_IRQ_BASE)
125#define EMMA2RH_IRQ_INT12 (12 + EMMA2RH_IRQ_BASE)
126#define EMMA2RH_IRQ_INT13 (13 + EMMA2RH_IRQ_BASE)
127#define EMMA2RH_IRQ_INT14 (14 + EMMA2RH_IRQ_BASE)
128#define EMMA2RH_IRQ_INT15 (15 + EMMA2RH_IRQ_BASE)
129#define EMMA2RH_IRQ_INT16 (16 + EMMA2RH_IRQ_BASE)
130#define EMMA2RH_IRQ_INT17 (17 + EMMA2RH_IRQ_BASE)
131#define EMMA2RH_IRQ_INT18 (18 + EMMA2RH_IRQ_BASE)
132#define EMMA2RH_IRQ_INT19 (19 + EMMA2RH_IRQ_BASE)
133#define EMMA2RH_IRQ_INT20 (20 + EMMA2RH_IRQ_BASE)
134#define EMMA2RH_IRQ_INT21 (21 + EMMA2RH_IRQ_BASE)
135#define EMMA2RH_IRQ_INT22 (22 + EMMA2RH_IRQ_BASE)
136#define EMMA2RH_IRQ_INT23 (23 + EMMA2RH_IRQ_BASE)
137#define EMMA2RH_IRQ_INT24 (24 + EMMA2RH_IRQ_BASE)
138#define EMMA2RH_IRQ_INT25 (25 + EMMA2RH_IRQ_BASE)
139#define EMMA2RH_IRQ_INT26 (26 + EMMA2RH_IRQ_BASE)
140#define EMMA2RH_IRQ_INT27 (27 + EMMA2RH_IRQ_BASE)
141#define EMMA2RH_IRQ_INT28 (28 + EMMA2RH_IRQ_BASE)
142#define EMMA2RH_IRQ_INT29 (29 + EMMA2RH_IRQ_BASE)
143#define EMMA2RH_IRQ_INT30 (30 + EMMA2RH_IRQ_BASE)
144#define EMMA2RH_IRQ_INT31 (31 + EMMA2RH_IRQ_BASE)
145#define EMMA2RH_IRQ_INT32 (32 + EMMA2RH_IRQ_BASE)
146#define EMMA2RH_IRQ_INT33 (33 + EMMA2RH_IRQ_BASE)
147#define EMMA2RH_IRQ_INT34 (34 + EMMA2RH_IRQ_BASE)
148#define EMMA2RH_IRQ_INT35 (35 + EMMA2RH_IRQ_BASE)
149#define EMMA2RH_IRQ_INT36 (36 + EMMA2RH_IRQ_BASE)
150#define EMMA2RH_IRQ_INT37 (37 + EMMA2RH_IRQ_BASE)
151#define EMMA2RH_IRQ_INT38 (38 + EMMA2RH_IRQ_BASE)
152#define EMMA2RH_IRQ_INT39 (39 + EMMA2RH_IRQ_BASE)
153#define EMMA2RH_IRQ_INT40 (40 + EMMA2RH_IRQ_BASE)
154#define EMMA2RH_IRQ_INT41 (41 + EMMA2RH_IRQ_BASE)
155#define EMMA2RH_IRQ_INT42 (42 + EMMA2RH_IRQ_BASE)
156#define EMMA2RH_IRQ_INT43 (43 + EMMA2RH_IRQ_BASE)
157#define EMMA2RH_IRQ_INT44 (44 + EMMA2RH_IRQ_BASE)
158#define EMMA2RH_IRQ_INT45 (45 + EMMA2RH_IRQ_BASE)
159#define EMMA2RH_IRQ_INT46 (46 + EMMA2RH_IRQ_BASE)
160#define EMMA2RH_IRQ_INT47 (47 + EMMA2RH_IRQ_BASE)
161#define EMMA2RH_IRQ_INT48 (48 + EMMA2RH_IRQ_BASE)
162#define EMMA2RH_IRQ_INT49 (49 + EMMA2RH_IRQ_BASE)
163#define EMMA2RH_IRQ_INT50 (50 + EMMA2RH_IRQ_BASE)
164#define EMMA2RH_IRQ_INT51 (51 + EMMA2RH_IRQ_BASE)
165#define EMMA2RH_IRQ_INT52 (52 + EMMA2RH_IRQ_BASE)
166#define EMMA2RH_IRQ_INT53 (53 + EMMA2RH_IRQ_BASE)
167#define EMMA2RH_IRQ_INT54 (54 + EMMA2RH_IRQ_BASE)
168#define EMMA2RH_IRQ_INT55 (55 + EMMA2RH_IRQ_BASE)
169#define EMMA2RH_IRQ_INT56 (56 + EMMA2RH_IRQ_BASE)
170#define EMMA2RH_IRQ_INT57 (57 + EMMA2RH_IRQ_BASE)
171#define EMMA2RH_IRQ_INT58 (58 + EMMA2RH_IRQ_BASE)
172#define EMMA2RH_IRQ_INT59 (59 + EMMA2RH_IRQ_BASE)
173#define EMMA2RH_IRQ_INT60 (60 + EMMA2RH_IRQ_BASE)
174#define EMMA2RH_IRQ_INT61 (61 + EMMA2RH_IRQ_BASE)
175#define EMMA2RH_IRQ_INT62 (62 + EMMA2RH_IRQ_BASE)
176#define EMMA2RH_IRQ_INT63 (63 + EMMA2RH_IRQ_BASE)
177
178#define EMMA2RH_IRQ_PFUR0 EMMA2RH_IRQ_INT49
179#define EMMA2RH_IRQ_PFUR1 EMMA2RH_IRQ_INT50
180#define EMMA2RH_IRQ_PFUR2 EMMA2RH_IRQ_INT51
181#define EMMA2RH_IRQ_PIIC0 EMMA2RH_IRQ_INT56
182#define EMMA2RH_IRQ_PIIC1 EMMA2RH_IRQ_INT57
183#define EMMA2RH_IRQ_PIIC2 EMMA2RH_IRQ_INT58
184
185/*
186 * EMMA2RH Register Access
187 */
188
189#define EMMA2RH_BASE (0xa0000000)
190
191static inline void emma2rh_sync(void)
192{
193 volatile u32 *p = (volatile u32 *)0xbfc00000;
194 (void)(*p);
195}
196
197static inline void emma2rh_out32(u32 offset, u32 val)
198{
199 *(volatile u32 *)(EMMA2RH_BASE | offset) = val;
200 emma2rh_sync();
201}
202
203static inline u32 emma2rh_in32(u32 offset)
204{
205 u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset);
206 emma2rh_sync();
207 return val;
208}
209
210static inline void emma2rh_out16(u32 offset, u16 val)
211{
212 *(volatile u16 *)(EMMA2RH_BASE | offset) = val;
213 emma2rh_sync();
214}
215
216static inline u16 emma2rh_in16(u32 offset)
217{
218 u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset);
219 emma2rh_sync();
220 return val;
221}
222
223static inline void emma2rh_out8(u32 offset, u8 val)
224{
225 *(volatile u8 *)(EMMA2RH_BASE | offset) = val;
226 emma2rh_sync();
227}
228
229static inline u8 emma2rh_in8(u32 offset)
230{
231 u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset);
232 emma2rh_sync();
233 return val;
234}
235
236/**
237 * IIC registers map
238 **/
239
240/*---------------------------------------------------------------------------*/
241/* CNT - Control register (00H R/W) */
242/*---------------------------------------------------------------------------*/
243#define SPT 0x00000001
244#define STT 0x00000002
245#define ACKE 0x00000004
246#define WTIM 0x00000008
247#define SPIE 0x00000010
248#define WREL 0x00000020
249#define LREL 0x00000040
250#define IICE 0x00000080
251#define CNT_RESERVED 0x000000ff /* reserved bit 0 */
252
253#define I2C_EMMA_START (IICE | STT)
254#define I2C_EMMA_STOP (IICE | SPT)
255#define I2C_EMMA_REPSTART I2C_EMMA_START
256
257/*---------------------------------------------------------------------------*/
258/* STA - Status register (10H Read) */
259/*---------------------------------------------------------------------------*/
260#define MSTS 0x00000080
261#define ALD 0x00000040
262#define EXC 0x00000020
263#define COI 0x00000010
264#define TRC 0x00000008
265#define ACKD 0x00000004
266#define STD 0x00000002
267#define SPD 0x00000001
268
269/*---------------------------------------------------------------------------*/
270/* CSEL - Clock select register (20H R/W) */
271/*---------------------------------------------------------------------------*/
272#define FCL 0x00000080
273#define ND50 0x00000040
274#define CLD 0x00000020
275#define DAD 0x00000010
276#define SMC 0x00000008
277#define DFC 0x00000004
278#define CL 0x00000003
279#define CSEL_RESERVED 0x000000ff /* reserved bit 0 */
280
281#define FAST397 0x0000008b
282#define FAST297 0x0000008a
283#define FAST347 0x0000000b
284#define FAST260 0x0000000a
285#define FAST130 0x00000008
286#define STANDARD108 0x00000083
287#define STANDARD83 0x00000082
288#define STANDARD95 0x00000003
289#define STANDARD73 0x00000002
290#define STANDARD36 0x00000001
291#define STANDARD71 0x00000000
292
293/*---------------------------------------------------------------------------*/
294/* SVA - Slave address register (30H R/W) */
295/*---------------------------------------------------------------------------*/
296#define SVA 0x000000fe
297
298/*---------------------------------------------------------------------------*/
299/* SHR - Shift register (40H R/W) */
300/*---------------------------------------------------------------------------*/
301#define SR 0x000000ff
302
303/*---------------------------------------------------------------------------*/
304/* INT - Interrupt register (50H R/W) */
305/* INTM - Interrupt mask register (60H R/W) */
306/*---------------------------------------------------------------------------*/
307#define INTE0 0x00000001
308
309/***********************************************************************
310 * I2C registers
311 ***********************************************************************
312 */
313#define I2C_EMMA_CNT 0x00
314#define I2C_EMMA_STA 0x10
315#define I2C_EMMA_CSEL 0x20
316#define I2C_EMMA_SVA 0x30
317#define I2C_EMMA_SHR 0x40
318#define I2C_EMMA_INT 0x50
319#define I2C_EMMA_INTM 0x60
320
321/*
322 * include the board dependent part
323 */
324#if defined(CONFIG_MARKEINS)
325#include <asm/emma2rh/markeins.h>
326#else
327#error "Unknown EMMA2RH board!"
328#endif
329
330#endif /* __ASM_EMMA2RH_EMMA2RH_H */
diff --git a/include/asm-mips/emma2rh/markeins.h b/include/asm-mips/emma2rh/markeins.h
new file mode 100644
index 00000000000..8fa76679507
--- /dev/null
+++ b/include/asm-mips/emma2rh/markeins.h
@@ -0,0 +1,76 @@
1/*
2 * include/asm-mips/emma2rh/markeins.h
3 * This file is EMMA2RH board depended header.
4 *
5 * Copyright (C) NEC Electronics Corporation 2005-2006
6 *
7 * This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
8 * Copyright 2001 MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25#ifndef MARKEINS_H
26#define MARKEINS_H
27
28#define NUM_EMMA2RH_IRQ_SW 32
29#define NUM_EMMA2RH_IRQ_GPIO 32
30
31#define EMMA2RH_SW_CASCADE (EMMA2RH_IRQ_INT7 - EMMA2RH_IRQ_INT0)
32#define EMMA2RH_GPIO_CASCADE (EMMA2RH_IRQ_INT46 - EMMA2RH_IRQ_INT0)
33
34#define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ)
35#define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW)
36#define CPU_IRQ_BASE (EMMA2RH_GPIO_IRQ_BASE + NUM_EMMA2RH_IRQ_GPIO)
37
38#define EMMA2RH_SW_IRQ_INT0 (0+EMMA2RH_SW_IRQ_BASE)
39#define EMMA2RH_SW_IRQ_INT1 (1+EMMA2RH_SW_IRQ_BASE)
40#define EMMA2RH_SW_IRQ_INT2 (2+EMMA2RH_SW_IRQ_BASE)
41#define EMMA2RH_SW_IRQ_INT3 (3+EMMA2RH_SW_IRQ_BASE)
42#define EMMA2RH_SW_IRQ_INT4 (4+EMMA2RH_SW_IRQ_BASE)
43#define EMMA2RH_SW_IRQ_INT5 (5+EMMA2RH_SW_IRQ_BASE)
44#define EMMA2RH_SW_IRQ_INT6 (6+EMMA2RH_SW_IRQ_BASE)
45#define EMMA2RH_SW_IRQ_INT7 (7+EMMA2RH_SW_IRQ_BASE)
46#define EMMA2RH_SW_IRQ_INT8 (8+EMMA2RH_SW_IRQ_BASE)
47#define EMMA2RH_SW_IRQ_INT9 (9+EMMA2RH_SW_IRQ_BASE)
48#define EMMA2RH_SW_IRQ_INT10 (10+EMMA2RH_SW_IRQ_BASE)
49#define EMMA2RH_SW_IRQ_INT11 (11+EMMA2RH_SW_IRQ_BASE)
50#define EMMA2RH_SW_IRQ_INT12 (12+EMMA2RH_SW_IRQ_BASE)
51#define EMMA2RH_SW_IRQ_INT13 (13+EMMA2RH_SW_IRQ_BASE)
52#define EMMA2RH_SW_IRQ_INT14 (14+EMMA2RH_SW_IRQ_BASE)
53#define EMMA2RH_SW_IRQ_INT15 (15+EMMA2RH_SW_IRQ_BASE)
54#define EMMA2RH_SW_IRQ_INT16 (16+EMMA2RH_SW_IRQ_BASE)
55#define EMMA2RH_SW_IRQ_INT17 (17+EMMA2RH_SW_IRQ_BASE)
56#define EMMA2RH_SW_IRQ_INT18 (18+EMMA2RH_SW_IRQ_BASE)
57#define EMMA2RH_SW_IRQ_INT19 (19+EMMA2RH_SW_IRQ_BASE)
58#define EMMA2RH_SW_IRQ_INT20 (20+EMMA2RH_SW_IRQ_BASE)
59#define EMMA2RH_SW_IRQ_INT21 (21+EMMA2RH_SW_IRQ_BASE)
60#define EMMA2RH_SW_IRQ_INT22 (22+EMMA2RH_SW_IRQ_BASE)
61#define EMMA2RH_SW_IRQ_INT23 (23+EMMA2RH_SW_IRQ_BASE)
62#define EMMA2RH_SW_IRQ_INT24 (24+EMMA2RH_SW_IRQ_BASE)
63#define EMMA2RH_SW_IRQ_INT25 (25+EMMA2RH_SW_IRQ_BASE)
64#define EMMA2RH_SW_IRQ_INT26 (26+EMMA2RH_SW_IRQ_BASE)
65#define EMMA2RH_SW_IRQ_INT27 (27+EMMA2RH_SW_IRQ_BASE)
66#define EMMA2RH_SW_IRQ_INT28 (28+EMMA2RH_SW_IRQ_BASE)
67#define EMMA2RH_SW_IRQ_INT29 (29+EMMA2RH_SW_IRQ_BASE)
68#define EMMA2RH_SW_IRQ_INT30 (30+EMMA2RH_SW_IRQ_BASE)
69#define EMMA2RH_SW_IRQ_INT31 (31+EMMA2RH_SW_IRQ_BASE)
70
71#define MARKEINS_PCI_IRQ_INTA EMMA2RH_GPIO_IRQ_BASE+15
72#define MARKEINS_PCI_IRQ_INTB EMMA2RH_GPIO_IRQ_BASE+16
73#define MARKEINS_PCI_IRQ_INTC EMMA2RH_GPIO_IRQ_BASE+17
74#define MARKEINS_PCI_IRQ_INTD EMMA2RH_GPIO_IRQ_BASE+18
75
76#endif /* CONFIG_MARKEINS */
diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h
index 199e768ff73..58c561a9ec6 100644
--- a/include/asm-mips/fpu.h
+++ b/include/asm-mips/fpu.h
@@ -137,10 +137,9 @@ static inline fpureg_t *get_fpu_regs(struct task_struct *tsk)
137 if (cpu_has_fpu) { 137 if (cpu_has_fpu) {
138 if ((tsk == current) && __is_fpu_owner()) 138 if ((tsk == current) && __is_fpu_owner())
139 _save_fp(current); 139 _save_fp(current);
140 return tsk->thread.fpu.hard.fpr;
141 } 140 }
142 141
143 return tsk->thread.fpu.soft.fpr; 142 return tsk->thread.fpu.fpr;
144} 143}
145 144
146#endif /* _ASM_FPU_H */ 145#endif /* _ASM_FPU_H */
diff --git a/include/asm-mips/fpu_emulator.h b/include/asm-mips/fpu_emulator.h
index 16cb4d11dd0..2731c38bd7a 100644
--- a/include/asm-mips/fpu_emulator.h
+++ b/include/asm-mips/fpu_emulator.h
@@ -12,8 +12,8 @@
12 * with this program; if not, write to the Free Software Foundation, Inc., 12 * with this program; if not, write to the Free Software Foundation, Inc.,
13 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 13 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
14 * 14 *
15 * Further private data for which no space exists in mips_fpu_soft_struct. 15 * Further private data for which no space exists in mips_fpu_struct.
16 * This should be subsumed into the mips_fpu_soft_struct structure as 16 * This should be subsumed into the mips_fpu_struct structure as
17 * defined in processor.h as soon as the absurd wired absolute assembler 17 * defined in processor.h as soon as the absurd wired absolute assembler
18 * offsets become dynamic at compile time. 18 * offsets become dynamic at compile time.
19 * 19 *
diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h
index d71d878990d..ed023eae067 100644
--- a/include/asm-mips/futex.h
+++ b/include/asm-mips/futex.h
@@ -6,6 +6,7 @@
6#include <linux/futex.h> 6#include <linux/futex.h>
7#include <asm/errno.h> 7#include <asm/errno.h>
8#include <asm/uaccess.h> 8#include <asm/uaccess.h>
9#include <asm/war.h>
9 10
10#ifdef CONFIG_SMP 11#ifdef CONFIG_SMP
11#define __FUTEX_SMP_SYNC " sync \n" 12#define __FUTEX_SMP_SYNC " sync \n"
@@ -15,30 +16,60 @@
15 16
16#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ 17#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
17{ \ 18{ \
18 __asm__ __volatile__( \ 19 if (cpu_has_llsc && R10000_LLSC_WAR) { \
19 " .set push \n" \ 20 __asm__ __volatile__( \
20 " .set noat \n" \ 21 " .set push \n" \
21 " .set mips3 \n" \ 22 " .set noat \n" \
22 "1: ll %1, (%3) # __futex_atomic_op1 \n" \ 23 " .set mips3 \n" \
23 " .set mips0 \n" \ 24 "1: ll %1, %4 # __futex_atomic_op \n" \
24 " " insn " \n" \ 25 " .set mips0 \n" \
25 " .set mips3 \n" \ 26 " " insn " \n" \
26 "2: sc $1, (%3) \n" \ 27 " .set mips3 \n" \
27 " beqzl $1, 1b \n" \ 28 "2: sc $1, %2 \n" \
28 __FUTEX_SMP_SYNC \ 29 " beqzl $1, 1b \n" \
29 "3: \n" \ 30 __FUTEX_SMP_SYNC \
30 " .set pop \n" \ 31 "3: \n" \
31 " .set mips0 \n" \ 32 " .set pop \n" \
32 " .section .fixup,\"ax\" \n" \ 33 " .set mips0 \n" \
33 "4: li %0, %5 \n" \ 34 " .section .fixup,\"ax\" \n" \
34 " j 2b \n" \ 35 "4: li %0, %6 \n" \
35 " .previous \n" \ 36 " j 2b \n" \
36 " .section __ex_table,\"a\" \n" \ 37 " .previous \n" \
37 " "__UA_ADDR "\t1b, 4b \n" \ 38 " .section __ex_table,\"a\" \n" \
38 " "__UA_ADDR "\t2b, 4b \n" \ 39 " "__UA_ADDR "\t1b, 4b \n" \
39 " .previous \n" \ 40 " "__UA_ADDR "\t2b, 4b \n" \
40 : "=r" (ret), "=r" (oldval) \ 41 " .previous \n" \
41 : "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT)); \ 42 : "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \
43 : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \
44 : "memory"); \
45 } else if (cpu_has_llsc) { \
46 __asm__ __volatile__( \
47 " .set push \n" \
48 " .set noat \n" \
49 " .set mips3 \n" \
50 "1: ll %1, %4 # __futex_atomic_op \n" \
51 " .set mips0 \n" \
52 " " insn " \n" \
53 " .set mips3 \n" \
54 "2: sc $1, %2 \n" \
55 " beqz $1, 1b \n" \
56 __FUTEX_SMP_SYNC \
57 "3: \n" \
58 " .set pop \n" \
59 " .set mips0 \n" \
60 " .section .fixup,\"ax\" \n" \
61 "4: li %0, %6 \n" \
62 " j 2b \n" \
63 " .previous \n" \
64 " .section __ex_table,\"a\" \n" \
65 " "__UA_ADDR "\t1b, 4b \n" \
66 " "__UA_ADDR "\t2b, 4b \n" \
67 " .previous \n" \
68 : "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \
69 : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \
70 : "memory"); \
71 } else \
72 ret = -ENOSYS; \
42} 73}
43 74
44static inline int 75static inline int
@@ -59,23 +90,23 @@ futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
59 90
60 switch (op) { 91 switch (op) {
61 case FUTEX_OP_SET: 92 case FUTEX_OP_SET:
62 __futex_atomic_op("move $1, %z4", ret, oldval, uaddr, oparg); 93 __futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg);
63 break; 94 break;
64 95
65 case FUTEX_OP_ADD: 96 case FUTEX_OP_ADD:
66 __futex_atomic_op("addu $1, %1, %z4", 97 __futex_atomic_op("addu $1, %1, %z5",
67 ret, oldval, uaddr, oparg); 98 ret, oldval, uaddr, oparg);
68 break; 99 break;
69 case FUTEX_OP_OR: 100 case FUTEX_OP_OR:
70 __futex_atomic_op("or $1, %1, %z4", 101 __futex_atomic_op("or $1, %1, %z5",
71 ret, oldval, uaddr, oparg); 102 ret, oldval, uaddr, oparg);
72 break; 103 break;
73 case FUTEX_OP_ANDN: 104 case FUTEX_OP_ANDN:
74 __futex_atomic_op("and $1, %1, %z4", 105 __futex_atomic_op("and $1, %1, %z5",
75 ret, oldval, uaddr, ~oparg); 106 ret, oldval, uaddr, ~oparg);
76 break; 107 break;
77 case FUTEX_OP_XOR: 108 case FUTEX_OP_XOR:
78 __futex_atomic_op("xor $1, %1, %z4", 109 __futex_atomic_op("xor $1, %1, %z5",
79 ret, oldval, uaddr, oparg); 110 ret, oldval, uaddr, oparg);
80 break; 111 break;
81 default: 112 default:
@@ -101,7 +132,69 @@ futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
101static inline int 132static inline int
102futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) 133futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
103{ 134{
104 return -ENOSYS; 135 int retval;
136
137 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
138 return -EFAULT;
139
140 if (cpu_has_llsc && R10000_LLSC_WAR) {
141 __asm__ __volatile__(
142 "# futex_atomic_cmpxchg_inatomic \n"
143 " .set push \n"
144 " .set noat \n"
145 " .set mips3 \n"
146 "1: ll %0, %2 \n"
147 " bne %0, %z3, 3f \n"
148 " .set mips0 \n"
149 " move $1, %z4 \n"
150 " .set mips3 \n"
151 "2: sc $1, %1 \n"
152 " beqzl $1, 1b \n"
153 __FUTEX_SMP_SYNC
154 "3: \n"
155 " .set pop \n"
156 " .section .fixup,\"ax\" \n"
157 "4: li %0, %5 \n"
158 " j 3b \n"
159 " .previous \n"
160 " .section __ex_table,\"a\" \n"
161 " "__UA_ADDR "\t1b, 4b \n"
162 " "__UA_ADDR "\t2b, 4b \n"
163 " .previous \n"
164 : "=&r" (retval), "=R" (*uaddr)
165 : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
166 : "memory");
167 } else if (cpu_has_llsc) {
168 __asm__ __volatile__(
169 "# futex_atomic_cmpxchg_inatomic \n"
170 " .set push \n"
171 " .set noat \n"
172 " .set mips3 \n"
173 "1: ll %0, %2 \n"
174 " bne %0, %z3, 3f \n"
175 " .set mips0 \n"
176 " move $1, %z4 \n"
177 " .set mips3 \n"
178 "2: sc $1, %1 \n"
179 " beqz $1, 1b \n"
180 __FUTEX_SMP_SYNC
181 "3: \n"
182 " .set pop \n"
183 " .section .fixup,\"ax\" \n"
184 "4: li %0, %5 \n"
185 " j 3b \n"
186 " .previous \n"
187 " .section __ex_table,\"a\" \n"
188 " "__UA_ADDR "\t1b, 4b \n"
189 " "__UA_ADDR "\t2b, 4b \n"
190 " .previous \n"
191 : "=&r" (retval), "=R" (*uaddr)
192 : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
193 : "memory");
194 } else
195 return -ENOSYS;
196
197 return retval;
105} 198}
106 199
107#endif 200#endif
diff --git a/include/asm-mips/inst.h b/include/asm-mips/inst.h
index e0745f4ff62..1ed8d0f6257 100644
--- a/include/asm-mips/inst.h
+++ b/include/asm-mips/inst.h
@@ -6,6 +6,7 @@
6 * for more details. 6 * for more details.
7 * 7 *
8 * Copyright (C) 1996, 2000 by Ralf Baechle 8 * Copyright (C) 1996, 2000 by Ralf Baechle
9 * Copyright (C) 2006 by Thiemo Seufer
9 */ 10 */
10#ifndef _ASM_INST_H 11#ifndef _ASM_INST_H
11#define _ASM_INST_H 12#define _ASM_INST_H
@@ -21,14 +22,14 @@ enum major_op {
21 cop0_op, cop1_op, cop2_op, cop1x_op, 22 cop0_op, cop1_op, cop2_op, cop1x_op,
22 beql_op, bnel_op, blezl_op, bgtzl_op, 23 beql_op, bnel_op, blezl_op, bgtzl_op,
23 daddi_op, daddiu_op, ldl_op, ldr_op, 24 daddi_op, daddiu_op, ldl_op, ldr_op,
24 major_1c_op, jalx_op, major_1e_op, major_1f_op, 25 spec2_op, jalx_op, mdmx_op, spec3_op,
25 lb_op, lh_op, lwl_op, lw_op, 26 lb_op, lh_op, lwl_op, lw_op,
26 lbu_op, lhu_op, lwr_op, lwu_op, 27 lbu_op, lhu_op, lwr_op, lwu_op,
27 sb_op, sh_op, swl_op, sw_op, 28 sb_op, sh_op, swl_op, sw_op,
28 sdl_op, sdr_op, swr_op, cache_op, 29 sdl_op, sdr_op, swr_op, cache_op,
29 ll_op, lwc1_op, lwc2_op, pref_op, 30 ll_op, lwc1_op, lwc2_op, pref_op,
30 lld_op, ldc1_op, ldc2_op, ld_op, 31 lld_op, ldc1_op, ldc2_op, ld_op,
31 sc_op, swc1_op, swc2_op, rdhwr_op, 32 sc_op, swc1_op, swc2_op, major_3b_op,
32 scd_op, sdc1_op, sdc2_op, sd_op 33 scd_op, sdc1_op, sdc2_op, sd_op
33}; 34};
34 35
@@ -37,7 +38,7 @@ enum major_op {
37 */ 38 */
38enum spec_op { 39enum spec_op {
39 sll_op, movc_op, srl_op, sra_op, 40 sll_op, movc_op, srl_op, sra_op,
40 sllv_op, srlv_op, srav_op, spec1_unused_op, /* Opcode 0x07 is unused */ 41 sllv_op, pmon_op, srlv_op, srav_op,
41 jr_op, jalr_op, movz_op, movn_op, 42 jr_op, jalr_op, movz_op, movn_op,
42 syscall_op, break_op, spim_op, sync_op, 43 syscall_op, break_op, spim_op, sync_op,
43 mfhi_op, mthi_op, mflo_op, mtlo_op, 44 mfhi_op, mthi_op, mflo_op, mtlo_op,
@@ -55,6 +56,28 @@ enum spec_op {
55}; 56};
56 57
57/* 58/*
59 * func field of spec2 opcode.
60 */
61enum spec2_op {
62 madd_op, maddu_op, mul_op, spec2_3_unused_op,
63 msub_op, msubu_op, /* more unused ops */
64 clz_op = 0x20, clo_op,
65 dclz_op = 0x24, dclo_op,
66 sdbpp_op = 0x3f
67};
68
69/*
70 * func field of spec3 opcode.
71 */
72enum spec3_op {
73 ext_op, dextm_op, dextu_op, dext_op,
74 ins_op, dinsm_op, dinsu_op, dins_op,
75 bshfl_op = 0x20,
76 dbshfl_op = 0x24,
77 rdhwr_op = 0x3f
78};
79
80/*
58 * rt field of bcond opcodes. 81 * rt field of bcond opcodes.
59 */ 82 */
60enum rt_op { 83enum rt_op {
@@ -151,8 +174,8 @@ enum cop1x_func {
151 * func field for mad opcodes (MIPS IV). 174 * func field for mad opcodes (MIPS IV).
152 */ 175 */
153enum mad_func { 176enum mad_func {
154 madd_op = 0x08, msub_op = 0x0a, 177 madd_fp_op = 0x08, msub_fp_op = 0x0a,
155 nmadd_op = 0x0c, nmsub_op = 0x0e 178 nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e
156}; 179};
157 180
158/* 181/*
diff --git a/include/asm-mips/mach-ddb5074/mc146818rtc.h b/include/asm-mips/mach-ddb5074/mc146818rtc.h
deleted file mode 100644
index 2eb9acb10a5..00000000000
--- a/include/asm-mips/mach-ddb5074/mc146818rtc.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1998, 2001, 03 by Ralf Baechle
7 *
8 * RTC routines for PC style attached Dallas chip.
9 */
10#ifndef __ASM_MACH_DDB5074_MC146818RTC_H
11#define __ASM_MACH_DDB5074_MC146818RTC_H
12
13#include <asm/ddb5xxx/ddb5074.h>
14#include <asm/ddb5xxx/ddb5xxx.h>
15
16#define RTC_PORT(x) (0x70 + (x))
17#define RTC_IRQ 8
18
19static inline unsigned char CMOS_READ(unsigned long addr)
20{
21 return *(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr);
22}
23
24static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
25{
26 *(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr) = data;
27}
28
29#define RTC_ALWAYS_BCD 1
30
31#endif /* __ASM_MACH_DDB5074_MC146818RTC_H */
diff --git a/include/asm-mips/mach-dec/param.h b/include/asm-mips/mach-dec/param.h
deleted file mode 100644
index 3e4f0e39084..00000000000
--- a/include/asm-mips/mach-dec/param.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 by Ralf Baechle
7 */
8#ifndef __ASM_MACH_DEC_PARAM_H
9#define __ASM_MACH_DEC_PARAM_H
10
11/*
12 * log2(HZ), change this here if you want another HZ value. This is also
13 * used in dec_time_init. Minimum is 1, Maximum is 15.
14 */
15#define LOG_2_HZ 7
16#define HZ (1 << LOG_2_HZ)
17
18#endif /* __ASM_MACH_DEC_PARAM_H */
diff --git a/include/asm-mips/mach-mips/param.h b/include/asm-mips/mach-emma2rh/irq.h
index 805ef6d27d3..bce64244b80 100644
--- a/include/asm-mips/mach-mips/param.h
+++ b/include/asm-mips/mach-emma2rh/irq.h
@@ -5,9 +5,9 @@
5 * 5 *
6 * Copyright (C) 2003 by Ralf Baechle 6 * Copyright (C) 2003 by Ralf Baechle
7 */ 7 */
8#ifndef __ASM_MACH_MIPS_PARAM_H 8#ifndef __ASM_MACH_EMMA2RH_IRQ_H
9#define __ASM_MACH_MIPS_PARAM_H 9#define __ASM_MACH_EMMA2RH_IRQ_H
10 10
11#define HZ 100 /* Internal kernel timer frequency */ 11#define NR_IRQS 256
12 12
13#endif /* __ASM_MACH_MIPS_PARAM_H */ 13#endif /* __ASM_MACH_EMMA2RH_IRQ_H */
diff --git a/include/asm-mips/mach-excite/cpu-feature-overrides.h b/include/asm-mips/mach-excite/cpu-feature-overrides.h
new file mode 100644
index 00000000000..abb76b2fd86
--- /dev/null
+++ b/include/asm-mips/mach-excite/cpu-feature-overrides.h
@@ -0,0 +1,40 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com>
7 */
8#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
9#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
10
11/*
12 * Basler eXcite has an RM9122 processor.
13 */
14#define cpu_has_watch 1
15#define cpu_has_mips16 0
16#define cpu_has_divec 0
17#define cpu_has_vce 0
18#define cpu_has_cache_cdex_p 0
19#define cpu_has_cache_cdex_s 0
20#define cpu_has_prefetch 1
21#define cpu_has_mcheck 0
22#define cpu_has_ejtag 0
23
24#define cpu_has_llsc 1
25#define cpu_has_vtag_icache 0
26#define cpu_has_dc_aliases 0
27#define cpu_has_ic_fills_f_dc 0
28#define cpu_has_dsp 0
29#define cpu_icache_snoops_remote_store 0
30
31#define cpu_has_nofpuex 0
32#define cpu_has_64bits 1
33
34#define cpu_has_subset_pcaches 0
35
36#define cpu_dcache_line_size() 32
37#define cpu_icache_line_size() 32
38#define cpu_scache_line_size() 32
39
40#endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-excite/excite.h b/include/asm-mips/mach-excite/excite.h
new file mode 100644
index 00000000000..c52610de2b3
--- /dev/null
+++ b/include/asm-mips/mach-excite/excite.h
@@ -0,0 +1,155 @@
1#ifndef __EXCITE_H__
2#define __EXCITE_H__
3
4#include <linux/config.h>
5#include <linux/init.h>
6#include <asm/addrspace.h>
7#include <asm/types.h>
8
9#define EXCITE_CPU_EXT_CLOCK 100000000
10
11#if !defined(__ASSEMBLER__)
12void __init excite_kgdb_init(void);
13void excite_procfs_init(void);
14extern unsigned long memsize;
15extern char modetty[];
16extern u32 unit_id;
17#endif
18
19/* Base name for XICAP devices */
20#define XICAP_NAME "xicap_gpi"
21
22/* OCD register offsets */
23#define LKB0 0x0038
24#define LKB5 0x0128
25#define LKM5 0x012C
26#define LKB7 0x0138
27#define LKM7 0x013c
28#define LKB8 0x0140
29#define LKM8 0x0144
30#define LKB9 0x0148
31#define LKM9 0x014c
32#define LKB10 0x0150
33#define LKM10 0x0154
34#define LKB11 0x0158
35#define LKM11 0x015c
36#define LKB12 0x0160
37#define LKM12 0x0164
38#define LKB13 0x0168
39#define LKM13 0x016c
40#define LDP0 0x0200
41#define LDP1 0x0210
42#define LDP2 0x0220
43#define LDP3 0x0230
44#define INTPIN0 0x0A40
45#define INTPIN1 0x0A44
46#define INTPIN2 0x0A48
47#define INTPIN3 0x0A4C
48#define INTPIN4 0x0A50
49#define INTPIN5 0x0A54
50#define INTPIN6 0x0A58
51#define INTPIN7 0x0A5C
52
53
54
55
56/* TITAN register offsets */
57#define CPRR 0x0004
58#define CPDSR 0x0008
59#define CPTC0R 0x000c
60#define CPTC1R 0x0010
61#define CPCFG0 0x0020
62#define CPCFG1 0x0024
63#define CPDST0A 0x0028
64#define CPDST0B 0x002c
65#define CPDST1A 0x0030
66#define CPDST1B 0x0034
67#define CPXDSTA 0x0038
68#define CPXDSTB 0x003c
69#define CPXCISRA 0x0048
70#define CPXCISRB 0x004c
71#define CPGIG0ER 0x0050
72#define CPGIG1ER 0x0054
73#define CPGRWL 0x0068
74#define CPURSLMT 0x00f8
75#define UACFG 0x0200
76#define UAINTS 0x0204
77#define SDRXFCIE 0x4828
78#define SDTXFCIE 0x4928
79#define INTP0Status0 0x1B00
80#define INTP0Mask0 0x1B04
81#define INTP0Set0 0x1B08
82#define INTP0Clear0 0x1B0C
83#define GXCFG 0x5000
84#define GXDMADRPFX 0x5018
85#define GXDMA_DESCADR 0x501c
86#define GXCH0TDESSTRT 0x5054
87
88/* IRQ definitions */
89#define NMICONFIG 0xac0
90#define TITAN_MSGINT 0xc4
91#define TITAN_IRQ ((TITAN_MSGINT / 0x20) + 2)
92#define FPGA0_MSGINT 0x5a
93#define FPGA0_IRQ ((FPGA0_MSGINT / 0x20) + 2)
94#define FPGA1_MSGINT 0x7b
95#define FPGA1_IRQ ((FPGA1_MSGINT / 0x20) + 2)
96#define PHY_MSGINT 0x9c
97#define PHY_IRQ ((PHY_MSGINT / 0x20) + 2)
98
99#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE)
100/* Pre-release units used interrupt pin #9 */
101#define USB_IRQ 11
102#else
103/* Re-designed units use interrupt pin #1 */
104#define USB_MSGINT 0x39
105#define USB_IRQ ((USB_MSGINT / 0x20) + 2)
106#endif
107#define TIMER_IRQ 12
108
109
110/* Device address ranges */
111#define EXCITE_OFFS_OCD 0x1fffc000
112#define EXCITE_SIZE_OCD (16 * 1024)
113#define EXCITE_PHYS_OCD CPHYSADDR(EXCITE_OFFS_OCD)
114#define EXCITE_ADDR_OCD CKSEG1ADDR(EXCITE_OFFS_OCD)
115
116#define EXCITE_OFFS_SCRAM 0x1fffa000
117#define EXCITE_SIZE_SCRAM (8 << 10)
118#define EXCITE_PHYS_SCRAM CPHYSADDR(EXCITE_OFFS_SCRAM)
119#define EXCITE_ADDR_SCRAM CKSEG1ADDR(EXCITE_OFFS_SCRAM)
120
121#define EXCITE_OFFS_PCI_IO 0x1fff8000
122#define EXCITE_SIZE_PCI_IO (8 << 10)
123#define EXCITE_PHYS_PCI_IO CPHYSADDR(EXCITE_OFFS_PCI_IO)
124#define EXCITE_ADDR_PCI_IO CKSEG1ADDR(EXCITE_OFFS_PCI_IO)
125
126#define EXCITE_OFFS_TITAN 0x1fff0000
127#define EXCITE_SIZE_TITAN (32 << 10)
128#define EXCITE_PHYS_TITAN CPHYSADDR(EXCITE_OFFS_TITAN)
129#define EXCITE_ADDR_TITAN CKSEG1ADDR(EXCITE_OFFS_TITAN)
130
131#define EXCITE_OFFS_PCI_MEM 0x1ffe0000
132#define EXCITE_SIZE_PCI_MEM (64 << 10)
133#define EXCITE_PHYS_PCI_MEM CPHYSADDR(EXCITE_OFFS_PCI_MEM)
134#define EXCITE_ADDR_PCI_MEM CKSEG1ADDR(EXCITE_OFFS_PCI_MEM)
135
136#define EXCITE_OFFS_FPGA 0x1ffdc000
137#define EXCITE_SIZE_FPGA (16 << 10)
138#define EXCITE_PHYS_FPGA CPHYSADDR(EXCITE_OFFS_FPGA)
139#define EXCITE_ADDR_FPGA CKSEG1ADDR(EXCITE_OFFS_FPGA)
140
141#define EXCITE_OFFS_NAND 0x1ffd8000
142#define EXCITE_SIZE_NAND (16 << 10)
143#define EXCITE_PHYS_NAND CPHYSADDR(EXCITE_OFFS_NAND)
144#define EXCITE_ADDR_NAND CKSEG1ADDR(EXCITE_OFFS_NAND)
145
146#define EXCITE_OFFS_BOOTROM 0x1f000000
147#define EXCITE_SIZE_BOOTROM (8 << 20)
148#define EXCITE_PHYS_BOOTROM CPHYSADDR(EXCITE_OFFS_BOOTROM)
149#define EXCITE_ADDR_BOOTROM CKSEG1ADDR(EXCITE_OFFS_BOOTROM)
150
151/* FPGA address offsets */
152#define EXCITE_FPGA_DPR 0x0104 /* dual-ported ram */
153#define EXCITE_FPGA_SYSCTL 0x0200 /* system control register block */
154
155#endif /* __EXCITE_H__ */
diff --git a/include/asm-mips/mach-excite/excite_nandflash.h b/include/asm-mips/mach-excite/excite_nandflash.h
new file mode 100644
index 00000000000..c4cf6140622
--- /dev/null
+++ b/include/asm-mips/mach-excite/excite_nandflash.h
@@ -0,0 +1,7 @@
1#ifndef __EXCITE_NANDFLASH_H__
2#define __EXCITE_NANDFLASH_H__
3
4/* Resource names */
5#define EXCITE_NANDFLASH_RESOURCE_REGS "excite_nandflash_regs"
6
7#endif /* __EXCITE_NANDFLASH_H__ */
diff --git a/include/asm-mips/mach-excite/rm9k_eth.h b/include/asm-mips/mach-excite/rm9k_eth.h
new file mode 100644
index 00000000000..94705a46f72
--- /dev/null
+++ b/include/asm-mips/mach-excite/rm9k_eth.h
@@ -0,0 +1,23 @@
1#if !defined(__RM9K_ETH_H__)
2#define __RM9K_ETH_H__
3
4#define RM9K_GE_NAME "rm9k_ge"
5
6/* Resource names */
7#define RM9K_GE_RESOURCE_MAC "rm9k_ge_mac"
8#define RM9K_GE_RESOURCE_MSTAT "rm9k_ge_mstat"
9#define RM9K_GE_RESOURCE_PKTPROC "rm9k_ge_pktproc"
10#define RM9K_GE_RESOURCE_XDMA "rm9k_ge_xdma"
11#define RM9K_GE_RESOURCE_FIFO_RX "rm9k_ge_fifo_rx"
12#define RM9K_GE_RESOURCE_FIFO_TX "rm9k_ge_fifo_tx"
13#define RM9K_GE_RESOURCE_FIFOMEM_RX "rm9k_ge_fifo_memory_rx"
14#define RM9K_GE_RESOURCE_FIFOMEM_TX "rm9k_ge_fifo_memory_tx"
15#define RM9K_GE_RESOURCE_PHY "rm9k_ge_phy"
16#define RM9K_GE_RESOURCE_DMADESC_RX "rm9k_ge_dmadesc_rx"
17#define RM9K_GE_RESOURCE_DMADESC_TX "rm9k_ge_dmadesc_tx"
18#define RM9K_GE_RESOURCE_IRQ_MAIN "rm9k_ge_irq_main"
19#define RM9K_GE_RESOURCE_IRQ_PHY "rm9k_ge_irq_phy"
20#define RM9K_GE_RESOURCE_GPI_SLICE "rm9k_ge_gpi_slice"
21#define RM9K_GE_RESOURCE_MDIO_CHANNEL "rm9k_ge_mdio_channel"
22
23#endif /* !defined(__RM9K_ETH_H__) */
diff --git a/include/asm-mips/mach-excite/rm9k_wdt.h b/include/asm-mips/mach-excite/rm9k_wdt.h
new file mode 100644
index 00000000000..3fa3c08d2da
--- /dev/null
+++ b/include/asm-mips/mach-excite/rm9k_wdt.h
@@ -0,0 +1,12 @@
1#ifndef __RM9K_WDT_H__
2#define __RM9K_WDT_H__
3
4/* Device name */
5#define WDT_NAME "wdt_gpi"
6
7/* Resource names */
8#define WDT_RESOURCE_REGS "excite_watchdog_regs"
9#define WDT_RESOURCE_IRQ "excite_watchdog_irq"
10#define WDT_RESOURCE_COUNTER "excite_watchdog_counter"
11
12#endif /* __RM9K_WDT_H__ */
diff --git a/include/asm-mips/mach-excite/rm9k_xicap.h b/include/asm-mips/mach-excite/rm9k_xicap.h
new file mode 100644
index 00000000000..009577734a8
--- /dev/null
+++ b/include/asm-mips/mach-excite/rm9k_xicap.h
@@ -0,0 +1,16 @@
1#ifndef __EXCITE_XICAP_H__
2#define __EXCITE_XICAP_H__
3
4
5/* Resource names */
6#define XICAP_RESOURCE_FIFO_RX "xicap_fifo_rx"
7#define XICAP_RESOURCE_FIFO_TX "xicap_fifo_tx"
8#define XICAP_RESOURCE_XDMA "xicap_xdma"
9#define XICAP_RESOURCE_DMADESC "xicap_dmadesc"
10#define XICAP_RESOURCE_PKTPROC "xicap_pktproc"
11#define XICAP_RESOURCE_IRQ "xicap_irq"
12#define XICAP_RESOURCE_GPI_SLICE "xicap_gpi_slice"
13#define XICAP_RESOURCE_FIFO_BLK "xicap_fifo_blocks"
14#define XICAP_RESOURCE_PKT_STREAM "xicap_pkt_stream"
15
16#endif /* __EXCITE_XICAP_H__ */
diff --git a/include/asm-mips/mach-generic/param.h b/include/asm-mips/mach-generic/param.h
deleted file mode 100644
index a0d12f964e4..00000000000
--- a/include/asm-mips/mach-generic/param.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 by Ralf Baechle
7 */
8#ifndef __ASM_MACH_GENERIC_PARAM_H
9#define __ASM_MACH_GENERIC_PARAM_H
10
11#define HZ 1000 /* Internal kernel timer frequency */
12
13#endif /* __ASM_MACH_GENERIC_PARAM_H */
diff --git a/include/asm-mips/mach-ip22/cpu-feature-overrides.h b/include/asm-mips/mach-ip22/cpu-feature-overrides.h
index 2a37bedb405..f7c5dc8a533 100644
--- a/include/asm-mips/mach-ip22/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ip22/cpu-feature-overrides.h
@@ -13,7 +13,7 @@
13 */ 13 */
14#define cpu_has_tlb 1 14#define cpu_has_tlb 1
15#define cpu_has_4kex 1 15#define cpu_has_4kex 1
16#define cpu_has_4kcache 1 16#define cpu_has_4k_cache 1
17#define cpu_has_fpu 1 17#define cpu_has_fpu 1
18#define cpu_has_32fpr 1 18#define cpu_has_32fpr 1
19#define cpu_has_counter 1 19#define cpu_has_counter 1
diff --git a/include/asm-mips/mach-ip27/cpu-feature-overrides.h b/include/asm-mips/mach-ip27/cpu-feature-overrides.h
index 2d2f5b91e47..19c2d135985 100644
--- a/include/asm-mips/mach-ip27/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ip27/cpu-feature-overrides.h
@@ -31,6 +31,9 @@
31#define cpu_has_nofpuex 0 31#define cpu_has_nofpuex 0
32#define cpu_has_64bits 1 32#define cpu_has_64bits 1
33 33
34#define cpu_has_4kex 1
35#define cpu_has_4k_cache 1
36
34#define cpu_has_subset_pcaches 1 37#define cpu_has_subset_pcaches 1
35 38
36#define cpu_dcache_line_size() 32 39#define cpu_dcache_line_size() 32
diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/include/asm-mips/mach-ip32/cpu-feature-overrides.h
index 5312a11098d..2a3de092bf1 100644
--- a/include/asm-mips/mach-ip32/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ip32/cpu-feature-overrides.h
@@ -37,6 +37,8 @@
37#define cpu_has_vtag_icache 0 37#define cpu_has_vtag_icache 0
38#define cpu_has_ic_fills_f_dc 0 38#define cpu_has_ic_fills_f_dc 0
39#define cpu_has_dsp 0 39#define cpu_has_dsp 0
40#define cpu_has_4k_cache 1
41
40 42
41#define cpu_has_mips32r1 0 43#define cpu_has_mips32r1 0
42#define cpu_has_mips32r2 0 44#define cpu_has_mips32r2 0
diff --git a/include/asm-mips/mach-jazz/param.h b/include/asm-mips/mach-jazz/param.h
deleted file mode 100644
index 639763a517b..00000000000
--- a/include/asm-mips/mach-jazz/param.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003 by Ralf Baechle
7 */
8#ifndef __ASM_MACH_JAZZ_PARAM_H
9#define __ASM_MACH_JAZZ_PARAM_H
10
11/*
12 * Jazz is currently using the internal 100Hz timer of the R4030
13 */
14#define HZ 100 /* Internal kernel timer frequency */
15
16#endif /* __ASM_MACH_JAZZ_PARAM_H */
diff --git a/include/asm-mips/mach-mips/cpu-feature-overrides.h b/include/asm-mips/mach-mips/cpu-feature-overrides.h
index 7efbff50fcd..e960679f54b 100644
--- a/include/asm-mips/mach-mips/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-mips/cpu-feature-overrides.h
@@ -16,7 +16,7 @@
16#ifdef CONFIG_CPU_MIPS32 16#ifdef CONFIG_CPU_MIPS32
17#define cpu_has_tlb 1 17#define cpu_has_tlb 1
18#define cpu_has_4kex 1 18#define cpu_has_4kex 1
19#define cpu_has_4kcache 1 19#define cpu_has_4k_cache 1
20/* #define cpu_has_fpu ? */ 20/* #define cpu_has_fpu ? */
21/* #define cpu_has_32fpr ? */ 21/* #define cpu_has_32fpr ? */
22#define cpu_has_counter 1 22#define cpu_has_counter 1
@@ -46,7 +46,7 @@
46#ifdef CONFIG_CPU_MIPS64 46#ifdef CONFIG_CPU_MIPS64
47#define cpu_has_tlb 1 47#define cpu_has_tlb 1
48#define cpu_has_4kex 1 48#define cpu_has_4kex 1
49#define cpu_has_4kcache 1 49#define cpu_has_4k_cache 1
50/* #define cpu_has_fpu ? */ 50/* #define cpu_has_fpu ? */
51/* #define cpu_has_32fpr ? */ 51/* #define cpu_has_32fpr ? */
52#define cpu_has_counter 1 52#define cpu_has_counter 1
diff --git a/include/asm-mips/mach-qemu/param.h b/include/asm-mips/mach-qemu/param.h
deleted file mode 100644
index cb30ee490ae..00000000000
--- a/include/asm-mips/mach-qemu/param.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005 by Ralf Baechle
7 */
8#ifndef __ASM_MACH_QEMU_PARAM_H
9#define __ASM_MACH_QEMU_PARAM_H
10
11#define HZ 100 /* Internal kernel timer frequency */
12
13#endif /* __ASM_MACH_QEMU_PARAM_H */
diff --git a/include/asm-mips/mach-rm200/cpu-feature-overrides.h b/include/asm-mips/mach-rm200/cpu-feature-overrides.h
index 91e7cf5f2bf..11410ae10d3 100644
--- a/include/asm-mips/mach-rm200/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-rm200/cpu-feature-overrides.h
@@ -14,7 +14,7 @@
14 14
15#define cpu_has_tlb 1 15#define cpu_has_tlb 1
16#define cpu_has_4kex 1 16#define cpu_has_4kex 1
17#define cpu_has_4kcache 1 17#define cpu_has_4k_cache 1
18#define cpu_has_fpu 1 18#define cpu_has_fpu 1
19#define cpu_has_32fpr 1 19#define cpu_has_32fpr 1
20#define cpu_has_counter 1 20#define cpu_has_counter 1
@@ -35,10 +35,8 @@
35#define cpu_has_nofpuex 0 35#define cpu_has_nofpuex 0
36#define cpu_has_64bits 1 36#define cpu_has_64bits 1
37 37
38#define cpu_has_subset_pcaches 0 /* No S-cache on R5000 I think ... */
39#define cpu_dcache_line_size() 32 38#define cpu_dcache_line_size() 32
40#define cpu_icache_line_size() 32 39#define cpu_icache_line_size() 32
41#define cpu_scache_line_size() 0 /* No S-cache on R5000 I think ... */
42 40
43#define cpu_has_mips32r1 0 41#define cpu_has_mips32r1 0
44#define cpu_has_mips32r2 0 42#define cpu_has_mips32r2 0
diff --git a/include/asm-mips/mach-sim/cpu-feature-overrides.h b/include/asm-mips/mach-sim/cpu-feature-overrides.h
index f86f2751bc0..d736bdadb6d 100644
--- a/include/asm-mips/mach-sim/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-sim/cpu-feature-overrides.h
@@ -15,7 +15,7 @@
15#ifdef CONFIG_CPU_MIPS32 15#ifdef CONFIG_CPU_MIPS32
16#define cpu_has_tlb 1 16#define cpu_has_tlb 1
17#define cpu_has_4kex 1 17#define cpu_has_4kex 1
18#define cpu_has_4kcache 1 18#define cpu_has_4k_cache 1
19#define cpu_has_fpu 0 19#define cpu_has_fpu 0
20/* #define cpu_has_32fpr ? */ 20/* #define cpu_has_32fpr ? */
21#define cpu_has_counter 1 21#define cpu_has_counter 1
@@ -40,7 +40,7 @@
40#ifdef CONFIG_CPU_MIPS64 40#ifdef CONFIG_CPU_MIPS64
41#define cpu_has_tlb 1 41#define cpu_has_tlb 1
42#define cpu_has_4kex 1 42#define cpu_has_4kex 1
43#define cpu_has_4kcache 1 43#define cpu_has_4k_cache 1
44/* #define cpu_has_fpu ? */ 44/* #define cpu_has_fpu ? */
45/* #define cpu_has_32fpr ? */ 45/* #define cpu_has_32fpr ? */
46#define cpu_has_counter 1 46#define cpu_has_counter 1
diff --git a/include/asm-mips/mach-wrppmc/mach-gt64120.h b/include/asm-mips/mach-wrppmc/mach-gt64120.h
new file mode 100644
index 00000000000..ba9205a0458
--- /dev/null
+++ b/include/asm-mips/mach-wrppmc/mach-gt64120.h
@@ -0,0 +1,84 @@
1/*
2 * This is a direct copy of the ev96100.h file, with a global
3 * search and replace. The numbers are the same.
4 *
5 * The reason I'm duplicating this is so that the 64120/96100
6 * defines won't be confusing in the source code.
7 */
8#ifndef __ASM_MIPS_GT64120_H
9#define __ASM_MIPS_GT64120_H
10
11/*
12 * This is the CPU physical memory map of PPMC Board:
13 *
14 * 0x00000000-0x03FFFFFF - 64MB SDRAM (SCS[0]#)
15 * 0x1C000000-0x1C000000 - LED (CS0)
16 * 0x1C800000-0x1C800007 - UART 16550 port (CS1)
17 * 0x1F000000-0x1F000000 - MailBox (CS3)
18 * 0x1FC00000-0x20000000 - 4MB Flash (BOOT CS)
19 */
20
21#define WRPPMC_SDRAM_SCS0_BASE 0x00000000
22#define WRPPMC_SDRAM_SCS0_SIZE 0x04000000
23
24#define WRPPMC_UART16550_BASE 0x1C800000
25#define WRPPMC_UART16550_CLOCK 3686400 /* 3.68MHZ */
26
27#define WRPPMC_LED_BASE 0x1C000000
28#define WRPPMC_MBOX_BASE 0x1F000000
29
30#define WRPPMC_BOOTROM_BASE 0x1FC00000
31#define WRPPMC_BOOTROM_SIZE 0x00400000 /* 4M Flash */
32
33#define WRPPMC_MIPS_TIMER_IRQ 7 /* MIPS compare/count timer interrupt */
34#define WRPPMC_UART16550_IRQ 6
35#define WRPPMC_PCI_INTA_IRQ 3
36
37/*
38 * PCI Bus I/O and Memory resources allocation
39 *
40 * NOTE: We only have PCI_0 hose interface
41 */
42#define GT_PCI_MEM_BASE 0x13000000UL
43#define GT_PCI_MEM_SIZE 0x02000000UL
44#define GT_PCI_IO_BASE 0x11000000UL
45#define GT_PCI_IO_SIZE 0x02000000UL
46#define GT_ISA_IO_BASE PCI_IO_BASE
47
48/*
49 * PCI interrupts will come in on either the INTA or INTD interrups lines,
50 * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our
51 * boards, they all either come in on IntD or they all come in on IntA, they
52 * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
53 * "requested" interrupt numbers and go through the list whenever we get an
54 * IntA/D.
55 *
56 * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and
57 * INTD is 11.
58 */
59#define GT_TIMER 4
60#define GT_INTA 2
61#define GT_INTD 5
62
63#ifndef __ASSEMBLY__
64
65/*
66 * GT64120 internal register space base address
67 */
68extern unsigned long gt64120_base;
69
70#define GT64120_BASE (gt64120_base)
71
72/* define WRPPMC_EARLY_DEBUG to enable early output something to UART */
73#undef WRPPMC_EARLY_DEBUG
74
75#ifdef WRPPMC_EARLY_DEBUG
76extern void wrppmc_led_on(int mask);
77extern void wrppmc_led_off(int mask);
78extern void wrppmc_early_printk(const char *fmt, ...);
79#else
80#define wrppmc_early_printk(fmt, ...) do {} while (0)
81#endif /* WRPPMC_EARLY_DEBUG */
82
83#endif /* __ASSEMBLY__ */
84#endif /* __ASM_MIPS_GT64120_H */
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 87e95b5e27d..673977901ed 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -290,7 +290,7 @@
290#define ST0_DL (_ULCAST_(1) << 24) 290#define ST0_DL (_ULCAST_(1) << 24)
291 291
292/* 292/*
293 * Enable the MIPS DSP ASE 293 * Enable the MIPS MDMX and DSP ASEs
294 */ 294 */
295#define ST0_MX 0x01000000 295#define ST0_MX 0x01000000
296 296
@@ -1450,12 +1450,10 @@ static inline void __emt(unsigned int previous)
1450{ 1450{
1451 if ((previous & __EMT_ENABLE)) 1451 if ((previous & __EMT_ENABLE))
1452 __asm__ __volatile__( 1452 __asm__ __volatile__(
1453 " .set noreorder \n"
1454 " .set mips32r2 \n" 1453 " .set mips32r2 \n"
1455 " .word 0x41600be1 # emt \n" 1454 " .word 0x41600be1 # emt \n"
1456 " ehb \n" 1455 " ehb \n"
1457 " .set mips0 \n" 1456 " .set mips0 \n");
1458 " .set reorder \n");
1459} 1457}
1460 1458
1461static inline void __ehb(void) 1459static inline void __ehb(void)
diff --git a/include/asm-mips/mmzone.h b/include/asm-mips/mmzone.h
index e132975256b..dc231c89bef 100644
--- a/include/asm-mips/mmzone.h
+++ b/include/asm-mips/mmzone.h
@@ -13,17 +13,6 @@
13#define kvaddr_to_nid(kvaddr) pa_to_nid(__pa(kvaddr)) 13#define kvaddr_to_nid(kvaddr) pa_to_nid(__pa(kvaddr))
14#define pfn_to_nid(pfn) pa_to_nid((pfn) << PAGE_SHIFT) 14#define pfn_to_nid(pfn) pa_to_nid((pfn) << PAGE_SHIFT)
15 15
16#define pfn_valid(pfn) \
17({ \
18 unsigned long __pfn = (pfn); \
19 int __n = pfn_to_nid(__pfn); \
20 ((__n >= 0) ? (__pfn < NODE_DATA(__n)->node_start_pfn + \
21 NODE_DATA(__n)->node_spanned_pages) : 0);\
22})
23
24/* XXX: FIXME -- wli */
25#define kern_addr_valid(addr) (0)
26
27#endif /* CONFIG_DISCONTIGMEM */ 16#endif /* CONFIG_DISCONTIGMEM */
28 17
29#endif /* _ASM_MMZONE_H_ */ 18#endif /* _ASM_MMZONE_H_ */
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index f2b3314fcab..6b97744f00c 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -138,9 +138,30 @@ typedef struct { unsigned long pgprot; } pgprot_t;
138 138
139#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) 139#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
140 140
141#ifndef CONFIG_SPARSEMEM
141#ifndef CONFIG_NEED_MULTIPLE_NODES 142#ifndef CONFIG_NEED_MULTIPLE_NODES
142#define pfn_valid(pfn) ((pfn) < max_mapnr) 143#define pfn_valid(pfn) ((pfn) < max_mapnr)
143#endif 144#endif
145#endif
146
147#ifdef CONFIG_FLATMEM
148
149#define pfn_valid(pfn) ((pfn) < max_mapnr)
150
151#elif defined(CONFIG_NEED_MULTIPLE_NODES)
152
153#define pfn_valid(pfn) \
154({ \
155 unsigned long __pfn = (pfn); \
156 int __n = pfn_to_nid(__pfn); \
157 ((__n >= 0) ? (__pfn < NODE_DATA(__n)->node_start_pfn + \
158 NODE_DATA(__n)->node_spanned_pages) \
159 : 0); \
160})
161
162#else
163#error Provide a definition of pfn_valid
164#endif
144 165
145#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) 166#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
146#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) 167#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
diff --git a/include/asm-mips/param.h b/include/asm-mips/param.h
index 2bead8273ce..1d9bb8c5ab2 100644
--- a/include/asm-mips/param.h
+++ b/include/asm-mips/param.h
@@ -11,7 +11,7 @@
11 11
12#ifdef __KERNEL__ 12#ifdef __KERNEL__
13 13
14# include <param.h> /* Internal kernel timer frequency */ 14# define HZ CONFIG_HZ /* Internal kernel timer frequency */
15# define USER_HZ 100 /* .. some user interfaces are in "ticks" */ 15# define USER_HZ 100 /* .. some user interfaces are in "ticks" */
16# define CLOCKS_PER_SEC (USER_HZ) /* like times() */ 16# define CLOCKS_PER_SEC (USER_HZ) /* like times() */
17#endif 17#endif
diff --git a/include/asm-mips/pci/bridge.h b/include/asm-mips/pci/bridge.h
index b4ee995c56e..0c45e7598f3 100644
--- a/include/asm-mips/pci/bridge.h
+++ b/include/asm-mips/pci/bridge.h
@@ -15,6 +15,7 @@
15#include <linux/types.h> 15#include <linux/types.h>
16#include <linux/pci.h> 16#include <linux/pci.h>
17#include <asm/xtalk/xwidget.h> /* generic widget header */ 17#include <asm/xtalk/xwidget.h> /* generic widget header */
18#include <asm/sn/types.h>
18 19
19/* I/O page size */ 20/* I/O page size */
20 21
@@ -848,4 +849,6 @@ struct bridge_controller {
848extern void register_bridge_irq(unsigned int irq); 849extern void register_bridge_irq(unsigned int irq);
849extern int request_bridge_irq(struct bridge_controller *bc); 850extern int request_bridge_irq(struct bridge_controller *bc);
850 851
852extern struct pci_ops bridge_pci_ops;
853
851#endif /* _ASM_PCI_BRIDGE_H */ 854#endif /* _ASM_PCI_BRIDGE_H */
diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index e1c0e88f03f..4b26d852813 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -176,48 +176,67 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
176 ((swp_entry_t) { ((type) << 10) | ((offset) << 15) }) 176 ((swp_entry_t) { ((type) << 10) | ((offset) << 15) })
177 177
178/* 178/*
179 * Bits 0, 1, 2, 9 and 10 are taken, split up the 27 bits of offset 179 * Bits 0, 4, 8, and 9 are taken, split up 28 bits of offset into this range:
180 * into this range:
181 */ 180 */
182#define PTE_FILE_MAX_BITS 27 181#define PTE_FILE_MAX_BITS 28
183 182
184#define pte_to_pgoff(_pte) \ 183#define pte_to_pgoff(_pte) ((((_pte).pte >> 1 ) & 0x07) | \
185 ((((_pte).pte >> 3) & 0x3f ) + (((_pte).pte >> 11) << 8 )) 184 (((_pte).pte >> 2 ) & 0x38) | \
185 (((_pte).pte >> 10) << 6 ))
186 186
187#define pgoff_to_pte(off) \ 187#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x07) << 1 ) | \
188 ((pte_t) { (((off) & 0x3f) << 3) + (((off) >> 8) << 11) + _PAGE_FILE }) 188 (((off) & 0x38) << 2 ) | \
189 (((off) >> 6 ) << 10) | \
190 _PAGE_FILE })
189 191
190#else 192#else
191 193
192/* Swap entries must have VALID and GLOBAL bits cleared. */ 194/* Swap entries must have VALID and GLOBAL bits cleared. */
195#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
196#define __swp_type(x) (((x).val >> 2) & 0x1f)
197#define __swp_offset(x) ((x).val >> 7)
198#define __swp_entry(type,offset) \
199 ((swp_entry_t) { ((type) << 2) | ((offset) << 7) })
200#else
193#define __swp_type(x) (((x).val >> 8) & 0x1f) 201#define __swp_type(x) (((x).val >> 8) & 0x1f)
194#define __swp_offset(x) ((x).val >> 13) 202#define __swp_offset(x) ((x).val >> 13)
195#define __swp_entry(type,offset) \ 203#define __swp_entry(type,offset) \
196 ((swp_entry_t) { ((type) << 8) | ((offset) << 13) }) 204 ((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
205#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
197 206
207#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
198/* 208/*
199 * Bits 0, 1, 2, 7 and 8 are taken, split up the 27 bits of offset 209 * Bits 0 and 1 of pte_high are taken, use the rest for the page offset...
200 * into this range:
201 */ 210 */
202#define PTE_FILE_MAX_BITS 27 211#define PTE_FILE_MAX_BITS 30
203 212
204#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 213#define pte_to_pgoff(_pte) ((_pte).pte_high >> 2)
205 /* fixme */ 214#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) << 2 })
206#define pte_to_pgoff(_pte) (((_pte).pte_high >> 6) + ((_pte).pte_high & 0x3f))
207#define pgoff_to_pte(off) \
208 ((pte_t){(((off) & 0x3f) + ((off) << 6) + _PAGE_FILE)})
209 215
210#else 216#else
211#define pte_to_pgoff(_pte) \ 217/*
212 ((((_pte).pte >> 3) & 0x1f ) + (((_pte).pte >> 9) << 6 )) 218 * Bits 0, 4, 6, and 7 are taken, split up 28 bits of offset into this range:
219 */
220#define PTE_FILE_MAX_BITS 28
221
222#define pte_to_pgoff(_pte) ((((_pte).pte >> 1) & 0x7) | \
223 (((_pte).pte >> 2) & 0x8) | \
224 (((_pte).pte >> 8) << 4))
213 225
214#define pgoff_to_pte(off) \ 226#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x7) << 1) | \
215 ((pte_t) { (((off) & 0x1f) << 3) + (((off) >> 6) << 9) + _PAGE_FILE }) 227 (((off) & 0x8) << 2) | \
228 (((off) >> 4) << 8) | \
229 _PAGE_FILE })
216#endif 230#endif
217 231
218#endif 232#endif
219 233
234#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
235#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
236#define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
237#else
220#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 238#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
221#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 239#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
240#endif
222 241
223#endif /* _ASM_PGTABLE_32_H */ 242#endif /* _ASM_PGTABLE_32_H */
diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h
index 0ae30d56d01..e3db93212ea 100644
--- a/include/asm-mips/pgtable-64.h
+++ b/include/asm-mips/pgtable-64.h
@@ -223,15 +223,12 @@ static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
223#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 223#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
224 224
225/* 225/*
226 * Bits 0, 1, 2, 7 and 8 are taken, split up the 32 bits of offset 226 * Bits 0, 4, 6, and 7 are taken. Let's leave bits 1, 2, 3, and 5 alone to
227 * into this range: 227 * make things easier, and only use the upper 56 bits for the page offset...
228 */ 228 */
229#define PTE_FILE_MAX_BITS 32 229#define PTE_FILE_MAX_BITS 56
230 230
231#define pte_to_pgoff(_pte) \ 231#define pte_to_pgoff(_pte) ((_pte).pte >> 8)
232 ((((_pte).pte >> 3) & 0x1f ) + (((_pte).pte >> 9) << 6 )) 232#define pgoff_to_pte(off) ((pte_t) { ((off) << 8) | _PAGE_FILE })
233
234#define pgoff_to_pte(off) \
235 ((pte_t) { (((off) & 0x1f) << 3) + (((off) >> 6) << 9) + _PAGE_FILE })
236 233
237#endif /* _ASM_PGTABLE_64_H */ 234#endif /* _ASM_PGTABLE_64_H */
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index d02b47933d7..a36ca1be17f 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -69,7 +69,15 @@ extern unsigned long zero_page_mask;
69#define ZERO_PAGE(vaddr) \ 69#define ZERO_PAGE(vaddr) \
70 (virt_to_page(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask))) 70 (virt_to_page(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask)))
71 71
72#define __HAVE_ARCH_MULTIPLE_ZERO_PAGE 72#define __HAVE_ARCH_MOVE_PTE
73#define move_pte(pte, prot, old_addr, new_addr) \
74({ \
75 pte_t newpte = (pte); \
76 if (pte_present(pte) && pfn_valid(pte_pfn(pte)) && \
77 pte_page(pte) == ZERO_PAGE(old_addr)) \
78 newpte = mk_pte(ZERO_PAGE(new_addr), (prot)); \
79 newpte; \
80})
73 81
74extern void paging_init(void); 82extern void paging_init(void);
75 83
@@ -81,10 +89,11 @@ extern void paging_init(void);
81#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT)) 89#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
82#define pmd_page_kernel(pmd) pmd_val(pmd) 90#define pmd_page_kernel(pmd) pmd_val(pmd)
83 91
84#define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL))
85#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
86
87#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 92#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
93
94#define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
95#define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT)
96
88static inline void set_pte(pte_t *ptep, pte_t pte) 97static inline void set_pte(pte_t *ptep, pte_t pte)
89{ 98{
90 ptep->pte_high = pte.pte_high; 99 ptep->pte_high = pte.pte_high;
@@ -92,27 +101,35 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
92 ptep->pte_low = pte.pte_low; 101 ptep->pte_low = pte.pte_low;
93 //printk("pte_high %x pte_low %x\n", ptep->pte_high, ptep->pte_low); 102 //printk("pte_high %x pte_low %x\n", ptep->pte_high, ptep->pte_low);
94 103
95 if (pte_val(pte) & _PAGE_GLOBAL) { 104 if (pte.pte_low & _PAGE_GLOBAL) {
96 pte_t *buddy = ptep_buddy(ptep); 105 pte_t *buddy = ptep_buddy(ptep);
97 /* 106 /*
98 * Make sure the buddy is global too (if it's !none, 107 * Make sure the buddy is global too (if it's !none,
99 * it better already be global) 108 * it better already be global)
100 */ 109 */
101 if (pte_none(*buddy)) 110 if (pte_none(*buddy)) {
102 buddy->pte_low |= _PAGE_GLOBAL; 111 buddy->pte_low |= _PAGE_GLOBAL;
112 buddy->pte_high |= _PAGE_GLOBAL;
113 }
103 } 114 }
104} 115}
105#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) 116#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
106 117
107static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 118static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
108{ 119{
120 pte_t null = __pte(0);
121
109 /* Preserve global status for the pair */ 122 /* Preserve global status for the pair */
110 if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL) 123 if (ptep_buddy(ptep)->pte_low & _PAGE_GLOBAL)
111 set_pte_at(mm, addr, ptep, __pte(_PAGE_GLOBAL)); 124 null.pte_low = null.pte_high = _PAGE_GLOBAL;
112 else 125
113 set_pte_at(mm, addr, ptep, __pte(0)); 126 set_pte_at(mm, addr, ptep, null);
114} 127}
115#else 128#else
129
130#define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL))
131#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
132
116/* 133/*
117 * Certain architectures need to do special things when pte's 134 * Certain architectures need to do special things when pte's
118 * within a page table are directly modified. Thus, the following 135 * within a page table are directly modified. Thus, the following
@@ -173,75 +190,76 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
173 */ 190 */
174static inline int pte_user(pte_t pte) { BUG(); return 0; } 191static inline int pte_user(pte_t pte) { BUG(); return 0; }
175#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 192#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
176static inline int pte_read(pte_t pte) { return (pte).pte_low & _PAGE_READ; } 193static inline int pte_read(pte_t pte) { return pte.pte_low & _PAGE_READ; }
177static inline int pte_write(pte_t pte) { return (pte).pte_low & _PAGE_WRITE; } 194static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; }
178static inline int pte_dirty(pte_t pte) { return (pte).pte_low & _PAGE_MODIFIED; } 195static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; }
179static inline int pte_young(pte_t pte) { return (pte).pte_low & _PAGE_ACCESSED; } 196static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; }
180static inline int pte_file(pte_t pte) { return (pte).pte_low & _PAGE_FILE; } 197static inline int pte_file(pte_t pte) { return pte.pte_low & _PAGE_FILE; }
198
181static inline pte_t pte_wrprotect(pte_t pte) 199static inline pte_t pte_wrprotect(pte_t pte)
182{ 200{
183 (pte).pte_low &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE); 201 pte.pte_low &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
184 (pte).pte_high &= ~_PAGE_SILENT_WRITE; 202 pte.pte_high &= ~_PAGE_SILENT_WRITE;
185 return pte; 203 return pte;
186} 204}
187 205
188static inline pte_t pte_rdprotect(pte_t pte) 206static inline pte_t pte_rdprotect(pte_t pte)
189{ 207{
190 (pte).pte_low &= ~(_PAGE_READ | _PAGE_SILENT_READ); 208 pte.pte_low &= ~(_PAGE_READ | _PAGE_SILENT_READ);
191 (pte).pte_high &= ~_PAGE_SILENT_READ; 209 pte.pte_high &= ~_PAGE_SILENT_READ;
192 return pte; 210 return pte;
193} 211}
194 212
195static inline pte_t pte_mkclean(pte_t pte) 213static inline pte_t pte_mkclean(pte_t pte)
196{ 214{
197 (pte).pte_low &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE); 215 pte.pte_low &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
198 (pte).pte_high &= ~_PAGE_SILENT_WRITE; 216 pte.pte_high &= ~_PAGE_SILENT_WRITE;
199 return pte; 217 return pte;
200} 218}
201 219
202static inline pte_t pte_mkold(pte_t pte) 220static inline pte_t pte_mkold(pte_t pte)
203{ 221{
204 (pte).pte_low &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ); 222 pte.pte_low &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ);
205 (pte).pte_high &= ~_PAGE_SILENT_READ; 223 pte.pte_high &= ~_PAGE_SILENT_READ;
206 return pte; 224 return pte;
207} 225}
208 226
209static inline pte_t pte_mkwrite(pte_t pte) 227static inline pte_t pte_mkwrite(pte_t pte)
210{ 228{
211 (pte).pte_low |= _PAGE_WRITE; 229 pte.pte_low |= _PAGE_WRITE;
212 if ((pte).pte_low & _PAGE_MODIFIED) { 230 if (pte.pte_low & _PAGE_MODIFIED) {
213 (pte).pte_low |= _PAGE_SILENT_WRITE; 231 pte.pte_low |= _PAGE_SILENT_WRITE;
214 (pte).pte_high |= _PAGE_SILENT_WRITE; 232 pte.pte_high |= _PAGE_SILENT_WRITE;
215 } 233 }
216 return pte; 234 return pte;
217} 235}
218 236
219static inline pte_t pte_mkread(pte_t pte) 237static inline pte_t pte_mkread(pte_t pte)
220{ 238{
221 (pte).pte_low |= _PAGE_READ; 239 pte.pte_low |= _PAGE_READ;
222 if ((pte).pte_low & _PAGE_ACCESSED) { 240 if (pte.pte_low & _PAGE_ACCESSED) {
223 (pte).pte_low |= _PAGE_SILENT_READ; 241 pte.pte_low |= _PAGE_SILENT_READ;
224 (pte).pte_high |= _PAGE_SILENT_READ; 242 pte.pte_high |= _PAGE_SILENT_READ;
225 } 243 }
226 return pte; 244 return pte;
227} 245}
228 246
229static inline pte_t pte_mkdirty(pte_t pte) 247static inline pte_t pte_mkdirty(pte_t pte)
230{ 248{
231 (pte).pte_low |= _PAGE_MODIFIED; 249 pte.pte_low |= _PAGE_MODIFIED;
232 if ((pte).pte_low & _PAGE_WRITE) { 250 if (pte.pte_low & _PAGE_WRITE) {
233 (pte).pte_low |= _PAGE_SILENT_WRITE; 251 pte.pte_low |= _PAGE_SILENT_WRITE;
234 (pte).pte_high |= _PAGE_SILENT_WRITE; 252 pte.pte_high |= _PAGE_SILENT_WRITE;
235 } 253 }
236 return pte; 254 return pte;
237} 255}
238 256
239static inline pte_t pte_mkyoung(pte_t pte) 257static inline pte_t pte_mkyoung(pte_t pte)
240{ 258{
241 (pte).pte_low |= _PAGE_ACCESSED; 259 pte.pte_low |= _PAGE_ACCESSED;
242 if ((pte).pte_low & _PAGE_READ) 260 if (pte.pte_low & _PAGE_READ)
243 (pte).pte_low |= _PAGE_SILENT_READ; 261 pte.pte_low |= _PAGE_SILENT_READ;
244 (pte).pte_high |= _PAGE_SILENT_READ; 262 pte.pte_high |= _PAGE_SILENT_READ;
245 return pte; 263 return pte;
246} 264}
247#else 265#else
@@ -334,8 +352,9 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
334#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 352#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
335static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 353static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
336{ 354{
337 pte.pte_low &= _PAGE_CHG_MASK; 355 pte.pte_low &= _PAGE_CHG_MASK;
338 pte.pte_low |= pgprot_val(newprot); 356 pte.pte_high &= ~0x3f;
357 pte.pte_low |= pgprot_val(newprot);
339 pte.pte_high |= pgprot_val(newprot) & 0x3f; 358 pte.pte_high |= pgprot_val(newprot) & 0x3f;
340 return pte; 359 return pte;
341} 360}
@@ -359,9 +378,7 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
359 __update_cache(vma, address, pte); 378 __update_cache(vma, address, pte);
360} 379}
361 380
362#ifndef CONFIG_NEED_MULTIPLE_NODES
363#define kern_addr_valid(addr) (1) 381#define kern_addr_valid(addr) (1)
364#endif
365 382
366#ifdef CONFIG_64BIT_PHYS_ADDR 383#ifdef CONFIG_64BIT_PHYS_ADDR
367extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot); 384extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot);
diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h
index 532df530b4e..5f80ba71ab9 100644
--- a/include/asm-mips/processor.h
+++ b/include/asm-mips/processor.h
@@ -70,11 +70,6 @@ extern unsigned int vced_count, vcei_count;
70 70
71typedef __u64 fpureg_t; 71typedef __u64 fpureg_t;
72 72
73struct mips_fpu_hard_struct {
74 fpureg_t fpr[NUM_FPU_REGS];
75 unsigned int fcr31;
76};
77
78/* 73/*
79 * It would be nice to add some more fields for emulator statistics, but there 74 * It would be nice to add some more fields for emulator statistics, but there
80 * are a number of fixed offsets in offset.h and elsewhere that would have to 75 * are a number of fixed offsets in offset.h and elsewhere that would have to
@@ -82,18 +77,13 @@ struct mips_fpu_hard_struct {
82 * the FPU emulator for now. See asm-mips/fpu_emulator.h. 77 * the FPU emulator for now. See asm-mips/fpu_emulator.h.
83 */ 78 */
84 79
85struct mips_fpu_soft_struct { 80struct mips_fpu_struct {
86 fpureg_t fpr[NUM_FPU_REGS]; 81 fpureg_t fpr[NUM_FPU_REGS];
87 unsigned int fcr31; 82 unsigned int fcr31;
88}; 83};
89 84
90union mips_fpu_union {
91 struct mips_fpu_hard_struct hard;
92 struct mips_fpu_soft_struct soft;
93};
94
95#define INIT_FPU { \ 85#define INIT_FPU { \
96 {{0,},} \ 86 {0,} \
97} 87}
98 88
99#define NUM_DSP_REGS 6 89#define NUM_DSP_REGS 6
@@ -132,7 +122,7 @@ struct thread_struct {
132 unsigned long cp0_status; 122 unsigned long cp0_status;
133 123
134 /* Saved fpu/fpu emulator stuff. */ 124 /* Saved fpu/fpu emulator stuff. */
135 union mips_fpu_union fpu; 125 struct mips_fpu_struct fpu;
136#ifdef CONFIG_MIPS_MT_FPAFF 126#ifdef CONFIG_MIPS_MT_FPAFF
137 /* Emulated instruction count */ 127 /* Emulated instruction count */
138 unsigned long emulated_fp; 128 unsigned long emulated_fp;
diff --git a/include/asm-mips/qemu.h b/include/asm-mips/qemu.h
index 905c3958590..531caf44560 100644
--- a/include/asm-mips/qemu.h
+++ b/include/asm-mips/qemu.h
@@ -21,4 +21,10 @@
21 */ 21 */
22#define QEMU_C0_COUNTER_CLOCK 100000000 22#define QEMU_C0_COUNTER_CLOCK 100000000
23 23
24/*
25 * Magic qemu system control location.
26 */
27#define QEMU_RESTART_REG 0xBFBF0000
28#define QEMU_HALT_REG 0xBFBF0004
29
24#endif /* __ASM_QEMU_H */ 30#endif /* __ASM_QEMU_H */
diff --git a/include/asm-mips/rm9k-ocd.h b/include/asm-mips/rm9k-ocd.h
new file mode 100644
index 00000000000..b0b80d9ecf9
--- /dev/null
+++ b/include/asm-mips/rm9k-ocd.h
@@ -0,0 +1,56 @@
1/*
2 * Copyright (C) 2004 by Basler Vision Technologies AG
3 * Author: Thomas Koeller <thomas.koeller@baslerweb.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#if !defined(_ASM_RM9K_OCD_H)
21#define _ASM_RM9K_OCD_H
22
23#include <linux/types.h>
24#include <linux/spinlock.h>
25#include <asm/io.h>
26
27extern volatile void __iomem * const ocd_base;
28extern volatile void __iomem * const titan_base;
29
30#define ocd_addr(__x__) (ocd_base + (__x__))
31#define titan_addr(__x__) (titan_base + (__x__))
32#define scram_addr(__x__) (scram_base + (__x__))
33
34/* OCD register access */
35#define ocd_readl(__offs__) __raw_readl(ocd_addr(__offs__))
36#define ocd_readw(__offs__) __raw_readw(ocd_addr(__offs__))
37#define ocd_readb(__offs__) __raw_readb(ocd_addr(__offs__))
38#define ocd_writel(__val__, __offs__) \
39 __raw_writel((__val__), ocd_addr(__offs__))
40#define ocd_writew(__val__, __offs__) \
41 __raw_writew((__val__), ocd_addr(__offs__))
42#define ocd_writeb(__val__, __offs__) \
43 __raw_writeb((__val__), ocd_addr(__offs__))
44
45/* TITAN register access - 32 bit-wide only */
46#define titan_readl(__offs__) __raw_readl(titan_addr(__offs__))
47#define titan_writel(__val__, __offs__) \
48 __raw_writel((__val__), titan_addr(__offs__))
49
50/* Protect access to shared TITAN registers */
51extern spinlock_t titan_lock;
52extern int titan_irqflags;
53#define lock_titan_regs() spin_lock_irqsave(&titan_lock, titan_irqflags)
54#define unlock_titan_regs() spin_unlock_irqrestore(&titan_lock, titan_irqflags)
55
56#endif /* !defined(_ASM_RM9K_OCD_H) */
diff --git a/include/asm-mips/sigcontext.h b/include/asm-mips/sigcontext.h
index 8edabb0be23..cefa657dd04 100644
--- a/include/asm-mips/sigcontext.h
+++ b/include/asm-mips/sigcontext.h
@@ -55,8 +55,14 @@ struct sigcontext {
55struct sigcontext { 55struct sigcontext {
56 unsigned long sc_regs[32]; 56 unsigned long sc_regs[32];
57 unsigned long sc_fpregs[32]; 57 unsigned long sc_fpregs[32];
58 unsigned long sc_hi[4]; 58 unsigned long sc_mdhi;
59 unsigned long sc_lo[4]; 59 unsigned long sc_hi1;
60 unsigned long sc_hi2;
61 unsigned long sc_hi3;
62 unsigned long sc_mdlo;
63 unsigned long sc_lo1;
64 unsigned long sc_lo2;
65 unsigned long sc_lo3;
60 unsigned long sc_pc; 66 unsigned long sc_pc;
61 unsigned int sc_fpc_csr; 67 unsigned int sc_fpc_csr;
62 unsigned int sc_used_math; 68 unsigned int sc_used_math;
diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h
index ffcb7a336b1..1608fd71d6f 100644
--- a/include/asm-mips/smp.h
+++ b/include/asm-mips/smp.h
@@ -47,7 +47,6 @@ extern struct call_data_struct *call_data;
47#define SMP_CALL_FUNCTION 0x2 47#define SMP_CALL_FUNCTION 0x2
48 48
49extern cpumask_t phys_cpu_present_map; 49extern cpumask_t phys_cpu_present_map;
50extern cpumask_t cpu_online_map;
51#define cpu_possible_map phys_cpu_present_map 50#define cpu_possible_map phys_cpu_present_map
52 51
53extern cpumask_t cpu_callout_map; 52extern cpumask_t cpu_callout_map;
@@ -85,9 +84,9 @@ extern void prom_init_secondary(void);
85extern void plat_smp_setup(void); 84extern void plat_smp_setup(void);
86 85
87/* 86/*
88 * Called after init_IRQ but before __cpu_up. 87 * Called in smp_prepare_cpus.
89 */ 88 */
90extern void prom_prepare_cpus(unsigned int max_cpus); 89extern void plat_prepare_cpus(unsigned int max_cpus);
91 90
92/* 91/*
93 * Last chance for the board code to finish SMP initialization before 92 * Last chance for the board code to finish SMP initialization before
diff --git a/include/asm-mips/sn/addrs.h b/include/asm-mips/sn/addrs.h
index 3f6891b0c0e..8fa0af6b68d 100644
--- a/include/asm-mips/sn/addrs.h
+++ b/include/asm-mips/sn/addrs.h
@@ -26,13 +26,8 @@
26 26
27#ifndef __ASSEMBLY__ 27#ifndef __ASSEMBLY__
28 28
29#if defined(CONFIG_SGI_IO) /* FIXME */
30#define PS_UINT_CAST (__psunsigned_t)
31#define UINT64_CAST (__uint64_t)
32#else /* CONFIG_SGI_IO */
33#define PS_UINT_CAST (unsigned long) 29#define PS_UINT_CAST (unsigned long)
34#define UINT64_CAST (unsigned long) 30#define UINT64_CAST (unsigned long)
35#endif /* CONFIG_SGI_IO */
36 31
37#define HUBREG_CAST (volatile hubreg_t *) 32#define HUBREG_CAST (volatile hubreg_t *)
38 33
@@ -252,14 +247,6 @@
252 * for _x. 247 * for _x.
253 */ 248 */
254 249
255#ifdef _STANDALONE
256
257/* DO NOT USE THESE DIRECTLY IN THE KERNEL. SEE BELOW. */
258#define LOCAL_HUB(_x) (HUBREG_CAST (IALIAS_BASE + (_x)))
259#define REMOTE_HUB(_n, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \
260 0x800000 + (_x)))
261#endif /* _STANDALONE */
262
263/* 250/*
264 * WARNING: 251 * WARNING:
265 * When certain Hub chip workaround are defined, it's not sufficient 252 * When certain Hub chip workaround are defined, it's not sufficient
@@ -326,20 +313,6 @@
326 PHYS_TO_K0(NODE_OFFSET(nasid) | ARCS_SPB_OFFSET) 313 PHYS_TO_K0(NODE_OFFSET(nasid) | ARCS_SPB_OFFSET)
327#define ARCS_SPB_SIZE 0x0400 314#define ARCS_SPB_SIZE 0x0400
328 315
329#ifdef _STANDALONE
330
331#define ARCS_TVECTOR_OFFSET 0x2800
332#define ARCS_PVECTOR_OFFSET 0x2c00
333
334/*
335 * These addresses are used by the master CPU to install the transfer
336 * and private vectors. All others use the SPB to find them.
337 */
338#define TVADDR (NODE_CAC_BASE(get_nasid()) + ARCS_TVECTOR_OFFSET)
339#define PVADDR (NODE_CAC_BASE(get_nasid()) + ARCS_PVECTOR_OFFSET)
340
341#endif /* _STANDALONE */
342
343#define KLDIR_OFFSET 0x2000 316#define KLDIR_OFFSET 0x2000
344#define KLDIR_ADDR(nasid) \ 317#define KLDIR_ADDR(nasid) \
345 TO_NODE_UNCAC((nasid), KLDIR_OFFSET) 318 TO_NODE_UNCAC((nasid), KLDIR_OFFSET)
diff --git a/include/asm-mips/sn/sn0/sn0_fru.h b/include/asm-mips/sn/fru.h
index 82c6377c275..b3e3606723b 100644
--- a/include/asm-mips/sn/sn0/sn0_fru.h
+++ b/include/asm-mips/sn/fru.h
@@ -6,10 +6,10 @@
6 * Derived from IRIX <sys/SN/SN0/sn0_fru.h> 6 * Derived from IRIX <sys/SN/SN0/sn0_fru.h>
7 * 7 *
8 * Copyright (C) 1992 - 1997, 1999 Silcon Graphics, Inc. 8 * Copyright (C) 1992 - 1997, 1999 Silcon Graphics, Inc.
9 * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org) 9 * Copyright (C) 1999, 2006 Ralf Baechle (ralf@linux-mips)
10 */ 10 */
11#ifndef _ASM_SN_SN0_SN0_FRU_H 11#ifndef __ASM_SN_FRU_H
12#define _ASM_SN_SN0_SN0_FRU_H 12#define __ASM_SN_FRU_H
13 13
14#define MAX_DIMMS 8 /* max # of dimm banks */ 14#define MAX_DIMMS 8 /* max # of dimm banks */
15#define MAX_PCIDEV 8 /* max # of pci devices on a pci bus */ 15#define MAX_PCIDEV 8 /* max # of pci devices on a pci bus */
@@ -41,4 +41,4 @@ typedef struct kf_pci_bus_s {
41 /* confidence level that the pci dev is bad */ 41 /* confidence level that the pci dev is bad */
42} kf_pci_bus_t; 42} kf_pci_bus_t;
43 43
44#endif /* _ASM_SN_SN0_SN0_FRU_H */ 44#endif /* __ASM_SN_FRU_H */
diff --git a/include/asm-mips/sn/klconfig.h b/include/asm-mips/sn/klconfig.h
index 19e0e926be5..52238e65af8 100644
--- a/include/asm-mips/sn/klconfig.h
+++ b/include/asm-mips/sn/klconfig.h
@@ -36,7 +36,7 @@
36//#include <sys/SN/router.h> 36//#include <sys/SN/router.h>
37// XXX Stolen from <sys/SN/router.h>: 37// XXX Stolen from <sys/SN/router.h>:
38#define MAX_ROUTER_PORTS (6) /* Max. number of ports on a router */ 38#define MAX_ROUTER_PORTS (6) /* Max. number of ports on a router */
39#include <asm/sn/sn0/sn0_fru.h> 39#include <asm/sn/fru.h>
40//#include <sys/graph.h> 40//#include <sys/graph.h>
41//#include <sys/xtalk/xbow.h> 41//#include <sys/xtalk/xbow.h>
42 42
@@ -53,32 +53,21 @@
53#include <asm/sn/agent.h> 53#include <asm/sn/agent.h>
54#include <asm/arc/types.h> 54#include <asm/arc/types.h>
55#include <asm/arc/hinv.h> 55#include <asm/arc/hinv.h>
56#if defined(CONFIG_SGI_IO) || defined(CONFIG_SGI_IP35) 56#if defined(CONFIG_SGI_IP35)
57// The hack file has to be before vector and after sn0_fru.... 57// The hack file has to be before vector and after sn0_fru....
58#include <asm/hack.h> 58#include <asm/hack.h>
59#include <asm/sn/vector.h> 59#include <asm/sn/vector.h>
60#include <asm/xtalk/xtalk.h> 60#include <asm/xtalk/xtalk.h>
61#endif /* CONFIG_SGI_IO || CONFIG_SGI_IP35 */ 61#endif /* CONFIG_SGI_IP35 */
62#endif /* CONFIG_SGI_IP27 || CONFIG_SGI_IP35 */ 62#endif /* CONFIG_SGI_IP27 || CONFIG_SGI_IP35 */
63 63
64#define KLCFGINFO_MAGIC 0xbeedbabe 64#define KLCFGINFO_MAGIC 0xbeedbabe
65 65
66#ifdef FRUTEST
67typedef u64 klconf_off_t;
68#else
69typedef s32 klconf_off_t; 66typedef s32 klconf_off_t;
70#endif
71 67
72/* 68/*
73 * Some IMPORTANT OFFSETS. These are the offsets on all NODES. 69 * Some IMPORTANT OFFSETS. These are the offsets on all NODES.
74 */ 70 */
75#if 0
76#define RAMBASE 0
77#define ARCSSPB_OFF 0x1000 /* shift it to sys/arcs/spb.h */
78
79#define OFF_HWGRAPH 0
80#endif
81
82#define MAX_MODULE_ID 255 71#define MAX_MODULE_ID 255
83#define SIZE_PAD 4096 /* 4k padding for structures */ 72#define SIZE_PAD 4096 /* 4k padding for structures */
84/* 73/*
@@ -133,15 +122,9 @@ typedef s32 klconf_off_t;
133 122
134 123
135typedef struct console_s { 124typedef struct console_s {
136#if defined(CONFIG_SGI_IO) /* FIXME */
137 __psunsigned_t uart_base;
138 __psunsigned_t config_base;
139 __psunsigned_t memory_base;
140#else
141 unsigned long uart_base; 125 unsigned long uart_base;
142 unsigned long config_base; 126 unsigned long config_base;
143 unsigned long memory_base; 127 unsigned long memory_base;
144#endif
145 short baud; 128 short baud;
146 short flag; 129 short flag;
147 int type; 130 int type;
@@ -173,10 +156,6 @@ typedef struct kl_config_hdr {
173 156
174 157
175#define KL_CONFIG_HDR(_nasid) ((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid))) 158#define KL_CONFIG_HDR(_nasid) ((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid)))
176#if 0
177#define KL_CONFIG_MALLOC_HDR(_nasid) \
178 (KL_CONFIG_HDR(_nasid)->ch_malloc_hdr)
179#endif
180#define KL_CONFIG_INFO_OFFSET(_nasid) \ 159#define KL_CONFIG_INFO_OFFSET(_nasid) \
181 (KL_CONFIG_HDR(_nasid)->ch_board_info) 160 (KL_CONFIG_HDR(_nasid)->ch_board_info)
182#define KL_CONFIG_INFO_SET_OFFSET(_nasid, _off) \ 161#define KL_CONFIG_INFO_SET_OFFSET(_nasid, _off) \
@@ -196,23 +175,13 @@ typedef struct kl_config_hdr {
196 175
197/* --- New Macros for the changed kl_config_hdr_t structure --- */ 176/* --- New Macros for the changed kl_config_hdr_t structure --- */
198 177
199#if defined(CONFIG_SGI_IO)
200#define PTR_CH_MALLOC_HDR(_k) ((klc_malloc_hdr_t *)\
201 ((__psunsigned_t)_k + (_k->ch_malloc_hdr_off)))
202#else
203#define PTR_CH_MALLOC_HDR(_k) ((klc_malloc_hdr_t *)\ 178#define PTR_CH_MALLOC_HDR(_k) ((klc_malloc_hdr_t *)\
204 (unsigned long)_k + (_k->ch_malloc_hdr_off))) 179 (unsigned long)_k + (_k->ch_malloc_hdr_off)))
205#endif
206 180
207#define KL_CONFIG_CH_MALLOC_HDR(_n) PTR_CH_MALLOC_HDR(KL_CONFIG_HDR(_n)) 181#define KL_CONFIG_CH_MALLOC_HDR(_n) PTR_CH_MALLOC_HDR(KL_CONFIG_HDR(_n))
208 182
209#if defined(CONFIG_SGI_IO)
210#define PTR_CH_CONS_INFO(_k) ((console_t *)\
211 ((__psunsigned_t)_k + (_k->ch_cons_off)))
212#else
213#define PTR_CH_CONS_INFO(_k) ((console_t *)\ 183#define PTR_CH_CONS_INFO(_k) ((console_t *)\
214 ((unsigned long)_k + (_k->ch_cons_off))) 184 ((unsigned long)_k + (_k->ch_cons_off)))
215#endif
216 185
217#define KL_CONFIG_CH_CONS_INFO(_n) PTR_CH_CONS_INFO(KL_CONFIG_HDR(_n)) 186#define KL_CONFIG_CH_CONS_INFO(_n) PTR_CH_CONS_INFO(KL_CONFIG_HDR(_n))
218 187
@@ -489,14 +458,6 @@ typedef struct lboard_s {
489#define KLCF_NUM_COMPS(_brd) ((_brd)->brd_numcompts) 458#define KLCF_NUM_COMPS(_brd) ((_brd)->brd_numcompts)
490#define KLCF_MODULE_ID(_brd) ((_brd)->brd_module) 459#define KLCF_MODULE_ID(_brd) ((_brd)->brd_module)
491 460
492#ifdef FRUTEST
493
494#define KLCF_NEXT(_brd) ((_brd)->brd_next ? (lboard_t *)((_brd)->brd_next): NULL)
495#define KLCF_COMP(_brd, _ndx) (klinfo_t *)((_brd)->brd_compts[(_ndx)])
496#define KLCF_COMP_ERROR(_brd, _comp) (_brd = _brd , (_comp)->errinfo)
497
498#else
499
500#define KLCF_NEXT(_brd) \ 461#define KLCF_NEXT(_brd) \
501 ((_brd)->brd_next ? \ 462 ((_brd)->brd_next ? \
502 (lboard_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), (_brd)->brd_next)):\ 463 (lboard_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), (_brd)->brd_next)):\
@@ -508,8 +469,6 @@ typedef struct lboard_s {
508#define KLCF_COMP_ERROR(_brd, _comp) \ 469#define KLCF_COMP_ERROR(_brd, _comp) \
509 (NODE_OFFSET_TO_K1(NASID_GET(_brd), (_comp)->errinfo)) 470 (NODE_OFFSET_TO_K1(NASID_GET(_brd), (_comp)->errinfo))
510 471
511#endif
512
513#define KLCF_COMP_TYPE(_comp) ((_comp)->struct_type) 472#define KLCF_COMP_TYPE(_comp) ((_comp)->struct_type)
514#define KLCF_BRIDGE_W_ID(_comp) ((_comp)->physid) /* Widget ID */ 473#define KLCF_BRIDGE_W_ID(_comp) ((_comp)->physid) /* Widget ID */
515 474
@@ -630,18 +589,6 @@ typedef struct klport_s {
630 klconf_off_t port_offset; 589 klconf_off_t port_offset;
631} klport_t; 590} klport_t;
632 591
633#if 0
634/*
635 * This is very similar to the klport_s but instead of having a componant
636 * offset it has a board offset.
637 */
638typedef struct klxbow_port_s {
639 nasid_t port_nasid;
640 unsigned char port_flag;
641 klconf_off_t board_offset;
642} klxbow_port_t;
643#endif
644
645typedef struct klcpu_s { /* CPU */ 592typedef struct klcpu_s { /* CPU */
646 klinfo_t cpu_info; 593 klinfo_t cpu_info;
647 unsigned short cpu_prid; /* Processor PRID value */ 594 unsigned short cpu_prid; /* Processor PRID value */
@@ -944,36 +891,6 @@ extern klcpu_t *nasid_slice_to_cpuinfo(nasid_t, int);
944extern lboard_t *find_lboard_class(lboard_t *start, unsigned char brd_class); 891extern lboard_t *find_lboard_class(lboard_t *start, unsigned char brd_class);
945 892
946 893
947#if defined(CONFIG_SGI_IO)
948extern xwidgetnum_t nodevertex_widgetnum_get(vertex_hdl_t node_vtx);
949extern vertex_hdl_t nodevertex_xbow_peer_get(vertex_hdl_t node_vtx);
950extern lboard_t *find_gfxpipe(int pipenum);
951extern void setup_gfxpipe_link(vertex_hdl_t vhdl,int pipenum);
952extern lboard_t *find_lboard_module_class(lboard_t *start, moduleid_t mod,
953 unsigned char brd_class);
954extern lboard_t *find_nic_lboard(lboard_t *, nic_t);
955extern lboard_t *find_nic_type_lboard(nasid_t, unsigned char, nic_t);
956extern lboard_t *find_lboard_modslot(lboard_t *start, moduleid_t mod, slotid_t slot);
957extern lboard_t *find_lboard_module(lboard_t *start, moduleid_t mod);
958extern lboard_t *get_board_name(nasid_t nasid, moduleid_t mod, slotid_t slot, char *name);
959extern int config_find_nic_router(nasid_t, nic_t, lboard_t **, klrou_t**);
960extern int config_find_nic_hub(nasid_t, nic_t, lboard_t **, klhub_t**);
961extern int config_find_xbow(nasid_t, lboard_t **, klxbow_t**);
962extern klcpu_t *get_cpuinfo(cpuid_t cpu);
963extern int update_klcfg_cpuinfo(nasid_t, int);
964extern void board_to_path(lboard_t *brd, char *path);
965extern moduleid_t get_module_id(nasid_t nasid);
966extern void nic_name_convert(char *old_name, char *new_name);
967extern int module_brds(nasid_t nasid, lboard_t **module_brds, int n);
968extern lboard_t *brd_from_key(ulong_t key);
969extern void device_component_canonical_name_get(lboard_t *,klinfo_t *,
970 char *);
971extern int board_serial_number_get(lboard_t *,char *);
972extern int is_master_baseio(nasid_t,moduleid_t,slotid_t);
973extern nasid_t get_actual_nasid(lboard_t *brd) ;
974extern net_vec_t klcfg_discover_route(lboard_t *, lboard_t *, int);
975#else /* CONFIG_SGI_IO */
976extern klcpu_t *sn_get_cpuinfo(cpuid_t cpu); 894extern klcpu_t *sn_get_cpuinfo(cpuid_t cpu);
977#endif /* CONFIG_SGI_IO */
978 895
979#endif /* _ASM_SN_KLCONFIG_H */ 896#endif /* _ASM_SN_KLCONFIG_H */
diff --git a/include/asm-mips/sn/kldir.h b/include/asm-mips/sn/kldir.h
index e3e231f0b79..0573cbffc10 100644
--- a/include/asm-mips/sn/kldir.h
+++ b/include/asm-mips/sn/kldir.h
@@ -12,10 +12,6 @@
12#define _ASM_SN_KLDIR_H 12#define _ASM_SN_KLDIR_H
13 13
14 14
15#if defined(CONFIG_SGI_IO)
16#include <asm/hack.h>
17#endif
18
19/* 15/*
20 * The kldir memory area resides at a fixed place in each node's memory and 16 * The kldir memory area resides at a fixed place in each node's memory and
21 * provides pointers to most other IP27 memory areas. This allows us to 17 * provides pointers to most other IP27 memory areas. This allows us to
@@ -135,8 +131,6 @@
135#define KLDIR_OFF_STRIDE 0x28 131#define KLDIR_OFF_STRIDE 0x28
136#endif /* __ASSEMBLY__ */ 132#endif /* __ASSEMBLY__ */
137 133
138#if !defined(CONFIG_SGI_IO)
139
140/* 134/*
141 * This is defined here because IP27_SYMMON_STK_SIZE must be at least what 135 * This is defined here because IP27_SYMMON_STK_SIZE must be at least what
142 * we define here. Since it's set up in the prom. We can't redefine it later 136 * we define here. Since it's set up in the prom. We can't redefine it later
@@ -146,7 +140,7 @@
146 */ 140 */
147#define SYMMON_STACK_SIZE 0x8000 141#define SYMMON_STACK_SIZE 0x8000
148 142
149#if defined (PROM) || defined (SABLE) 143#if defined (PROM)
150 144
151/* 145/*
152 * These defines are prom version dependent. No code other than the IP27 146 * These defines are prom version dependent. No code other than the IP27
@@ -183,7 +177,7 @@
183#define IP27_FREEMEM_COUNT 1 177#define IP27_FREEMEM_COUNT 1
184#define IP27_FREEMEM_STRIDE 0 178#define IP27_FREEMEM_STRIDE 0
185 179
186#endif /* PROM || SABLE*/ 180#endif /* PROM */
187/* 181/*
188 * There will be only one of these in a partition so the IO6 must set it up. 182 * There will be only one of these in a partition so the IO6 must set it up.
189 */ 183 */
@@ -206,17 +200,11 @@
206#define KLDIR_ENT_SIZE 0x40 200#define KLDIR_ENT_SIZE 0x40
207#define KLDIR_MAX_ENTRIES (0x400 / 0x40) 201#define KLDIR_MAX_ENTRIES (0x400 / 0x40)
208 202
209#endif /* !CONFIG_SGI_IO */
210
211#ifndef __ASSEMBLY__ 203#ifndef __ASSEMBLY__
212typedef struct kldir_ent_s { 204typedef struct kldir_ent_s {
213 u64 magic; /* Indicates validity of entry */ 205 u64 magic; /* Indicates validity of entry */
214 off_t offset; /* Offset from start of node space */ 206 off_t offset; /* Offset from start of node space */
215#if defined(CONFIG_SGI_IO) /* FIXME */
216 __psunsigned_t pointer; /* Pointer to area in some cases */
217#else
218 unsigned long pointer; /* Pointer to area in some cases */ 207 unsigned long pointer; /* Pointer to area in some cases */
219#endif
220 size_t size; /* Size in bytes */ 208 size_t size; /* Size in bytes */
221 u64 count; /* Repeat count if array, 1 if not */ 209 u64 count; /* Repeat count if array, 1 if not */
222 size_t stride; /* Stride if array, 0 if not */ 210 size_t stride; /* Stride if array, 0 if not */
@@ -226,22 +214,4 @@ typedef struct kldir_ent_s {
226} kldir_ent_t; 214} kldir_ent_t;
227#endif /* !__ASSEMBLY__ */ 215#endif /* !__ASSEMBLY__ */
228 216
229#if defined(CONFIG_SGI_IO)
230
231#define KLDIR_ENT_SIZE 0x40
232#define KLDIR_MAX_ENTRIES (0x400 / 0x40)
233
234/*
235 * The actual offsets of each memory area are machine-dependent
236 */
237#ifdef CONFIG_SGI_IP27
238// Not yet #include <asm/sn/sn0/kldir.h>
239#elif defined(CONFIG_SGI_IP35)
240#include <asm/sn/sn1/kldir.h>
241#else
242#error "kldir.h is currently defined for IP27 and IP35 platforms only"
243#endif
244
245#endif /* CONFIG_SGI_IO */
246
247#endif /* _ASM_SN_KLDIR_H */ 217#endif /* _ASM_SN_KLDIR_H */
diff --git a/include/asm-mips/sn/sn0/addrs.h b/include/asm-mips/sn/sn0/addrs.h
index c0905c1ac93..9e8cc52910f 100644
--- a/include/asm-mips/sn/sn0/addrs.h
+++ b/include/asm-mips/sn/sn0/addrs.h
@@ -48,7 +48,7 @@
48 * so for now we just use defines bracketed by an ifdef. 48 * so for now we just use defines bracketed by an ifdef.
49 */ 49 */
50 50
51#ifdef CONFIG_SGI_SN0_N_MODE 51#ifdef CONFIG_SGI_SN_N_MODE
52 52
53#define NODE_SIZE_BITS 31 53#define NODE_SIZE_BITS 31
54#define BWIN_SIZE_BITS 28 54#define BWIN_SIZE_BITS 28
@@ -62,7 +62,7 @@
62#define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10) 62#define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10)
63#define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3) 63#define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3)
64 64
65#else /* !defined(CONFIG_SGI_SN0_N_MODE), assume that M-mode is desired */ 65#else /* !defined(CONFIG_SGI_SN_N_MODE), assume that M-mode is desired */
66 66
67#define NODE_SIZE_BITS 32 67#define NODE_SIZE_BITS 32
68#define BWIN_SIZE_BITS 29 68#define BWIN_SIZE_BITS 29
@@ -76,7 +76,7 @@
76#define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10) 76#define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10)
77#define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3) 77#define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3)
78 78
79#endif /* !defined(CONFIG_SGI_SN0_N_MODE) */ 79#endif /* !defined(CONFIG_SGI_SN_N_MODE) */
80 80
81#define NODE_ADDRSPACE_SIZE (UINT64_CAST 1 << NODE_SIZE_BITS) 81#define NODE_ADDRSPACE_SIZE (UINT64_CAST 1 << NODE_SIZE_BITS)
82 82
@@ -84,15 +84,15 @@
84#define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \ 84#define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \
85 NASID_SHFT) & NASID_BITMASK) 85 NASID_SHFT) & NASID_BITMASK)
86 86
87#if !defined(__ASSEMBLY__) && !defined(_STANDALONE) 87#if !defined(__ASSEMBLY__)
88 88
89#define NODE_SWIN_BASE(nasid, widget) \ 89#define NODE_SWIN_BASE(nasid, widget) \
90 ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \ 90 ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
91 : RAW_NODE_SWIN_BASE(nasid, widget)) 91 : RAW_NODE_SWIN_BASE(nasid, widget))
92#else /* __ASSEMBLY__ || _STANDALONE */ 92#else /* __ASSEMBLY__ */
93#define NODE_SWIN_BASE(nasid, widget) \ 93#define NODE_SWIN_BASE(nasid, widget) \
94 (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS)) 94 (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS))
95#endif /* __ASSEMBLY__ || _STANDALONE */ 95#endif /* __ASSEMBLY__ */
96 96
97/* 97/*
98 * The following definitions pertain to the IO special address 98 * The following definitions pertain to the IO special address
@@ -142,12 +142,7 @@
142#define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid))) 142#define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid)))
143 143
144/* Turn on sable logging for the processors whose bits are set. */ 144/* Turn on sable logging for the processors whose bits are set. */
145#ifdef SABLE
146#define SABLE_LOG_TRIGGER(_map) \
147 *((volatile hubreg_t *)(IO_BASE + 0x17ffff0)) = (_map)
148#else
149#define SABLE_LOG_TRIGGER(_map) 145#define SABLE_LOG_TRIGGER(_map)
150#endif /* SABLE */
151 146
152#ifndef __ASSEMBLY__ 147#ifndef __ASSEMBLY__
153#define KERN_NMI_ADDR(nasid, slice) \ 148#define KERN_NMI_ADDR(nasid, slice) \
@@ -280,76 +275,6 @@
280 275
281#define _ARCSPROM 276#define _ARCSPROM
282 277
283#ifdef _STANDALONE
284
285/*
286 * The PROM needs to pass the device base address and the
287 * device pci cfg space address to the device drivers during
288 * install. The COMPONENT->Key field is used for this purpose.
289 * Macros needed by SN0 device drivers to convert the
290 * COMPONENT->Key field to the respective base address.
291 * Key field looks as follows:
292 *
293 * +----------------------------------------------------+
294 * |devnasid | widget |pciid |hubwidid|hstnasid | adap |
295 * | 2 | 1 | 1 | 1 | 2 | 1 |
296 * +----------------------------------------------------+
297 * | | | | | | |
298 * 64 48 40 32 24 8 0
299 *
300 * These are used by standalone drivers till the io infrastructure
301 * is in place.
302 */
303
304#ifndef __ASSEMBLY__
305
306#define uchar unsigned char
307
308#define KEY_DEVNASID_SHFT 48
309#define KEY_WIDID_SHFT 40
310#define KEY_PCIID_SHFT 32
311#define KEY_HUBWID_SHFT 24
312#define KEY_HSTNASID_SHFT 8
313
314#define MK_SN0_KEY(nasid, widid, pciid) \
315 ((((__psunsigned_t)nasid)<< KEY_DEVNASID_SHFT |\
316 ((__psunsigned_t)widid) << KEY_WIDID_SHFT) |\
317 ((__psunsigned_t)pciid) << KEY_PCIID_SHFT)
318
319#define ADD_HUBWID_KEY(key,hubwid)\
320 (key|=((__psunsigned_t)hubwid << KEY_HUBWID_SHFT))
321
322#define ADD_HSTNASID_KEY(key,hstnasid)\
323 (key|=((__psunsigned_t)hstnasid << KEY_HSTNASID_SHFT))
324
325#define GET_DEVNASID_FROM_KEY(key) ((short)(key >> KEY_DEVNASID_SHFT))
326#define GET_WIDID_FROM_KEY(key) ((uchar)(key >> KEY_WIDID_SHFT))
327#define GET_PCIID_FROM_KEY(key) ((uchar)(key >> KEY_PCIID_SHFT))
328#define GET_HUBWID_FROM_KEY(key) ((uchar)(key >> KEY_HUBWID_SHFT))
329#define GET_HSTNASID_FROM_KEY(key) ((short)(key >> KEY_HSTNASID_SHFT))
330
331#define PCI_64_TARGID_SHFT 60
332
333#define GET_PCIBASE_FROM_KEY(key) (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
334 GET_WIDID_FROM_KEY(key))\
335 | BRIDGE_DEVIO(GET_PCIID_FROM_KEY(key)))
336
337#define GET_PCICFGBASE_FROM_KEY(key) \
338 (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
339 GET_WIDID_FROM_KEY(key))\
340 | BRIDGE_TYPE0_CFG_DEV(GET_PCIID_FROM_KEY(key)))
341
342#define GET_WIDBASE_FROM_KEY(key) \
343 (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
344 GET_WIDID_FROM_KEY(key)))
345
346#define PUT_INSTALL_STATUS(c,s) c->Revision = s
347#define GET_INSTALL_STATUS(c) c->Revision
348
349#endif /* !__ASSEMBLY__ */
350
351#endif /* _STANDALONE */
352
353#if defined (HUB_ERR_STS_WAR) 278#if defined (HUB_ERR_STS_WAR)
354 279
355#define ERR_STS_WAR_REGISTER IIO_IIBUSERR 280#define ERR_STS_WAR_REGISTER IIO_IIBUSERR
diff --git a/include/asm-mips/sn/sn0/arch.h b/include/asm-mips/sn/sn0/arch.h
index 7a221666c58..f734f2007f2 100644
--- a/include/asm-mips/sn/sn0/arch.h
+++ b/include/asm-mips/sn/sn0/arch.h
@@ -12,8 +12,6 @@
12#define _ASM_SN_SN0_ARCH_H 12#define _ASM_SN_SN0_ARCH_H
13 13
14 14
15#ifndef SABLE
16
17#ifndef SN0XXL /* 128 cpu SMP max */ 15#ifndef SN0XXL /* 128 cpu SMP max */
18/* 16/*
19 * This is the maximum number of nodes that can be part of a kernel. 17 * This is the maximum number of nodes that can be part of a kernel.
@@ -53,25 +51,16 @@
53 */ 51 */
54#define MAX_PARTITIONS MAX_REGIONS 52#define MAX_PARTITIONS MAX_REGIONS
55 53
56
57#else
58
59#define MAX_COMPACT_NODES 4
60#define MAX_NASIDS 4
61#define MAXCPUS 8
62
63#endif
64
65#define NASID_MASK_BYTES ((MAX_NASIDS + 7) / 8) 54#define NASID_MASK_BYTES ((MAX_NASIDS + 7) / 8)
66 55
67/* 56/*
68 * Slot constants for SN0 57 * Slot constants for SN0
69 */ 58 */
70#ifdef CONFIG_SGI_SN0_N_MODE 59#ifdef CONFIG_SGI_SN_N_MODE
71#define MAX_MEM_SLOTS 16 /* max slots per node */ 60#define MAX_MEM_SLOTS 16 /* max slots per node */
72#else /* !CONFIG_SGI_SN0_N_MODE, assume M_MODE */ 61#else /* !CONFIG_SGI_SN_N_MODE, assume CONFIG_SGI_SN_M_MODE */
73#define MAX_MEM_SLOTS 32 /* max slots per node */ 62#define MAX_MEM_SLOTS 32 /* max slots per node */
74#endif /* defined(N_MODE) */ 63#endif /* CONFIG_SGI_SN_M_MODE */
75 64
76#define SLOT_SHIFT (27) 65#define SLOT_SHIFT (27)
77#define SLOT_MIN_MEM_SIZE (32*1024*1024) 66#define SLOT_MIN_MEM_SIZE (32*1024*1024)
diff --git a/include/asm-mips/sn/sn0/hub.h b/include/asm-mips/sn/sn0/hub.h
index f5dbba6f461..3e228f8e796 100644
--- a/include/asm-mips/sn/sn0/hub.h
+++ b/include/asm-mips/sn/sn0/hub.h
@@ -31,10 +31,6 @@
31#include <asm/sn/sn0/hubni.h> 31#include <asm/sn/sn0/hubni.h>
32//#include <asm/sn/sn0/hubcore.h> 32//#include <asm/sn/sn0/hubcore.h>
33 33
34#ifdef SABLE
35#define IP27_NO_HUBUART_INT 1
36#endif
37
38/* Translation of uncached attributes */ 34/* Translation of uncached attributes */
39#define UATTR_HSPEC 0 35#define UATTR_HSPEC 0
40#define UATTR_IO 1 36#define UATTR_IO 1
diff --git a/include/asm-mips/sn/sn0/hubio.h b/include/asm-mips/sn/sn0/hubio.h
index f314da21b97..ef91b336355 100644
--- a/include/asm-mips/sn/sn0/hubio.h
+++ b/include/asm-mips/sn/sn0/hubio.h
@@ -486,22 +486,6 @@ typedef union h1_icrba_u {
486#define ICRBN_A_CERR_SHFT 54 486#define ICRBN_A_CERR_SHFT 54
487#define ICRBN_A_ERR_MASK 0x3ff 487#define ICRBN_A_ERR_MASK 0x3ff
488 488
489#if 0 /* Disabled, this causes namespace polution and break allmodconfig */
490/*
491 * Easy access macros.
492 */
493#define a_error icrba_fields_s.error
494#define a_ecode icrba_fields_s.ecode
495#define a_lnetuce icrba_fields_s.lnetuce
496#define a_mark icrba_fields_s.mark
497#define a_xerr icrba_fields_s.xerr
498#define a_sidn icrba_fields_s.sidn
499#define a_tnum icrba_fields_s.tnum
500#define a_addr icrba_fields_s.addr
501#define a_valid icrba_fields_s.valid
502#define a_iow icrba_fields_s.iow
503#endif
504
505#endif /* !__ASSEMBLY__ */ 489#endif /* !__ASSEMBLY__ */
506 490
507#define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */ 491#define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */
diff --git a/include/asm-mips/sn/sn0/hubmd.h b/include/asm-mips/sn/sn0/hubmd.h
index f0100024188..14c225d8066 100644
--- a/include/asm-mips/sn/sn0/hubmd.h
+++ b/include/asm-mips/sn/sn0/hubmd.h
@@ -91,7 +91,7 @@
91#define MD_UREG1_14 0x2200f0 /* uController/UART 1 register */ 91#define MD_UREG1_14 0x2200f0 /* uController/UART 1 register */
92#define MD_UREG1_15 0x2200f8 /* uController/UART 1 register */ 92#define MD_UREG1_15 0x2200f8 /* uController/UART 1 register */
93 93
94#ifdef CONFIG_SGI_SN0_N_MODE 94#ifdef CONFIG_SGI_SN_N_MODE
95#define MD_MEM_BANKS 4 /* 4 banks of memory max in N mode */ 95#define MD_MEM_BANKS 4 /* 4 banks of memory max in N mode */
96#else 96#else
97#define MD_MEM_BANKS 8 /* 8 banks of memory max in M mode */ 97#define MD_MEM_BANKS 8 /* 8 banks of memory max in M mode */
diff --git a/include/asm-mips/sn/sn0/hubpi.h b/include/asm-mips/sn/sn0/hubpi.h
index 355bba8552e..e39f5f9da04 100644
--- a/include/asm-mips/sn/sn0/hubpi.h
+++ b/include/asm-mips/sn/sn0/hubpi.h
@@ -398,24 +398,6 @@ typedef u64 rtc_time_t;
398 398
399/* PI_RT_FILTER_CTRL mask and shift definitions */ 399/* PI_RT_FILTER_CTRL mask and shift definitions */
400 400
401#if 0
402/*
403 * XXX - This register's definition has changed, but it's only implemented
404 * in Hub 2.
405 */
406#define PRFC_DROP_COUNT_SHFT 27
407#define PRFC_DROP_COUNT_MASK (UINT64_CAST 0x3ff << 27)
408#define PRFC_DROP_CTR_SHFT 18
409#define PRFC_DROP_CTR_MASK (UINT64_CAST 0x1ff << 18)
410#define PRFC_MASK_ENABLE_SHFT 10
411#define PRFC_MASK_ENABLE_MASK (UINT64_CAST 0x7f << 10)
412#define PRFC_MASK_CTR_SHFT 2
413#define PRFC_MASK_CTR_MASK (UINT64_CAST 0xff << 2)
414#define PRFC_OFFSET_SHFT 0
415#define PRFC_OFFSET_MASK (UINT64_CAST 3)
416#endif /* 0 */
417
418
419/* 401/*
420 * Bits for NACK_CNT_A/B and NACK_CMP 402 * Bits for NACK_CNT_A/B and NACK_CMP
421 */ 403 */
diff --git a/include/asm-mips/sn/sn0/ip27.h b/include/asm-mips/sn/sn0/ip27.h
index ade0e974dd7..3c97e0855c8 100644
--- a/include/asm-mips/sn/sn0/ip27.h
+++ b/include/asm-mips/sn/sn0/ip27.h
@@ -6,7 +6,7 @@
6 * Derived from IRIX <sys/SN/SN0/IP27.h>. 6 * Derived from IRIX <sys/SN/SN0/IP27.h>.
7 * 7 *
8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc. 8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
9 * Copyright (C) 1999 by Ralf Baechle 9 * Copyright (C) 1999, 2006 by Ralf Baechle
10 */ 10 */
11#ifndef _ASM_SN_SN0_IP27_H 11#ifndef _ASM_SN_SN0_IP27_H
12#define _ASM_SN_SN0_IP27_H 12#define _ASM_SN_SN0_IP27_H
@@ -82,11 +82,4 @@
82#define SEND_NMI(_nasid, _slice) \ 82#define SEND_NMI(_nasid, _slice) \
83 REMOTE_HUB_S((_nasid), (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1) 83 REMOTE_HUB_S((_nasid), (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1)
84 84
85/* Sanity hazzard ... Below all the Origin hacks are following. */
86
87#define SN00_BRIDGE 0x9200000008000000
88#define SN00I_BRIDGE0 0x920000000b000000
89#define SN00I_BRIDGE1 0x920000000e000000
90#define SN00I_BRIDGE2 0x920000000f000000
91
92#endif /* _ASM_SN_SN0_IP27_H */ 85#endif /* _ASM_SN_SN0_IP27_H */
diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h
index b3bc698dfde..b9ba54d0dd3 100644
--- a/include/asm-mips/sni.h
+++ b/include/asm-mips/sni.h
@@ -15,9 +15,6 @@
15/* 15/*
16 * ASIC PCI registers for little endian configuration. 16 * ASIC PCI registers for little endian configuration.
17 */ 17 */
18#ifndef __MIPSEL__
19#error "Fix me for big endian"
20#endif
21#define PCIMT_UCONF 0xbfff0000 18#define PCIMT_UCONF 0xbfff0000
22#define PCIMT_IOADTIMEOUT2 0xbfff0008 19#define PCIMT_IOADTIMEOUT2 0xbfff0008
23#define PCIMT_IOMEMCONF 0xbfff0010 20#define PCIMT_IOMEMCONF 0xbfff0010
@@ -51,9 +48,9 @@
51#define PCIMT_PCI_CONF 0xbfff0100 48#define PCIMT_PCI_CONF 0xbfff0100
52 49
53/* 50/*
54 * Data port for the PCI bus. 51 * Data port for the PCI bus in IO space
55 */ 52 */
56#define PCIMT_CONFIG_DATA 0xb4000cfc 53#define PCIMT_CONFIG_DATA 0x0cfc
57 54
58/* 55/*
59 * Board specific registers 56 * Board specific registers
diff --git a/include/asm-mips/sparsemem.h b/include/asm-mips/sparsemem.h
new file mode 100644
index 00000000000..795ac6c2320
--- /dev/null
+++ b/include/asm-mips/sparsemem.h
@@ -0,0 +1,14 @@
1#ifndef _MIPS_SPARSEMEM_H
2#define _MIPS_SPARSEMEM_H
3#ifdef CONFIG_SPARSEMEM
4
5/*
6 * SECTION_SIZE_BITS 2^N: how big each section will be
7 * MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space
8 */
9#define SECTION_SIZE_BITS 28
10#define MAX_PHYSMEM_BITS 35
11
12#endif /* CONFIG_SPARSEMEM */
13#endif /* _MIPS_SPARSEMEM_H */
14
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h
index 9844f0c2dfe..3ac146c019c 100644
--- a/include/asm-mips/war.h
+++ b/include/asm-mips/war.h
@@ -171,7 +171,8 @@
171 * On the RM9000 there is a problem which makes the CreateDirtyExclusive 171 * On the RM9000 there is a problem which makes the CreateDirtyExclusive
172 * cache operation unusable on SMP systems. 172 * cache operation unusable on SMP systems.
173 */ 173 */
174#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) 174#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) || \
175 defined(CONFIG_BASLER_EXCITE)
175#define RM9000_CDEX_SMP_WAR 1 176#define RM9000_CDEX_SMP_WAR 1
176#endif 177#endif
177 178
@@ -181,7 +182,7 @@
181 * being fetched may case spurious exceptions. 182 * being fetched may case spurious exceptions.
182 */ 183 */
183#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \ 184#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \
184 defined(CONFIG_PMC_YOSEMITE) 185 defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE)
185#define ICACHE_REFILLS_WORKAROUND_WAR 1 186#define ICACHE_REFILLS_WORKAROUND_WAR 1
186#endif 187#endif
187 188
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-17 19:44:59 -0400