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Diffstat (limited to 'include/asm-mips/futex.h')
-rw-r--r--include/asm-mips/futex.h153
1 files changed, 123 insertions, 30 deletions
diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h
index d71d878990d..ed023eae067 100644
--- a/include/asm-mips/futex.h
+++ b/include/asm-mips/futex.h
@@ -6,6 +6,7 @@
6#include <linux/futex.h> 6#include <linux/futex.h>
7#include <asm/errno.h> 7#include <asm/errno.h>
8#include <asm/uaccess.h> 8#include <asm/uaccess.h>
9#include <asm/war.h>
9 10
10#ifdef CONFIG_SMP 11#ifdef CONFIG_SMP
11#define __FUTEX_SMP_SYNC " sync \n" 12#define __FUTEX_SMP_SYNC " sync \n"
@@ -15,30 +16,60 @@
15 16
16#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ 17#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
17{ \ 18{ \
18 __asm__ __volatile__( \ 19 if (cpu_has_llsc && R10000_LLSC_WAR) { \
19 " .set push \n" \ 20 __asm__ __volatile__( \
20 " .set noat \n" \ 21 " .set push \n" \
21 " .set mips3 \n" \ 22 " .set noat \n" \
22 "1: ll %1, (%3) # __futex_atomic_op1 \n" \ 23 " .set mips3 \n" \
23 " .set mips0 \n" \ 24 "1: ll %1, %4 # __futex_atomic_op \n" \
24 " " insn " \n" \ 25 " .set mips0 \n" \
25 " .set mips3 \n" \ 26 " " insn " \n" \
26 "2: sc $1, (%3) \n" \ 27 " .set mips3 \n" \
27 " beqzl $1, 1b \n" \ 28 "2: sc $1, %2 \n" \
28 __FUTEX_SMP_SYNC \ 29 " beqzl $1, 1b \n" \
29 "3: \n" \ 30 __FUTEX_SMP_SYNC \
30 " .set pop \n" \ 31 "3: \n" \
31 " .set mips0 \n" \ 32 " .set pop \n" \
32 " .section .fixup,\"ax\" \n" \ 33 " .set mips0 \n" \
33 "4: li %0, %5 \n" \ 34 " .section .fixup,\"ax\" \n" \
34 " j 2b \n" \ 35 "4: li %0, %6 \n" \
35 " .previous \n" \ 36 " j 2b \n" \
36 " .section __ex_table,\"a\" \n" \ 37 " .previous \n" \
37 " "__UA_ADDR "\t1b, 4b \n" \ 38 " .section __ex_table,\"a\" \n" \
38 " "__UA_ADDR "\t2b, 4b \n" \ 39 " "__UA_ADDR "\t1b, 4b \n" \
39 " .previous \n" \ 40 " "__UA_ADDR "\t2b, 4b \n" \
40 : "=r" (ret), "=r" (oldval) \ 41 " .previous \n" \
41 : "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT)); \ 42 : "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \
43 : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \
44 : "memory"); \
45 } else if (cpu_has_llsc) { \
46 __asm__ __volatile__( \
47 " .set push \n" \
48 " .set noat \n" \
49 " .set mips3 \n" \
50 "1: ll %1, %4 # __futex_atomic_op \n" \
51 " .set mips0 \n" \
52 " " insn " \n" \
53 " .set mips3 \n" \
54 "2: sc $1, %2 \n" \
55 " beqz $1, 1b \n" \
56 __FUTEX_SMP_SYNC \
57 "3: \n" \
58 " .set pop \n" \
59 " .set mips0 \n" \
60 " .section .fixup,\"ax\" \n" \
61 "4: li %0, %6 \n" \
62 " j 2b \n" \
63 " .previous \n" \
64 " .section __ex_table,\"a\" \n" \
65 " "__UA_ADDR "\t1b, 4b \n" \
66 " "__UA_ADDR "\t2b, 4b \n" \
67 " .previous \n" \
68 : "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \
69 : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \
70 : "memory"); \
71 } else \
72 ret = -ENOSYS; \
42} 73}
43 74
44static inline int 75static inline int
@@ -59,23 +90,23 @@ futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
59 90
60 switch (op) { 91 switch (op) {
61 case FUTEX_OP_SET: 92 case FUTEX_OP_SET:
62 __futex_atomic_op("move $1, %z4", ret, oldval, uaddr, oparg); 93 __futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg);
63 break; 94 break;
64 95
65 case FUTEX_OP_ADD: 96 case FUTEX_OP_ADD:
66 __futex_atomic_op("addu $1, %1, %z4", 97 __futex_atomic_op("addu $1, %1, %z5",
67 ret, oldval, uaddr, oparg); 98 ret, oldval, uaddr, oparg);
68 break; 99 break;
69 case FUTEX_OP_OR: 100 case FUTEX_OP_OR:
70 __futex_atomic_op("or $1, %1, %z4", 101 __futex_atomic_op("or $1, %1, %z5",
71 ret, oldval, uaddr, oparg); 102 ret, oldval, uaddr, oparg);
72 break; 103 break;
73 case FUTEX_OP_ANDN: 104 case FUTEX_OP_ANDN:
74 __futex_atomic_op("and $1, %1, %z4", 105 __futex_atomic_op("and $1, %1, %z5",
75 ret, oldval, uaddr, ~oparg); 106 ret, oldval, uaddr, ~oparg);
76 break; 107 break;
77 case FUTEX_OP_XOR: 108 case FUTEX_OP_XOR:
78 __futex_atomic_op("xor $1, %1, %z4", 109 __futex_atomic_op("xor $1, %1, %z5",
79 ret, oldval, uaddr, oparg); 110 ret, oldval, uaddr, oparg);
80 break; 111 break;
81 default: 112 default:
@@ -101,7 +132,69 @@ futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
101static inline int 132static inline int
102futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval) 133futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
103{ 134{
104 return -ENOSYS; 135 int retval;
136
137 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
138 return -EFAULT;
139
140 if (cpu_has_llsc && R10000_LLSC_WAR) {
141 __asm__ __volatile__(
142 "# futex_atomic_cmpxchg_inatomic \n"
143 " .set push \n"
144 " .set noat \n"
145 " .set mips3 \n"
146 "1: ll %0, %2 \n"
147 " bne %0, %z3, 3f \n"
148 " .set mips0 \n"
149 " move $1, %z4 \n"
150 " .set mips3 \n"
151 "2: sc $1, %1 \n"
152 " beqzl $1, 1b \n"
153 __FUTEX_SMP_SYNC
154 "3: \n"
155 " .set pop \n"
156 " .section .fixup,\"ax\" \n"
157 "4: li %0, %5 \n"
158 " j 3b \n"
159 " .previous \n"
160 " .section __ex_table,\"a\" \n"
161 " "__UA_ADDR "\t1b, 4b \n"
162 " "__UA_ADDR "\t2b, 4b \n"
163 " .previous \n"
164 : "=&r" (retval), "=R" (*uaddr)
165 : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
166 : "memory");
167 } else if (cpu_has_llsc) {
168 __asm__ __volatile__(
169 "# futex_atomic_cmpxchg_inatomic \n"
170 " .set push \n"
171 " .set noat \n"
172 " .set mips3 \n"
173 "1: ll %0, %2 \n"
174 " bne %0, %z3, 3f \n"
175 " .set mips0 \n"
176 " move $1, %z4 \n"
177 " .set mips3 \n"
178 "2: sc $1, %1 \n"
179 " beqz $1, 1b \n"
180 __FUTEX_SMP_SYNC
181 "3: \n"
182 " .set pop \n"
183 " .section .fixup,\"ax\" \n"
184 "4: li %0, %5 \n"
185 " j 3b \n"
186 " .previous \n"
187 " .section __ex_table,\"a\" \n"
188 " "__UA_ADDR "\t1b, 4b \n"
189 " "__UA_ADDR "\t2b, 4b \n"
190 " .previous \n"
191 : "=&r" (retval), "=R" (*uaddr)
192 : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
193 : "memory");
194 } else
195 return -ENOSYS;
196
197 return retval;
105} 198}
106 199
107#endif 200#endif
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