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-rw-r--r--include/asm-arm/arch-s3c2410/anubis-map.h10
-rw-r--r--include/asm-arm/arch-s3c2410/fb.h70
-rw-r--r--include/asm-arm/arch-s3c2410/hardware.h7
-rw-r--r--include/asm-arm/arch-s3c2410/io.h60
-rw-r--r--include/asm-arm/arch-s3c2410/regs-clock.h21
-rw-r--r--include/asm-arm/arch-s3c2410/regs-gpio.h6
-rw-r--r--include/asm-arm/arch-s3c2410/regs-lcd.h17
7 files changed, 166 insertions, 25 deletions
diff --git a/include/asm-arm/arch-s3c2410/anubis-map.h b/include/asm-arm/arch-s3c2410/anubis-map.h
index 97741d6e506..d529ffda859 100644
--- a/include/asm-arm/arch-s3c2410/anubis-map.h
+++ b/include/asm-arm/arch-s3c2410/anubis-map.h
@@ -20,22 +20,22 @@
20 20
21/* start peripherals off after the S3C2410 */ 21/* start peripherals off after the S3C2410 */
22 22
23#define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x02000000)) 23#define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000))
24 24
25#define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26)) 25#define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26))
26 26
27/* we put the CPLD registers next, to get them out of the way */ 27/* we put the CPLD registers next, to get them out of the way */
28 28
29#define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) /* 0x01300000 */ 29#define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) /* 0x01800000 */
30#define ANUBIS_PA_CTRL1 (ANUBIS_PA_CPLD) 30#define ANUBIS_PA_CTRL1 (ANUBIS_PA_CPLD)
31 31
32#define ANUBIS_VA_CTRL2 ANUBIS_IOADDR(0x00100000) /* 0x01400000 */ 32#define ANUBIS_VA_CTRL2 ANUBIS_IOADDR(0x00100000) /* 0x01900000 */
33#define ANUBIS_PA_CTRL2 (ANUBIS_PA_CPLD) 33#define ANUBIS_PA_CTRL2 (ANUBIS_PA_CPLD)
34 34
35#define ANUBIS_VA_CTRL3 ANUBIS_IOADDR(0x00200000) /* 0x01500000 */ 35#define ANUBIS_VA_CTRL3 ANUBIS_IOADDR(0x00200000) /* 0x01A00000 */
36#define ANUBIS_PA_CTRL3 (ANUBIS_PA_CPLD) 36#define ANUBIS_PA_CTRL3 (ANUBIS_PA_CPLD)
37 37
38#define ANUBIS_VA_CTRL4 ANUBIS_IOADDR(0x00300000) /* 0x01600000 */ 38#define ANUBIS_VA_CTRL4 ANUBIS_IOADDR(0x00300000) /* 0x01B00000 */
39#define ANUBIS_PA_CTRL4 (ANUBIS_PA_CPLD) 39#define ANUBIS_PA_CTRL4 (ANUBIS_PA_CPLD)
40 40
41#define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000) 41#define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000)
diff --git a/include/asm-arm/arch-s3c2410/fb.h b/include/asm-arm/arch-s3c2410/fb.h
new file mode 100644
index 00000000000..4790491ba9d
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/fb.h
@@ -0,0 +1,70 @@
1/* linux/include/asm/arch-s3c2410/fb.h
2 *
3 * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org>
4 *
5 * Inspired by pxafb.h
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 *
12 * Changelog:
13 * 07-Sep-2004 RTP Created file
14 * 03-Nov-2004 BJD Updated and minor cleanups
15 * 03-Aug-2005 RTP Renamed to fb.h
16 * 26-Oct-2005 BJD Changed name of platdata init
17*/
18
19#ifndef __ASM_ARM_FB_H
20#define __ASM_ARM_FB_H
21
22#include <asm/arch/regs-lcd.h>
23
24struct s3c2410fb_val {
25 unsigned int defval;
26 unsigned int min;
27 unsigned int max;
28};
29
30struct s3c2410fb_hw {
31 unsigned long lcdcon1;
32 unsigned long lcdcon2;
33 unsigned long lcdcon3;
34 unsigned long lcdcon4;
35 unsigned long lcdcon5;
36};
37
38struct s3c2410fb_mach_info {
39 unsigned char fixed_syncs; /* do not update sync/border */
40
41 /* Screen size */
42 int width;
43 int height;
44
45 /* Screen info */
46 struct s3c2410fb_val xres;
47 struct s3c2410fb_val yres;
48 struct s3c2410fb_val bpp;
49
50 /* lcd configuration registers */
51 struct s3c2410fb_hw regs;
52
53 /* GPIOs */
54
55 unsigned long gpcup;
56 unsigned long gpcup_mask;
57 unsigned long gpccon;
58 unsigned long gpccon_mask;
59 unsigned long gpdup;
60 unsigned long gpdup_mask;
61 unsigned long gpdcon;
62 unsigned long gpdcon_mask;
63
64 /* lpc3600 control register */
65 unsigned long lpcsel;
66};
67
68extern void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *);
69
70#endif /* __ASM_ARM_FB_H */
diff --git a/include/asm-arm/arch-s3c2410/hardware.h b/include/asm-arm/arch-s3c2410/hardware.h
index 48a39918a76..1c9de29cafe 100644
--- a/include/asm-arm/arch-s3c2410/hardware.h
+++ b/include/asm-arm/arch-s3c2410/hardware.h
@@ -92,6 +92,13 @@ extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
92 92
93extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg); 93extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
94 94
95#ifdef CONFIG_CPU_S3C2440
96
97extern int s3c2440_set_dsc(unsigned int pin, unsigned int value);
98
99#endif /* CONFIG_CPU_S3C2440 */
100
101
95#endif /* __ASSEMBLY__ */ 102#endif /* __ASSEMBLY__ */
96 103
97#include <asm/sizes.h> 104#include <asm/sizes.h>
diff --git a/include/asm-arm/arch-s3c2410/io.h b/include/asm-arm/arch-s3c2410/io.h
index 418233a7ee6..16fbc8afffd 100644
--- a/include/asm-arm/arch-s3c2410/io.h
+++ b/include/asm-arm/arch-s3c2410/io.h
@@ -9,12 +9,14 @@
9 * 06-Dec-1997 RMK Created. 9 * 06-Dec-1997 RMK Created.
10 * 02-Sep-2003 BJD Modified for S3C2410 10 * 02-Sep-2003 BJD Modified for S3C2410
11 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA 11 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
12 * 12 * 13-Oct-2005 BJD Fixed problems with LDRH/STRH offset range
13 */ 13 */
14 14
15#ifndef __ASM_ARM_ARCH_IO_H 15#ifndef __ASM_ARM_ARCH_IO_H
16#define __ASM_ARM_ARCH_IO_H 16#define __ASM_ARM_ARCH_IO_H
17 17
18#include <asm/hardware.h>
19
18#define IO_SPACE_LIMIT 0xffffffff 20#define IO_SPACE_LIMIT 0xffffffff
19 21
20/* 22/*
@@ -97,7 +99,7 @@ DECLARE_IO(int,l,"")
97 else \ 99 else \
98 __asm__ __volatile__( \ 100 __asm__ __volatile__( \
99 "strb %0, [%1, #0] @ outbc" \ 101 "strb %0, [%1, #0] @ outbc" \
100 : : "r" (value), "r" ((port))); \ 102 : : "r" (value), "r" ((port))); \
101}) 103})
102 104
103#define __inbc(port) \ 105#define __inbc(port) \
@@ -110,35 +112,61 @@ DECLARE_IO(int,l,"")
110 else \ 112 else \
111 __asm__ __volatile__( \ 113 __asm__ __volatile__( \
112 "ldrb %0, [%1, #0] @ inbc" \ 114 "ldrb %0, [%1, #0] @ inbc" \
113 : "=r" (result) : "r" ((port))); \ 115 : "=r" (result) : "r" ((port))); \
114 result; \ 116 result; \
115}) 117})
116 118
117#define __outwc(value,port) \ 119#define __outwc(value,port) \
118({ \ 120({ \
119 unsigned long v = value; \ 121 unsigned long v = value; \
120 if (__PORT_PCIO((port))) \ 122 if (__PORT_PCIO((port))) { \
121 __asm__ __volatile__( \ 123 if ((port) < 256 && (port) > -256) \
122 "strh %0, [%1, %2] @ outwc" \ 124 __asm__ __volatile__( \
123 : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \ 125 "strh %0, [%1, %2] @ outwc" \
124 else \ 126 : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \
127 else if ((port) > 0) \
128 __asm__ __volatile__( \
129 "strh %0, [%1, %2] @ outwc" \
130 : : "r" (v), \
131 "r" (PCIO_BASE + ((port) & ~0xff)), \
132 "Jr" (((port) & 0xff))); \
133 else \
134 __asm__ __volatile__( \
135 "strh %0, [%1, #0] @ outwc" \
136 : : "r" (v), \
137 "r" (PCIO_BASE + (port))); \
138 } else \
125 __asm__ __volatile__( \ 139 __asm__ __volatile__( \
126 "strh %0, [%1, #0] @ outwc" \ 140 "strh %0, [%1, #0] @ outwc" \
127 : : "r" (v), "r" ((port))); \ 141 : : "r" (v), "r" ((port))); \
128}) 142})
129 143
130#define __inwc(port) \ 144#define __inwc(port) \
131({ \ 145({ \
132 unsigned short result; \ 146 unsigned short result; \
133 if (__PORT_PCIO((port))) \ 147 if (__PORT_PCIO((port))) { \
134 __asm__ __volatile__( \ 148 if ((port) < 256 && (port) > -256 ) \
135 "ldrh %0, [%1, %2] @ inwc" \ 149 __asm__ __volatile__( \
136 : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \ 150 "ldrh %0, [%1, %2] @ inwc" \
137 else \ 151 : "=r" (result) \
152 : "r" (PCIO_BASE), \
153 "Jr" ((port))); \
154 else if ((port) > 0) \
155 __asm__ __volatile__( \
156 "ldrh %0, [%1, %2] @ inwc" \
157 : "=r" (result) \
158 : "r" (PCIO_BASE + ((port) & ~0xff)), \
159 "Jr" (((port) & 0xff))); \
160 else \
161 __asm__ __volatile__( \
162 "ldrh %0, [%1, #0] @ inwc" \
163 : "=r" (result) \
164 : "r" (PCIO_BASE + ((port)))); \
165 } else \
138 __asm__ __volatile__( \ 166 __asm__ __volatile__( \
139 "ldrh %0, [%1, #0] @ inwc" \ 167 "ldrh %0, [%1, #0] @ inwc" \
140 : "=r" (result) : "r" ((port))); \ 168 : "=r" (result) : "r" ((port))); \
141 result; \ 169 result; \
142}) 170})
143 171
144#define __outlc(value,port) \ 172#define __outlc(value,port) \
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index 16f4c3cc138..34360706e01 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -18,7 +18,9 @@
18 * 10-Feb-2005 Ben Dooks Fixed CAMDIVN address (Guillaume Gourat) 18 * 10-Feb-2005 Ben Dooks Fixed CAMDIVN address (Guillaume Gourat)
19 * 10-Mar-2005 Lucas Villa Real Changed S3C2410_VA to S3C24XX_VA 19 * 10-Mar-2005 Lucas Villa Real Changed S3C2410_VA to S3C24XX_VA
20 * 27-Aug-2005 Ben Dooks Add clock-slow info 20 * 27-Aug-2005 Ben Dooks Add clock-slow info
21 */ 21 * 20-Oct-2005 Ben Dooks Fixed overflow in PLL (Guillaume Gourat)
22 * 20-Oct-2005 Ben Dooks Add masks for DCLK (Guillaume Gourat)
23*/
22 24
23#ifndef __ASM_ARM_REGS_CLOCK 25#ifndef __ASM_ARM_REGS_CLOCK
24#define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $" 26#define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $"
@@ -66,11 +68,16 @@
66#define S3C2410_DCLKCON_DCLK0_UCLK (1<<1) 68#define S3C2410_DCLKCON_DCLK0_UCLK (1<<1)
67#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4) 69#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
68#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8) 70#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
71#define S3C2410_DCLKCON_DCLK0_DIV_MASK ((0xf)<<4)
72#define S3C2410_DCLKCON_DCLK0_CMP_MASK ((0xf)<<8)
69 73
70#define S3C2410_DCLKCON_DCLK1EN (1<<16) 74#define S3C2410_DCLKCON_DCLK1EN (1<<16)
71#define S3C2410_DCLKCON_DCLK1_PCLK (0<<17) 75#define S3C2410_DCLKCON_DCLK1_PCLK (0<<17)
72#define S3C2410_DCLKCON_DCLK1_UCLK (1<<17) 76#define S3C2410_DCLKCON_DCLK1_UCLK (1<<17)
73#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20) 77#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
78#define S3C2410_DCLKCON_DCLK1_CMP(x) (((x) - 1) <<24)
79#define S3C2410_DCLKCON_DCLK1_DIV_MASK ((0xf) <<20)
80#define S3C2410_DCLKCON_DCLK1_CMP_MASK ((0xf) <<24)
74 81
75#define S3C2410_CLKDIVN_PDIVN (1<<0) 82#define S3C2410_CLKDIVN_PDIVN (1<<0)
76#define S3C2410_CLKDIVN_HDIVN (1<<1) 83#define S3C2410_CLKDIVN_HDIVN (1<<1)
@@ -83,10 +90,13 @@
83 90
84#ifndef __ASSEMBLY__ 91#ifndef __ASSEMBLY__
85 92
93#include <asm/div64.h>
94
86static inline unsigned int 95static inline unsigned int
87s3c2410_get_pll(int pllval, int baseclk) 96s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
88{ 97{
89 int mdiv, pdiv, sdiv; 98 unsigned int mdiv, pdiv, sdiv;
99 uint64_t fvco;
90 100
91 mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT; 101 mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
92 pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT; 102 pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
@@ -96,7 +106,10 @@ s3c2410_get_pll(int pllval, int baseclk)
96 pdiv &= S3C2410_PLLCON_PDIVMASK; 106 pdiv &= S3C2410_PLLCON_PDIVMASK;
97 sdiv &= S3C2410_PLLCON_SDIVMASK; 107 sdiv &= S3C2410_PLLCON_SDIVMASK;
98 108
99 return (baseclk * (mdiv + 8)) / ((pdiv + 2) << sdiv); 109 fvco = (uint64_t)baseclk * (mdiv + 8);
110 do_div(fvco, (pdiv + 2) << sdiv);
111
112 return (unsigned int)fvco;
100} 113}
101 114
102#endif /* __ASSEMBLY__ */ 115#endif /* __ASSEMBLY__ */
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index 2053cbacffc..cb33d57c146 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -20,6 +20,7 @@
20 * 18-11-2004 BJD Added S3C2440 AC97 controls 20 * 18-11-2004 BJD Added S3C2440 AC97 controls
21 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA 21 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
22 * 28-Mar-2005 LCVR Fixed definition of GPB10 22 * 28-Mar-2005 LCVR Fixed definition of GPB10
23 * 26-Oct-2005 BJD Added generic configuration types
23*/ 24*/
24 25
25 26
@@ -43,6 +44,11 @@
43/* general configuration options */ 44/* general configuration options */
44 45
45#define S3C2410_GPIO_LEAVE (0xFFFFFFFF) 46#define S3C2410_GPIO_LEAVE (0xFFFFFFFF)
47#define S3C2410_GPIO_INPUT (0xFFFFFFF0)
48#define S3C2410_GPIO_OUTPUT (0xFFFFFFF1)
49#define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */
50#define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* not available on A */
51#define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */
46 52
47/* configure GPIO ports A..G */ 53/* configure GPIO ports A..G */
48 54
diff --git a/include/asm-arm/arch-s3c2410/regs-lcd.h b/include/asm-arm/arch-s3c2410/regs-lcd.h
index 7f882ea92b2..b6b1b4e8bbe 100644
--- a/include/asm-arm/arch-s3c2410/regs-lcd.h
+++ b/include/asm-arm/arch-s3c2410/regs-lcd.h
@@ -51,21 +51,32 @@
51 51
52#define S3C2410_LCDCON1_ENVID (1) 52#define S3C2410_LCDCON1_ENVID (1)
53 53
54#define S3C2410_LCDCON1_MODEMASK 0x1E
55
54#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) 56#define S3C2410_LCDCON2_VBPD(x) ((x) << 24)
55#define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14) 57#define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14)
56#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) 58#define S3C2410_LCDCON2_VFPD(x) ((x) << 6)
57#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) 59#define S3C2410_LCDCON2_VSPW(x) ((x) << 0)
58 60
61#define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF)
62#define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF)
63#define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F)
64
59#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) 65#define S3C2410_LCDCON3_HBPD(x) ((x) << 19)
60#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) 66#define S3C2410_LCDCON3_WDLY(x) ((x) << 19)
61#define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8) 67#define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8)
62#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) 68#define S3C2410_LCDCON3_HFPD(x) ((x) << 0)
63#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0) 69#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
64 70
71#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
72#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF)
73
65#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) 74#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
66#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) 75#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
67#define S3C2410_LCDCON4_WLH(x) ((x) << 0) 76#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
68 77
78#define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF)
79
69#define S3C2410_LCDCON5_BPP24BL (1<<12) 80#define S3C2410_LCDCON5_BPP24BL (1<<12)
70#define S3C2410_LCDCON5_FRM565 (1<<11) 81#define S3C2410_LCDCON5_FRM565 (1<<11)
71#define S3C2410_LCDCON5_INVVCLK (1<<10) 82#define S3C2410_LCDCON5_INVVCLK (1<<10)
@@ -100,10 +111,16 @@
100#define S3C2410_DITHMODE S3C2410_LCDREG(0x4C) 111#define S3C2410_DITHMODE S3C2410_LCDREG(0x4C)
101#define S3C2410_TPAL S3C2410_LCDREG(0x50) 112#define S3C2410_TPAL S3C2410_LCDREG(0x50)
102 113
114#define S3C2410_TPAL_EN (1<<24)
115
103/* interrupt info */ 116/* interrupt info */
104#define S3C2410_LCDINTPND S3C2410_LCDREG(0x54) 117#define S3C2410_LCDINTPND S3C2410_LCDREG(0x54)
105#define S3C2410_LCDSRCPND S3C2410_LCDREG(0x58) 118#define S3C2410_LCDSRCPND S3C2410_LCDREG(0x58)
106#define S3C2410_LCDINTMSK S3C2410_LCDREG(0x5C) 119#define S3C2410_LCDINTMSK S3C2410_LCDREG(0x5C)
120#define S3C2410_LCDINT_FIWSEL (1<<2)
121#define S3C2410_LCDINT_FRSYNC (1<<1)
122#define S3C2410_LCDINT_FICNT (1<<0)
123
107#define S3C2410_LPCSEL S3C2410_LCDREG(0x60) 124#define S3C2410_LPCSEL S3C2410_LCDREG(0x60)
108 125
109#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4)) 126#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4))
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