diff options
Diffstat (limited to 'include/asm-arm/arch-s3c2410/regs-clock.h')
-rw-r--r-- | include/asm-arm/arch-s3c2410/regs-clock.h | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h index 16f4c3cc138..34360706e01 100644 --- a/include/asm-arm/arch-s3c2410/regs-clock.h +++ b/include/asm-arm/arch-s3c2410/regs-clock.h | |||
@@ -18,7 +18,9 @@ | |||
18 | * 10-Feb-2005 Ben Dooks Fixed CAMDIVN address (Guillaume Gourat) | 18 | * 10-Feb-2005 Ben Dooks Fixed CAMDIVN address (Guillaume Gourat) |
19 | * 10-Mar-2005 Lucas Villa Real Changed S3C2410_VA to S3C24XX_VA | 19 | * 10-Mar-2005 Lucas Villa Real Changed S3C2410_VA to S3C24XX_VA |
20 | * 27-Aug-2005 Ben Dooks Add clock-slow info | 20 | * 27-Aug-2005 Ben Dooks Add clock-slow info |
21 | */ | 21 | * 20-Oct-2005 Ben Dooks Fixed overflow in PLL (Guillaume Gourat) |
22 | * 20-Oct-2005 Ben Dooks Add masks for DCLK (Guillaume Gourat) | ||
23 | */ | ||
22 | 24 | ||
23 | #ifndef __ASM_ARM_REGS_CLOCK | 25 | #ifndef __ASM_ARM_REGS_CLOCK |
24 | #define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $" | 26 | #define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $" |
@@ -66,11 +68,16 @@ | |||
66 | #define S3C2410_DCLKCON_DCLK0_UCLK (1<<1) | 68 | #define S3C2410_DCLKCON_DCLK0_UCLK (1<<1) |
67 | #define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4) | 69 | #define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4) |
68 | #define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8) | 70 | #define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8) |
71 | #define S3C2410_DCLKCON_DCLK0_DIV_MASK ((0xf)<<4) | ||
72 | #define S3C2410_DCLKCON_DCLK0_CMP_MASK ((0xf)<<8) | ||
69 | 73 | ||
70 | #define S3C2410_DCLKCON_DCLK1EN (1<<16) | 74 | #define S3C2410_DCLKCON_DCLK1EN (1<<16) |
71 | #define S3C2410_DCLKCON_DCLK1_PCLK (0<<17) | 75 | #define S3C2410_DCLKCON_DCLK1_PCLK (0<<17) |
72 | #define S3C2410_DCLKCON_DCLK1_UCLK (1<<17) | 76 | #define S3C2410_DCLKCON_DCLK1_UCLK (1<<17) |
73 | #define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20) | 77 | #define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20) |
78 | #define S3C2410_DCLKCON_DCLK1_CMP(x) (((x) - 1) <<24) | ||
79 | #define S3C2410_DCLKCON_DCLK1_DIV_MASK ((0xf) <<20) | ||
80 | #define S3C2410_DCLKCON_DCLK1_CMP_MASK ((0xf) <<24) | ||
74 | 81 | ||
75 | #define S3C2410_CLKDIVN_PDIVN (1<<0) | 82 | #define S3C2410_CLKDIVN_PDIVN (1<<0) |
76 | #define S3C2410_CLKDIVN_HDIVN (1<<1) | 83 | #define S3C2410_CLKDIVN_HDIVN (1<<1) |
@@ -83,10 +90,13 @@ | |||
83 | 90 | ||
84 | #ifndef __ASSEMBLY__ | 91 | #ifndef __ASSEMBLY__ |
85 | 92 | ||
93 | #include <asm/div64.h> | ||
94 | |||
86 | static inline unsigned int | 95 | static inline unsigned int |
87 | s3c2410_get_pll(int pllval, int baseclk) | 96 | s3c2410_get_pll(unsigned int pllval, unsigned int baseclk) |
88 | { | 97 | { |
89 | int mdiv, pdiv, sdiv; | 98 | unsigned int mdiv, pdiv, sdiv; |
99 | uint64_t fvco; | ||
90 | 100 | ||
91 | mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT; | 101 | mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT; |
92 | pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT; | 102 | pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT; |
@@ -96,7 +106,10 @@ s3c2410_get_pll(int pllval, int baseclk) | |||
96 | pdiv &= S3C2410_PLLCON_PDIVMASK; | 106 | pdiv &= S3C2410_PLLCON_PDIVMASK; |
97 | sdiv &= S3C2410_PLLCON_SDIVMASK; | 107 | sdiv &= S3C2410_PLLCON_SDIVMASK; |
98 | 108 | ||
99 | return (baseclk * (mdiv + 8)) / ((pdiv + 2) << sdiv); | 109 | fvco = (uint64_t)baseclk * (mdiv + 8); |
110 | do_div(fvco, (pdiv + 2) << sdiv); | ||
111 | |||
112 | return (unsigned int)fvco; | ||
100 | } | 113 | } |
101 | 114 | ||
102 | #endif /* __ASSEMBLY__ */ | 115 | #endif /* __ASSEMBLY__ */ |