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-rw-r--r--drivers/edac/amd64_edac.c270
-rw-r--r--drivers/edac/amd64_edac_inj.c6
-rw-r--r--drivers/edac/amd76x_edac.c14
-rw-r--r--drivers/edac/cpc925_edac.c22
-rw-r--r--drivers/edac/e752x_edac.c39
-rw-r--r--drivers/edac/e7xxx_edac.c35
-rw-r--r--drivers/edac/edac_core.h10
-rw-r--r--drivers/edac/edac_device.c47
-rw-r--r--drivers/edac/edac_device_sysfs.c70
-rw-r--r--drivers/edac/edac_mc.c121
-rw-r--r--drivers/edac/edac_mc_sysfs.c37
-rw-r--r--drivers/edac/edac_module.c2
-rw-r--r--drivers/edac/edac_pci.c26
-rw-r--r--drivers/edac/edac_pci_sysfs.c48
-rw-r--r--drivers/edac/i3000_edac.c25
-rw-r--r--drivers/edac/i3200_edac.c26
-rw-r--r--drivers/edac/i5000_edac.c163
-rw-r--r--drivers/edac/i5100_edac.c4
-rw-r--r--drivers/edac/i5400_edac.c165
-rw-r--r--drivers/edac/i7300_edac.c151
-rw-r--r--drivers/edac/i7core_edac.c144
-rw-r--r--drivers/edac/i82443bxgx_edac.c35
-rw-r--r--drivers/edac/i82860_edac.c23
-rw-r--r--drivers/edac/i82875p_edac.c27
-rw-r--r--drivers/edac/i82975x_edac.c29
-rw-r--r--drivers/edac/mpc85xx_edac.c22
-rw-r--r--drivers/edac/mv64x60_edac.c26
-rw-r--r--drivers/edac/r82600_edac.c30
-rw-r--r--drivers/edac/sb_edac.c240
-rw-r--r--drivers/edac/x38_edac.c26
30 files changed, 921 insertions, 962 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 9fbced7f65e..b4752955473 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -321,8 +321,8 @@ found:
321 return edac_mc_find((int)node_id); 321 return edac_mc_find((int)node_id);
322 322
323err_no_match: 323err_no_match:
324 debugf2("sys_addr 0x%lx doesn't match any node\n", 324 edac_dbg(2, "sys_addr 0x%lx doesn't match any node\n",
325 (unsigned long)sys_addr); 325 (unsigned long)sys_addr);
326 326
327 return NULL; 327 return NULL;
328} 328}
@@ -393,15 +393,15 @@ static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr)
393 mask = ~mask; 393 mask = ~mask;
394 394
395 if ((input_addr & mask) == (base & mask)) { 395 if ((input_addr & mask) == (base & mask)) {
396 debugf2("InputAddr 0x%lx matches csrow %d (node %d)\n", 396 edac_dbg(2, "InputAddr 0x%lx matches csrow %d (node %d)\n",
397 (unsigned long)input_addr, csrow, 397 (unsigned long)input_addr, csrow,
398 pvt->mc_node_id); 398 pvt->mc_node_id);
399 399
400 return csrow; 400 return csrow;
401 } 401 }
402 } 402 }
403 debugf2("no matching csrow for InputAddr 0x%lx (MC node %d)\n", 403 edac_dbg(2, "no matching csrow for InputAddr 0x%lx (MC node %d)\n",
404 (unsigned long)input_addr, pvt->mc_node_id); 404 (unsigned long)input_addr, pvt->mc_node_id);
405 405
406 return -1; 406 return -1;
407} 407}
@@ -430,20 +430,20 @@ int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
430 430
431 /* only revE and later have the DRAM Hole Address Register */ 431 /* only revE and later have the DRAM Hole Address Register */
432 if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_E) { 432 if (boot_cpu_data.x86 == 0xf && pvt->ext_model < K8_REV_E) {
433 debugf1(" revision %d for node %d does not support DHAR\n", 433 edac_dbg(1, " revision %d for node %d does not support DHAR\n",
434 pvt->ext_model, pvt->mc_node_id); 434 pvt->ext_model, pvt->mc_node_id);
435 return 1; 435 return 1;
436 } 436 }
437 437
438 /* valid for Fam10h and above */ 438 /* valid for Fam10h and above */
439 if (boot_cpu_data.x86 >= 0x10 && !dhar_mem_hoist_valid(pvt)) { 439 if (boot_cpu_data.x86 >= 0x10 && !dhar_mem_hoist_valid(pvt)) {
440 debugf1(" Dram Memory Hoisting is DISABLED on this system\n"); 440 edac_dbg(1, " Dram Memory Hoisting is DISABLED on this system\n");
441 return 1; 441 return 1;
442 } 442 }
443 443
444 if (!dhar_valid(pvt)) { 444 if (!dhar_valid(pvt)) {
445 debugf1(" Dram Memory Hoisting is DISABLED on this node %d\n", 445 edac_dbg(1, " Dram Memory Hoisting is DISABLED on this node %d\n",
446 pvt->mc_node_id); 446 pvt->mc_node_id);
447 return 1; 447 return 1;
448 } 448 }
449 449
@@ -475,9 +475,9 @@ int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
475 else 475 else
476 *hole_offset = k8_dhar_offset(pvt); 476 *hole_offset = k8_dhar_offset(pvt);
477 477
478 debugf1(" DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n", 478 edac_dbg(1, " DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n",
479 pvt->mc_node_id, (unsigned long)*hole_base, 479 pvt->mc_node_id, (unsigned long)*hole_base,
480 (unsigned long)*hole_offset, (unsigned long)*hole_size); 480 (unsigned long)*hole_offset, (unsigned long)*hole_size);
481 481
482 return 0; 482 return 0;
483} 483}
@@ -528,10 +528,9 @@ static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr)
528 /* use DHAR to translate SysAddr to DramAddr */ 528 /* use DHAR to translate SysAddr to DramAddr */
529 dram_addr = sys_addr - hole_offset; 529 dram_addr = sys_addr - hole_offset;
530 530
531 debugf2("using DHAR to translate SysAddr 0x%lx to " 531 edac_dbg(2, "using DHAR to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
532 "DramAddr 0x%lx\n", 532 (unsigned long)sys_addr,
533 (unsigned long)sys_addr, 533 (unsigned long)dram_addr);
534 (unsigned long)dram_addr);
535 534
536 return dram_addr; 535 return dram_addr;
537 } 536 }
@@ -548,9 +547,8 @@ static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr)
548 */ 547 */
549 dram_addr = (sys_addr & GENMASK(0, 39)) - dram_base; 548 dram_addr = (sys_addr & GENMASK(0, 39)) - dram_base;
550 549
551 debugf2("using DRAM Base register to translate SysAddr 0x%lx to " 550 edac_dbg(2, "using DRAM Base register to translate SysAddr 0x%lx to DramAddr 0x%lx\n",
552 "DramAddr 0x%lx\n", (unsigned long)sys_addr, 551 (unsigned long)sys_addr, (unsigned long)dram_addr);
553 (unsigned long)dram_addr);
554 return dram_addr; 552 return dram_addr;
555} 553}
556 554
@@ -586,9 +584,9 @@ static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr)
586 input_addr = ((dram_addr >> intlv_shift) & GENMASK(12, 35)) + 584 input_addr = ((dram_addr >> intlv_shift) & GENMASK(12, 35)) +
587 (dram_addr & 0xfff); 585 (dram_addr & 0xfff);
588 586
589 debugf2(" Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n", 587 edac_dbg(2, " Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n",
590 intlv_shift, (unsigned long)dram_addr, 588 intlv_shift, (unsigned long)dram_addr,
591 (unsigned long)input_addr); 589 (unsigned long)input_addr);
592 590
593 return input_addr; 591 return input_addr;
594} 592}
@@ -604,8 +602,8 @@ static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr)
604 input_addr = 602 input_addr =
605 dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr)); 603 dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr));
606 604
607 debugf2("SysAdddr 0x%lx translates to InputAddr 0x%lx\n", 605 edac_dbg(2, "SysAdddr 0x%lx translates to InputAddr 0x%lx\n",
608 (unsigned long)sys_addr, (unsigned long)input_addr); 606 (unsigned long)sys_addr, (unsigned long)input_addr);
609 607
610 return input_addr; 608 return input_addr;
611} 609}
@@ -637,8 +635,8 @@ static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr)
637 635
638 intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0)); 636 intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0));
639 if (intlv_shift == 0) { 637 if (intlv_shift == 0) {
640 debugf1(" InputAddr 0x%lx translates to DramAddr of " 638 edac_dbg(1, " InputAddr 0x%lx translates to DramAddr of same value\n",
641 "same value\n", (unsigned long)input_addr); 639 (unsigned long)input_addr);
642 640
643 return input_addr; 641 return input_addr;
644 } 642 }
@@ -649,9 +647,9 @@ static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr)
649 intlv_sel = dram_intlv_sel(pvt, node_id) & ((1 << intlv_shift) - 1); 647 intlv_sel = dram_intlv_sel(pvt, node_id) & ((1 << intlv_shift) - 1);
650 dram_addr = bits + (intlv_sel << 12); 648 dram_addr = bits + (intlv_sel << 12);
651 649
652 debugf1("InputAddr 0x%lx translates to DramAddr 0x%lx " 650 edac_dbg(1, "InputAddr 0x%lx translates to DramAddr 0x%lx (%d node interleave bits)\n",
653 "(%d node interleave bits)\n", (unsigned long)input_addr, 651 (unsigned long)input_addr,
654 (unsigned long)dram_addr, intlv_shift); 652 (unsigned long)dram_addr, intlv_shift);
655 653
656 return dram_addr; 654 return dram_addr;
657} 655}
@@ -673,9 +671,9 @@ static u64 dram_addr_to_sys_addr(struct mem_ctl_info *mci, u64 dram_addr)
673 (dram_addr < (hole_base + hole_size))) { 671 (dram_addr < (hole_base + hole_size))) {
674 sys_addr = dram_addr + hole_offset; 672 sys_addr = dram_addr + hole_offset;
675 673
676 debugf1("using DHAR to translate DramAddr 0x%lx to " 674 edac_dbg(1, "using DHAR to translate DramAddr 0x%lx to SysAddr 0x%lx\n",
677 "SysAddr 0x%lx\n", (unsigned long)dram_addr, 675 (unsigned long)dram_addr,
678 (unsigned long)sys_addr); 676 (unsigned long)sys_addr);
679 677
680 return sys_addr; 678 return sys_addr;
681 } 679 }
@@ -697,9 +695,9 @@ static u64 dram_addr_to_sys_addr(struct mem_ctl_info *mci, u64 dram_addr)
697 */ 695 */
698 sys_addr |= ~((sys_addr & (1ull << 39)) - 1); 696 sys_addr |= ~((sys_addr & (1ull << 39)) - 1);
699 697
700 debugf1(" Node %d, DramAddr 0x%lx to SysAddr 0x%lx\n", 698 edac_dbg(1, " Node %d, DramAddr 0x%lx to SysAddr 0x%lx\n",
701 pvt->mc_node_id, (unsigned long)dram_addr, 699 pvt->mc_node_id, (unsigned long)dram_addr,
702 (unsigned long)sys_addr); 700 (unsigned long)sys_addr);
703 701
704 return sys_addr; 702 return sys_addr;
705} 703}
@@ -768,49 +766,48 @@ static void amd64_debug_display_dimm_sizes(struct amd64_pvt *, u8);
768 766
769static void amd64_dump_dramcfg_low(u32 dclr, int chan) 767static void amd64_dump_dramcfg_low(u32 dclr, int chan)
770{ 768{
771 debugf1("F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr); 769 edac_dbg(1, "F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr);
772 770
773 debugf1(" DIMM type: %sbuffered; all DIMMs support ECC: %s\n", 771 edac_dbg(1, " DIMM type: %sbuffered; all DIMMs support ECC: %s\n",
774 (dclr & BIT(16)) ? "un" : "", 772 (dclr & BIT(16)) ? "un" : "",
775 (dclr & BIT(19)) ? "yes" : "no"); 773 (dclr & BIT(19)) ? "yes" : "no");
776 774
777 debugf1(" PAR/ERR parity: %s\n", 775 edac_dbg(1, " PAR/ERR parity: %s\n",
778 (dclr & BIT(8)) ? "enabled" : "disabled"); 776 (dclr & BIT(8)) ? "enabled" : "disabled");
779 777
780 if (boot_cpu_data.x86 == 0x10) 778 if (boot_cpu_data.x86 == 0x10)
781 debugf1(" DCT 128bit mode width: %s\n", 779 edac_dbg(1, " DCT 128bit mode width: %s\n",
782 (dclr & BIT(11)) ? "128b" : "64b"); 780 (dclr & BIT(11)) ? "128b" : "64b");
783 781
784 debugf1(" x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n", 782 edac_dbg(1, " x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n",
785 (dclr & BIT(12)) ? "yes" : "no", 783 (dclr & BIT(12)) ? "yes" : "no",
786 (dclr & BIT(13)) ? "yes" : "no", 784 (dclr & BIT(13)) ? "yes" : "no",
787 (dclr & BIT(14)) ? "yes" : "no", 785 (dclr & BIT(14)) ? "yes" : "no",
788 (dclr & BIT(15)) ? "yes" : "no"); 786 (dclr & BIT(15)) ? "yes" : "no");
789} 787}
790 788
791/* Display and decode various NB registers for debug purposes. */ 789/* Display and decode various NB registers for debug purposes. */
792static void dump_misc_regs(struct amd64_pvt *pvt) 790static void dump_misc_regs(struct amd64_pvt *pvt)
793{ 791{
794 debugf1("F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap); 792 edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);
795 793
796 debugf1(" NB two channel DRAM capable: %s\n", 794 edac_dbg(1, " NB two channel DRAM capable: %s\n",
797 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no"); 795 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no");
798 796
799 debugf1(" ECC capable: %s, ChipKill ECC capable: %s\n", 797 edac_dbg(1, " ECC capable: %s, ChipKill ECC capable: %s\n",
800 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no", 798 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no",
801 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no"); 799 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no");
802 800
803 amd64_dump_dramcfg_low(pvt->dclr0, 0); 801 amd64_dump_dramcfg_low(pvt->dclr0, 0);
804 802
805 debugf1("F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare); 803 edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare);
806 804
807 debugf1("F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, " 805 edac_dbg(1, "F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, offset: 0x%08x\n",
808 "offset: 0x%08x\n", 806 pvt->dhar, dhar_base(pvt),
809 pvt->dhar, dhar_base(pvt), 807 (boot_cpu_data.x86 == 0xf) ? k8_dhar_offset(pvt)
810 (boot_cpu_data.x86 == 0xf) ? k8_dhar_offset(pvt) 808 : f10_dhar_offset(pvt));
811 : f10_dhar_offset(pvt));
812 809
813 debugf1(" DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no"); 810 edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
814 811
815 amd64_debug_display_dimm_sizes(pvt, 0); 812 amd64_debug_display_dimm_sizes(pvt, 0);
816 813
@@ -857,15 +854,15 @@ static void read_dct_base_mask(struct amd64_pvt *pvt)
857 u32 *base1 = &pvt->csels[1].csbases[cs]; 854 u32 *base1 = &pvt->csels[1].csbases[cs];
858 855
859 if (!amd64_read_dct_pci_cfg(pvt, reg0, base0)) 856 if (!amd64_read_dct_pci_cfg(pvt, reg0, base0))
860 debugf0(" DCSB0[%d]=0x%08x reg: F2x%x\n", 857 edac_dbg(0, " DCSB0[%d]=0x%08x reg: F2x%x\n",
861 cs, *base0, reg0); 858 cs, *base0, reg0);
862 859
863 if (boot_cpu_data.x86 == 0xf || dct_ganging_enabled(pvt)) 860 if (boot_cpu_data.x86 == 0xf || dct_ganging_enabled(pvt))
864 continue; 861 continue;
865 862
866 if (!amd64_read_dct_pci_cfg(pvt, reg1, base1)) 863 if (!amd64_read_dct_pci_cfg(pvt, reg1, base1))
867 debugf0(" DCSB1[%d]=0x%08x reg: F2x%x\n", 864 edac_dbg(0, " DCSB1[%d]=0x%08x reg: F2x%x\n",
868 cs, *base1, reg1); 865 cs, *base1, reg1);
869 } 866 }
870 867
871 for_each_chip_select_mask(cs, 0, pvt) { 868 for_each_chip_select_mask(cs, 0, pvt) {
@@ -875,15 +872,15 @@ static void read_dct_base_mask(struct amd64_pvt *pvt)
875 u32 *mask1 = &pvt->csels[1].csmasks[cs]; 872 u32 *mask1 = &pvt->csels[1].csmasks[cs];
876 873
877 if (!amd64_read_dct_pci_cfg(pvt, reg0, mask0)) 874 if (!amd64_read_dct_pci_cfg(pvt, reg0, mask0))
878 debugf0(" DCSM0[%d]=0x%08x reg: F2x%x\n", 875 edac_dbg(0, " DCSM0[%d]=0x%08x reg: F2x%x\n",
879 cs, *mask0, reg0); 876 cs, *mask0, reg0);
880 877
881 if (boot_cpu_data.x86 == 0xf || dct_ganging_enabled(pvt)) 878 if (boot_cpu_data.x86 == 0xf || dct_ganging_enabled(pvt))
882 continue; 879 continue;
883 880
884 if (!amd64_read_dct_pci_cfg(pvt, reg1, mask1)) 881 if (!amd64_read_dct_pci_cfg(pvt, reg1, mask1))
885 debugf0(" DCSM1[%d]=0x%08x reg: F2x%x\n", 882 edac_dbg(0, " DCSM1[%d]=0x%08x reg: F2x%x\n",
886 cs, *mask1, reg1); 883 cs, *mask1, reg1);
887 } 884 }
888} 885}
889 886
@@ -1193,7 +1190,7 @@ static int f1x_early_channel_count(struct amd64_pvt *pvt)
1193 * Need to check DCT0[0] and DCT1[0] to see if only one of them has 1190 * Need to check DCT0[0] and DCT1[0] to see if only one of them has
1194 * their CSEnable bit on. If so, then SINGLE DIMM case. 1191 * their CSEnable bit on. If so, then SINGLE DIMM case.
1195 */ 1192 */
1196 debugf0("Data width is not 128 bits - need more decoding\n"); 1193 edac_dbg(0, "Data width is not 128 bits - need more decoding\n");
1197 1194
1198 /* 1195 /*
1199 * Check DRAM Bank Address Mapping values for each DIMM to see if there 1196 * Check DRAM Bank Address Mapping values for each DIMM to see if there
@@ -1272,25 +1269,24 @@ static void read_dram_ctl_register(struct amd64_pvt *pvt)
1272 return; 1269 return;
1273 1270
1274 if (!amd64_read_dct_pci_cfg(pvt, DCT_SEL_LO, &pvt->dct_sel_lo)) { 1271 if (!amd64_read_dct_pci_cfg(pvt, DCT_SEL_LO, &pvt->dct_sel_lo)) {
1275 debugf0("F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n", 1272 edac_dbg(0, "F2x110 (DCTSelLow): 0x%08x, High range addrs at: 0x%x\n",
1276 pvt->dct_sel_lo, dct_sel_baseaddr(pvt)); 1273 pvt->dct_sel_lo, dct_sel_baseaddr(pvt));
1277 1274
1278 debugf0(" DCTs operate in %s mode.\n", 1275 edac_dbg(0, " DCTs operate in %s mode\n",
1279 (dct_ganging_enabled(pvt) ? "ganged" : "unganged")); 1276 (dct_ganging_enabled(pvt) ? "ganged" : "unganged"));
1280 1277
1281 if (!dct_ganging_enabled(pvt)) 1278 if (!dct_ganging_enabled(pvt))
1282 debugf0(" Address range split per DCT: %s\n", 1279 edac_dbg(0, " Address range split per DCT: %s\n",
1283 (dct_high_range_enabled(pvt) ? "yes" : "no")); 1280 (dct_high_range_enabled(pvt) ? "yes" : "no"));
1284 1281
1285 debugf0(" data interleave for ECC: %s, " 1282 edac_dbg(0, " data interleave for ECC: %s, DRAM cleared since last warm reset: %s\n",
1286 "DRAM cleared since last warm reset: %s\n", 1283 (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"),
1287 (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"), 1284 (dct_memory_cleared(pvt) ? "yes" : "no"));
1288 (dct_memory_cleared(pvt) ? "yes" : "no"));
1289 1285
1290 debugf0(" channel interleave: %s, " 1286 edac_dbg(0, " channel interleave: %s, "
1291 "interleave bits selector: 0x%x\n", 1287 "interleave bits selector: 0x%x\n",
1292 (dct_interleave_enabled(pvt) ? "enabled" : "disabled"), 1288 (dct_interleave_enabled(pvt) ? "enabled" : "disabled"),
1293 dct_sel_interleave_addr(pvt)); 1289 dct_sel_interleave_addr(pvt));
1294 } 1290 }
1295 1291
1296 amd64_read_dct_pci_cfg(pvt, DCT_SEL_HI, &pvt->dct_sel_hi); 1292 amd64_read_dct_pci_cfg(pvt, DCT_SEL_HI, &pvt->dct_sel_hi);
@@ -1428,7 +1424,7 @@ static int f1x_lookup_addr_in_dct(u64 in_addr, u32 nid, u8 dct)
1428 1424
1429 pvt = mci->pvt_info; 1425 pvt = mci->pvt_info;
1430 1426
1431 debugf1("input addr: 0x%llx, DCT: %d\n", in_addr, dct); 1427 edac_dbg(1, "input addr: 0x%llx, DCT: %d\n", in_addr, dct);
1432 1428
1433 for_each_chip_select(csrow, dct, pvt) { 1429 for_each_chip_select(csrow, dct, pvt) {
1434 if (!csrow_enabled(csrow, dct, pvt)) 1430 if (!csrow_enabled(csrow, dct, pvt))
@@ -1436,19 +1432,18 @@ static int f1x_lookup_addr_in_dct(u64 in_addr, u32 nid, u8 dct)
1436 1432
1437 get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask); 1433 get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask);
1438 1434
1439 debugf1(" CSROW=%d CSBase=0x%llx CSMask=0x%llx\n", 1435 edac_dbg(1, " CSROW=%d CSBase=0x%llx CSMask=0x%llx\n",
1440 csrow, cs_base, cs_mask); 1436 csrow, cs_base, cs_mask);
1441 1437
1442 cs_mask = ~cs_mask; 1438 cs_mask = ~cs_mask;
1443 1439
1444 debugf1(" (InputAddr & ~CSMask)=0x%llx " 1440 edac_dbg(1, " (InputAddr & ~CSMask)=0x%llx (CSBase & ~CSMask)=0x%llx\n",
1445 "(CSBase & ~CSMask)=0x%llx\n", 1441 (in_addr & cs_mask), (cs_base & cs_mask));
1446 (in_addr & cs_mask), (cs_base & cs_mask));
1447 1442
1448 if ((in_addr & cs_mask) == (cs_base & cs_mask)) { 1443 if ((in_addr & cs_mask) == (cs_base & cs_mask)) {
1449 cs_found = f10_process_possible_spare(pvt, dct, csrow); 1444 cs_found = f10_process_possible_spare(pvt, dct, csrow);
1450 1445
1451 debugf1(" MATCH csrow=%d\n", cs_found); 1446 edac_dbg(1, " MATCH csrow=%d\n", cs_found);
1452 break; 1447 break;
1453 } 1448 }
1454 } 1449 }
@@ -1505,8 +1500,8 @@ static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
1505 u8 intlv_en = dram_intlv_en(pvt, range); 1500 u8 intlv_en = dram_intlv_en(pvt, range);
1506 u32 intlv_sel = dram_intlv_sel(pvt, range); 1501 u32 intlv_sel = dram_intlv_sel(pvt, range);
1507 1502
1508 debugf1("(range %d) SystemAddr= 0x%llx Limit=0x%llx\n", 1503 edac_dbg(1, "(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
1509 range, sys_addr, get_dram_limit(pvt, range)); 1504 range, sys_addr, get_dram_limit(pvt, range));
1510 1505
1511 if (dhar_valid(pvt) && 1506 if (dhar_valid(pvt) &&
1512 dhar_base(pvt) <= sys_addr && 1507 dhar_base(pvt) <= sys_addr &&
@@ -1562,7 +1557,7 @@ static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
1562 (chan_addr & 0xfff); 1557 (chan_addr & 0xfff);
1563 } 1558 }
1564 1559
1565 debugf1(" Normalized DCT addr: 0x%llx\n", chan_addr); 1560 edac_dbg(1, " Normalized DCT addr: 0x%llx\n", chan_addr);
1566 1561
1567 cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, channel); 1562 cs_found = f1x_lookup_addr_in_dct(chan_addr, node_id, channel);
1568 1563
@@ -1664,7 +1659,8 @@ static void amd64_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
1664 dcsb = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->csels[1].csbases 1659 dcsb = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->csels[1].csbases
1665 : pvt->csels[0].csbases; 1660 : pvt->csels[0].csbases;
1666 1661
1667 debugf1("F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n", ctrl, dbam); 1662 edac_dbg(1, "F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n",
1663 ctrl, dbam);
1668 1664
1669 edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl); 1665 edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl);
1670 1666
@@ -1840,7 +1836,7 @@ static int decode_syndrome(u16 syndrome, u16 *vectors, unsigned num_vecs,
1840 } 1836 }
1841 } 1837 }
1842 1838
1843 debugf0("syndrome(%x) not found\n", syndrome); 1839 edac_dbg(0, "syndrome(%x) not found\n", syndrome);
1844 return -1; 1840 return -1;
1845} 1841}
1846 1842
@@ -2047,9 +2043,9 @@ static int reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 f1_id, u16 f3_id)
2047 2043
2048 return -ENODEV; 2044 return -ENODEV;
2049 } 2045 }
2050 debugf1("F1: %s\n", pci_name(pvt->F1)); 2046 edac_dbg(1, "F1: %s\n", pci_name(pvt->F1));
2051 debugf1("F2: %s\n", pci_name(pvt->F2)); 2047 edac_dbg(1, "F2: %s\n", pci_name(pvt->F2));
2052 debugf1("F3: %s\n", pci_name(pvt->F3)); 2048 edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));
2053 2049
2054 return 0; 2050 return 0;
2055} 2051}
@@ -2076,15 +2072,15 @@ static void read_mc_regs(struct amd64_pvt *pvt)
2076 * those are Read-As-Zero 2072 * those are Read-As-Zero
2077 */ 2073 */
2078 rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); 2074 rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem);
2079 debugf0(" TOP_MEM: 0x%016llx\n", pvt->top_mem); 2075 edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem);
2080 2076
2081 /* check first whether TOP_MEM2 is enabled */ 2077 /* check first whether TOP_MEM2 is enabled */
2082 rdmsrl(MSR_K8_SYSCFG, msr_val); 2078 rdmsrl(MSR_K8_SYSCFG, msr_val);
2083 if (msr_val & (1U << 21)) { 2079 if (msr_val & (1U << 21)) {
2084 rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); 2080 rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2);
2085 debugf0(" TOP_MEM2: 0x%016llx\n", pvt->top_mem2); 2081 edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2);
2086 } else 2082 } else
2087 debugf0(" TOP_MEM2 disabled.\n"); 2083 edac_dbg(0, " TOP_MEM2 disabled\n");
2088 2084
2089 amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap); 2085 amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap);
2090 2086
@@ -2100,17 +2096,17 @@ static void read_mc_regs(struct amd64_pvt *pvt)
2100 if (!rw) 2096 if (!rw)
2101 continue; 2097 continue;
2102 2098
2103 debugf1(" DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n", 2099 edac_dbg(1, " DRAM range[%d], base: 0x%016llx; limit: 0x%016llx\n",
2104 range, 2100 range,
2105 get_dram_base(pvt, range), 2101 get_dram_base(pvt, range),
2106 get_dram_limit(pvt, range)); 2102 get_dram_limit(pvt, range));
2107 2103
2108 debugf1(" IntlvEn=%s; Range access: %s%s IntlvSel=%d DstNode=%d\n", 2104 edac_dbg(1, " IntlvEn=%s; Range access: %s%s IntlvSel=%d DstNode=%d\n",
2109 dram_intlv_en(pvt, range) ? "Enabled" : "Disabled", 2105 dram_intlv_en(pvt, range) ? "Enabled" : "Disabled",
2110 (rw & 0x1) ? "R" : "-", 2106 (rw & 0x1) ? "R" : "-",
2111 (rw & 0x2) ? "W" : "-", 2107 (rw & 0x2) ? "W" : "-",
2112 dram_intlv_sel(pvt, range), 2108 dram_intlv_sel(pvt, range),
2113 dram_dst_node(pvt, range)); 2109 dram_dst_node(pvt, range));
2114 } 2110 }
2115 2111
2116 read_dct_base_mask(pvt); 2112 read_dct_base_mask(pvt);
@@ -2191,9 +2187,9 @@ static u32 amd64_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr)
2191 2187
2192 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode) << (20 - PAGE_SHIFT); 2188 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode) << (20 - PAGE_SHIFT);
2193 2189
2194 debugf0(" (csrow=%d) DBAM map index= %d\n", csrow_nr, cs_mode); 2190 edac_dbg(0, " (csrow=%d) DBAM map index= %d\n", csrow_nr, cs_mode);
2195 debugf0(" nr_pages/channel= %u channel-count = %d\n", 2191 edac_dbg(0, " nr_pages/channel= %u channel-count = %d\n",
2196 nr_pages, pvt->channel_count); 2192 nr_pages, pvt->channel_count);
2197 2193
2198 return nr_pages; 2194 return nr_pages;
2199} 2195}
@@ -2218,22 +2214,19 @@ static int init_csrows(struct mem_ctl_info *mci)
2218 2214
2219 pvt->nbcfg = val; 2215 pvt->nbcfg = val;
2220 2216
2221 debugf0("node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n", 2217 edac_dbg(0, "node %d, NBCFG=0x%08x[ChipKillEccCap: %d|DramEccEn: %d]\n",
2222 pvt->mc_node_id, val, 2218 pvt->mc_node_id, val,
2223 !!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE)); 2219 !!(val & NBCFG_CHIPKILL), !!(val & NBCFG_ECC_ENABLE));
2224 2220
2225 for_each_chip_select(i, 0, pvt) { 2221 for_each_chip_select(i, 0, pvt) {
2226 csrow = mci->csrows[i]; 2222 csrow = mci->csrows[i];
2227 2223
2228 if (!csrow_enabled(i, 0, pvt) && !csrow_enabled(i, 1, pvt)) { 2224 if (!csrow_enabled(i, 0, pvt) && !csrow_enabled(i, 1, pvt)) {
2229 debugf1("----CSROW %d EMPTY for node %d\n", i, 2225 edac_dbg(1, "----CSROW %d VALID for MC node %d\n",
2230 pvt->mc_node_id); 2226 i, pvt->mc_node_id);
2231 continue; 2227 continue;
2232 } 2228 }
2233 2229
2234 debugf1("----CSROW %d VALID for MC node %d\n",
2235 i, pvt->mc_node_id);
2236
2237 empty = 0; 2230 empty = 0;
2238 if (csrow_enabled(i, 0, pvt)) 2231 if (csrow_enabled(i, 0, pvt))
2239 nr_pages = amd64_csrow_nr_pages(pvt, 0, i); 2232 nr_pages = amd64_csrow_nr_pages(pvt, 0, i);
@@ -2245,8 +2238,9 @@ static int init_csrows(struct mem_ctl_info *mci)
2245 2238
2246 mtype = amd64_determine_memory_type(pvt, i); 2239 mtype = amd64_determine_memory_type(pvt, i);
2247 2240
2248 debugf1(" for MC node %d csrow %d:\n", pvt->mc_node_id, i); 2241 edac_dbg(1, " for MC node %d csrow %d:\n", pvt->mc_node_id, i);
2249 debugf1(" nr_pages: %u\n", nr_pages * pvt->channel_count); 2242 edac_dbg(1, " nr_pages: %u\n",
2243 nr_pages * pvt->channel_count);
2250 2244
2251 /* 2245 /*
2252 * determine whether CHIPKILL or JUST ECC or NO ECC is operating 2246 * determine whether CHIPKILL or JUST ECC or NO ECC is operating
@@ -2298,9 +2292,9 @@ static bool amd64_nb_mce_bank_enabled_on_node(unsigned nid)
2298 struct msr *reg = per_cpu_ptr(msrs, cpu); 2292 struct msr *reg = per_cpu_ptr(msrs, cpu);
2299 nbe = reg->l & MSR_MCGCTL_NBE; 2293 nbe = reg->l & MSR_MCGCTL_NBE;
2300 2294
2301 debugf0("core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n", 2295 edac_dbg(0, "core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n",
2302 cpu, reg->q, 2296 cpu, reg->q,
2303 (nbe ? "enabled" : "disabled")); 2297 (nbe ? "enabled" : "disabled"));
2304 2298
2305 if (!nbe) 2299 if (!nbe)
2306 goto out; 2300 goto out;
@@ -2371,8 +2365,8 @@ static bool enable_ecc_error_reporting(struct ecc_settings *s, u8 nid,
2371 2365
2372 amd64_read_pci_cfg(F3, NBCFG, &value); 2366 amd64_read_pci_cfg(F3, NBCFG, &value);
2373 2367
2374 debugf0("1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n", 2368 edac_dbg(0, "1: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
2375 nid, value, !!(value & NBCFG_ECC_ENABLE)); 2369 nid, value, !!(value & NBCFG_ECC_ENABLE));
2376 2370
2377 if (!(value & NBCFG_ECC_ENABLE)) { 2371 if (!(value & NBCFG_ECC_ENABLE)) {
2378 amd64_warn("DRAM ECC disabled on this node, enabling...\n"); 2372 amd64_warn("DRAM ECC disabled on this node, enabling...\n");
@@ -2396,8 +2390,8 @@ static bool enable_ecc_error_reporting(struct ecc_settings *s, u8 nid,
2396 s->flags.nb_ecc_prev = 1; 2390 s->flags.nb_ecc_prev = 1;
2397 } 2391 }
2398 2392
2399 debugf0("2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n", 2393 edac_dbg(0, "2: node %d, NBCFG=0x%08x[DramEccEn: %d]\n",
2400 nid, value, !!(value & NBCFG_ECC_ENABLE)); 2394 nid, value, !!(value & NBCFG_ECC_ENABLE));
2401 2395
2402 return ret; 2396 return ret;
2403} 2397}
@@ -2615,11 +2609,11 @@ static int amd64_init_one_instance(struct pci_dev *F2)
2615 2609
2616 ret = -ENODEV; 2610 ret = -ENODEV;
2617 if (edac_mc_add_mc(mci)) { 2611 if (edac_mc_add_mc(mci)) {
2618 debugf1("failed edac_mc_add_mc()\n"); 2612 edac_dbg(1, "failed edac_mc_add_mc()\n");
2619 goto err_add_mc; 2613 goto err_add_mc;
2620 } 2614 }
2621 if (set_mc_sysfs_attrs(mci)) { 2615 if (set_mc_sysfs_attrs(mci)) {
2622 debugf1("failed edac_mc_add_mc()\n"); 2616 edac_dbg(1, "failed edac_mc_add_mc()\n");
2623 goto err_add_sysfs; 2617 goto err_add_sysfs;
2624 } 2618 }
2625 2619
@@ -2660,7 +2654,7 @@ static int __devinit amd64_probe_one_instance(struct pci_dev *pdev,
2660 2654
2661 ret = pci_enable_device(pdev); 2655 ret = pci_enable_device(pdev);
2662 if (ret < 0) { 2656 if (ret < 0) {
2663 debugf0("ret=%d\n", ret); 2657 edac_dbg(0, "ret=%d\n", ret);
2664 return -EIO; 2658 return -EIO;
2665 } 2659 }
2666 2660
diff --git a/drivers/edac/amd64_edac_inj.c b/drivers/edac/amd64_edac_inj.c
index ef1ff4ea957..53d972e00df 100644
--- a/drivers/edac/amd64_edac_inj.c
+++ b/drivers/edac/amd64_edac_inj.c
@@ -142,7 +142,8 @@ static ssize_t amd64_inject_read_store(struct device *dev,
142 /* Issue 'word' and 'bit' along with the READ request */ 142 /* Issue 'word' and 'bit' along with the READ request */
143 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits); 143 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
144 144
145 debugf0("section=0x%x word_bits=0x%x\n", section, word_bits); 145 edac_dbg(0, "section=0x%x word_bits=0x%x\n",
146 section, word_bits);
146 147
147 return count; 148 return count;
148 } 149 }
@@ -177,7 +178,8 @@ static ssize_t amd64_inject_write_store(struct device *dev,
177 /* Issue 'word' and 'bit' along with the READ request */ 178 /* Issue 'word' and 'bit' along with the READ request */
178 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits); 179 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
179 180
180 debugf0("section=0x%x word_bits=0x%x\n", section, word_bits); 181 edac_dbg(0, "section=0x%x word_bits=0x%x\n",
182 section, word_bits);
181 183
182 return count; 184 return count;
183 } 185 }
diff --git a/drivers/edac/amd76x_edac.c b/drivers/edac/amd76x_edac.c
index b6e94ae4bf6..a015fbaa955 100644
--- a/drivers/edac/amd76x_edac.c
+++ b/drivers/edac/amd76x_edac.c
@@ -180,7 +180,7 @@ static int amd76x_process_error_info(struct mem_ctl_info *mci,
180static void amd76x_check(struct mem_ctl_info *mci) 180static void amd76x_check(struct mem_ctl_info *mci)
181{ 181{
182 struct amd76x_error_info info; 182 struct amd76x_error_info info;
183 debugf3("\n"); 183 edac_dbg(3, "\n");
184 amd76x_get_error_info(mci, &info); 184 amd76x_get_error_info(mci, &info);
185 amd76x_process_error_info(mci, &info, 1); 185 amd76x_process_error_info(mci, &info, 1);
186} 186}
@@ -241,7 +241,7 @@ static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
241 u32 ems_mode; 241 u32 ems_mode;
242 struct amd76x_error_info discard; 242 struct amd76x_error_info discard;
243 243
244 debugf0("\n"); 244 edac_dbg(0, "\n");
245 pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems); 245 pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems);
246 ems_mode = (ems >> 10) & 0x3; 246 ems_mode = (ems >> 10) & 0x3;
247 247
@@ -256,7 +256,7 @@ static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
256 if (mci == NULL) 256 if (mci == NULL)
257 return -ENOMEM; 257 return -ENOMEM;
258 258
259 debugf0("mci = %p\n", mci); 259 edac_dbg(0, "mci = %p\n", mci);
260 mci->pdev = &pdev->dev; 260 mci->pdev = &pdev->dev;
261 mci->mtype_cap = MEM_FLAG_RDDR; 261 mci->mtype_cap = MEM_FLAG_RDDR;
262 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; 262 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
@@ -276,7 +276,7 @@ static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
276 * type of memory controller. The ID is therefore hardcoded to 0. 276 * type of memory controller. The ID is therefore hardcoded to 0.
277 */ 277 */
278 if (edac_mc_add_mc(mci)) { 278 if (edac_mc_add_mc(mci)) {
279 debugf3("failed edac_mc_add_mc()\n"); 279 edac_dbg(3, "failed edac_mc_add_mc()\n");
280 goto fail; 280 goto fail;
281 } 281 }
282 282
@@ -292,7 +292,7 @@ static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
292 } 292 }
293 293
294 /* get this far and it's successful */ 294 /* get this far and it's successful */
295 debugf3("success\n"); 295 edac_dbg(3, "success\n");
296 return 0; 296 return 0;
297 297
298fail: 298fail:
@@ -304,7 +304,7 @@ fail:
304static int __devinit amd76x_init_one(struct pci_dev *pdev, 304static int __devinit amd76x_init_one(struct pci_dev *pdev,
305 const struct pci_device_id *ent) 305 const struct pci_device_id *ent)
306{ 306{
307 debugf0("\n"); 307 edac_dbg(0, "\n");
308 308
309 /* don't need to call pci_enable_device() */ 309 /* don't need to call pci_enable_device() */
310 return amd76x_probe1(pdev, ent->driver_data); 310 return amd76x_probe1(pdev, ent->driver_data);
@@ -322,7 +322,7 @@ static void __devexit amd76x_remove_one(struct pci_dev *pdev)
322{ 322{
323 struct mem_ctl_info *mci; 323 struct mem_ctl_info *mci;
324 324
325 debugf0("\n"); 325 edac_dbg(0, "\n");
326 326
327 if (amd76x_pci) 327 if (amd76x_pci)
328 edac_pci_release_generic_ctl(amd76x_pci); 328 edac_pci_release_generic_ctl(amd76x_pci);
diff --git a/drivers/edac/cpc925_edac.c b/drivers/edac/cpc925_edac.c
index fa39a7840e2..a7ea3986d42 100644
--- a/drivers/edac/cpc925_edac.c
+++ b/drivers/edac/cpc925_edac.c
@@ -316,12 +316,12 @@ static void get_total_mem(struct cpc925_mc_pdata *pdata)
316 reg += aw; 316 reg += aw;
317 size = of_read_number(reg, sw); 317 size = of_read_number(reg, sw);
318 reg += sw; 318 reg += sw;
319 debugf1("start 0x%lx, size 0x%lx\n", start, size); 319 edac_dbg(1, "start 0x%lx, size 0x%lx\n", start, size);
320 pdata->total_mem += size; 320 pdata->total_mem += size;
321 } while (reg < reg_end); 321 } while (reg < reg_end);
322 322
323 of_node_put(np); 323 of_node_put(np);
324 debugf0("total_mem 0x%lx\n", pdata->total_mem); 324 edac_dbg(0, "total_mem 0x%lx\n", pdata->total_mem);
325} 325}
326 326
327static void cpc925_init_csrows(struct mem_ctl_info *mci) 327static void cpc925_init_csrows(struct mem_ctl_info *mci)
@@ -511,7 +511,7 @@ static void cpc925_mc_get_pfn(struct mem_ctl_info *mci, u32 mear,
511 *offset = pa & (PAGE_SIZE - 1); 511 *offset = pa & (PAGE_SIZE - 1);
512 *pfn = pa >> PAGE_SHIFT; 512 *pfn = pa >> PAGE_SHIFT;
513 513
514 debugf0("ECC physical address 0x%lx\n", pa); 514 edac_dbg(0, "ECC physical address 0x%lx\n", pa);
515} 515}
516 516
517static int cpc925_mc_find_channel(struct mem_ctl_info *mci, u16 syndrome) 517static int cpc925_mc_find_channel(struct mem_ctl_info *mci, u16 syndrome)
@@ -851,8 +851,8 @@ static void cpc925_add_edac_devices(void __iomem *vbase)
851 goto err2; 851 goto err2;
852 } 852 }
853 853
854 debugf0("Successfully added edac device for %s\n", 854 edac_dbg(0, "Successfully added edac device for %s\n",
855 dev_info->ctl_name); 855 dev_info->ctl_name);
856 856
857 continue; 857 continue;
858 858
@@ -883,8 +883,8 @@ static void cpc925_del_edac_devices(void)
883 if (dev_info->exit) 883 if (dev_info->exit)
884 dev_info->exit(dev_info); 884 dev_info->exit(dev_info);
885 885
886 debugf0("Successfully deleted edac device for %s\n", 886 edac_dbg(0, "Successfully deleted edac device for %s\n",
887 dev_info->ctl_name); 887 dev_info->ctl_name);
888 } 888 }
889} 889}
890 890
@@ -899,7 +899,7 @@ static int cpc925_get_sdram_scrub_rate(struct mem_ctl_info *mci)
899 mscr = __raw_readl(pdata->vbase + REG_MSCR_OFFSET); 899 mscr = __raw_readl(pdata->vbase + REG_MSCR_OFFSET);
900 si = (mscr & MSCR_SI_MASK) >> MSCR_SI_SHIFT; 900 si = (mscr & MSCR_SI_MASK) >> MSCR_SI_SHIFT;
901 901
902 debugf0("Mem Scrub Ctrl Register 0x%x\n", mscr); 902 edac_dbg(0, "Mem Scrub Ctrl Register 0x%x\n", mscr);
903 903
904 if (((mscr & MSCR_SCRUB_MOD_MASK) != MSCR_BACKGR_SCRUB) || 904 if (((mscr & MSCR_SCRUB_MOD_MASK) != MSCR_BACKGR_SCRUB) ||
905 (si == 0)) { 905 (si == 0)) {
@@ -927,7 +927,7 @@ static int cpc925_mc_get_channels(void __iomem *vbase)
927 ((mbcr & MBCR_64BITBUS_MASK) == 0)) 927 ((mbcr & MBCR_64BITBUS_MASK) == 0))
928 dual = 1; 928 dual = 1;
929 929
930 debugf0("%s channel\n", (dual > 0) ? "Dual" : "Single"); 930 edac_dbg(0, "%s channel\n", (dual > 0) ? "Dual" : "Single");
931 931
932 return dual; 932 return dual;
933} 933}
@@ -942,7 +942,7 @@ static int __devinit cpc925_probe(struct platform_device *pdev)
942 struct resource *r; 942 struct resource *r;
943 int res = 0, nr_channels; 943 int res = 0, nr_channels;
944 944
945 debugf0("%s platform device found!\n", pdev->name); 945 edac_dbg(0, "%s platform device found!\n", pdev->name);
946 946
947 if (!devres_open_group(&pdev->dev, cpc925_probe, GFP_KERNEL)) { 947 if (!devres_open_group(&pdev->dev, cpc925_probe, GFP_KERNEL)) {
948 res = -ENOMEM; 948 res = -ENOMEM;
@@ -1024,7 +1024,7 @@ static int __devinit cpc925_probe(struct platform_device *pdev)
1024 cpc925_add_edac_devices(vbase); 1024 cpc925_add_edac_devices(vbase);
1025 1025
1026 /* get this far and it's successful */ 1026 /* get this far and it's successful */
1027 debugf0("success\n"); 1027 edac_dbg(0, "success\n");
1028 1028
1029 res = 0; 1029 res = 0;
1030 goto out; 1030 goto out;
diff --git a/drivers/edac/e752x_edac.c b/drivers/edac/e752x_edac.c
index 39c8997b216..675ba3c284e 100644
--- a/drivers/edac/e752x_edac.c
+++ b/drivers/edac/e752x_edac.c
@@ -309,7 +309,7 @@ static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
309 u32 remap; 309 u32 remap;
310 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; 310 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
311 311
312 debugf3("\n"); 312 edac_dbg(3, "\n");
313 313
314 if (page < pvt->tolm) 314 if (page < pvt->tolm)
315 return page; 315 return page;
@@ -335,7 +335,7 @@ static void do_process_ce(struct mem_ctl_info *mci, u16 error_one,
335 int i; 335 int i;
336 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; 336 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
337 337
338 debugf3("\n"); 338 edac_dbg(3, "\n");
339 339
340 /* convert the addr to 4k page */ 340 /* convert the addr to 4k page */
341 page = sec1_add >> (PAGE_SHIFT - 4); 341 page = sec1_add >> (PAGE_SHIFT - 4);
@@ -394,7 +394,7 @@ static void do_process_ue(struct mem_ctl_info *mci, u16 error_one,
394 int row; 394 int row;
395 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; 395 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
396 396
397 debugf3("\n"); 397 edac_dbg(3, "\n");
398 398
399 if (error_one & 0x0202) { 399 if (error_one & 0x0202) {
400 error_2b = ded_add; 400 error_2b = ded_add;
@@ -453,7 +453,7 @@ static inline void process_ue_no_info_wr(struct mem_ctl_info *mci,
453 if (!handle_error) 453 if (!handle_error)
454 return; 454 return;
455 455
456 debugf3("\n"); 456 edac_dbg(3, "\n");
457 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 0, 0, 0, 457 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 0, 0, 0,
458 -1, -1, -1, 458 -1, -1, -1,
459 "e752x UE log memory write", "", NULL); 459 "e752x UE log memory write", "", NULL);
@@ -982,7 +982,7 @@ static void e752x_check(struct mem_ctl_info *mci)
982{ 982{
983 struct e752x_error_info info; 983 struct e752x_error_info info;
984 984
985 debugf3("\n"); 985 edac_dbg(3, "\n");
986 e752x_get_error_info(mci, &info); 986 e752x_get_error_info(mci, &info);
987 e752x_process_error_info(mci, &info, 1); 987 e752x_process_error_info(mci, &info, 1);
988} 988}
@@ -1102,8 +1102,7 @@ static void e752x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
1102 pci_read_config_byte(pdev, E752X_DRB + index, &value); 1102 pci_read_config_byte(pdev, E752X_DRB + index, &value);
1103 /* convert a 128 or 64 MiB DRB to a page size. */ 1103 /* convert a 128 or 64 MiB DRB to a page size. */
1104 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT); 1104 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
1105 debugf3("(%d) cumul_size 0x%x\n", index, 1105 edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
1106 cumul_size);
1107 if (cumul_size == last_cumul_size) 1106 if (cumul_size == last_cumul_size)
1108 continue; /* not populated */ 1107 continue; /* not populated */
1109 1108
@@ -1129,7 +1128,7 @@ static void e752x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
1129 for (i = 0; i < csrow->nr_channels; i++) { 1128 for (i = 0; i < csrow->nr_channels; i++) {
1130 struct dimm_info *dimm = csrow->channels[i]->dimm; 1129 struct dimm_info *dimm = csrow->channels[i]->dimm;
1131 1130
1132 debugf3("Initializing rank at (%i,%i)\n", index, i); 1131 edac_dbg(3, "Initializing rank at (%i,%i)\n", index, i);
1133 dimm->nr_pages = nr_pages / csrow->nr_channels; 1132 dimm->nr_pages = nr_pages / csrow->nr_channels;
1134 dimm->grain = 1 << 12; /* 4KiB - resolution of CELOG */ 1133 dimm->grain = 1 << 12; /* 4KiB - resolution of CELOG */
1135 dimm->mtype = MEM_RDDR; /* only one type supported */ 1134 dimm->mtype = MEM_RDDR; /* only one type supported */
@@ -1270,8 +1269,8 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
1270 int drc_chan; /* Number of channels 0=1chan,1=2chan */ 1269 int drc_chan; /* Number of channels 0=1chan,1=2chan */
1271 struct e752x_error_info discard; 1270 struct e752x_error_info discard;
1272 1271
1273 debugf0("mci\n"); 1272 edac_dbg(0, "mci\n");
1274 debugf0("Starting Probe1\n"); 1273 edac_dbg(0, "Starting Probe1\n");
1275 1274
1276 /* check to see if device 0 function 1 is enabled; if it isn't, we 1275 /* check to see if device 0 function 1 is enabled; if it isn't, we
1277 * assume the BIOS has reserved it for a reason and is expecting 1276 * assume the BIOS has reserved it for a reason and is expecting
@@ -1301,7 +1300,7 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
1301 if (mci == NULL) 1300 if (mci == NULL)
1302 return -ENOMEM; 1301 return -ENOMEM;
1303 1302
1304 debugf3("init mci\n"); 1303 edac_dbg(3, "init mci\n");
1305 mci->mtype_cap = MEM_FLAG_RDDR; 1304 mci->mtype_cap = MEM_FLAG_RDDR;
1306 /* 3100 IMCH supports SECDEC only */ 1305 /* 3100 IMCH supports SECDEC only */
1307 mci->edac_ctl_cap = (dev_idx == I3100) ? EDAC_FLAG_SECDED : 1306 mci->edac_ctl_cap = (dev_idx == I3100) ? EDAC_FLAG_SECDED :
@@ -1311,7 +1310,7 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
1311 mci->mod_ver = E752X_REVISION; 1310 mci->mod_ver = E752X_REVISION;
1312 mci->pdev = &pdev->dev; 1311 mci->pdev = &pdev->dev;
1313 1312
1314 debugf3("init pvt\n"); 1313 edac_dbg(3, "init pvt\n");
1315 pvt = (struct e752x_pvt *)mci->pvt_info; 1314 pvt = (struct e752x_pvt *)mci->pvt_info;
1316 pvt->dev_info = &e752x_devs[dev_idx]; 1315 pvt->dev_info = &e752x_devs[dev_idx];
1317 pvt->mc_symmetric = ((ddrcsr & 0x10) != 0); 1316 pvt->mc_symmetric = ((ddrcsr & 0x10) != 0);
@@ -1321,7 +1320,7 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
1321 return -ENODEV; 1320 return -ENODEV;
1322 } 1321 }
1323 1322
1324 debugf3("more mci init\n"); 1323 edac_dbg(3, "more mci init\n");
1325 mci->ctl_name = pvt->dev_info->ctl_name; 1324 mci->ctl_name = pvt->dev_info->ctl_name;
1326 mci->dev_name = pci_name(pdev); 1325 mci->dev_name = pci_name(pdev);
1327 mci->edac_check = e752x_check; 1326 mci->edac_check = e752x_check;
@@ -1343,7 +1342,7 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
1343 mci->edac_cap = EDAC_FLAG_SECDED; /* the only mode supported */ 1342 mci->edac_cap = EDAC_FLAG_SECDED; /* the only mode supported */
1344 else 1343 else
1345 mci->edac_cap |= EDAC_FLAG_NONE; 1344 mci->edac_cap |= EDAC_FLAG_NONE;
1346 debugf3("tolm, remapbase, remaplimit\n"); 1345 edac_dbg(3, "tolm, remapbase, remaplimit\n");
1347 1346
1348 /* load the top of low memory, remap base, and remap limit vars */ 1347 /* load the top of low memory, remap base, and remap limit vars */
1349 pci_read_config_word(pdev, E752X_TOLM, &pci_data); 1348 pci_read_config_word(pdev, E752X_TOLM, &pci_data);
@@ -1360,7 +1359,7 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
1360 * type of memory controller. The ID is therefore hardcoded to 0. 1359 * type of memory controller. The ID is therefore hardcoded to 0.
1361 */ 1360 */
1362 if (edac_mc_add_mc(mci)) { 1361 if (edac_mc_add_mc(mci)) {
1363 debugf3("failed edac_mc_add_mc()\n"); 1362 edac_dbg(3, "failed edac_mc_add_mc()\n");
1364 goto fail; 1363 goto fail;
1365 } 1364 }
1366 1365
@@ -1378,7 +1377,7 @@ static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
1378 } 1377 }
1379 1378
1380 /* get this far and it's successful */ 1379 /* get this far and it's successful */
1381 debugf3("success\n"); 1380 edac_dbg(3, "success\n");
1382 return 0; 1381 return 0;
1383 1382
1384fail: 1383fail:
@@ -1394,7 +1393,7 @@ fail:
1394static int __devinit e752x_init_one(struct pci_dev *pdev, 1393static int __devinit e752x_init_one(struct pci_dev *pdev,
1395 const struct pci_device_id *ent) 1394 const struct pci_device_id *ent)
1396{ 1395{
1397 debugf0("\n"); 1396 edac_dbg(0, "\n");
1398 1397
1399 /* wake up and enable device */ 1398 /* wake up and enable device */
1400 if (pci_enable_device(pdev) < 0) 1399 if (pci_enable_device(pdev) < 0)
@@ -1408,7 +1407,7 @@ static void __devexit e752x_remove_one(struct pci_dev *pdev)
1408 struct mem_ctl_info *mci; 1407 struct mem_ctl_info *mci;
1409 struct e752x_pvt *pvt; 1408 struct e752x_pvt *pvt;
1410 1409
1411 debugf0("\n"); 1410 edac_dbg(0, "\n");
1412 1411
1413 if (e752x_pci) 1412 if (e752x_pci)
1414 edac_pci_release_generic_ctl(e752x_pci); 1413 edac_pci_release_generic_ctl(e752x_pci);
@@ -1454,7 +1453,7 @@ static int __init e752x_init(void)
1454{ 1453{
1455 int pci_rc; 1454 int pci_rc;
1456 1455
1457 debugf3("\n"); 1456 edac_dbg(3, "\n");
1458 1457
1459 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 1458 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1460 opstate_init(); 1459 opstate_init();
@@ -1465,7 +1464,7 @@ static int __init e752x_init(void)
1465 1464
1466static void __exit e752x_exit(void) 1465static void __exit e752x_exit(void)
1467{ 1466{
1468 debugf3("\n"); 1467 edac_dbg(3, "\n");
1469 pci_unregister_driver(&e752x_driver); 1468 pci_unregister_driver(&e752x_driver);
1470} 1469}
1471 1470
diff --git a/drivers/edac/e7xxx_edac.c b/drivers/edac/e7xxx_edac.c
index 691d7067a14..3ce661e883f 100644
--- a/drivers/edac/e7xxx_edac.c
+++ b/drivers/edac/e7xxx_edac.c
@@ -166,7 +166,7 @@ static const struct e7xxx_dev_info e7xxx_devs[] = {
166/* FIXME - is this valid for both SECDED and S4ECD4ED? */ 166/* FIXME - is this valid for both SECDED and S4ECD4ED? */
167static inline int e7xxx_find_channel(u16 syndrome) 167static inline int e7xxx_find_channel(u16 syndrome)
168{ 168{
169 debugf3("\n"); 169 edac_dbg(3, "\n");
170 170
171 if ((syndrome & 0xff00) == 0) 171 if ((syndrome & 0xff00) == 0)
172 return 0; 172 return 0;
@@ -186,7 +186,7 @@ static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
186 u32 remap; 186 u32 remap;
187 struct e7xxx_pvt *pvt = (struct e7xxx_pvt *)mci->pvt_info; 187 struct e7xxx_pvt *pvt = (struct e7xxx_pvt *)mci->pvt_info;
188 188
189 debugf3("\n"); 189 edac_dbg(3, "\n");
190 190
191 if ((page < pvt->tolm) || 191 if ((page < pvt->tolm) ||
192 ((page >= 0x100000) && (page < pvt->remapbase))) 192 ((page >= 0x100000) && (page < pvt->remapbase)))
@@ -208,7 +208,7 @@ static void process_ce(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
208 int row; 208 int row;
209 int channel; 209 int channel;
210 210
211 debugf3("\n"); 211 edac_dbg(3, "\n");
212 /* read the error address */ 212 /* read the error address */
213 error_1b = info->dram_celog_add; 213 error_1b = info->dram_celog_add;
214 /* FIXME - should use PAGE_SHIFT */ 214 /* FIXME - should use PAGE_SHIFT */
@@ -225,7 +225,7 @@ static void process_ce(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
225 225
226static void process_ce_no_info(struct mem_ctl_info *mci) 226static void process_ce_no_info(struct mem_ctl_info *mci)
227{ 227{
228 debugf3("\n"); 228 edac_dbg(3, "\n");
229 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 0, 0, 0, -1, -1, -1, 229 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 0, 0, 0, -1, -1, -1,
230 "e7xxx CE log register overflow", "", NULL); 230 "e7xxx CE log register overflow", "", NULL);
231} 231}
@@ -235,7 +235,7 @@ static void process_ue(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
235 u32 error_2b, block_page; 235 u32 error_2b, block_page;
236 int row; 236 int row;
237 237
238 debugf3("\n"); 238 edac_dbg(3, "\n");
239 /* read the error address */ 239 /* read the error address */
240 error_2b = info->dram_uelog_add; 240 error_2b = info->dram_uelog_add;
241 /* FIXME - should use PAGE_SHIFT */ 241 /* FIXME - should use PAGE_SHIFT */
@@ -248,7 +248,7 @@ static void process_ue(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
248 248
249static void process_ue_no_info(struct mem_ctl_info *mci) 249static void process_ue_no_info(struct mem_ctl_info *mci)
250{ 250{
251 debugf3("\n"); 251 edac_dbg(3, "\n");
252 252
253 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 0, 0, 0, -1, -1, -1, 253 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 0, 0, 0, -1, -1, -1,
254 "e7xxx UE log register overflow", "", NULL); 254 "e7xxx UE log register overflow", "", NULL);
@@ -334,7 +334,7 @@ static void e7xxx_check(struct mem_ctl_info *mci)
334{ 334{
335 struct e7xxx_error_info info; 335 struct e7xxx_error_info info;
336 336
337 debugf3("\n"); 337 edac_dbg(3, "\n");
338 e7xxx_get_error_info(mci, &info); 338 e7xxx_get_error_info(mci, &info);
339 e7xxx_process_error_info(mci, &info, 1); 339 e7xxx_process_error_info(mci, &info, 1);
340} 340}
@@ -383,8 +383,7 @@ static void e7xxx_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
383 pci_read_config_byte(pdev, E7XXX_DRB + index, &value); 383 pci_read_config_byte(pdev, E7XXX_DRB + index, &value);
384 /* convert a 64 or 32 MiB DRB to a page size. */ 384 /* convert a 64 or 32 MiB DRB to a page size. */
385 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT); 385 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
386 debugf3("(%d) cumul_size 0x%x\n", index, 386 edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
387 cumul_size);
388 if (cumul_size == last_cumul_size) 387 if (cumul_size == last_cumul_size)
389 continue; /* not populated */ 388 continue; /* not populated */
390 389
@@ -430,7 +429,7 @@ static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
430 int drc_chan; 429 int drc_chan;
431 struct e7xxx_error_info discard; 430 struct e7xxx_error_info discard;
432 431
433 debugf0("mci\n"); 432 edac_dbg(0, "mci\n");
434 433
435 pci_read_config_dword(pdev, E7XXX_DRC, &drc); 434 pci_read_config_dword(pdev, E7XXX_DRC, &drc);
436 435
@@ -453,7 +452,7 @@ static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
453 if (mci == NULL) 452 if (mci == NULL)
454 return -ENOMEM; 453 return -ENOMEM;
455 454
456 debugf3("init mci\n"); 455 edac_dbg(3, "init mci\n");
457 mci->mtype_cap = MEM_FLAG_RDDR; 456 mci->mtype_cap = MEM_FLAG_RDDR;
458 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED | 457 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
459 EDAC_FLAG_S4ECD4ED; 458 EDAC_FLAG_S4ECD4ED;
@@ -461,7 +460,7 @@ static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
461 mci->mod_name = EDAC_MOD_STR; 460 mci->mod_name = EDAC_MOD_STR;
462 mci->mod_ver = E7XXX_REVISION; 461 mci->mod_ver = E7XXX_REVISION;
463 mci->pdev = &pdev->dev; 462 mci->pdev = &pdev->dev;
464 debugf3("init pvt\n"); 463 edac_dbg(3, "init pvt\n");
465 pvt = (struct e7xxx_pvt *)mci->pvt_info; 464 pvt = (struct e7xxx_pvt *)mci->pvt_info;
466 pvt->dev_info = &e7xxx_devs[dev_idx]; 465 pvt->dev_info = &e7xxx_devs[dev_idx];
467 pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL, 466 pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
@@ -474,14 +473,14 @@ static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
474 goto fail0; 473 goto fail0;
475 } 474 }
476 475
477 debugf3("more mci init\n"); 476 edac_dbg(3, "more mci init\n");
478 mci->ctl_name = pvt->dev_info->ctl_name; 477 mci->ctl_name = pvt->dev_info->ctl_name;
479 mci->dev_name = pci_name(pdev); 478 mci->dev_name = pci_name(pdev);
480 mci->edac_check = e7xxx_check; 479 mci->edac_check = e7xxx_check;
481 mci->ctl_page_to_phys = ctl_page_to_phys; 480 mci->ctl_page_to_phys = ctl_page_to_phys;
482 e7xxx_init_csrows(mci, pdev, dev_idx, drc); 481 e7xxx_init_csrows(mci, pdev, dev_idx, drc);
483 mci->edac_cap |= EDAC_FLAG_NONE; 482 mci->edac_cap |= EDAC_FLAG_NONE;
484 debugf3("tolm, remapbase, remaplimit\n"); 483 edac_dbg(3, "tolm, remapbase, remaplimit\n");
485 /* load the top of low memory, remap base, and remap limit vars */ 484 /* load the top of low memory, remap base, and remap limit vars */
486 pci_read_config_word(pdev, E7XXX_TOLM, &pci_data); 485 pci_read_config_word(pdev, E7XXX_TOLM, &pci_data);
487 pvt->tolm = ((u32) pci_data) << 4; 486 pvt->tolm = ((u32) pci_data) << 4;
@@ -500,7 +499,7 @@ static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
500 * type of memory controller. The ID is therefore hardcoded to 0. 499 * type of memory controller. The ID is therefore hardcoded to 0.
501 */ 500 */
502 if (edac_mc_add_mc(mci)) { 501 if (edac_mc_add_mc(mci)) {
503 debugf3("failed edac_mc_add_mc()\n"); 502 edac_dbg(3, "failed edac_mc_add_mc()\n");
504 goto fail1; 503 goto fail1;
505 } 504 }
506 505
@@ -516,7 +515,7 @@ static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
516 } 515 }
517 516
518 /* get this far and it's successful */ 517 /* get this far and it's successful */
519 debugf3("success\n"); 518 edac_dbg(3, "success\n");
520 return 0; 519 return 0;
521 520
522fail1: 521fail1:
@@ -532,7 +531,7 @@ fail0:
532static int __devinit e7xxx_init_one(struct pci_dev *pdev, 531static int __devinit e7xxx_init_one(struct pci_dev *pdev,
533 const struct pci_device_id *ent) 532 const struct pci_device_id *ent)
534{ 533{
535 debugf0("\n"); 534 edac_dbg(0, "\n");
536 535
537 /* wake up and enable device */ 536 /* wake up and enable device */
538 return pci_enable_device(pdev) ? 537 return pci_enable_device(pdev) ?
@@ -544,7 +543,7 @@ static void __devexit e7xxx_remove_one(struct pci_dev *pdev)
544 struct mem_ctl_info *mci; 543 struct mem_ctl_info *mci;
545 struct e7xxx_pvt *pvt; 544 struct e7xxx_pvt *pvt;
546 545
547 debugf0("\n"); 546 edac_dbg(0, "\n");
548 547
549 if (e7xxx_pci) 548 if (e7xxx_pci)
550 edac_pci_release_generic_ctl(e7xxx_pci); 549 edac_pci_release_generic_ctl(e7xxx_pci);
diff --git a/drivers/edac/edac_core.h b/drivers/edac/edac_core.h
index 410738bf30f..ee25f5483f9 100644
--- a/drivers/edac/edac_core.h
+++ b/drivers/edac/edac_core.h
@@ -71,7 +71,7 @@ extern const char *edac_mem_types[];
71#ifdef CONFIG_EDAC_DEBUG 71#ifdef CONFIG_EDAC_DEBUG
72extern int edac_debug_level; 72extern int edac_debug_level;
73 73
74#define edac_debug_printk(level, fmt, ...) \ 74#define edac_dbg(level, fmt, ...) \
75do { \ 75do { \
76 if (level <= edac_debug_level) \ 76 if (level <= edac_debug_level) \
77 edac_printk(KERN_DEBUG, EDAC_DEBUG, \ 77 edac_printk(KERN_DEBUG, EDAC_DEBUG, \
@@ -80,7 +80,7 @@ do { \
80 80
81#else /* !CONFIG_EDAC_DEBUG */ 81#else /* !CONFIG_EDAC_DEBUG */
82 82
83#define edac_debug_printk(level, fmt, ...) \ 83#define edac_dbg(level, fmt, ...) \
84do { \ 84do { \
85 if (0) \ 85 if (0) \
86 edac_printk(KERN_DEBUG, EDAC_DEBUG, \ 86 edac_printk(KERN_DEBUG, EDAC_DEBUG, \
@@ -89,12 +89,6 @@ do { \
89 89
90#endif /* !CONFIG_EDAC_DEBUG */ 90#endif /* !CONFIG_EDAC_DEBUG */
91 91
92#define debugf0(fmt, ...) edac_debug_printk(0, fmt, ##__VA_ARGS__)
93#define debugf1(fmt, ...) edac_debug_printk(1, fmt, ##__VA_ARGS__)
94#define debugf2(fmt, ...) edac_debug_printk(2, fmt, ##__VA_ARGS__)
95#define debugf3(fmt, ...) edac_debug_printk(3, fmt, ##__VA_ARGS__)
96#define debugf4(fmt, ...) edac_debug_printk(4, fmt, ##__VA_ARGS__)
97
98#define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \ 92#define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
99 PCI_DEVICE_ID_ ## vend ## _ ## dev 93 PCI_DEVICE_ID_ ## vend ## _ ## dev
100 94
diff --git a/drivers/edac/edac_device.c b/drivers/edac/edac_device.c
index ed46949f25c..9523e76191f 100644
--- a/drivers/edac/edac_device.c
+++ b/drivers/edac/edac_device.c
@@ -40,12 +40,13 @@ static LIST_HEAD(edac_device_list);
40#ifdef CONFIG_EDAC_DEBUG 40#ifdef CONFIG_EDAC_DEBUG
41static void edac_device_dump_device(struct edac_device_ctl_info *edac_dev) 41static void edac_device_dump_device(struct edac_device_ctl_info *edac_dev)
42{ 42{
43 debugf3("\tedac_dev = %p dev_idx=%d \n", edac_dev, edac_dev->dev_idx); 43 edac_dbg(3, "\tedac_dev = %p dev_idx=%d\n",
44 debugf4("\tedac_dev->edac_check = %p\n", edac_dev->edac_check); 44 edac_dev, edac_dev->dev_idx);
45 debugf3("\tdev = %p\n", edac_dev->dev); 45 edac_dbg(4, "\tedac_dev->edac_check = %p\n", edac_dev->edac_check);
46 debugf3("\tmod_name:ctl_name = %s:%s\n", 46 edac_dbg(3, "\tdev = %p\n", edac_dev->dev);
47 edac_dev->mod_name, edac_dev->ctl_name); 47 edac_dbg(3, "\tmod_name:ctl_name = %s:%s\n",
48 debugf3("\tpvt_info = %p\n\n", edac_dev->pvt_info); 48 edac_dev->mod_name, edac_dev->ctl_name);
49 edac_dbg(3, "\tpvt_info = %p\n\n", edac_dev->pvt_info);
49} 50}
50#endif /* CONFIG_EDAC_DEBUG */ 51#endif /* CONFIG_EDAC_DEBUG */
51 52
@@ -82,8 +83,7 @@ struct edac_device_ctl_info *edac_device_alloc_ctl_info(
82 void *pvt, *p; 83 void *pvt, *p;
83 int err; 84 int err;
84 85
85 debugf4("instances=%d blocks=%d\n", 86 edac_dbg(4, "instances=%d blocks=%d\n", nr_instances, nr_blocks);
86 nr_instances, nr_blocks);
87 87
88 /* Calculate the size of memory we need to allocate AND 88 /* Calculate the size of memory we need to allocate AND
89 * determine the offsets of the various item arrays 89 * determine the offsets of the various item arrays
@@ -156,8 +156,8 @@ struct edac_device_ctl_info *edac_device_alloc_ctl_info(
156 /* Name of this edac device */ 156 /* Name of this edac device */
157 snprintf(dev_ctl->name,sizeof(dev_ctl->name),"%s",edac_device_name); 157 snprintf(dev_ctl->name,sizeof(dev_ctl->name),"%s",edac_device_name);
158 158
159 debugf4("edac_dev=%p next after end=%p\n", 159 edac_dbg(4, "edac_dev=%p next after end=%p\n",
160 dev_ctl, pvt + sz_private ); 160 dev_ctl, pvt + sz_private);
161 161
162 /* Initialize every Instance */ 162 /* Initialize every Instance */
163 for (instance = 0; instance < nr_instances; instance++) { 163 for (instance = 0; instance < nr_instances; instance++) {
@@ -178,10 +178,8 @@ struct edac_device_ctl_info *edac_device_alloc_ctl_info(
178 snprintf(blk->name, sizeof(blk->name), 178 snprintf(blk->name, sizeof(blk->name),
179 "%s%d", edac_block_name, block+offset_value); 179 "%s%d", edac_block_name, block+offset_value);
180 180
181 debugf4("instance=%d inst_p=%p block=#%d " 181 edac_dbg(4, "instance=%d inst_p=%p block=#%d block_p=%p name='%s'\n",
182 "block_p=%p name='%s'\n", 182 instance, inst, block, blk, blk->name);
183 instance, inst, block,
184 blk, blk->name);
185 183
186 /* if there are NO attributes OR no attribute pointer 184 /* if there are NO attributes OR no attribute pointer
187 * then continue on to next block iteration 185 * then continue on to next block iteration
@@ -194,8 +192,8 @@ struct edac_device_ctl_info *edac_device_alloc_ctl_info(
194 attrib_p = &dev_attrib[block*nr_instances*nr_attrib]; 192 attrib_p = &dev_attrib[block*nr_instances*nr_attrib];
195 blk->block_attributes = attrib_p; 193 blk->block_attributes = attrib_p;
196 194
197 debugf4("THIS BLOCK_ATTRIB=%p\n", 195 edac_dbg(4, "THIS BLOCK_ATTRIB=%p\n",
198 blk->block_attributes); 196 blk->block_attributes);
199 197
200 /* Initialize every user specified attribute in this 198 /* Initialize every user specified attribute in this
201 * block with the data the caller passed in 199 * block with the data the caller passed in
@@ -214,11 +212,10 @@ struct edac_device_ctl_info *edac_device_alloc_ctl_info(
214 212
215 attrib->block = blk; /* up link */ 213 attrib->block = blk; /* up link */
216 214
217 debugf4("alloc-attrib=%p attrib_name='%s' " 215 edac_dbg(4, "alloc-attrib=%p attrib_name='%s' attrib-spec=%p spec-name=%s\n",
218 "attrib-spec=%p spec-name=%s\n", 216 attrib, attrib->attr.name,
219 attrib, attrib->attr.name, 217 &attrib_spec[attr],
220 &attrib_spec[attr], 218 attrib_spec[attr].attr.name
221 attrib_spec[attr].attr.name
222 ); 219 );
223 } 220 }
224 } 221 }
@@ -273,7 +270,7 @@ static struct edac_device_ctl_info *find_edac_device_by_dev(struct device *dev)
273 struct edac_device_ctl_info *edac_dev; 270 struct edac_device_ctl_info *edac_dev;
274 struct list_head *item; 271 struct list_head *item;
275 272
276 debugf0("\n"); 273 edac_dbg(0, "\n");
277 274
278 list_for_each(item, &edac_device_list) { 275 list_for_each(item, &edac_device_list) {
279 edac_dev = list_entry(item, struct edac_device_ctl_info, link); 276 edac_dev = list_entry(item, struct edac_device_ctl_info, link);
@@ -408,7 +405,7 @@ static void edac_device_workq_function(struct work_struct *work_req)
408void edac_device_workq_setup(struct edac_device_ctl_info *edac_dev, 405void edac_device_workq_setup(struct edac_device_ctl_info *edac_dev,
409 unsigned msec) 406 unsigned msec)
410{ 407{
411 debugf0("\n"); 408 edac_dbg(0, "\n");
412 409
413 /* take the arg 'msec' and set it into the control structure 410 /* take the arg 'msec' and set it into the control structure
414 * to used in the time period calculation 411 * to used in the time period calculation
@@ -496,7 +493,7 @@ EXPORT_SYMBOL_GPL(edac_device_alloc_index);
496 */ 493 */
497int edac_device_add_device(struct edac_device_ctl_info *edac_dev) 494int edac_device_add_device(struct edac_device_ctl_info *edac_dev)
498{ 495{
499 debugf0("\n"); 496 edac_dbg(0, "\n");
500 497
501#ifdef CONFIG_EDAC_DEBUG 498#ifdef CONFIG_EDAC_DEBUG
502 if (edac_debug_level >= 3) 499 if (edac_debug_level >= 3)
@@ -570,7 +567,7 @@ struct edac_device_ctl_info *edac_device_del_device(struct device *dev)
570{ 567{
571 struct edac_device_ctl_info *edac_dev; 568 struct edac_device_ctl_info *edac_dev;
572 569
573 debugf0("\n"); 570 edac_dbg(0, "\n");
574 571
575 mutex_lock(&device_ctls_mutex); 572 mutex_lock(&device_ctls_mutex);
576 573
diff --git a/drivers/edac/edac_device_sysfs.c b/drivers/edac/edac_device_sysfs.c
index 1cee83ec35f..fb68a06ad68 100644
--- a/drivers/edac/edac_device_sysfs.c
+++ b/drivers/edac/edac_device_sysfs.c
@@ -202,7 +202,7 @@ static void edac_device_ctrl_master_release(struct kobject *kobj)
202{ 202{
203 struct edac_device_ctl_info *edac_dev = to_edacdev(kobj); 203 struct edac_device_ctl_info *edac_dev = to_edacdev(kobj);
204 204
205 debugf4("control index=%d\n", edac_dev->dev_idx); 205 edac_dbg(4, "control index=%d\n", edac_dev->dev_idx);
206 206
207 /* decrement the EDAC CORE module ref count */ 207 /* decrement the EDAC CORE module ref count */
208 module_put(edac_dev->owner); 208 module_put(edac_dev->owner);
@@ -233,12 +233,12 @@ int edac_device_register_sysfs_main_kobj(struct edac_device_ctl_info *edac_dev)
233 struct bus_type *edac_subsys; 233 struct bus_type *edac_subsys;
234 int err; 234 int err;
235 235
236 debugf1("\n"); 236 edac_dbg(1, "\n");
237 237
238 /* get the /sys/devices/system/edac reference */ 238 /* get the /sys/devices/system/edac reference */
239 edac_subsys = edac_get_sysfs_subsys(); 239 edac_subsys = edac_get_sysfs_subsys();
240 if (edac_subsys == NULL) { 240 if (edac_subsys == NULL) {
241 debugf1("no edac_subsys error\n"); 241 edac_dbg(1, "no edac_subsys error\n");
242 err = -ENODEV; 242 err = -ENODEV;
243 goto err_out; 243 goto err_out;
244 } 244 }
@@ -264,8 +264,8 @@ int edac_device_register_sysfs_main_kobj(struct edac_device_ctl_info *edac_dev)
264 &edac_subsys->dev_root->kobj, 264 &edac_subsys->dev_root->kobj,
265 "%s", edac_dev->name); 265 "%s", edac_dev->name);
266 if (err) { 266 if (err) {
267 debugf1("Failed to register '.../edac/%s'\n", 267 edac_dbg(1, "Failed to register '.../edac/%s'\n",
268 edac_dev->name); 268 edac_dev->name);
269 goto err_kobj_reg; 269 goto err_kobj_reg;
270 } 270 }
271 kobject_uevent(&edac_dev->kobj, KOBJ_ADD); 271 kobject_uevent(&edac_dev->kobj, KOBJ_ADD);
@@ -274,8 +274,7 @@ int edac_device_register_sysfs_main_kobj(struct edac_device_ctl_info *edac_dev)
274 * edac_device_unregister_sysfs_main_kobj() must be used 274 * edac_device_unregister_sysfs_main_kobj() must be used
275 */ 275 */
276 276
277 debugf4("Registered '.../edac/%s' kobject\n", 277 edac_dbg(4, "Registered '.../edac/%s' kobject\n", edac_dev->name);
278 edac_dev->name);
279 278
280 return 0; 279 return 0;
281 280
@@ -296,9 +295,8 @@ err_out:
296 */ 295 */
297void edac_device_unregister_sysfs_main_kobj(struct edac_device_ctl_info *dev) 296void edac_device_unregister_sysfs_main_kobj(struct edac_device_ctl_info *dev)
298{ 297{
299 debugf0("\n"); 298 edac_dbg(0, "\n");
300 debugf4("name of kobject is: %s\n", 299 edac_dbg(4, "name of kobject is: %s\n", kobject_name(&dev->kobj));
301 kobject_name(&dev->kobj));
302 300
303 /* 301 /*
304 * Unregister the edac device's kobject and 302 * Unregister the edac device's kobject and
@@ -336,7 +334,7 @@ static void edac_device_ctrl_instance_release(struct kobject *kobj)
336{ 334{
337 struct edac_device_instance *instance; 335 struct edac_device_instance *instance;
338 336
339 debugf1("\n"); 337 edac_dbg(1, "\n");
340 338
341 /* map from this kobj to the main control struct 339 /* map from this kobj to the main control struct
342 * and then dec the main kobj count 340 * and then dec the main kobj count
@@ -442,7 +440,7 @@ static void edac_device_ctrl_block_release(struct kobject *kobj)
442{ 440{
443 struct edac_device_block *block; 441 struct edac_device_block *block;
444 442
445 debugf1("\n"); 443 edac_dbg(1, "\n");
446 444
447 /* get the container of the kobj */ 445 /* get the container of the kobj */
448 block = to_block(kobj); 446 block = to_block(kobj);
@@ -524,10 +522,10 @@ static int edac_device_create_block(struct edac_device_ctl_info *edac_dev,
524 struct edac_dev_sysfs_block_attribute *sysfs_attrib; 522 struct edac_dev_sysfs_block_attribute *sysfs_attrib;
525 struct kobject *main_kobj; 523 struct kobject *main_kobj;
526 524
527 debugf4("Instance '%s' inst_p=%p block '%s' block_p=%p\n", 525 edac_dbg(4, "Instance '%s' inst_p=%p block '%s' block_p=%p\n",
528 instance->name, instance, block->name, block); 526 instance->name, instance, block->name, block);
529 debugf4("block kobj=%p block kobj->parent=%p\n", 527 edac_dbg(4, "block kobj=%p block kobj->parent=%p\n",
530 &block->kobj, &block->kobj.parent); 528 &block->kobj, &block->kobj.parent);
531 529
532 /* init this block's kobject */ 530 /* init this block's kobject */
533 memset(&block->kobj, 0, sizeof(struct kobject)); 531 memset(&block->kobj, 0, sizeof(struct kobject));
@@ -546,8 +544,7 @@ static int edac_device_create_block(struct edac_device_ctl_info *edac_dev,
546 &instance->kobj, 544 &instance->kobj,
547 "%s", block->name); 545 "%s", block->name);
548 if (err) { 546 if (err) {
549 debugf1("Failed to register instance '%s'\n", 547 edac_dbg(1, "Failed to register instance '%s'\n", block->name);
550 block->name);
551 kobject_put(main_kobj); 548 kobject_put(main_kobj);
552 err = -ENODEV; 549 err = -ENODEV;
553 goto err_out; 550 goto err_out;
@@ -560,10 +557,9 @@ static int edac_device_create_block(struct edac_device_ctl_info *edac_dev,
560 if (sysfs_attrib && block->nr_attribs) { 557 if (sysfs_attrib && block->nr_attribs) {
561 for (i = 0; i < block->nr_attribs; i++, sysfs_attrib++) { 558 for (i = 0; i < block->nr_attribs; i++, sysfs_attrib++) {
562 559
563 debugf4("creating block attrib='%s' " 560 edac_dbg(4, "creating block attrib='%s' attrib->%p to kobj=%p\n",
564 "attrib->%p to kobj=%p\n", 561 sysfs_attrib->attr.name,
565 sysfs_attrib->attr.name, 562 sysfs_attrib, &block->kobj);
566 sysfs_attrib, &block->kobj);
567 563
568 /* Create each block_attribute file */ 564 /* Create each block_attribute file */
569 err = sysfs_create_file(&block->kobj, 565 err = sysfs_create_file(&block->kobj,
@@ -646,14 +642,14 @@ static int edac_device_create_instance(struct edac_device_ctl_info *edac_dev,
646 err = kobject_init_and_add(&instance->kobj, &ktype_instance_ctrl, 642 err = kobject_init_and_add(&instance->kobj, &ktype_instance_ctrl,
647 &edac_dev->kobj, "%s", instance->name); 643 &edac_dev->kobj, "%s", instance->name);
648 if (err != 0) { 644 if (err != 0) {
649 debugf2("Failed to register instance '%s'\n", 645 edac_dbg(2, "Failed to register instance '%s'\n",
650 instance->name); 646 instance->name);
651 kobject_put(main_kobj); 647 kobject_put(main_kobj);
652 goto err_out; 648 goto err_out;
653 } 649 }
654 650
655 debugf4("now register '%d' blocks for instance %d\n", 651 edac_dbg(4, "now register '%d' blocks for instance %d\n",
656 instance->nr_blocks, idx); 652 instance->nr_blocks, idx);
657 653
658 /* register all blocks of this instance */ 654 /* register all blocks of this instance */
659 for (i = 0; i < instance->nr_blocks; i++) { 655 for (i = 0; i < instance->nr_blocks; i++) {
@@ -669,8 +665,8 @@ static int edac_device_create_instance(struct edac_device_ctl_info *edac_dev,
669 } 665 }
670 kobject_uevent(&instance->kobj, KOBJ_ADD); 666 kobject_uevent(&instance->kobj, KOBJ_ADD);
671 667
672 debugf4("Registered instance %d '%s' kobject\n", 668 edac_dbg(4, "Registered instance %d '%s' kobject\n",
673 idx, instance->name); 669 idx, instance->name);
674 670
675 return 0; 671 return 0;
676 672
@@ -714,7 +710,7 @@ static int edac_device_create_instances(struct edac_device_ctl_info *edac_dev)
714 int i, j; 710 int i, j;
715 int err; 711 int err;
716 712
717 debugf0("\n"); 713 edac_dbg(0, "\n");
718 714
719 /* iterate over creation of the instances */ 715 /* iterate over creation of the instances */
720 for (i = 0; i < edac_dev->nr_instances; i++) { 716 for (i = 0; i < edac_dev->nr_instances; i++) {
@@ -816,12 +812,12 @@ int edac_device_create_sysfs(struct edac_device_ctl_info *edac_dev)
816 int err; 812 int err;
817 struct kobject *edac_kobj = &edac_dev->kobj; 813 struct kobject *edac_kobj = &edac_dev->kobj;
818 814
819 debugf0("idx=%d\n", edac_dev->dev_idx); 815 edac_dbg(0, "idx=%d\n", edac_dev->dev_idx);
820 816
821 /* go create any main attributes callers wants */ 817 /* go create any main attributes callers wants */
822 err = edac_device_add_main_sysfs_attributes(edac_dev); 818 err = edac_device_add_main_sysfs_attributes(edac_dev);
823 if (err) { 819 if (err) {
824 debugf0("failed to add sysfs attribs\n"); 820 edac_dbg(0, "failed to add sysfs attribs\n");
825 goto err_out; 821 goto err_out;
826 } 822 }
827 823
@@ -831,8 +827,7 @@ int edac_device_create_sysfs(struct edac_device_ctl_info *edac_dev)
831 err = sysfs_create_link(edac_kobj, 827 err = sysfs_create_link(edac_kobj,
832 &edac_dev->dev->kobj, EDAC_DEVICE_SYMLINK); 828 &edac_dev->dev->kobj, EDAC_DEVICE_SYMLINK);
833 if (err) { 829 if (err) {
834 debugf0("sysfs_create_link() returned err= %d\n", 830 edac_dbg(0, "sysfs_create_link() returned err= %d\n", err);
835 err);
836 goto err_remove_main_attribs; 831 goto err_remove_main_attribs;
837 } 832 }
838 833
@@ -842,14 +837,13 @@ int edac_device_create_sysfs(struct edac_device_ctl_info *edac_dev)
842 */ 837 */
843 err = edac_device_create_instances(edac_dev); 838 err = edac_device_create_instances(edac_dev);
844 if (err) { 839 if (err) {
845 debugf0("edac_device_create_instances() " 840 edac_dbg(0, "edac_device_create_instances() returned err= %d\n",
846 "returned err= %d\n", err); 841 err);
847 goto err_remove_link; 842 goto err_remove_link;
848 } 843 }
849 844
850 845
851 debugf4("create-instances done, idx=%d\n", 846 edac_dbg(4, "create-instances done, idx=%d\n", edac_dev->dev_idx);
852 edac_dev->dev_idx);
853 847
854 return 0; 848 return 0;
855 849
@@ -872,7 +866,7 @@ err_out:
872 */ 866 */
873void edac_device_remove_sysfs(struct edac_device_ctl_info *edac_dev) 867void edac_device_remove_sysfs(struct edac_device_ctl_info *edac_dev)
874{ 868{
875 debugf0("\n"); 869 edac_dbg(0, "\n");
876 870
877 /* remove any main attributes for this device */ 871 /* remove any main attributes for this device */
878 edac_device_remove_main_sysfs_attributes(edac_dev); 872 edac_device_remove_main_sysfs_attributes(edac_dev);
diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c
index 4df9c4ac63c..a39fe6f966e 100644
--- a/drivers/edac/edac_mc.c
+++ b/drivers/edac/edac_mc.c
@@ -46,56 +46,57 @@ static LIST_HEAD(mc_devices);
46 46
47static void edac_mc_dump_channel(struct rank_info *chan) 47static void edac_mc_dump_channel(struct rank_info *chan)
48{ 48{
49 debugf4("\tchannel = %p\n", chan); 49 edac_dbg(4, "\tchannel = %p\n", chan);
50 debugf4("\tchannel->chan_idx = %d\n", chan->chan_idx); 50 edac_dbg(4, "\tchannel->chan_idx = %d\n", chan->chan_idx);
51 debugf4("\tchannel->csrow = %p\n\n", chan->csrow); 51 edac_dbg(4, "\tchannel->csrow = %p\n", chan->csrow);
52 debugf4("\tchannel->dimm = %p\n", chan->dimm); 52 edac_dbg(4, "\tchannel->dimm = %p\n", chan->dimm);
53} 53}
54 54
55static void edac_mc_dump_dimm(struct dimm_info *dimm) 55static void edac_mc_dump_dimm(struct dimm_info *dimm)
56{ 56{
57 int i; 57 int i;
58 58
59 debugf4("\tdimm = %p\n", dimm); 59 edac_dbg(4, "\tdimm = %p\n", dimm);
60 debugf4("\tdimm->label = '%s'\n", dimm->label); 60 edac_dbg(4, "\tdimm->label = '%s'\n", dimm->label);
61 debugf4("\tdimm->nr_pages = 0x%x\n", dimm->nr_pages); 61 edac_dbg(4, "\tdimm->nr_pages = 0x%x\n", dimm->nr_pages);
62 debugf4("\tdimm location "); 62 edac_dbg(4, "\tdimm location ");
63 for (i = 0; i < dimm->mci->n_layers; i++) { 63 for (i = 0; i < dimm->mci->n_layers; i++) {
64 printk(KERN_CONT "%d", dimm->location[i]); 64 printk(KERN_CONT "%d", dimm->location[i]);
65 if (i < dimm->mci->n_layers - 1) 65 if (i < dimm->mci->n_layers - 1)
66 printk(KERN_CONT "."); 66 printk(KERN_CONT ".");
67 } 67 }
68 printk(KERN_CONT "\n"); 68 printk(KERN_CONT "\n");
69 debugf4("\tdimm->grain = %d\n", dimm->grain); 69 edac_dbg(4, "\tdimm->grain = %d\n", dimm->grain);
70 debugf4("\tdimm->nr_pages = 0x%x\n", dimm->nr_pages); 70 edac_dbg(4, "\tdimm->nr_pages = 0x%x\n", dimm->nr_pages);
71} 71}
72 72
73static void edac_mc_dump_csrow(struct csrow_info *csrow) 73static void edac_mc_dump_csrow(struct csrow_info *csrow)
74{ 74{
75 debugf4("\tcsrow = %p\n", csrow); 75 edac_dbg(4, "\tcsrow = %p\n", csrow);
76 debugf4("\tcsrow->csrow_idx = %d\n", csrow->csrow_idx); 76 edac_dbg(4, "\tcsrow->csrow_idx = %d\n", csrow->csrow_idx);
77 debugf4("\tcsrow->first_page = 0x%lx\n", csrow->first_page); 77 edac_dbg(4, "\tcsrow->first_page = 0x%lx\n", csrow->first_page);
78 debugf4("\tcsrow->last_page = 0x%lx\n", csrow->last_page); 78 edac_dbg(4, "\tcsrow->last_page = 0x%lx\n", csrow->last_page);
79 debugf4("\tcsrow->page_mask = 0x%lx\n", csrow->page_mask); 79 edac_dbg(4, "\tcsrow->page_mask = 0x%lx\n", csrow->page_mask);
80 debugf4("\tcsrow->nr_channels = %d\n", csrow->nr_channels); 80 edac_dbg(4, "\tcsrow->nr_channels = %d\n", csrow->nr_channels);
81 debugf4("\tcsrow->channels = %p\n", csrow->channels); 81 edac_dbg(4, "\tcsrow->channels = %p\n", csrow->channels);
82 debugf4("\tcsrow->mci = %p\n\n", csrow->mci); 82 edac_dbg(4, "\tcsrow->mci = %p\n", csrow->mci);
83} 83}
84 84
85static void edac_mc_dump_mci(struct mem_ctl_info *mci) 85static void edac_mc_dump_mci(struct mem_ctl_info *mci)
86{ 86{
87 debugf3("\tmci = %p\n", mci); 87 edac_dbg(3, "\tmci = %p\n", mci);
88 debugf3("\tmci->mtype_cap = %lx\n", mci->mtype_cap); 88 edac_dbg(3, "\tmci->mtype_cap = %lx\n", mci->mtype_cap);
89 debugf3("\tmci->edac_ctl_cap = %lx\n", mci->edac_ctl_cap); 89 edac_dbg(3, "\tmci->edac_ctl_cap = %lx\n", mci->edac_ctl_cap);
90 debugf3("\tmci->edac_cap = %lx\n", mci->edac_cap); 90 edac_dbg(3, "\tmci->edac_cap = %lx\n", mci->edac_cap);
91 debugf4("\tmci->edac_check = %p\n", mci->edac_check); 91 edac_dbg(4, "\tmci->edac_check = %p\n", mci->edac_check);
92 debugf3("\tmci->nr_csrows = %d, csrows = %p\n", 92 edac_dbg(3, "\tmci->nr_csrows = %d, csrows = %p\n",
93 mci->nr_csrows, mci->csrows); 93 mci->nr_csrows, mci->csrows);
94 debugf3("\tmci->nr_dimms = %d, dimms = %p\n", 94 edac_dbg(3, "\tmci->nr_dimms = %d, dimms = %p\n",
95 mci->tot_dimms, mci->dimms); 95 mci->tot_dimms, mci->dimms);
96 debugf3("\tdev = %p\n", mci->pdev); 96 edac_dbg(3, "\tdev = %p\n", mci->pdev);
97 debugf3("\tmod_name:ctl_name = %s:%s\n", mci->mod_name, mci->ctl_name); 97 edac_dbg(3, "\tmod_name:ctl_name = %s:%s\n",
98 debugf3("\tpvt_info = %p\n\n", mci->pvt_info); 98 mci->mod_name, mci->ctl_name);
99 edac_dbg(3, "\tpvt_info = %p\n\n", mci->pvt_info);
99} 100}
100 101
101#endif /* CONFIG_EDAC_DEBUG */ 102#endif /* CONFIG_EDAC_DEBUG */
@@ -246,21 +247,21 @@ struct mem_ctl_info *edac_mc_alloc(unsigned mc_num,
246 layer = edac_align_ptr(&ptr, sizeof(*layer), n_layers); 247 layer = edac_align_ptr(&ptr, sizeof(*layer), n_layers);
247 for (i = 0; i < n_layers; i++) { 248 for (i = 0; i < n_layers; i++) {
248 count *= layers[i].size; 249 count *= layers[i].size;
249 debugf4("errcount layer %d size %d\n", i, count); 250 edac_dbg(4, "errcount layer %d size %d\n", i, count);
250 ce_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count); 251 ce_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count);
251 ue_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count); 252 ue_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count);
252 tot_errcount += 2 * count; 253 tot_errcount += 2 * count;
253 } 254 }
254 255
255 debugf4("allocating %d error counters\n", tot_errcount); 256 edac_dbg(4, "allocating %d error counters\n", tot_errcount);
256 pvt = edac_align_ptr(&ptr, sz_pvt, 1); 257 pvt = edac_align_ptr(&ptr, sz_pvt, 1);
257 size = ((unsigned long)pvt) + sz_pvt; 258 size = ((unsigned long)pvt) + sz_pvt;
258 259
259 debugf1("allocating %u bytes for mci data (%d %s, %d csrows/channels)\n", 260 edac_dbg(1, "allocating %u bytes for mci data (%d %s, %d csrows/channels)\n",
260 size, 261 size,
261 tot_dimms, 262 tot_dimms,
262 per_rank ? "ranks" : "dimms", 263 per_rank ? "ranks" : "dimms",
263 tot_csrows * tot_channels); 264 tot_csrows * tot_channels);
264 265
265 mci = kzalloc(size, GFP_KERNEL); 266 mci = kzalloc(size, GFP_KERNEL);
266 if (mci == NULL) 267 if (mci == NULL)
@@ -326,8 +327,8 @@ struct mem_ctl_info *edac_mc_alloc(unsigned mc_num,
326 memset(&pos, 0, sizeof(pos)); 327 memset(&pos, 0, sizeof(pos));
327 row = 0; 328 row = 0;
328 chn = 0; 329 chn = 0;
329 debugf4("initializing %d %s\n", tot_dimms, 330 edac_dbg(4, "initializing %d %s\n",
330 per_rank ? "ranks" : "dimms"); 331 tot_dimms, per_rank ? "ranks" : "dimms");
331 for (i = 0; i < tot_dimms; i++) { 332 for (i = 0; i < tot_dimms; i++) {
332 chan = mci->csrows[row]->channels[chn]; 333 chan = mci->csrows[row]->channels[chn];
333 off = EDAC_DIMM_OFF(layer, n_layers, pos[0], pos[1], pos[2]); 334 off = EDAC_DIMM_OFF(layer, n_layers, pos[0], pos[1], pos[2]);
@@ -340,9 +341,9 @@ struct mem_ctl_info *edac_mc_alloc(unsigned mc_num,
340 mci->dimms[off] = dimm; 341 mci->dimms[off] = dimm;
341 dimm->mci = mci; 342 dimm->mci = mci;
342 343
343 debugf2("%d: %s%i (%d:%d:%d): row %d, chan %d\n", i, 344 edac_dbg(2, "%d: %s%i (%d:%d:%d): row %d, chan %d\n",
344 per_rank ? "rank" : "dimm", off, 345 i, per_rank ? "rank" : "dimm", off,
345 pos[0], pos[1], pos[2], row, chn); 346 pos[0], pos[1], pos[2], row, chn);
346 347
347 /* 348 /*
348 * Copy DIMM location and initialize it. 349 * Copy DIMM location and initialize it.
@@ -427,7 +428,7 @@ EXPORT_SYMBOL_GPL(edac_mc_alloc);
427 */ 428 */
428void edac_mc_free(struct mem_ctl_info *mci) 429void edac_mc_free(struct mem_ctl_info *mci)
429{ 430{
430 debugf1("\n"); 431 edac_dbg(1, "\n");
431 432
432 /* the mci instance is freed here, when the sysfs object is dropped */ 433 /* the mci instance is freed here, when the sysfs object is dropped */
433 edac_unregister_sysfs(mci); 434 edac_unregister_sysfs(mci);
@@ -447,7 +448,7 @@ struct mem_ctl_info *find_mci_by_dev(struct device *dev)
447 struct mem_ctl_info *mci; 448 struct mem_ctl_info *mci;
448 struct list_head *item; 449 struct list_head *item;
449 450
450 debugf3("\n"); 451 edac_dbg(3, "\n");
451 452
452 list_for_each(item, &mc_devices) { 453 list_for_each(item, &mc_devices) {
453 mci = list_entry(item, struct mem_ctl_info, link); 454 mci = list_entry(item, struct mem_ctl_info, link);
@@ -515,7 +516,7 @@ static void edac_mc_workq_function(struct work_struct *work_req)
515 */ 516 */
516static void edac_mc_workq_setup(struct mem_ctl_info *mci, unsigned msec) 517static void edac_mc_workq_setup(struct mem_ctl_info *mci, unsigned msec)
517{ 518{
518 debugf0("\n"); 519 edac_dbg(0, "\n");
519 520
520 /* if this instance is not in the POLL state, then simply return */ 521 /* if this instance is not in the POLL state, then simply return */
521 if (mci->op_state != OP_RUNNING_POLL) 522 if (mci->op_state != OP_RUNNING_POLL)
@@ -542,7 +543,7 @@ static void edac_mc_workq_teardown(struct mem_ctl_info *mci)
542 543
543 status = cancel_delayed_work(&mci->work); 544 status = cancel_delayed_work(&mci->work);
544 if (status == 0) { 545 if (status == 0) {
545 debugf0("not canceled, flush the queue\n"); 546 edac_dbg(0, "not canceled, flush the queue\n");
546 547
547 /* workq instance might be running, wait for it */ 548 /* workq instance might be running, wait for it */
548 flush_workqueue(edac_workqueue); 549 flush_workqueue(edac_workqueue);
@@ -689,7 +690,7 @@ EXPORT_SYMBOL(edac_mc_find);
689/* FIXME - should a warning be printed if no error detection? correction? */ 690/* FIXME - should a warning be printed if no error detection? correction? */
690int edac_mc_add_mc(struct mem_ctl_info *mci) 691int edac_mc_add_mc(struct mem_ctl_info *mci)
691{ 692{
692 debugf0("\n"); 693 edac_dbg(0, "\n");
693 694
694#ifdef CONFIG_EDAC_DEBUG 695#ifdef CONFIG_EDAC_DEBUG
695 if (edac_debug_level >= 3) 696 if (edac_debug_level >= 3)
@@ -760,7 +761,7 @@ struct mem_ctl_info *edac_mc_del_mc(struct device *dev)
760{ 761{
761 struct mem_ctl_info *mci; 762 struct mem_ctl_info *mci;
762 763
763 debugf0("\n"); 764 edac_dbg(0, "\n");
764 765
765 mutex_lock(&mem_ctls_mutex); 766 mutex_lock(&mem_ctls_mutex);
766 767
@@ -798,7 +799,7 @@ static void edac_mc_scrub_block(unsigned long page, unsigned long offset,
798 void *virt_addr; 799 void *virt_addr;
799 unsigned long flags = 0; 800 unsigned long flags = 0;
800 801
801 debugf3("\n"); 802 edac_dbg(3, "\n");
802 803
803 /* ECC error page was not in our memory. Ignore it. */ 804 /* ECC error page was not in our memory. Ignore it. */
804 if (!pfn_valid(page)) 805 if (!pfn_valid(page))
@@ -828,7 +829,7 @@ int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, unsigned long page)
828 struct csrow_info **csrows = mci->csrows; 829 struct csrow_info **csrows = mci->csrows;
829 int row, i, j, n; 830 int row, i, j, n;
830 831
831 debugf1("MC%d: 0x%lx\n", mci->mc_idx, page); 832 edac_dbg(1, "MC%d: 0x%lx\n", mci->mc_idx, page);
832 row = -1; 833 row = -1;
833 834
834 for (i = 0; i < mci->nr_csrows; i++) { 835 for (i = 0; i < mci->nr_csrows; i++) {
@@ -841,10 +842,10 @@ int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, unsigned long page)
841 if (n == 0) 842 if (n == 0)
842 continue; 843 continue;
843 844
844 debugf3("MC%d: first(0x%lx) page(0x%lx) last(0x%lx) " 845 edac_dbg(3, "MC%d: first(0x%lx) page(0x%lx) last(0x%lx) mask(0x%lx)\n",
845 "mask(0x%lx)\n", mci->mc_idx, 846 mci->mc_idx,
846 csrow->first_page, page, csrow->last_page, 847 csrow->first_page, page, csrow->last_page,
847 csrow->page_mask); 848 csrow->page_mask);
848 849
849 if ((page >= csrow->first_page) && 850 if ((page >= csrow->first_page) &&
850 (page <= csrow->last_page) && 851 (page <= csrow->last_page) &&
@@ -1048,7 +1049,7 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type,
1048 u16 error_count; /* FIXME: make it a parameter */ 1049 u16 error_count; /* FIXME: make it a parameter */
1049 u8 grain_bits; 1050 u8 grain_bits;
1050 1051
1051 debugf3("MC%d\n", mci->mc_idx); 1052 edac_dbg(3, "MC%d\n", mci->mc_idx);
1052 1053
1053 /* 1054 /*
1054 * Check if the event report is consistent and if the memory 1055 * Check if the event report is consistent and if the memory
@@ -1126,10 +1127,9 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type,
1126 * get csrow/channel of the DIMM, in order to allow 1127 * get csrow/channel of the DIMM, in order to allow
1127 * incrementing the compat API counters 1128 * incrementing the compat API counters
1128 */ 1129 */
1129 debugf4("%s csrows map: (%d,%d)\n", 1130 edac_dbg(4, "%s csrows map: (%d,%d)\n",
1130 mci->mem_is_per_rank ? "rank" : "dimm", 1131 mci->mem_is_per_rank ? "rank" : "dimm",
1131 dimm->csrow, dimm->cschannel); 1132 dimm->csrow, dimm->cschannel);
1132
1133 if (row == -1) 1133 if (row == -1)
1134 row = dimm->csrow; 1134 row = dimm->csrow;
1135 else if (row >= 0 && row != dimm->csrow) 1135 else if (row >= 0 && row != dimm->csrow)
@@ -1145,8 +1145,7 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type,
1145 if (!enable_per_layer_report) { 1145 if (!enable_per_layer_report) {
1146 strcpy(label, "any memory"); 1146 strcpy(label, "any memory");
1147 } else { 1147 } else {
1148 debugf4("csrow/channel to increment: (%d,%d)\n", 1148 edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan);
1149 row, chan);
1150 if (p == label) 1149 if (p == label)
1151 strcpy(label, "unknown memory"); 1150 strcpy(label, "unknown memory");
1152 if (type == HW_EVENT_ERR_CORRECTED) { 1151 if (type == HW_EVENT_ERR_CORRECTED) {
diff --git a/drivers/edac/edac_mc_sysfs.c b/drivers/edac/edac_mc_sysfs.c
index f72de8ba6a3..eace646b57f 100644
--- a/drivers/edac/edac_mc_sysfs.c
+++ b/drivers/edac/edac_mc_sysfs.c
@@ -287,7 +287,7 @@ static void csrow_attr_release(struct device *dev)
287{ 287{
288 struct csrow_info *csrow = container_of(dev, struct csrow_info, dev); 288 struct csrow_info *csrow = container_of(dev, struct csrow_info, dev);
289 289
290 debugf1("Releasing csrow device %s\n", dev_name(dev)); 290 edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
291 kfree(csrow); 291 kfree(csrow);
292} 292}
293 293
@@ -376,7 +376,8 @@ static int edac_create_csrow_object(struct mem_ctl_info *mci,
376 dev_set_name(&csrow->dev, "csrow%d", index); 376 dev_set_name(&csrow->dev, "csrow%d", index);
377 dev_set_drvdata(&csrow->dev, csrow); 377 dev_set_drvdata(&csrow->dev, csrow);
378 378
379 debugf0("creating (virtual) csrow node %s\n", dev_name(&csrow->dev)); 379 edac_dbg(0, "creating (virtual) csrow node %s\n",
380 dev_name(&csrow->dev));
380 381
381 err = device_add(&csrow->dev); 382 err = device_add(&csrow->dev);
382 if (err < 0) 383 if (err < 0)
@@ -460,8 +461,8 @@ static void edac_delete_csrow_objects(struct mem_ctl_info *mci)
460 for (chan = csrow->nr_channels - 1; chan >= 0; chan--) { 461 for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
461 if (!csrow->channels[chan]->dimm->nr_pages) 462 if (!csrow->channels[chan]->dimm->nr_pages)
462 continue; 463 continue;
463 debugf1("Removing csrow %d channel %d sysfs nodes\n", 464 edac_dbg(1, "Removing csrow %d channel %d sysfs nodes\n",
464 i, chan); 465 i, chan);
465 device_remove_file(&csrow->dev, 466 device_remove_file(&csrow->dev,
466 dynamic_csrow_dimm_attr[chan]); 467 dynamic_csrow_dimm_attr[chan]);
467 device_remove_file(&csrow->dev, 468 device_remove_file(&csrow->dev,
@@ -591,7 +592,7 @@ static void dimm_attr_release(struct device *dev)
591{ 592{
592 struct dimm_info *dimm = container_of(dev, struct dimm_info, dev); 593 struct dimm_info *dimm = container_of(dev, struct dimm_info, dev);
593 594
594 debugf1("Releasing dimm device %s\n", dev_name(dev)); 595 edac_dbg(1, "Releasing dimm device %s\n", dev_name(dev));
595 kfree(dimm); 596 kfree(dimm);
596} 597}
597 598
@@ -622,7 +623,7 @@ static int edac_create_dimm_object(struct mem_ctl_info *mci,
622 623
623 err = device_add(&dimm->dev); 624 err = device_add(&dimm->dev);
624 625
625 debugf0("creating rank/dimm device %s\n", dev_name(&dimm->dev)); 626 edac_dbg(0, "creating rank/dimm device %s\n", dev_name(&dimm->dev));
626 627
627 return err; 628 return err;
628} 629}
@@ -897,7 +898,7 @@ static void mci_attr_release(struct device *dev)
897{ 898{
898 struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev); 899 struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
899 900
900 debugf1("Releasing csrow device %s\n", dev_name(dev)); 901 edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
901 kfree(mci); 902 kfree(mci);
902} 903}
903 904
@@ -964,7 +965,7 @@ int edac_create_sysfs_mci_device(struct mem_ctl_info *mci)
964 mci->bus.name = kasprintf(GFP_KERNEL, "mc%d", mci->mc_idx); 965 mci->bus.name = kasprintf(GFP_KERNEL, "mc%d", mci->mc_idx);
965 if (!mci->bus.name) 966 if (!mci->bus.name)
966 return -ENOMEM; 967 return -ENOMEM;
967 debugf0("creating bus %s\n",mci->bus.name); 968 edac_dbg(0, "creating bus %s\n", mci->bus.name);
968 err = bus_register(&mci->bus); 969 err = bus_register(&mci->bus);
969 if (err < 0) 970 if (err < 0)
970 return err; 971 return err;
@@ -979,7 +980,7 @@ int edac_create_sysfs_mci_device(struct mem_ctl_info *mci)
979 dev_set_drvdata(&mci->dev, mci); 980 dev_set_drvdata(&mci->dev, mci);
980 pm_runtime_forbid(&mci->dev); 981 pm_runtime_forbid(&mci->dev);
981 982
982 debugf0("creating device %s\n", dev_name(&mci->dev)); 983 edac_dbg(0, "creating device %s\n", dev_name(&mci->dev));
983 err = device_add(&mci->dev); 984 err = device_add(&mci->dev);
984 if (err < 0) { 985 if (err < 0) {
985 bus_unregister(&mci->bus); 986 bus_unregister(&mci->bus);
@@ -996,8 +997,7 @@ int edac_create_sysfs_mci_device(struct mem_ctl_info *mci)
996 if (dimm->nr_pages == 0) 997 if (dimm->nr_pages == 0)
997 continue; 998 continue;
998#ifdef CONFIG_EDAC_DEBUG 999#ifdef CONFIG_EDAC_DEBUG
999 debugf1("creating dimm%d, located at ", 1000 edac_dbg(1, "creating dimm%d, located at ", i);
1000 i);
1001 if (edac_debug_level >= 1) { 1001 if (edac_debug_level >= 1) {
1002 int lay; 1002 int lay;
1003 for (lay = 0; lay < mci->n_layers; lay++) 1003 for (lay = 0; lay < mci->n_layers; lay++)
@@ -1009,8 +1009,7 @@ int edac_create_sysfs_mci_device(struct mem_ctl_info *mci)
1009#endif 1009#endif
1010 err = edac_create_dimm_object(mci, dimm, i); 1010 err = edac_create_dimm_object(mci, dimm, i);
1011 if (err) { 1011 if (err) {
1012 debugf1("failure: create dimm %d obj\n", 1012 edac_dbg(1, "failure: create dimm %d obj\n", i);
1013 i);
1014 goto fail; 1013 goto fail;
1015 } 1014 }
1016 } 1015 }
@@ -1048,7 +1047,7 @@ void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
1048{ 1047{
1049 int i; 1048 int i;
1050 1049
1051 debugf0("\n"); 1050 edac_dbg(0, "\n");
1052 1051
1053#ifdef CONFIG_EDAC_DEBUG 1052#ifdef CONFIG_EDAC_DEBUG
1054 debugfs_remove(mci->debugfs); 1053 debugfs_remove(mci->debugfs);
@@ -1061,7 +1060,7 @@ void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
1061 struct dimm_info *dimm = mci->dimms[i]; 1060 struct dimm_info *dimm = mci->dimms[i];
1062 if (dimm->nr_pages == 0) 1061 if (dimm->nr_pages == 0)
1063 continue; 1062 continue;
1064 debugf0("removing device %s\n", dev_name(&dimm->dev)); 1063 edac_dbg(0, "removing device %s\n", dev_name(&dimm->dev));
1065 put_device(&dimm->dev); 1064 put_device(&dimm->dev);
1066 device_del(&dimm->dev); 1065 device_del(&dimm->dev);
1067 } 1066 }
@@ -1069,7 +1068,7 @@ void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
1069 1068
1070void edac_unregister_sysfs(struct mem_ctl_info *mci) 1069void edac_unregister_sysfs(struct mem_ctl_info *mci)
1071{ 1070{
1072 debugf1("Unregistering device %s\n", dev_name(&mci->dev)); 1071 edac_dbg(1, "Unregistering device %s\n", dev_name(&mci->dev));
1073 put_device(&mci->dev); 1072 put_device(&mci->dev);
1074 device_del(&mci->dev); 1073 device_del(&mci->dev);
1075 bus_unregister(&mci->bus); 1074 bus_unregister(&mci->bus);
@@ -1083,7 +1082,7 @@ static void mc_attr_release(struct device *dev)
1083 * parent device, used to create the /sys/devices/mc sysfs node. 1082 * parent device, used to create the /sys/devices/mc sysfs node.
1084 * So, there are no attributes on it. 1083 * So, there are no attributes on it.
1085 */ 1084 */
1086 debugf1("Releasing device %s\n", dev_name(dev)); 1085 edac_dbg(1, "Releasing device %s\n", dev_name(dev));
1087 kfree(dev); 1086 kfree(dev);
1088} 1087}
1089 1088
@@ -1101,7 +1100,7 @@ int __init edac_mc_sysfs_init(void)
1101 /* get the /sys/devices/system/edac subsys reference */ 1100 /* get the /sys/devices/system/edac subsys reference */
1102 edac_subsys = edac_get_sysfs_subsys(); 1101 edac_subsys = edac_get_sysfs_subsys();
1103 if (edac_subsys == NULL) { 1102 if (edac_subsys == NULL) {
1104 debugf1("no edac_subsys\n"); 1103 edac_dbg(1, "no edac_subsys\n");
1105 return -EINVAL; 1104 return -EINVAL;
1106 } 1105 }
1107 1106
@@ -1116,7 +1115,7 @@ int __init edac_mc_sysfs_init(void)
1116 if (err < 0) 1115 if (err < 0)
1117 return err; 1116 return err;
1118 1117
1119 debugf0("device %s created\n", dev_name(mci_pdev)); 1118 edac_dbg(0, "device %s created\n", dev_name(mci_pdev));
1120 1119
1121 return 0; 1120 return 0;
1122} 1121}
diff --git a/drivers/edac/edac_module.c b/drivers/edac/edac_module.c
index 9de24849290..cbba80d3423 100644
--- a/drivers/edac/edac_module.c
+++ b/drivers/edac/edac_module.c
@@ -113,7 +113,7 @@ error:
113 */ 113 */
114static void __exit edac_exit(void) 114static void __exit edac_exit(void)
115{ 115{
116 debugf0("\n"); 116 edac_dbg(0, "\n");
117 117
118 /* tear down the various subsystems */ 118 /* tear down the various subsystems */
119 edac_workqueue_teardown(); 119 edac_workqueue_teardown();
diff --git a/drivers/edac/edac_pci.c b/drivers/edac/edac_pci.c
index 51dd4e05a76..ee87ef972ea 100644
--- a/drivers/edac/edac_pci.c
+++ b/drivers/edac/edac_pci.c
@@ -45,7 +45,7 @@ struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt,
45 void *p = NULL, *pvt; 45 void *p = NULL, *pvt;
46 unsigned int size; 46 unsigned int size;
47 47
48 debugf1("\n"); 48 edac_dbg(1, "\n");
49 49
50 pci = edac_align_ptr(&p, sizeof(*pci), 1); 50 pci = edac_align_ptr(&p, sizeof(*pci), 1);
51 pvt = edac_align_ptr(&p, 1, sz_pvt); 51 pvt = edac_align_ptr(&p, 1, sz_pvt);
@@ -80,7 +80,7 @@ EXPORT_SYMBOL_GPL(edac_pci_alloc_ctl_info);
80 */ 80 */
81void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci) 81void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci)
82{ 82{
83 debugf1("\n"); 83 edac_dbg(1, "\n");
84 84
85 edac_pci_remove_sysfs(pci); 85 edac_pci_remove_sysfs(pci);
86} 86}
@@ -97,7 +97,7 @@ static struct edac_pci_ctl_info *find_edac_pci_by_dev(struct device *dev)
97 struct edac_pci_ctl_info *pci; 97 struct edac_pci_ctl_info *pci;
98 struct list_head *item; 98 struct list_head *item;
99 99
100 debugf1("\n"); 100 edac_dbg(1, "\n");
101 101
102 list_for_each(item, &edac_pci_list) { 102 list_for_each(item, &edac_pci_list) {
103 pci = list_entry(item, struct edac_pci_ctl_info, link); 103 pci = list_entry(item, struct edac_pci_ctl_info, link);
@@ -122,7 +122,7 @@ static int add_edac_pci_to_global_list(struct edac_pci_ctl_info *pci)
122 struct list_head *item, *insert_before; 122 struct list_head *item, *insert_before;
123 struct edac_pci_ctl_info *rover; 123 struct edac_pci_ctl_info *rover;
124 124
125 debugf1("\n"); 125 edac_dbg(1, "\n");
126 126
127 insert_before = &edac_pci_list; 127 insert_before = &edac_pci_list;
128 128
@@ -226,7 +226,7 @@ static void edac_pci_workq_function(struct work_struct *work_req)
226 int msec; 226 int msec;
227 unsigned long delay; 227 unsigned long delay;
228 228
229 debugf3("checking\n"); 229 edac_dbg(3, "checking\n");
230 230
231 mutex_lock(&edac_pci_ctls_mutex); 231 mutex_lock(&edac_pci_ctls_mutex);
232 232
@@ -261,7 +261,7 @@ static void edac_pci_workq_function(struct work_struct *work_req)
261static void edac_pci_workq_setup(struct edac_pci_ctl_info *pci, 261static void edac_pci_workq_setup(struct edac_pci_ctl_info *pci,
262 unsigned int msec) 262 unsigned int msec)
263{ 263{
264 debugf0("\n"); 264 edac_dbg(0, "\n");
265 265
266 INIT_DELAYED_WORK(&pci->work, edac_pci_workq_function); 266 INIT_DELAYED_WORK(&pci->work, edac_pci_workq_function);
267 queue_delayed_work(edac_workqueue, &pci->work, 267 queue_delayed_work(edac_workqueue, &pci->work,
@@ -276,7 +276,7 @@ static void edac_pci_workq_teardown(struct edac_pci_ctl_info *pci)
276{ 276{
277 int status; 277 int status;
278 278
279 debugf0("\n"); 279 edac_dbg(0, "\n");
280 280
281 status = cancel_delayed_work(&pci->work); 281 status = cancel_delayed_work(&pci->work);
282 if (status == 0) 282 if (status == 0)
@@ -293,7 +293,7 @@ static void edac_pci_workq_teardown(struct edac_pci_ctl_info *pci)
293void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci, 293void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci,
294 unsigned long value) 294 unsigned long value)
295{ 295{
296 debugf0("\n"); 296 edac_dbg(0, "\n");
297 297
298 edac_pci_workq_teardown(pci); 298 edac_pci_workq_teardown(pci);
299 299
@@ -333,7 +333,7 @@ EXPORT_SYMBOL_GPL(edac_pci_alloc_index);
333 */ 333 */
334int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx) 334int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx)
335{ 335{
336 debugf0("\n"); 336 edac_dbg(0, "\n");
337 337
338 pci->pci_idx = edac_idx; 338 pci->pci_idx = edac_idx;
339 pci->start_time = jiffies; 339 pci->start_time = jiffies;
@@ -393,7 +393,7 @@ struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev)
393{ 393{
394 struct edac_pci_ctl_info *pci; 394 struct edac_pci_ctl_info *pci;
395 395
396 debugf0("\n"); 396 edac_dbg(0, "\n");
397 397
398 mutex_lock(&edac_pci_ctls_mutex); 398 mutex_lock(&edac_pci_ctls_mutex);
399 399
@@ -430,7 +430,7 @@ EXPORT_SYMBOL_GPL(edac_pci_del_device);
430 */ 430 */
431static void edac_pci_generic_check(struct edac_pci_ctl_info *pci) 431static void edac_pci_generic_check(struct edac_pci_ctl_info *pci)
432{ 432{
433 debugf4("\n"); 433 edac_dbg(4, "\n");
434 edac_pci_do_parity_check(); 434 edac_pci_do_parity_check();
435} 435}
436 436
@@ -475,7 +475,7 @@ struct edac_pci_ctl_info *edac_pci_create_generic_ctl(struct device *dev,
475 pdata->edac_idx = edac_pci_idx++; 475 pdata->edac_idx = edac_pci_idx++;
476 476
477 if (edac_pci_add_device(pci, pdata->edac_idx) > 0) { 477 if (edac_pci_add_device(pci, pdata->edac_idx) > 0) {
478 debugf3("failed edac_pci_add_device()\n"); 478 edac_dbg(3, "failed edac_pci_add_device()\n");
479 edac_pci_free_ctl_info(pci); 479 edac_pci_free_ctl_info(pci);
480 return NULL; 480 return NULL;
481 } 481 }
@@ -491,7 +491,7 @@ EXPORT_SYMBOL_GPL(edac_pci_create_generic_ctl);
491 */ 491 */
492void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci) 492void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci)
493{ 493{
494 debugf0("pci mod=%s\n", pci->mod_name); 494 edac_dbg(0, "pci mod=%s\n", pci->mod_name);
495 495
496 edac_pci_del_device(pci->dev); 496 edac_pci_del_device(pci->dev);
497 edac_pci_free_ctl_info(pci); 497 edac_pci_free_ctl_info(pci);
diff --git a/drivers/edac/edac_pci_sysfs.c b/drivers/edac/edac_pci_sysfs.c
index 6678216a7cb..e164c555a33 100644
--- a/drivers/edac/edac_pci_sysfs.c
+++ b/drivers/edac/edac_pci_sysfs.c
@@ -78,7 +78,7 @@ static void edac_pci_instance_release(struct kobject *kobj)
78{ 78{
79 struct edac_pci_ctl_info *pci; 79 struct edac_pci_ctl_info *pci;
80 80
81 debugf0("\n"); 81 edac_dbg(0, "\n");
82 82
83 /* Form pointer to containing struct, the pci control struct */ 83 /* Form pointer to containing struct, the pci control struct */
84 pci = to_instance(kobj); 84 pci = to_instance(kobj);
@@ -161,7 +161,7 @@ static int edac_pci_create_instance_kobj(struct edac_pci_ctl_info *pci, int idx)
161 struct kobject *main_kobj; 161 struct kobject *main_kobj;
162 int err; 162 int err;
163 163
164 debugf0("\n"); 164 edac_dbg(0, "\n");
165 165
166 /* First bump the ref count on the top main kobj, which will 166 /* First bump the ref count on the top main kobj, which will
167 * track the number of PCI instances we have, and thus nest 167 * track the number of PCI instances we have, and thus nest
@@ -177,14 +177,13 @@ static int edac_pci_create_instance_kobj(struct edac_pci_ctl_info *pci, int idx)
177 err = kobject_init_and_add(&pci->kobj, &ktype_pci_instance, 177 err = kobject_init_and_add(&pci->kobj, &ktype_pci_instance,
178 edac_pci_top_main_kobj, "pci%d", idx); 178 edac_pci_top_main_kobj, "pci%d", idx);
179 if (err != 0) { 179 if (err != 0) {
180 debugf2("failed to register instance pci%d\n", 180 edac_dbg(2, "failed to register instance pci%d\n", idx);
181 idx);
182 kobject_put(edac_pci_top_main_kobj); 181 kobject_put(edac_pci_top_main_kobj);
183 goto error_out; 182 goto error_out;
184 } 183 }
185 184
186 kobject_uevent(&pci->kobj, KOBJ_ADD); 185 kobject_uevent(&pci->kobj, KOBJ_ADD);
187 debugf1("Register instance 'pci%d' kobject\n", idx); 186 edac_dbg(1, "Register instance 'pci%d' kobject\n", idx);
188 187
189 return 0; 188 return 0;
190 189
@@ -201,7 +200,7 @@ error_out:
201static void edac_pci_unregister_sysfs_instance_kobj( 200static void edac_pci_unregister_sysfs_instance_kobj(
202 struct edac_pci_ctl_info *pci) 201 struct edac_pci_ctl_info *pci)
203{ 202{
204 debugf0("\n"); 203 edac_dbg(0, "\n");
205 204
206 /* Unregister the instance kobject and allow its release 205 /* Unregister the instance kobject and allow its release
207 * function release the main reference count and then 206 * function release the main reference count and then
@@ -317,7 +316,7 @@ static struct edac_pci_dev_attribute *edac_pci_attr[] = {
317 */ 316 */
318static void edac_pci_release_main_kobj(struct kobject *kobj) 317static void edac_pci_release_main_kobj(struct kobject *kobj)
319{ 318{
320 debugf0("here to module_put(THIS_MODULE)\n"); 319 edac_dbg(0, "here to module_put(THIS_MODULE)\n");
321 320
322 kfree(kobj); 321 kfree(kobj);
323 322
@@ -345,7 +344,7 @@ static int edac_pci_main_kobj_setup(void)
345 int err; 344 int err;
346 struct bus_type *edac_subsys; 345 struct bus_type *edac_subsys;
347 346
348 debugf0("\n"); 347 edac_dbg(0, "\n");
349 348
350 /* check and count if we have already created the main kobject */ 349 /* check and count if we have already created the main kobject */
351 if (atomic_inc_return(&edac_pci_sysfs_refcount) != 1) 350 if (atomic_inc_return(&edac_pci_sysfs_refcount) != 1)
@@ -356,7 +355,7 @@ static int edac_pci_main_kobj_setup(void)
356 */ 355 */
357 edac_subsys = edac_get_sysfs_subsys(); 356 edac_subsys = edac_get_sysfs_subsys();
358 if (edac_subsys == NULL) { 357 if (edac_subsys == NULL) {
359 debugf1("no edac_subsys\n"); 358 edac_dbg(1, "no edac_subsys\n");
360 err = -ENODEV; 359 err = -ENODEV;
361 goto decrement_count_fail; 360 goto decrement_count_fail;
362 } 361 }
@@ -366,14 +365,14 @@ static int edac_pci_main_kobj_setup(void)
366 * level main kobj for EDAC PCI 365 * level main kobj for EDAC PCI
367 */ 366 */
368 if (!try_module_get(THIS_MODULE)) { 367 if (!try_module_get(THIS_MODULE)) {
369 debugf1("try_module_get() failed\n"); 368 edac_dbg(1, "try_module_get() failed\n");
370 err = -ENODEV; 369 err = -ENODEV;
371 goto mod_get_fail; 370 goto mod_get_fail;
372 } 371 }
373 372
374 edac_pci_top_main_kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL); 373 edac_pci_top_main_kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL);
375 if (!edac_pci_top_main_kobj) { 374 if (!edac_pci_top_main_kobj) {
376 debugf1("Failed to allocate\n"); 375 edac_dbg(1, "Failed to allocate\n");
377 err = -ENOMEM; 376 err = -ENOMEM;
378 goto kzalloc_fail; 377 goto kzalloc_fail;
379 } 378 }
@@ -383,7 +382,7 @@ static int edac_pci_main_kobj_setup(void)
383 &ktype_edac_pci_main_kobj, 382 &ktype_edac_pci_main_kobj,
384 &edac_subsys->dev_root->kobj, "pci"); 383 &edac_subsys->dev_root->kobj, "pci");
385 if (err) { 384 if (err) {
386 debugf1("Failed to register '.../edac/pci'\n"); 385 edac_dbg(1, "Failed to register '.../edac/pci'\n");
387 goto kobject_init_and_add_fail; 386 goto kobject_init_and_add_fail;
388 } 387 }
389 388
@@ -392,7 +391,7 @@ static int edac_pci_main_kobj_setup(void)
392 * must be used, for resources to be cleaned up properly 391 * must be used, for resources to be cleaned up properly
393 */ 392 */
394 kobject_uevent(edac_pci_top_main_kobj, KOBJ_ADD); 393 kobject_uevent(edac_pci_top_main_kobj, KOBJ_ADD);
395 debugf1("Registered '.../edac/pci' kobject\n"); 394 edac_dbg(1, "Registered '.../edac/pci' kobject\n");
396 395
397 return 0; 396 return 0;
398 397
@@ -421,14 +420,14 @@ decrement_count_fail:
421 */ 420 */
422static void edac_pci_main_kobj_teardown(void) 421static void edac_pci_main_kobj_teardown(void)
423{ 422{
424 debugf0("\n"); 423 edac_dbg(0, "\n");
425 424
426 /* Decrement the count and only if no more controller instances 425 /* Decrement the count and only if no more controller instances
427 * are connected perform the unregisteration of the top level 426 * are connected perform the unregisteration of the top level
428 * main kobj 427 * main kobj
429 */ 428 */
430 if (atomic_dec_return(&edac_pci_sysfs_refcount) == 0) { 429 if (atomic_dec_return(&edac_pci_sysfs_refcount) == 0) {
431 debugf0("called kobject_put on main kobj\n"); 430 edac_dbg(0, "called kobject_put on main kobj\n");
432 kobject_put(edac_pci_top_main_kobj); 431 kobject_put(edac_pci_top_main_kobj);
433 } 432 }
434 edac_put_sysfs_subsys(); 433 edac_put_sysfs_subsys();
@@ -445,7 +444,7 @@ int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci)
445 int err; 444 int err;
446 struct kobject *edac_kobj = &pci->kobj; 445 struct kobject *edac_kobj = &pci->kobj;
447 446
448 debugf0("idx=%d\n", pci->pci_idx); 447 edac_dbg(0, "idx=%d\n", pci->pci_idx);
449 448
450 /* create the top main EDAC PCI kobject, IF needed */ 449 /* create the top main EDAC PCI kobject, IF needed */
451 err = edac_pci_main_kobj_setup(); 450 err = edac_pci_main_kobj_setup();
@@ -459,8 +458,7 @@ int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci)
459 458
460 err = sysfs_create_link(edac_kobj, &pci->dev->kobj, EDAC_PCI_SYMLINK); 459 err = sysfs_create_link(edac_kobj, &pci->dev->kobj, EDAC_PCI_SYMLINK);
461 if (err) { 460 if (err) {
462 debugf0("sysfs_create_link() returned err= %d\n", 461 edac_dbg(0, "sysfs_create_link() returned err= %d\n", err);
463 err);
464 goto symlink_fail; 462 goto symlink_fail;
465 } 463 }
466 464
@@ -483,7 +481,7 @@ unregister_cleanup:
483 */ 481 */
484void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci) 482void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci)
485{ 483{
486 debugf0("index=%d\n", pci->pci_idx); 484 edac_dbg(0, "index=%d\n", pci->pci_idx);
487 485
488 /* Remove the symlink */ 486 /* Remove the symlink */
489 sysfs_remove_link(&pci->kobj, EDAC_PCI_SYMLINK); 487 sysfs_remove_link(&pci->kobj, EDAC_PCI_SYMLINK);
@@ -495,7 +493,7 @@ void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci)
495 * if this 'pci' is the last instance. 493 * if this 'pci' is the last instance.
496 * If it is, the main kobject will be unregistered as a result 494 * If it is, the main kobject will be unregistered as a result
497 */ 495 */
498 debugf0("calling edac_pci_main_kobj_teardown()\n"); 496 edac_dbg(0, "calling edac_pci_main_kobj_teardown()\n");
499 edac_pci_main_kobj_teardown(); 497 edac_pci_main_kobj_teardown();
500} 498}
501 499
@@ -571,7 +569,7 @@ static void edac_pci_dev_parity_test(struct pci_dev *dev)
571 569
572 local_irq_restore(flags); 570 local_irq_restore(flags);
573 571
574 debugf4("PCI STATUS= 0x%04x %s\n", status, dev_name(&dev->dev)); 572 edac_dbg(4, "PCI STATUS= 0x%04x %s\n", status, dev_name(&dev->dev));
575 573
576 /* check the status reg for errors on boards NOT marked as broken 574 /* check the status reg for errors on boards NOT marked as broken
577 * if broken, we cannot trust any of the status bits 575 * if broken, we cannot trust any of the status bits
@@ -602,13 +600,15 @@ static void edac_pci_dev_parity_test(struct pci_dev *dev)
602 } 600 }
603 601
604 602
605 debugf4("PCI HEADER TYPE= 0x%02x %s\n", header_type, dev_name(&dev->dev)); 603 edac_dbg(4, "PCI HEADER TYPE= 0x%02x %s\n",
604 header_type, dev_name(&dev->dev));
606 605
607 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { 606 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
608 /* On bridges, need to examine secondary status register */ 607 /* On bridges, need to examine secondary status register */
609 status = get_pci_parity_status(dev, 1); 608 status = get_pci_parity_status(dev, 1);
610 609
611 debugf4("PCI SEC_STATUS= 0x%04x %s\n", status, dev_name(&dev->dev)); 610 edac_dbg(4, "PCI SEC_STATUS= 0x%04x %s\n",
611 status, dev_name(&dev->dev));
612 612
613 /* check the secondary status reg for errors, 613 /* check the secondary status reg for errors,
614 * on NOT broken boards 614 * on NOT broken boards
@@ -670,7 +670,7 @@ void edac_pci_do_parity_check(void)
670{ 670{
671 int before_count; 671 int before_count;
672 672
673 debugf3("\n"); 673 edac_dbg(3, "\n");
674 674
675 /* if policy has PCI check off, leave now */ 675 /* if policy has PCI check off, leave now */
676 if (!check_pci_errors) 676 if (!check_pci_errors)
diff --git a/drivers/edac/i3000_edac.c b/drivers/edac/i3000_edac.c
index 67975ba252f..399aec351aa 100644
--- a/drivers/edac/i3000_edac.c
+++ b/drivers/edac/i3000_edac.c
@@ -275,7 +275,7 @@ static void i3000_check(struct mem_ctl_info *mci)
275{ 275{
276 struct i3000_error_info info; 276 struct i3000_error_info info;
277 277
278 debugf1("MC%d\n", mci->mc_idx); 278 edac_dbg(1, "MC%d\n", mci->mc_idx);
279 i3000_get_error_info(mci, &info); 279 i3000_get_error_info(mci, &info);
280 i3000_process_error_info(mci, &info, 1); 280 i3000_process_error_info(mci, &info, 1);
281} 281}
@@ -322,7 +322,7 @@ static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
322 unsigned long mchbar; 322 unsigned long mchbar;
323 void __iomem *window; 323 void __iomem *window;
324 324
325 debugf0("MC:\n"); 325 edac_dbg(0, "MC:\n");
326 326
327 pci_read_config_dword(pdev, I3000_MCHBAR, (u32 *) & mchbar); 327 pci_read_config_dword(pdev, I3000_MCHBAR, (u32 *) & mchbar);
328 mchbar &= I3000_MCHBAR_MASK; 328 mchbar &= I3000_MCHBAR_MASK;
@@ -366,7 +366,7 @@ static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
366 if (!mci) 366 if (!mci)
367 return -ENOMEM; 367 return -ENOMEM;
368 368
369 debugf3("MC: init mci\n"); 369 edac_dbg(3, "MC: init mci\n");
370 370
371 mci->pdev = &pdev->dev; 371 mci->pdev = &pdev->dev;
372 mci->mtype_cap = MEM_FLAG_DDR2; 372 mci->mtype_cap = MEM_FLAG_DDR2;
@@ -399,8 +399,7 @@ static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
399 cumul_size = value << (I3000_DRB_SHIFT - PAGE_SHIFT); 399 cumul_size = value << (I3000_DRB_SHIFT - PAGE_SHIFT);
400 if (interleaved) 400 if (interleaved)
401 cumul_size <<= 1; 401 cumul_size <<= 1;
402 debugf3("MC: (%d) cumul_size 0x%x\n", 402 edac_dbg(3, "MC: (%d) cumul_size 0x%x\n", i, cumul_size);
403 i, cumul_size);
404 if (cumul_size == last_cumul_size) 403 if (cumul_size == last_cumul_size)
405 continue; 404 continue;
406 405
@@ -429,7 +428,7 @@ static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
429 428
430 rc = -ENODEV; 429 rc = -ENODEV;
431 if (edac_mc_add_mc(mci)) { 430 if (edac_mc_add_mc(mci)) {
432 debugf3("MC: failed edac_mc_add_mc()\n"); 431 edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
433 goto fail; 432 goto fail;
434 } 433 }
435 434
@@ -445,7 +444,7 @@ static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
445 } 444 }
446 445
447 /* get this far and it's successful */ 446 /* get this far and it's successful */
448 debugf3("MC: success\n"); 447 edac_dbg(3, "MC: success\n");
449 return 0; 448 return 0;
450 449
451fail: 450fail:
@@ -461,7 +460,7 @@ static int __devinit i3000_init_one(struct pci_dev *pdev,
461{ 460{
462 int rc; 461 int rc;
463 462
464 debugf0("MC:\n"); 463 edac_dbg(0, "MC:\n");
465 464
466 if (pci_enable_device(pdev) < 0) 465 if (pci_enable_device(pdev) < 0)
467 return -EIO; 466 return -EIO;
@@ -477,7 +476,7 @@ static void __devexit i3000_remove_one(struct pci_dev *pdev)
477{ 476{
478 struct mem_ctl_info *mci; 477 struct mem_ctl_info *mci;
479 478
480 debugf0("\n"); 479 edac_dbg(0, "\n");
481 480
482 if (i3000_pci) 481 if (i3000_pci)
483 edac_pci_release_generic_ctl(i3000_pci); 482 edac_pci_release_generic_ctl(i3000_pci);
@@ -511,7 +510,7 @@ static int __init i3000_init(void)
511{ 510{
512 int pci_rc; 511 int pci_rc;
513 512
514 debugf3("MC:\n"); 513 edac_dbg(3, "MC:\n");
515 514
516 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 515 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
517 opstate_init(); 516 opstate_init();
@@ -525,14 +524,14 @@ static int __init i3000_init(void)
525 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 524 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
526 PCI_DEVICE_ID_INTEL_3000_HB, NULL); 525 PCI_DEVICE_ID_INTEL_3000_HB, NULL);
527 if (!mci_pdev) { 526 if (!mci_pdev) {
528 debugf0("i3000 pci_get_device fail\n"); 527 edac_dbg(0, "i3000 pci_get_device fail\n");
529 pci_rc = -ENODEV; 528 pci_rc = -ENODEV;
530 goto fail1; 529 goto fail1;
531 } 530 }
532 531
533 pci_rc = i3000_init_one(mci_pdev, i3000_pci_tbl); 532 pci_rc = i3000_init_one(mci_pdev, i3000_pci_tbl);
534 if (pci_rc < 0) { 533 if (pci_rc < 0) {
535 debugf0("i3000 init fail\n"); 534 edac_dbg(0, "i3000 init fail\n");
536 pci_rc = -ENODEV; 535 pci_rc = -ENODEV;
537 goto fail1; 536 goto fail1;
538 } 537 }
@@ -552,7 +551,7 @@ fail0:
552 551
553static void __exit i3000_exit(void) 552static void __exit i3000_exit(void)
554{ 553{
555 debugf3("MC:\n"); 554 edac_dbg(3, "MC:\n");
556 555
557 pci_unregister_driver(&i3000_driver); 556 pci_unregister_driver(&i3000_driver);
558 if (!i3000_registered) { 557 if (!i3000_registered) {
diff --git a/drivers/edac/i3200_edac.c b/drivers/edac/i3200_edac.c
index 9698ca39e38..dfd843a0481 100644
--- a/drivers/edac/i3200_edac.c
+++ b/drivers/edac/i3200_edac.c
@@ -110,10 +110,10 @@ static int how_many_channels(struct pci_dev *pdev)
110 110
111 pci_read_config_byte(pdev, I3200_CAPID0 + 8, &capid0_8b); 111 pci_read_config_byte(pdev, I3200_CAPID0 + 8, &capid0_8b);
112 if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */ 112 if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */
113 debugf0("In single channel mode.\n"); 113 edac_dbg(0, "In single channel mode\n");
114 return 1; 114 return 1;
115 } else { 115 } else {
116 debugf0("In dual channel mode.\n"); 116 edac_dbg(0, "In dual channel mode\n");
117 return 2; 117 return 2;
118 } 118 }
119} 119}
@@ -245,7 +245,7 @@ static void i3200_check(struct mem_ctl_info *mci)
245{ 245{
246 struct i3200_error_info info; 246 struct i3200_error_info info;
247 247
248 debugf1("MC%d\n", mci->mc_idx); 248 edac_dbg(1, "MC%d\n", mci->mc_idx);
249 i3200_get_and_clear_error_info(mci, &info); 249 i3200_get_and_clear_error_info(mci, &info);
250 i3200_process_error_info(mci, &info); 250 i3200_process_error_info(mci, &info);
251} 251}
@@ -332,7 +332,7 @@ static int i3200_probe1(struct pci_dev *pdev, int dev_idx)
332 void __iomem *window; 332 void __iomem *window;
333 struct i3200_priv *priv; 333 struct i3200_priv *priv;
334 334
335 debugf0("MC:\n"); 335 edac_dbg(0, "MC:\n");
336 336
337 window = i3200_map_mchbar(pdev); 337 window = i3200_map_mchbar(pdev);
338 if (!window) 338 if (!window)
@@ -352,7 +352,7 @@ static int i3200_probe1(struct pci_dev *pdev, int dev_idx)
352 if (!mci) 352 if (!mci)
353 return -ENOMEM; 353 return -ENOMEM;
354 354
355 debugf3("MC: init mci\n"); 355 edac_dbg(3, "MC: init mci\n");
356 356
357 mci->pdev = &pdev->dev; 357 mci->pdev = &pdev->dev;
358 mci->mtype_cap = MEM_FLAG_DDR2; 358 mci->mtype_cap = MEM_FLAG_DDR2;
@@ -403,12 +403,12 @@ static int i3200_probe1(struct pci_dev *pdev, int dev_idx)
403 403
404 rc = -ENODEV; 404 rc = -ENODEV;
405 if (edac_mc_add_mc(mci)) { 405 if (edac_mc_add_mc(mci)) {
406 debugf3("MC: failed edac_mc_add_mc()\n"); 406 edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
407 goto fail; 407 goto fail;
408 } 408 }
409 409
410 /* get this far and it's successful */ 410 /* get this far and it's successful */
411 debugf3("MC: success\n"); 411 edac_dbg(3, "MC: success\n");
412 return 0; 412 return 0;
413 413
414fail: 414fail:
@@ -424,7 +424,7 @@ static int __devinit i3200_init_one(struct pci_dev *pdev,
424{ 424{
425 int rc; 425 int rc;
426 426
427 debugf0("MC:\n"); 427 edac_dbg(0, "MC:\n");
428 428
429 if (pci_enable_device(pdev) < 0) 429 if (pci_enable_device(pdev) < 0)
430 return -EIO; 430 return -EIO;
@@ -441,7 +441,7 @@ static void __devexit i3200_remove_one(struct pci_dev *pdev)
441 struct mem_ctl_info *mci; 441 struct mem_ctl_info *mci;
442 struct i3200_priv *priv; 442 struct i3200_priv *priv;
443 443
444 debugf0("\n"); 444 edac_dbg(0, "\n");
445 445
446 mci = edac_mc_del_mc(&pdev->dev); 446 mci = edac_mc_del_mc(&pdev->dev);
447 if (!mci) 447 if (!mci)
@@ -475,7 +475,7 @@ static int __init i3200_init(void)
475{ 475{
476 int pci_rc; 476 int pci_rc;
477 477
478 debugf3("MC:\n"); 478 edac_dbg(3, "MC:\n");
479 479
480 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 480 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
481 opstate_init(); 481 opstate_init();
@@ -489,14 +489,14 @@ static int __init i3200_init(void)
489 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 489 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
490 PCI_DEVICE_ID_INTEL_3200_HB, NULL); 490 PCI_DEVICE_ID_INTEL_3200_HB, NULL);
491 if (!mci_pdev) { 491 if (!mci_pdev) {
492 debugf0("i3200 pci_get_device fail\n"); 492 edac_dbg(0, "i3200 pci_get_device fail\n");
493 pci_rc = -ENODEV; 493 pci_rc = -ENODEV;
494 goto fail1; 494 goto fail1;
495 } 495 }
496 496
497 pci_rc = i3200_init_one(mci_pdev, i3200_pci_tbl); 497 pci_rc = i3200_init_one(mci_pdev, i3200_pci_tbl);
498 if (pci_rc < 0) { 498 if (pci_rc < 0) {
499 debugf0("i3200 init fail\n"); 499 edac_dbg(0, "i3200 init fail\n");
500 pci_rc = -ENODEV; 500 pci_rc = -ENODEV;
501 goto fail1; 501 goto fail1;
502 } 502 }
@@ -516,7 +516,7 @@ fail0:
516 516
517static void __exit i3200_exit(void) 517static void __exit i3200_exit(void)
518{ 518{
519 debugf3("MC:\n"); 519 edac_dbg(3, "MC:\n");
520 520
521 pci_unregister_driver(&i3200_driver); 521 pci_unregister_driver(&i3200_driver);
522 if (!i3200_registered) { 522 if (!i3200_registered) {
diff --git a/drivers/edac/i5000_edac.c b/drivers/edac/i5000_edac.c
index 0e16db620ad..96431a547e4 100644
--- a/drivers/edac/i5000_edac.c
+++ b/drivers/edac/i5000_edac.c
@@ -478,10 +478,9 @@ static void i5000_process_fatal_error_info(struct mem_ctl_info *mci,
478 ras = NREC_RAS(info->nrecmemb); 478 ras = NREC_RAS(info->nrecmemb);
479 cas = NREC_CAS(info->nrecmemb); 479 cas = NREC_CAS(info->nrecmemb);
480 480
481 debugf0("\t\tCSROW= %d Channel= %d " 481 edac_dbg(0, "\t\tCSROW= %d Channel= %d (DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
482 "(DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n", 482 rank, channel, bank,
483 rank, channel, bank, 483 rdwr ? "Write" : "Read", ras, cas);
484 rdwr ? "Write" : "Read", ras, cas);
485 484
486 /* Only 1 bit will be on */ 485 /* Only 1 bit will be on */
487 switch (allErrors) { 486 switch (allErrors) {
@@ -558,7 +557,7 @@ static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
558 /* ONLY ONE of the possible error bits will be set, as per the docs */ 557 /* ONLY ONE of the possible error bits will be set, as per the docs */
559 ue_errors = allErrors & FERR_NF_UNCORRECTABLE; 558 ue_errors = allErrors & FERR_NF_UNCORRECTABLE;
560 if (ue_errors) { 559 if (ue_errors) {
561 debugf0("\tUncorrected bits= 0x%x\n", ue_errors); 560 edac_dbg(0, "\tUncorrected bits= 0x%x\n", ue_errors);
562 561
563 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd); 562 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
564 563
@@ -574,11 +573,9 @@ static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
574 ras = NREC_RAS(info->nrecmemb); 573 ras = NREC_RAS(info->nrecmemb);
575 cas = NREC_CAS(info->nrecmemb); 574 cas = NREC_CAS(info->nrecmemb);
576 575
577 debugf0 576 edac_dbg(0, "\t\tCSROW= %d Channels= %d,%d (Branch= %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
578 ("\t\tCSROW= %d Channels= %d,%d (Branch= %d " 577 rank, channel, channel + 1, branch >> 1, bank,
579 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n", 578 rdwr ? "Write" : "Read", ras, cas);
580 rank, channel, channel + 1, branch >> 1, bank,
581 rdwr ? "Write" : "Read", ras, cas);
582 579
583 switch (ue_errors) { 580 switch (ue_errors) {
584 case FERR_NF_M12ERR: 581 case FERR_NF_M12ERR:
@@ -630,7 +627,7 @@ static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
630 /* Check correctable errors */ 627 /* Check correctable errors */
631 ce_errors = allErrors & FERR_NF_CORRECTABLE; 628 ce_errors = allErrors & FERR_NF_CORRECTABLE;
632 if (ce_errors) { 629 if (ce_errors) {
633 debugf0("\tCorrected bits= 0x%x\n", ce_errors); 630 edac_dbg(0, "\tCorrected bits= 0x%x\n", ce_errors);
634 631
635 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd); 632 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
636 633
@@ -648,10 +645,9 @@ static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
648 ras = REC_RAS(info->recmemb); 645 ras = REC_RAS(info->recmemb);
649 cas = REC_CAS(info->recmemb); 646 cas = REC_CAS(info->recmemb);
650 647
651 debugf0("\t\tCSROW= %d Channel= %d (Branch %d " 648 edac_dbg(0, "\t\tCSROW= %d Channel= %d (Branch %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
652 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n", 649 rank, channel, branch >> 1, bank,
653 rank, channel, branch >> 1, bank, 650 rdwr ? "Write" : "Read", ras, cas);
654 rdwr ? "Write" : "Read", ras, cas);
655 651
656 switch (ce_errors) { 652 switch (ce_errors) {
657 case FERR_NF_M17ERR: 653 case FERR_NF_M17ERR:
@@ -763,7 +759,7 @@ static void i5000_clear_error(struct mem_ctl_info *mci)
763static void i5000_check_error(struct mem_ctl_info *mci) 759static void i5000_check_error(struct mem_ctl_info *mci)
764{ 760{
765 struct i5000_error_info info; 761 struct i5000_error_info info;
766 debugf4("MC%d\n", mci->mc_idx); 762 edac_dbg(4, "MC%d\n", mci->mc_idx);
767 i5000_get_error_info(mci, &info); 763 i5000_get_error_info(mci, &info);
768 i5000_process_error_info(mci, &info, 1); 764 i5000_process_error_info(mci, &info, 1);
769} 765}
@@ -834,15 +830,16 @@ static int i5000_get_devices(struct mem_ctl_info *mci, int dev_idx)
834 830
835 pvt->fsb_error_regs = pdev; 831 pvt->fsb_error_regs = pdev;
836 832
837 debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x\n", 833 edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s %x:%x\n",
838 pci_name(pvt->system_address), 834 pci_name(pvt->system_address),
839 pvt->system_address->vendor, pvt->system_address->device); 835 pvt->system_address->vendor, pvt->system_address->device);
840 debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x\n", 836 edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
841 pci_name(pvt->branchmap_werrors), 837 pci_name(pvt->branchmap_werrors),
842 pvt->branchmap_werrors->vendor, pvt->branchmap_werrors->device); 838 pvt->branchmap_werrors->vendor,
843 debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x\n", 839 pvt->branchmap_werrors->device);
844 pci_name(pvt->fsb_error_regs), 840 edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s %x:%x\n",
845 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device); 841 pci_name(pvt->fsb_error_regs),
842 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
846 843
847 pdev = NULL; 844 pdev = NULL;
848 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 845 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
@@ -965,24 +962,25 @@ static void decode_mtr(int slot_row, u16 mtr)
965 962
966 ans = MTR_DIMMS_PRESENT(mtr); 963 ans = MTR_DIMMS_PRESENT(mtr);
967 964
968 debugf2("\tMTR%d=0x%x: DIMMs are %s\n", slot_row, mtr, 965 edac_dbg(2, "\tMTR%d=0x%x: DIMMs are %sPresent\n",
969 ans ? "Present" : "NOT Present"); 966 slot_row, mtr, ans ? "" : "NOT ");
970 if (!ans) 967 if (!ans)
971 return; 968 return;
972 969
973 debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr)); 970 edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
974 debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr)); 971 edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
975 debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANK(mtr) ? "double" : "single"); 972 edac_dbg(2, "\t\tNUMRANK: %s\n",
976 debugf2("\t\tNUMROW: %s\n", 973 MTR_DIMM_RANK(mtr) ? "double" : "single");
977 MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" : 974 edac_dbg(2, "\t\tNUMROW: %s\n",
978 MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" : 975 MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" :
979 MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" : 976 MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" :
980 "reserved"); 977 MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" :
981 debugf2("\t\tNUMCOL: %s\n", 978 "reserved");
982 MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" : 979 edac_dbg(2, "\t\tNUMCOL: %s\n",
983 MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" : 980 MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" :
984 MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" : 981 MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" :
985 "reserved"); 982 MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" :
983 "reserved");
986} 984}
987 985
988static void handle_channel(struct i5000_pvt *pvt, int slot, int channel, 986static void handle_channel(struct i5000_pvt *pvt, int slot, int channel,
@@ -1053,7 +1051,7 @@ static void calculate_dimm_size(struct i5000_pvt *pvt)
1053 "--------------------------------"); 1051 "--------------------------------");
1054 p += n; 1052 p += n;
1055 space -= n; 1053 space -= n;
1056 debugf2("%s\n", mem_buffer); 1054 edac_dbg(2, "%s\n", mem_buffer);
1057 p = mem_buffer; 1055 p = mem_buffer;
1058 space = PAGE_SIZE; 1056 space = PAGE_SIZE;
1059 } 1057 }
@@ -1074,7 +1072,7 @@ static void calculate_dimm_size(struct i5000_pvt *pvt)
1074 } 1072 }
1075 p += n; 1073 p += n;
1076 space -= n; 1074 space -= n;
1077 debugf2("%s\n", mem_buffer); 1075 edac_dbg(2, "%s\n", mem_buffer);
1078 p = mem_buffer; 1076 p = mem_buffer;
1079 space = PAGE_SIZE; 1077 space = PAGE_SIZE;
1080 } 1078 }
@@ -1084,7 +1082,7 @@ static void calculate_dimm_size(struct i5000_pvt *pvt)
1084 "--------------------------------"); 1082 "--------------------------------");
1085 p += n; 1083 p += n;
1086 space -= n; 1084 space -= n;
1087 debugf2("%s\n", mem_buffer); 1085 edac_dbg(2, "%s\n", mem_buffer);
1088 p = mem_buffer; 1086 p = mem_buffer;
1089 space = PAGE_SIZE; 1087 space = PAGE_SIZE;
1090 1088
@@ -1097,7 +1095,7 @@ static void calculate_dimm_size(struct i5000_pvt *pvt)
1097 p += n; 1095 p += n;
1098 space -= n; 1096 space -= n;
1099 } 1097 }
1100 debugf2("%s\n", mem_buffer); 1098 edac_dbg(2, "%s\n", mem_buffer);
1101 p = mem_buffer; 1099 p = mem_buffer;
1102 space = PAGE_SIZE; 1100 space = PAGE_SIZE;
1103 1101
@@ -1110,7 +1108,7 @@ static void calculate_dimm_size(struct i5000_pvt *pvt)
1110 } 1108 }
1111 1109
1112 /* output the last message and free buffer */ 1110 /* output the last message and free buffer */
1113 debugf2("%s\n", mem_buffer); 1111 edac_dbg(2, "%s\n", mem_buffer);
1114 kfree(mem_buffer); 1112 kfree(mem_buffer);
1115} 1113}
1116 1114
@@ -1140,17 +1138,18 @@ static void i5000_get_mc_regs(struct mem_ctl_info *mci)
1140 maxdimmperch = pvt->maxdimmperch; 1138 maxdimmperch = pvt->maxdimmperch;
1141 maxch = pvt->maxch; 1139 maxch = pvt->maxch;
1142 1140
1143 debugf2("AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n", 1141 edac_dbg(2, "AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n",
1144 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch); 1142 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
1145 1143
1146 /* Get the Branch Map regs */ 1144 /* Get the Branch Map regs */
1147 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm); 1145 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
1148 pvt->tolm >>= 12; 1146 pvt->tolm >>= 12;
1149 debugf2("\nTOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm, 1147 edac_dbg(2, "TOLM (number of 256M regions) =%u (0x%x)\n",
1150 pvt->tolm); 1148 pvt->tolm, pvt->tolm);
1151 1149
1152 actual_tolm = pvt->tolm << 28; 1150 actual_tolm = pvt->tolm << 28;
1153 debugf2("Actual TOLM byte addr=%u (0x%x)\n", actual_tolm, actual_tolm); 1151 edac_dbg(2, "Actual TOLM byte addr=%u (0x%x)\n",
1152 actual_tolm, actual_tolm);
1154 1153
1155 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0); 1154 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
1156 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1); 1155 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
@@ -1160,15 +1159,18 @@ static void i5000_get_mc_regs(struct mem_ctl_info *mci)
1160 limit = (pvt->mir0 >> 4) & 0x0FFF; 1159 limit = (pvt->mir0 >> 4) & 0x0FFF;
1161 way0 = pvt->mir0 & 0x1; 1160 way0 = pvt->mir0 & 0x1;
1162 way1 = pvt->mir0 & 0x2; 1161 way1 = pvt->mir0 & 0x2;
1163 debugf2("MIR0: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0); 1162 edac_dbg(2, "MIR0: limit= 0x%x WAY1= %u WAY0= %x\n",
1163 limit, way1, way0);
1164 limit = (pvt->mir1 >> 4) & 0x0FFF; 1164 limit = (pvt->mir1 >> 4) & 0x0FFF;
1165 way0 = pvt->mir1 & 0x1; 1165 way0 = pvt->mir1 & 0x1;
1166 way1 = pvt->mir1 & 0x2; 1166 way1 = pvt->mir1 & 0x2;
1167 debugf2("MIR1: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0); 1167 edac_dbg(2, "MIR1: limit= 0x%x WAY1= %u WAY0= %x\n",
1168 limit, way1, way0);
1168 limit = (pvt->mir2 >> 4) & 0x0FFF; 1169 limit = (pvt->mir2 >> 4) & 0x0FFF;
1169 way0 = pvt->mir2 & 0x1; 1170 way0 = pvt->mir2 & 0x1;
1170 way1 = pvt->mir2 & 0x2; 1171 way1 = pvt->mir2 & 0x2;
1171 debugf2("MIR2: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0); 1172 edac_dbg(2, "MIR2: limit= 0x%x WAY1= %u WAY0= %x\n",
1173 limit, way1, way0);
1172 1174
1173 /* Get the MTR[0-3] regs */ 1175 /* Get the MTR[0-3] regs */
1174 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) { 1176 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
@@ -1177,31 +1179,31 @@ static void i5000_get_mc_regs(struct mem_ctl_info *mci)
1177 pci_read_config_word(pvt->branch_0, where, 1179 pci_read_config_word(pvt->branch_0, where,
1178 &pvt->b0_mtr[slot_row]); 1180 &pvt->b0_mtr[slot_row]);
1179 1181
1180 debugf2("MTR%d where=0x%x B0 value=0x%x\n", slot_row, where, 1182 edac_dbg(2, "MTR%d where=0x%x B0 value=0x%x\n",
1181 pvt->b0_mtr[slot_row]); 1183 slot_row, where, pvt->b0_mtr[slot_row]);
1182 1184
1183 if (pvt->maxch >= CHANNELS_PER_BRANCH) { 1185 if (pvt->maxch >= CHANNELS_PER_BRANCH) {
1184 pci_read_config_word(pvt->branch_1, where, 1186 pci_read_config_word(pvt->branch_1, where,
1185 &pvt->b1_mtr[slot_row]); 1187 &pvt->b1_mtr[slot_row]);
1186 debugf2("MTR%d where=0x%x B1 value=0x%x\n", slot_row, 1188 edac_dbg(2, "MTR%d where=0x%x B1 value=0x%x\n",
1187 where, pvt->b1_mtr[slot_row]); 1189 slot_row, where, pvt->b1_mtr[slot_row]);
1188 } else { 1190 } else {
1189 pvt->b1_mtr[slot_row] = 0; 1191 pvt->b1_mtr[slot_row] = 0;
1190 } 1192 }
1191 } 1193 }
1192 1194
1193 /* Read and dump branch 0's MTRs */ 1195 /* Read and dump branch 0's MTRs */
1194 debugf2("\nMemory Technology Registers:\n"); 1196 edac_dbg(2, "Memory Technology Registers:\n");
1195 debugf2(" Branch 0:\n"); 1197 edac_dbg(2, " Branch 0:\n");
1196 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) { 1198 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1197 decode_mtr(slot_row, pvt->b0_mtr[slot_row]); 1199 decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
1198 } 1200 }
1199 pci_read_config_word(pvt->branch_0, AMB_PRESENT_0, 1201 pci_read_config_word(pvt->branch_0, AMB_PRESENT_0,
1200 &pvt->b0_ambpresent0); 1202 &pvt->b0_ambpresent0);
1201 debugf2("\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0); 1203 edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
1202 pci_read_config_word(pvt->branch_0, AMB_PRESENT_1, 1204 pci_read_config_word(pvt->branch_0, AMB_PRESENT_1,
1203 &pvt->b0_ambpresent1); 1205 &pvt->b0_ambpresent1);
1204 debugf2("\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1); 1206 edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
1205 1207
1206 /* Only if we have 2 branchs (4 channels) */ 1208 /* Only if we have 2 branchs (4 channels) */
1207 if (pvt->maxch < CHANNELS_PER_BRANCH) { 1209 if (pvt->maxch < CHANNELS_PER_BRANCH) {
@@ -1209,18 +1211,18 @@ static void i5000_get_mc_regs(struct mem_ctl_info *mci)
1209 pvt->b1_ambpresent1 = 0; 1211 pvt->b1_ambpresent1 = 0;
1210 } else { 1212 } else {
1211 /* Read and dump branch 1's MTRs */ 1213 /* Read and dump branch 1's MTRs */
1212 debugf2(" Branch 1:\n"); 1214 edac_dbg(2, " Branch 1:\n");
1213 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) { 1215 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1214 decode_mtr(slot_row, pvt->b1_mtr[slot_row]); 1216 decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
1215 } 1217 }
1216 pci_read_config_word(pvt->branch_1, AMB_PRESENT_0, 1218 pci_read_config_word(pvt->branch_1, AMB_PRESENT_0,
1217 &pvt->b1_ambpresent0); 1219 &pvt->b1_ambpresent0);
1218 debugf2("\t\tAMB-Branch 1-present0 0x%x:\n", 1220 edac_dbg(2, "\t\tAMB-Branch 1-present0 0x%x:\n",
1219 pvt->b1_ambpresent0); 1221 pvt->b1_ambpresent0);
1220 pci_read_config_word(pvt->branch_1, AMB_PRESENT_1, 1222 pci_read_config_word(pvt->branch_1, AMB_PRESENT_1,
1221 &pvt->b1_ambpresent1); 1223 &pvt->b1_ambpresent1);
1222 debugf2("\t\tAMB-Branch 1-present1 0x%x:\n", 1224 edac_dbg(2, "\t\tAMB-Branch 1-present1 0x%x:\n",
1223 pvt->b1_ambpresent1); 1225 pvt->b1_ambpresent1);
1224 } 1226 }
1225 1227
1226 /* Go and determine the size of each DIMM and place in an 1228 /* Go and determine the size of each DIMM and place in an
@@ -1355,9 +1357,9 @@ static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
1355 int num_channels; 1357 int num_channels;
1356 int num_dimms_per_channel; 1358 int num_dimms_per_channel;
1357 1359
1358 debugf0("MC: %s(), pdev bus %u dev=0x%x fn=0x%x\n", 1360 edac_dbg(0, "MC: pdev bus %u dev=0x%x fn=0x%x\n",
1359 __FILE__, pdev->bus->number, 1361 pdev->bus->number,
1360 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 1362 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1361 1363
1362 /* We only are looking for func 0 of the set */ 1364 /* We only are looking for func 0 of the set */
1363 if (PCI_FUNC(pdev->devfn) != 0) 1365 if (PCI_FUNC(pdev->devfn) != 0)
@@ -1379,8 +1381,8 @@ static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
1379 i5000_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel, 1381 i5000_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel,
1380 &num_channels); 1382 &num_channels);
1381 1383
1382 debugf0("MC: Number of Branches=2 Channels= %d DIMMS= %d\n", 1384 edac_dbg(0, "MC: Number of Branches=2 Channels= %d DIMMS= %d\n",
1383 num_channels, num_dimms_per_channel); 1385 num_channels, num_dimms_per_channel);
1384 1386
1385 /* allocate a new MC control structure */ 1387 /* allocate a new MC control structure */
1386 1388
@@ -1397,7 +1399,7 @@ static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
1397 if (mci == NULL) 1399 if (mci == NULL)
1398 return -ENOMEM; 1400 return -ENOMEM;
1399 1401
1400 debugf0("MC: %s(): mci = %p\n", __FILE__, mci); 1402 edac_dbg(0, "MC: mci = %p\n", mci);
1401 1403
1402 mci->pdev = &pdev->dev; /* record ptr to the generic device */ 1404 mci->pdev = &pdev->dev; /* record ptr to the generic device */
1403 1405
@@ -1429,19 +1431,16 @@ static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
1429 /* initialize the MC control structure 'csrows' table 1431 /* initialize the MC control structure 'csrows' table
1430 * with the mapping and control information */ 1432 * with the mapping and control information */
1431 if (i5000_init_csrows(mci)) { 1433 if (i5000_init_csrows(mci)) {
1432 debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n" 1434 edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i5000_init_csrows() returned nonzero value\n");
1433 " because i5000_init_csrows() returned nonzero "
1434 "value\n");
1435 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */ 1435 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
1436 } else { 1436 } else {
1437 debugf1("MC: Enable error reporting now\n"); 1437 edac_dbg(1, "MC: Enable error reporting now\n");
1438 i5000_enable_error_reporting(mci); 1438 i5000_enable_error_reporting(mci);
1439 } 1439 }
1440 1440
1441 /* add this new MC control structure to EDAC's list of MCs */ 1441 /* add this new MC control structure to EDAC's list of MCs */
1442 if (edac_mc_add_mc(mci)) { 1442 if (edac_mc_add_mc(mci)) {
1443 debugf0("MC: %s(): failed edac_mc_add_mc()\n", 1443 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
1444 __FILE__);
1445 /* FIXME: perhaps some code should go here that disables error 1444 /* FIXME: perhaps some code should go here that disables error
1446 * reporting if we just enabled it 1445 * reporting if we just enabled it
1447 */ 1446 */
@@ -1485,7 +1484,7 @@ static int __devinit i5000_init_one(struct pci_dev *pdev,
1485{ 1484{
1486 int rc; 1485 int rc;
1487 1486
1488 debugf0("MC: %s()\n", __FILE__); 1487 edac_dbg(0, "MC:\n");
1489 1488
1490 /* wake up device */ 1489 /* wake up device */
1491 rc = pci_enable_device(pdev); 1490 rc = pci_enable_device(pdev);
@@ -1504,7 +1503,7 @@ static void __devexit i5000_remove_one(struct pci_dev *pdev)
1504{ 1503{
1505 struct mem_ctl_info *mci; 1504 struct mem_ctl_info *mci;
1506 1505
1507 debugf0("%s()\n", __FILE__); 1506 edac_dbg(0, "\n");
1508 1507
1509 if (i5000_pci) 1508 if (i5000_pci)
1510 edac_pci_release_generic_ctl(i5000_pci); 1509 edac_pci_release_generic_ctl(i5000_pci);
@@ -1550,7 +1549,7 @@ static int __init i5000_init(void)
1550{ 1549{
1551 int pci_rc; 1550 int pci_rc;
1552 1551
1553 debugf2("MC: %s()\n", __FILE__); 1552 edac_dbg(2, "MC:\n");
1554 1553
1555 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 1554 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1556 opstate_init(); 1555 opstate_init();
@@ -1566,7 +1565,7 @@ static int __init i5000_init(void)
1566 */ 1565 */
1567static void __exit i5000_exit(void) 1566static void __exit i5000_exit(void)
1568{ 1567{
1569 debugf2("MC: %s()\n", __FILE__); 1568 edac_dbg(2, "MC:\n");
1570 pci_unregister_driver(&i5000_driver); 1569 pci_unregister_driver(&i5000_driver);
1571} 1570}
1572 1571
diff --git a/drivers/edac/i5100_edac.c b/drivers/edac/i5100_edac.c
index 19aa2843c46..a9b996c8ef2 100644
--- a/drivers/edac/i5100_edac.c
+++ b/drivers/edac/i5100_edac.c
@@ -859,8 +859,8 @@ static void __devinit i5100_init_csrows(struct mem_ctl_info *mci)
859 i5100_rank_to_slot(mci, chan, rank)); 859 i5100_rank_to_slot(mci, chan, rank));
860 } 860 }
861 861
862 debugf2("dimm channel %d, rank %d, size %ld\n", 862 edac_dbg(2, "dimm channel %d, rank %d, size %ld\n",
863 chan, rank, (long)PAGES_TO_MiB(npages)); 863 chan, rank, (long)PAGES_TO_MiB(npages));
864 } 864 }
865} 865}
866 866
diff --git a/drivers/edac/i5400_edac.c b/drivers/edac/i5400_edac.c
index 3004b946c40..90fad3a9c3f 100644
--- a/drivers/edac/i5400_edac.c
+++ b/drivers/edac/i5400_edac.c
@@ -542,10 +542,9 @@ static void i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci,
542 ras = nrec_ras(info); 542 ras = nrec_ras(info);
543 cas = nrec_cas(info); 543 cas = nrec_cas(info);
544 544
545 debugf0("\t\tDIMM= %d Channels= %d,%d (Branch= %d " 545 edac_dbg(0, "\t\tDIMM= %d Channels= %d,%d (Branch= %d DRAM Bank= %d Buffer ID = %d rdwr= %s ras= %d cas= %d)\n",
546 "DRAM Bank= %d Buffer ID = %d rdwr= %s ras= %d cas= %d)\n", 546 rank, channel, channel + 1, branch >> 1, bank,
547 rank, channel, channel + 1, branch >> 1, bank, 547 buf_id, rdwr_str(rdwr), ras, cas);
548 buf_id, rdwr_str(rdwr), ras, cas);
549 548
550 /* Only 1 bit will be on */ 549 /* Only 1 bit will be on */
551 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name)); 550 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
@@ -595,7 +594,7 @@ static void i5400_process_nonfatal_error_info(struct mem_ctl_info *mci,
595 594
596 /* Correctable errors */ 595 /* Correctable errors */
597 if (allErrors & ERROR_NF_CORRECTABLE) { 596 if (allErrors & ERROR_NF_CORRECTABLE) {
598 debugf0("\tCorrected bits= 0x%lx\n", allErrors); 597 edac_dbg(0, "\tCorrected bits= 0x%lx\n", allErrors);
599 598
600 branch = extract_fbdchan_indx(info->ferr_nf_fbd); 599 branch = extract_fbdchan_indx(info->ferr_nf_fbd);
601 600
@@ -616,10 +615,9 @@ static void i5400_process_nonfatal_error_info(struct mem_ctl_info *mci,
616 /* Only 1 bit will be on */ 615 /* Only 1 bit will be on */
617 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name)); 616 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
618 617
619 debugf0("\t\tDIMM= %d Channel= %d (Branch %d " 618 edac_dbg(0, "\t\tDIMM= %d Channel= %d (Branch %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
620 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n", 619 rank, channel, branch >> 1, bank,
621 rank, channel, branch >> 1, bank, 620 rdwr_str(rdwr), ras, cas);
622 rdwr_str(rdwr), ras, cas);
623 621
624 /* Form out message */ 622 /* Form out message */
625 snprintf(msg, sizeof(msg), 623 snprintf(msg, sizeof(msg),
@@ -682,7 +680,7 @@ static void i5400_clear_error(struct mem_ctl_info *mci)
682static void i5400_check_error(struct mem_ctl_info *mci) 680static void i5400_check_error(struct mem_ctl_info *mci)
683{ 681{
684 struct i5400_error_info info; 682 struct i5400_error_info info;
685 debugf4("MC%d\n", mci->mc_idx); 683 edac_dbg(4, "MC%d\n", mci->mc_idx);
686 i5400_get_error_info(mci, &info); 684 i5400_get_error_info(mci, &info);
687 i5400_process_error_info(mci, &info); 685 i5400_process_error_info(mci, &info);
688} 686}
@@ -768,15 +766,16 @@ static int i5400_get_devices(struct mem_ctl_info *mci, int dev_idx)
768 } 766 }
769 pvt->fsb_error_regs = pdev; 767 pvt->fsb_error_regs = pdev;
770 768
771 debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x\n", 769 edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s %x:%x\n",
772 pci_name(pvt->system_address), 770 pci_name(pvt->system_address),
773 pvt->system_address->vendor, pvt->system_address->device); 771 pvt->system_address->vendor, pvt->system_address->device);
774 debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x\n", 772 edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
775 pci_name(pvt->branchmap_werrors), 773 pci_name(pvt->branchmap_werrors),
776 pvt->branchmap_werrors->vendor, pvt->branchmap_werrors->device); 774 pvt->branchmap_werrors->vendor,
777 debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x\n", 775 pvt->branchmap_werrors->device);
778 pci_name(pvt->fsb_error_regs), 776 edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s %x:%x\n",
779 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device); 777 pci_name(pvt->fsb_error_regs),
778 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
780 779
781 pvt->branch_0 = pci_get_device(PCI_VENDOR_ID_INTEL, 780 pvt->branch_0 = pci_get_device(PCI_VENDOR_ID_INTEL,
782 PCI_DEVICE_ID_INTEL_5400_FBD0, NULL); 781 PCI_DEVICE_ID_INTEL_5400_FBD0, NULL);
@@ -864,8 +863,8 @@ static int determine_mtr(struct i5400_pvt *pvt, int dimm, int channel)
864 n = dimm; 863 n = dimm;
865 864
866 if (n >= DIMMS_PER_CHANNEL) { 865 if (n >= DIMMS_PER_CHANNEL) {
867 debugf0("ERROR: trying to access an invalid dimm: %d\n", 866 edac_dbg(0, "ERROR: trying to access an invalid dimm: %d\n",
868 dimm); 867 dimm);
869 return 0; 868 return 0;
870 } 869 }
871 870
@@ -885,28 +884,29 @@ static void decode_mtr(int slot_row, u16 mtr)
885 884
886 ans = MTR_DIMMS_PRESENT(mtr); 885 ans = MTR_DIMMS_PRESENT(mtr);
887 886
888 debugf2("\tMTR%d=0x%x: DIMMs are %s\n", slot_row, mtr, 887 edac_dbg(2, "\tMTR%d=0x%x: DIMMs are %sPresent\n",
889 ans ? "Present" : "NOT Present"); 888 slot_row, mtr, ans ? "" : "NOT ");
890 if (!ans) 889 if (!ans)
891 return; 890 return;
892 891
893 debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr)); 892 edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
894 893
895 debugf2("\t\tELECTRICAL THROTTLING is %s\n", 894 edac_dbg(2, "\t\tELECTRICAL THROTTLING is %s\n",
896 MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled"); 895 MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");
897 896
898 debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr)); 897 edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
899 debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANK(mtr) ? "double" : "single"); 898 edac_dbg(2, "\t\tNUMRANK: %s\n",
900 debugf2("\t\tNUMROW: %s\n", 899 MTR_DIMM_RANK(mtr) ? "double" : "single");
901 MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" : 900 edac_dbg(2, "\t\tNUMROW: %s\n",
902 MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" : 901 MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" :
903 MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" : 902 MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" :
904 "65,536 - 16 rows"); 903 MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" :
905 debugf2("\t\tNUMCOL: %s\n", 904 "65,536 - 16 rows");
906 MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" : 905 edac_dbg(2, "\t\tNUMCOL: %s\n",
907 MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" : 906 MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" :
908 MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" : 907 MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" :
909 "reserved"); 908 MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" :
909 "reserved");
910} 910}
911 911
912static void handle_channel(struct i5400_pvt *pvt, int dimm, int channel, 912static void handle_channel(struct i5400_pvt *pvt, int dimm, int channel,
@@ -979,7 +979,7 @@ static void calculate_dimm_size(struct i5400_pvt *pvt)
979 "-------------------------------"); 979 "-------------------------------");
980 p += n; 980 p += n;
981 space -= n; 981 space -= n;
982 debugf2("%s\n", mem_buffer); 982 edac_dbg(2, "%s\n", mem_buffer);
983 p = mem_buffer; 983 p = mem_buffer;
984 space = PAGE_SIZE; 984 space = PAGE_SIZE;
985 } 985 }
@@ -994,7 +994,7 @@ static void calculate_dimm_size(struct i5400_pvt *pvt)
994 p += n; 994 p += n;
995 space -= n; 995 space -= n;
996 } 996 }
997 debugf2("%s\n", mem_buffer); 997 edac_dbg(2, "%s\n", mem_buffer);
998 p = mem_buffer; 998 p = mem_buffer;
999 space = PAGE_SIZE; 999 space = PAGE_SIZE;
1000 } 1000 }
@@ -1004,7 +1004,7 @@ static void calculate_dimm_size(struct i5400_pvt *pvt)
1004 "-------------------------------"); 1004 "-------------------------------");
1005 p += n; 1005 p += n;
1006 space -= n; 1006 space -= n;
1007 debugf2("%s\n", mem_buffer); 1007 edac_dbg(2, "%s\n", mem_buffer);
1008 p = mem_buffer; 1008 p = mem_buffer;
1009 space = PAGE_SIZE; 1009 space = PAGE_SIZE;
1010 1010
@@ -1019,7 +1019,7 @@ static void calculate_dimm_size(struct i5400_pvt *pvt)
1019 } 1019 }
1020 1020
1021 space -= n; 1021 space -= n;
1022 debugf2("%s\n", mem_buffer); 1022 edac_dbg(2, "%s\n", mem_buffer);
1023 p = mem_buffer; 1023 p = mem_buffer;
1024 space = PAGE_SIZE; 1024 space = PAGE_SIZE;
1025 1025
@@ -1032,7 +1032,7 @@ static void calculate_dimm_size(struct i5400_pvt *pvt)
1032 } 1032 }
1033 1033
1034 /* output the last message and free buffer */ 1034 /* output the last message and free buffer */
1035 debugf2("%s\n", mem_buffer); 1035 edac_dbg(2, "%s\n", mem_buffer);
1036 kfree(mem_buffer); 1036 kfree(mem_buffer);
1037} 1037}
1038 1038
@@ -1062,18 +1062,18 @@ static void i5400_get_mc_regs(struct mem_ctl_info *mci)
1062 maxdimmperch = pvt->maxdimmperch; 1062 maxdimmperch = pvt->maxdimmperch;
1063 maxch = pvt->maxch; 1063 maxch = pvt->maxch;
1064 1064
1065 debugf2("AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n", 1065 edac_dbg(2, "AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n",
1066 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch); 1066 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
1067 1067
1068 /* Get the Branch Map regs */ 1068 /* Get the Branch Map regs */
1069 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm); 1069 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
1070 pvt->tolm >>= 12; 1070 pvt->tolm >>= 12;
1071 debugf2("\nTOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm, 1071 edac_dbg(2, "\nTOLM (number of 256M regions) =%u (0x%x)\n",
1072 pvt->tolm); 1072 pvt->tolm, pvt->tolm);
1073 1073
1074 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28)); 1074 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28));
1075 debugf2("Actual TOLM byte addr=%u.%03u GB (0x%x)\n", 1075 edac_dbg(2, "Actual TOLM byte addr=%u.%03u GB (0x%x)\n",
1076 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28); 1076 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);
1077 1077
1078 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0); 1078 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
1079 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1); 1079 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
@@ -1082,11 +1082,13 @@ static void i5400_get_mc_regs(struct mem_ctl_info *mci)
1082 limit = (pvt->mir0 >> 4) & 0x0fff; 1082 limit = (pvt->mir0 >> 4) & 0x0fff;
1083 way0 = pvt->mir0 & 0x1; 1083 way0 = pvt->mir0 & 0x1;
1084 way1 = pvt->mir0 & 0x2; 1084 way1 = pvt->mir0 & 0x2;
1085 debugf2("MIR0: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0); 1085 edac_dbg(2, "MIR0: limit= 0x%x WAY1= %u WAY0= %x\n",
1086 limit, way1, way0);
1086 limit = (pvt->mir1 >> 4) & 0xfff; 1087 limit = (pvt->mir1 >> 4) & 0xfff;
1087 way0 = pvt->mir1 & 0x1; 1088 way0 = pvt->mir1 & 0x1;
1088 way1 = pvt->mir1 & 0x2; 1089 way1 = pvt->mir1 & 0x2;
1089 debugf2("MIR1: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0); 1090 edac_dbg(2, "MIR1: limit= 0x%x WAY1= %u WAY0= %x\n",
1091 limit, way1, way0);
1090 1092
1091 /* Get the set of MTR[0-3] regs by each branch */ 1093 /* Get the set of MTR[0-3] regs by each branch */
1092 for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) { 1094 for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) {
@@ -1096,8 +1098,8 @@ static void i5400_get_mc_regs(struct mem_ctl_info *mci)
1096 pci_read_config_word(pvt->branch_0, where, 1098 pci_read_config_word(pvt->branch_0, where,
1097 &pvt->b0_mtr[slot_row]); 1099 &pvt->b0_mtr[slot_row]);
1098 1100
1099 debugf2("MTR%d where=0x%x B0 value=0x%x\n", slot_row, where, 1101 edac_dbg(2, "MTR%d where=0x%x B0 value=0x%x\n",
1100 pvt->b0_mtr[slot_row]); 1102 slot_row, where, pvt->b0_mtr[slot_row]);
1101 1103
1102 if (pvt->maxch < CHANNELS_PER_BRANCH) { 1104 if (pvt->maxch < CHANNELS_PER_BRANCH) {
1103 pvt->b1_mtr[slot_row] = 0; 1105 pvt->b1_mtr[slot_row] = 0;
@@ -1107,22 +1109,22 @@ static void i5400_get_mc_regs(struct mem_ctl_info *mci)
1107 /* Branch 1 set of MTR registers */ 1109 /* Branch 1 set of MTR registers */
1108 pci_read_config_word(pvt->branch_1, where, 1110 pci_read_config_word(pvt->branch_1, where,
1109 &pvt->b1_mtr[slot_row]); 1111 &pvt->b1_mtr[slot_row]);
1110 debugf2("MTR%d where=0x%x B1 value=0x%x\n", slot_row, where, 1112 edac_dbg(2, "MTR%d where=0x%x B1 value=0x%x\n",
1111 pvt->b1_mtr[slot_row]); 1113 slot_row, where, pvt->b1_mtr[slot_row]);
1112 } 1114 }
1113 1115
1114 /* Read and dump branch 0's MTRs */ 1116 /* Read and dump branch 0's MTRs */
1115 debugf2("\nMemory Technology Registers:\n"); 1117 edac_dbg(2, "Memory Technology Registers:\n");
1116 debugf2(" Branch 0:\n"); 1118 edac_dbg(2, " Branch 0:\n");
1117 for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) 1119 for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++)
1118 decode_mtr(slot_row, pvt->b0_mtr[slot_row]); 1120 decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
1119 1121
1120 pci_read_config_word(pvt->branch_0, AMBPRESENT_0, 1122 pci_read_config_word(pvt->branch_0, AMBPRESENT_0,
1121 &pvt->b0_ambpresent0); 1123 &pvt->b0_ambpresent0);
1122 debugf2("\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0); 1124 edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
1123 pci_read_config_word(pvt->branch_0, AMBPRESENT_1, 1125 pci_read_config_word(pvt->branch_0, AMBPRESENT_1,
1124 &pvt->b0_ambpresent1); 1126 &pvt->b0_ambpresent1);
1125 debugf2("\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1); 1127 edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
1126 1128
1127 /* Only if we have 2 branchs (4 channels) */ 1129 /* Only if we have 2 branchs (4 channels) */
1128 if (pvt->maxch < CHANNELS_PER_BRANCH) { 1130 if (pvt->maxch < CHANNELS_PER_BRANCH) {
@@ -1130,18 +1132,18 @@ static void i5400_get_mc_regs(struct mem_ctl_info *mci)
1130 pvt->b1_ambpresent1 = 0; 1132 pvt->b1_ambpresent1 = 0;
1131 } else { 1133 } else {
1132 /* Read and dump branch 1's MTRs */ 1134 /* Read and dump branch 1's MTRs */
1133 debugf2(" Branch 1:\n"); 1135 edac_dbg(2, " Branch 1:\n");
1134 for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) 1136 for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++)
1135 decode_mtr(slot_row, pvt->b1_mtr[slot_row]); 1137 decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
1136 1138
1137 pci_read_config_word(pvt->branch_1, AMBPRESENT_0, 1139 pci_read_config_word(pvt->branch_1, AMBPRESENT_0,
1138 &pvt->b1_ambpresent0); 1140 &pvt->b1_ambpresent0);
1139 debugf2("\t\tAMB-Branch 1-present0 0x%x:\n", 1141 edac_dbg(2, "\t\tAMB-Branch 1-present0 0x%x:\n",
1140 pvt->b1_ambpresent0); 1142 pvt->b1_ambpresent0);
1141 pci_read_config_word(pvt->branch_1, AMBPRESENT_1, 1143 pci_read_config_word(pvt->branch_1, AMBPRESENT_1,
1142 &pvt->b1_ambpresent1); 1144 &pvt->b1_ambpresent1);
1143 debugf2("\t\tAMB-Branch 1-present1 0x%x:\n", 1145 edac_dbg(2, "\t\tAMB-Branch 1-present1 0x%x:\n",
1144 pvt->b1_ambpresent1); 1146 pvt->b1_ambpresent1);
1145 } 1147 }
1146 1148
1147 /* Go and determine the size of each DIMM and place in an 1149 /* Go and determine the size of each DIMM and place in an
@@ -1193,9 +1195,9 @@ static int i5400_init_dimms(struct mem_ctl_info *mci)
1193 1195
1194 size_mb = pvt->dimm_info[slot][channel].megabytes; 1196 size_mb = pvt->dimm_info[slot][channel].megabytes;
1195 1197
1196 debugf2("dimm (branch %d channel %d slot %d): %d.%03d GB\n", 1198 edac_dbg(2, "dimm (branch %d channel %d slot %d): %d.%03d GB\n",
1197 channel / 2, channel % 2, slot, 1199 channel / 2, channel % 2, slot,
1198 size_mb / 1000, size_mb % 1000); 1200 size_mb / 1000, size_mb % 1000);
1199 1201
1200 dimm->nr_pages = size_mb << 8; 1202 dimm->nr_pages = size_mb << 8;
1201 dimm->grain = 8; 1203 dimm->grain = 8;
@@ -1259,9 +1261,9 @@ static int i5400_probe1(struct pci_dev *pdev, int dev_idx)
1259 if (dev_idx >= ARRAY_SIZE(i5400_devs)) 1261 if (dev_idx >= ARRAY_SIZE(i5400_devs))
1260 return -EINVAL; 1262 return -EINVAL;
1261 1263
1262 debugf0("MC: %s(), pdev bus %u dev=0x%x fn=0x%x\n", 1264 edac_dbg(0, "MC: pdev bus %u dev=0x%x fn=0x%x\n",
1263 __FILE__, pdev->bus->number, 1265 pdev->bus->number,
1264 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 1266 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1265 1267
1266 /* We only are looking for func 0 of the set */ 1268 /* We only are looking for func 0 of the set */
1267 if (PCI_FUNC(pdev->devfn) != 0) 1269 if (PCI_FUNC(pdev->devfn) != 0)
@@ -1285,7 +1287,7 @@ static int i5400_probe1(struct pci_dev *pdev, int dev_idx)
1285 if (mci == NULL) 1287 if (mci == NULL)
1286 return -ENOMEM; 1288 return -ENOMEM;
1287 1289
1288 debugf0("MC: %s(): mci = %p\n", __FILE__, mci); 1290 edac_dbg(0, "MC: mci = %p\n", mci);
1289 1291
1290 mci->pdev = &pdev->dev; /* record ptr to the generic device */ 1292 mci->pdev = &pdev->dev; /* record ptr to the generic device */
1291 1293
@@ -1317,19 +1319,16 @@ static int i5400_probe1(struct pci_dev *pdev, int dev_idx)
1317 /* initialize the MC control structure 'dimms' table 1319 /* initialize the MC control structure 'dimms' table
1318 * with the mapping and control information */ 1320 * with the mapping and control information */
1319 if (i5400_init_dimms(mci)) { 1321 if (i5400_init_dimms(mci)) {
1320 debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n" 1322 edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i5400_init_dimms() returned nonzero value\n");
1321 " because i5400_init_dimms() returned nonzero "
1322 "value\n");
1323 mci->edac_cap = EDAC_FLAG_NONE; /* no dimms found */ 1323 mci->edac_cap = EDAC_FLAG_NONE; /* no dimms found */
1324 } else { 1324 } else {
1325 debugf1("MC: Enable error reporting now\n"); 1325 edac_dbg(1, "MC: Enable error reporting now\n");
1326 i5400_enable_error_reporting(mci); 1326 i5400_enable_error_reporting(mci);
1327 } 1327 }
1328 1328
1329 /* add this new MC control structure to EDAC's list of MCs */ 1329 /* add this new MC control structure to EDAC's list of MCs */
1330 if (edac_mc_add_mc(mci)) { 1330 if (edac_mc_add_mc(mci)) {
1331 debugf0("MC: %s(): failed edac_mc_add_mc()\n", 1331 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
1332 __FILE__);
1333 /* FIXME: perhaps some code should go here that disables error 1332 /* FIXME: perhaps some code should go here that disables error
1334 * reporting if we just enabled it 1333 * reporting if we just enabled it
1335 */ 1334 */
@@ -1373,7 +1372,7 @@ static int __devinit i5400_init_one(struct pci_dev *pdev,
1373{ 1372{
1374 int rc; 1373 int rc;
1375 1374
1376 debugf0("MC: %s()\n", __FILE__); 1375 edac_dbg(0, "MC:\n");
1377 1376
1378 /* wake up device */ 1377 /* wake up device */
1379 rc = pci_enable_device(pdev); 1378 rc = pci_enable_device(pdev);
@@ -1392,7 +1391,7 @@ static void __devexit i5400_remove_one(struct pci_dev *pdev)
1392{ 1391{
1393 struct mem_ctl_info *mci; 1392 struct mem_ctl_info *mci;
1394 1393
1395 debugf0("%s()\n", __FILE__); 1394 edac_dbg(0, "\n");
1396 1395
1397 if (i5400_pci) 1396 if (i5400_pci)
1398 edac_pci_release_generic_ctl(i5400_pci); 1397 edac_pci_release_generic_ctl(i5400_pci);
@@ -1438,7 +1437,7 @@ static int __init i5400_init(void)
1438{ 1437{
1439 int pci_rc; 1438 int pci_rc;
1440 1439
1441 debugf2("MC: %s()\n", __FILE__); 1440 edac_dbg(2, "MC:\n");
1442 1441
1443 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 1442 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1444 opstate_init(); 1443 opstate_init();
@@ -1454,7 +1453,7 @@ static int __init i5400_init(void)
1454 */ 1453 */
1455static void __exit i5400_exit(void) 1454static void __exit i5400_exit(void)
1456{ 1455{
1457 debugf2("MC: %s()\n", __FILE__); 1456 edac_dbg(2, "MC:\n");
1458 pci_unregister_driver(&i5400_driver); 1457 pci_unregister_driver(&i5400_driver);
1459} 1458}
1460 1459
diff --git a/drivers/edac/i7300_edac.c b/drivers/edac/i7300_edac.c
index 7eca688f788..738b8919194 100644
--- a/drivers/edac/i7300_edac.c
+++ b/drivers/edac/i7300_edac.c
@@ -596,9 +596,8 @@ static int decode_mtr(struct i7300_pvt *pvt,
596 mtr = pvt->mtr[slot][branch]; 596 mtr = pvt->mtr[slot][branch];
597 ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0; 597 ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0;
598 598
599 debugf2("\tMTR%d CH%d: DIMMs are %s (mtr)\n", 599 edac_dbg(2, "\tMTR%d CH%d: DIMMs are %sPresent (mtr)\n",
600 slot, channel, 600 slot, channel, ans ? "" : "NOT ");
601 ans ? "Present" : "NOT Present");
602 601
603 /* Determine if there is a DIMM present in this DIMM slot */ 602 /* Determine if there is a DIMM present in this DIMM slot */
604 if (!ans) 603 if (!ans)
@@ -620,24 +619,25 @@ static int decode_mtr(struct i7300_pvt *pvt,
620 619
621 dinfo->megabytes = 1 << addrBits; 620 dinfo->megabytes = 1 << addrBits;
622 621
623 debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr)); 622 edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
624 623
625 debugf2("\t\tELECTRICAL THROTTLING is %s\n", 624 edac_dbg(2, "\t\tELECTRICAL THROTTLING is %s\n",
626 MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled"); 625 MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");
627 626
628 debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr)); 627 edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
629 debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANKS(mtr) ? "double" : "single"); 628 edac_dbg(2, "\t\tNUMRANK: %s\n",
630 debugf2("\t\tNUMROW: %s\n", 629 MTR_DIMM_RANKS(mtr) ? "double" : "single");
631 MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" : 630 edac_dbg(2, "\t\tNUMROW: %s\n",
632 MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" : 631 MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" :
633 MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" : 632 MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" :
634 "65,536 - 16 rows"); 633 MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" :
635 debugf2("\t\tNUMCOL: %s\n", 634 "65,536 - 16 rows");
636 MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" : 635 edac_dbg(2, "\t\tNUMCOL: %s\n",
637 MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" : 636 MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" :
638 MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" : 637 MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" :
639 "reserved"); 638 MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" :
640 debugf2("\t\tSIZE: %d MB\n", dinfo->megabytes); 639 "reserved");
640 edac_dbg(2, "\t\tSIZE: %d MB\n", dinfo->megabytes);
641 641
642 /* 642 /*
643 * The type of error detection actually depends of the 643 * The type of error detection actually depends of the
@@ -653,9 +653,9 @@ static int decode_mtr(struct i7300_pvt *pvt,
653 dimm->mtype = MEM_FB_DDR2; 653 dimm->mtype = MEM_FB_DDR2;
654 if (IS_SINGLE_MODE(pvt->mc_settings_a)) { 654 if (IS_SINGLE_MODE(pvt->mc_settings_a)) {
655 dimm->edac_mode = EDAC_SECDED; 655 dimm->edac_mode = EDAC_SECDED;
656 debugf2("\t\tECC code is 8-byte-over-32-byte SECDED+ code\n"); 656 edac_dbg(2, "\t\tECC code is 8-byte-over-32-byte SECDED+ code\n");
657 } else { 657 } else {
658 debugf2("\t\tECC code is on Lockstep mode\n"); 658 edac_dbg(2, "\t\tECC code is on Lockstep mode\n");
659 if (MTR_DRAM_WIDTH(mtr) == 8) 659 if (MTR_DRAM_WIDTH(mtr) == 8)
660 dimm->edac_mode = EDAC_S8ECD8ED; 660 dimm->edac_mode = EDAC_S8ECD8ED;
661 else 661 else
@@ -664,9 +664,9 @@ static int decode_mtr(struct i7300_pvt *pvt,
664 664
665 /* ask what device type on this row */ 665 /* ask what device type on this row */
666 if (MTR_DRAM_WIDTH(mtr) == 8) { 666 if (MTR_DRAM_WIDTH(mtr) == 8) {
667 debugf2("\t\tScrub algorithm for x8 is on %s mode\n", 667 edac_dbg(2, "\t\tScrub algorithm for x8 is on %s mode\n",
668 IS_SCRBALGO_ENHANCED(pvt->mc_settings) ? 668 IS_SCRBALGO_ENHANCED(pvt->mc_settings) ?
669 "enhanced" : "normal"); 669 "enhanced" : "normal");
670 670
671 dimm->dtype = DEV_X8; 671 dimm->dtype = DEV_X8;
672 } else 672 } else
@@ -700,14 +700,14 @@ static void print_dimm_size(struct i7300_pvt *pvt)
700 p += n; 700 p += n;
701 space -= n; 701 space -= n;
702 } 702 }
703 debugf2("%s\n", pvt->tmp_prt_buffer); 703 edac_dbg(2, "%s\n", pvt->tmp_prt_buffer);
704 p = pvt->tmp_prt_buffer; 704 p = pvt->tmp_prt_buffer;
705 space = PAGE_SIZE; 705 space = PAGE_SIZE;
706 n = snprintf(p, space, "-------------------------------" 706 n = snprintf(p, space, "-------------------------------"
707 "------------------------------"); 707 "------------------------------");
708 p += n; 708 p += n;
709 space -= n; 709 space -= n;
710 debugf2("%s\n", pvt->tmp_prt_buffer); 710 edac_dbg(2, "%s\n", pvt->tmp_prt_buffer);
711 p = pvt->tmp_prt_buffer; 711 p = pvt->tmp_prt_buffer;
712 space = PAGE_SIZE; 712 space = PAGE_SIZE;
713 713
@@ -723,7 +723,7 @@ static void print_dimm_size(struct i7300_pvt *pvt)
723 space -= n; 723 space -= n;
724 } 724 }
725 725
726 debugf2("%s\n", pvt->tmp_prt_buffer); 726 edac_dbg(2, "%s\n", pvt->tmp_prt_buffer);
727 p = pvt->tmp_prt_buffer; 727 p = pvt->tmp_prt_buffer;
728 space = PAGE_SIZE; 728 space = PAGE_SIZE;
729 } 729 }
@@ -732,7 +732,7 @@ static void print_dimm_size(struct i7300_pvt *pvt)
732 "------------------------------"); 732 "------------------------------");
733 p += n; 733 p += n;
734 space -= n; 734 space -= n;
735 debugf2("%s\n", pvt->tmp_prt_buffer); 735 edac_dbg(2, "%s\n", pvt->tmp_prt_buffer);
736 p = pvt->tmp_prt_buffer; 736 p = pvt->tmp_prt_buffer;
737 space = PAGE_SIZE; 737 space = PAGE_SIZE;
738#endif 738#endif
@@ -755,7 +755,7 @@ static int i7300_init_csrows(struct mem_ctl_info *mci)
755 755
756 pvt = mci->pvt_info; 756 pvt = mci->pvt_info;
757 757
758 debugf2("Memory Technology Registers:\n"); 758 edac_dbg(2, "Memory Technology Registers:\n");
759 759
760 /* Get the AMB present registers for the four channels */ 760 /* Get the AMB present registers for the four channels */
761 for (branch = 0; branch < MAX_BRANCHES; branch++) { 761 for (branch = 0; branch < MAX_BRANCHES; branch++) {
@@ -764,15 +764,15 @@ static int i7300_init_csrows(struct mem_ctl_info *mci)
764 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], 764 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
765 AMBPRESENT_0, 765 AMBPRESENT_0,
766 &pvt->ambpresent[channel]); 766 &pvt->ambpresent[channel]);
767 debugf2("\t\tAMB-present CH%d = 0x%x:\n", 767 edac_dbg(2, "\t\tAMB-present CH%d = 0x%x:\n",
768 channel, pvt->ambpresent[channel]); 768 channel, pvt->ambpresent[channel]);
769 769
770 channel = to_channel(1, branch); 770 channel = to_channel(1, branch);
771 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], 771 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
772 AMBPRESENT_1, 772 AMBPRESENT_1,
773 &pvt->ambpresent[channel]); 773 &pvt->ambpresent[channel]);
774 debugf2("\t\tAMB-present CH%d = 0x%x:\n", 774 edac_dbg(2, "\t\tAMB-present CH%d = 0x%x:\n",
775 channel, pvt->ambpresent[channel]); 775 channel, pvt->ambpresent[channel]);
776 } 776 }
777 777
778 /* Get the set of MTR[0-7] regs by each branch */ 778 /* Get the set of MTR[0-7] regs by each branch */
@@ -814,12 +814,11 @@ static int i7300_init_csrows(struct mem_ctl_info *mci)
814static void decode_mir(int mir_no, u16 mir[MAX_MIR]) 814static void decode_mir(int mir_no, u16 mir[MAX_MIR])
815{ 815{
816 if (mir[mir_no] & 3) 816 if (mir[mir_no] & 3)
817 debugf2("MIR%d: limit= 0x%x Branch(es) that participate:" 817 edac_dbg(2, "MIR%d: limit= 0x%x Branch(es) that participate: %s %s\n",
818 " %s %s\n", 818 mir_no,
819 mir_no, 819 (mir[mir_no] >> 4) & 0xfff,
820 (mir[mir_no] >> 4) & 0xfff, 820 (mir[mir_no] & 1) ? "B0" : "",
821 (mir[mir_no] & 1) ? "B0" : "", 821 (mir[mir_no] & 2) ? "B1" : "");
822 (mir[mir_no] & 2) ? "B1" : "");
823} 822}
824 823
825/** 824/**
@@ -839,17 +838,17 @@ static int i7300_get_mc_regs(struct mem_ctl_info *mci)
839 pci_read_config_dword(pvt->pci_dev_16_0_fsb_ctlr, AMBASE, 838 pci_read_config_dword(pvt->pci_dev_16_0_fsb_ctlr, AMBASE,
840 (u32 *) &pvt->ambase); 839 (u32 *) &pvt->ambase);
841 840
842 debugf2("AMBASE= 0x%lx\n", (long unsigned int)pvt->ambase); 841 edac_dbg(2, "AMBASE= 0x%lx\n", (long unsigned int)pvt->ambase);
843 842
844 /* Get the Branch Map regs */ 843 /* Get the Branch Map regs */
845 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, TOLM, &pvt->tolm); 844 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, TOLM, &pvt->tolm);
846 pvt->tolm >>= 12; 845 pvt->tolm >>= 12;
847 debugf2("TOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm, 846 edac_dbg(2, "TOLM (number of 256M regions) =%u (0x%x)\n",
848 pvt->tolm); 847 pvt->tolm, pvt->tolm);
849 848
850 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28)); 849 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28));
851 debugf2("Actual TOLM byte addr=%u.%03u GB (0x%x)\n", 850 edac_dbg(2, "Actual TOLM byte addr=%u.%03u GB (0x%x)\n",
852 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28); 851 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);
853 852
854 /* Get memory controller settings */ 853 /* Get memory controller settings */
855 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS, 854 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS,
@@ -858,15 +857,15 @@ static int i7300_get_mc_regs(struct mem_ctl_info *mci)
858 &pvt->mc_settings_a); 857 &pvt->mc_settings_a);
859 858
860 if (IS_SINGLE_MODE(pvt->mc_settings_a)) 859 if (IS_SINGLE_MODE(pvt->mc_settings_a))
861 debugf0("Memory controller operating on single mode\n"); 860 edac_dbg(0, "Memory controller operating on single mode\n");
862 else 861 else
863 debugf0("Memory controller operating on %s mode\n", 862 edac_dbg(0, "Memory controller operating on %smirrored mode\n",
864 IS_MIRRORED(pvt->mc_settings) ? "mirrored" : "non-mirrored"); 863 IS_MIRRORED(pvt->mc_settings) ? "" : "non-");
865 864
866 debugf0("Error detection is %s\n", 865 edac_dbg(0, "Error detection is %s\n",
867 IS_ECC_ENABLED(pvt->mc_settings) ? "enabled" : "disabled"); 866 IS_ECC_ENABLED(pvt->mc_settings) ? "enabled" : "disabled");
868 debugf0("Retry is %s\n", 867 edac_dbg(0, "Retry is %s\n",
869 IS_RETRY_ENABLED(pvt->mc_settings) ? "enabled" : "disabled"); 868 IS_RETRY_ENABLED(pvt->mc_settings) ? "enabled" : "disabled");
870 869
871 /* Get Memory Interleave Range registers */ 870 /* Get Memory Interleave Range registers */
872 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR0, 871 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR0,
@@ -960,18 +959,18 @@ static int __devinit i7300_get_devices(struct mem_ctl_info *mci)
960 } 959 }
961 } 960 }
962 961
963 debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x\n", 962 edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s %x:%x\n",
964 pci_name(pvt->pci_dev_16_0_fsb_ctlr), 963 pci_name(pvt->pci_dev_16_0_fsb_ctlr),
965 pvt->pci_dev_16_0_fsb_ctlr->vendor, 964 pvt->pci_dev_16_0_fsb_ctlr->vendor,
966 pvt->pci_dev_16_0_fsb_ctlr->device); 965 pvt->pci_dev_16_0_fsb_ctlr->device);
967 debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x\n", 966 edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
968 pci_name(pvt->pci_dev_16_1_fsb_addr_map), 967 pci_name(pvt->pci_dev_16_1_fsb_addr_map),
969 pvt->pci_dev_16_1_fsb_addr_map->vendor, 968 pvt->pci_dev_16_1_fsb_addr_map->vendor,
970 pvt->pci_dev_16_1_fsb_addr_map->device); 969 pvt->pci_dev_16_1_fsb_addr_map->device);
971 debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x\n", 970 edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s %x:%x\n",
972 pci_name(pvt->pci_dev_16_2_fsb_err_regs), 971 pci_name(pvt->pci_dev_16_2_fsb_err_regs),
973 pvt->pci_dev_16_2_fsb_err_regs->vendor, 972 pvt->pci_dev_16_2_fsb_err_regs->vendor,
974 pvt->pci_dev_16_2_fsb_err_regs->device); 973 pvt->pci_dev_16_2_fsb_err_regs->device);
975 974
976 pvt->pci_dev_2x_0_fbd_branch[0] = pci_get_device(PCI_VENDOR_ID_INTEL, 975 pvt->pci_dev_2x_0_fbd_branch[0] = pci_get_device(PCI_VENDOR_ID_INTEL,
977 PCI_DEVICE_ID_INTEL_I7300_MCH_FB0, 976 PCI_DEVICE_ID_INTEL_I7300_MCH_FB0,
@@ -1022,9 +1021,9 @@ static int __devinit i7300_init_one(struct pci_dev *pdev,
1022 if (rc == -EIO) 1021 if (rc == -EIO)
1023 return rc; 1022 return rc;
1024 1023
1025 debugf0("MC: pdev bus %u dev=0x%x fn=0x%x\n", 1024 edac_dbg(0, "MC: pdev bus %u dev=0x%x fn=0x%x\n",
1026 pdev->bus->number, 1025 pdev->bus->number,
1027 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 1026 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1028 1027
1029 /* We only are looking for func 0 of the set */ 1028 /* We only are looking for func 0 of the set */
1030 if (PCI_FUNC(pdev->devfn) != 0) 1029 if (PCI_FUNC(pdev->devfn) != 0)
@@ -1044,7 +1043,7 @@ static int __devinit i7300_init_one(struct pci_dev *pdev,
1044 if (mci == NULL) 1043 if (mci == NULL)
1045 return -ENOMEM; 1044 return -ENOMEM;
1046 1045
1047 debugf0("MC: mci = %p\n", mci); 1046 edac_dbg(0, "MC: mci = %p\n", mci);
1048 1047
1049 mci->pdev = &pdev->dev; /* record ptr to the generic device */ 1048 mci->pdev = &pdev->dev; /* record ptr to the generic device */
1050 1049
@@ -1077,18 +1076,16 @@ static int __devinit i7300_init_one(struct pci_dev *pdev,
1077 /* initialize the MC control structure 'csrows' table 1076 /* initialize the MC control structure 'csrows' table
1078 * with the mapping and control information */ 1077 * with the mapping and control information */
1079 if (i7300_get_mc_regs(mci)) { 1078 if (i7300_get_mc_regs(mci)) {
1080 debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n" 1079 edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i7300_init_csrows() returned nonzero value\n");
1081 " because i7300_init_csrows() returned nonzero "
1082 "value\n");
1083 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */ 1080 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
1084 } else { 1081 } else {
1085 debugf1("MC: Enable error reporting now\n"); 1082 edac_dbg(1, "MC: Enable error reporting now\n");
1086 i7300_enable_error_reporting(mci); 1083 i7300_enable_error_reporting(mci);
1087 } 1084 }
1088 1085
1089 /* add this new MC control structure to EDAC's list of MCs */ 1086 /* add this new MC control structure to EDAC's list of MCs */
1090 if (edac_mc_add_mc(mci)) { 1087 if (edac_mc_add_mc(mci)) {
1091 debugf0("MC: failed edac_mc_add_mc()\n"); 1088 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
1092 /* FIXME: perhaps some code should go here that disables error 1089 /* FIXME: perhaps some code should go here that disables error
1093 * reporting if we just enabled it 1090 * reporting if we just enabled it
1094 */ 1091 */
@@ -1130,7 +1127,7 @@ static void __devexit i7300_remove_one(struct pci_dev *pdev)
1130 struct mem_ctl_info *mci; 1127 struct mem_ctl_info *mci;
1131 char *tmp; 1128 char *tmp;
1132 1129
1133 debugf0("\n"); 1130 edac_dbg(0, "\n");
1134 1131
1135 if (i7300_pci) 1132 if (i7300_pci)
1136 edac_pci_release_generic_ctl(i7300_pci); 1133 edac_pci_release_generic_ctl(i7300_pci);
@@ -1177,7 +1174,7 @@ static int __init i7300_init(void)
1177{ 1174{
1178 int pci_rc; 1175 int pci_rc;
1179 1176
1180 debugf2("\n"); 1177 edac_dbg(2, "\n");
1181 1178
1182 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 1179 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1183 opstate_init(); 1180 opstate_init();
@@ -1192,7 +1189,7 @@ static int __init i7300_init(void)
1192 */ 1189 */
1193static void __exit i7300_exit(void) 1190static void __exit i7300_exit(void)
1194{ 1191{
1195 debugf2("\n"); 1192 edac_dbg(2, "\n");
1196 pci_unregister_driver(&i7300_driver); 1193 pci_unregister_driver(&i7300_driver);
1197} 1194}
1198 1195
diff --git a/drivers/edac/i7core_edac.c b/drivers/edac/i7core_edac.c
index f851a433d62..0899d7da724 100644
--- a/drivers/edac/i7core_edac.c
+++ b/drivers/edac/i7core_edac.c
@@ -516,29 +516,28 @@ static int get_dimm_config(struct mem_ctl_info *mci)
516 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod); 516 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
517 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map); 517 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
518 518
519 debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n", 519 edac_dbg(0, "QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
520 pvt->i7core_dev->socket, pvt->info.mc_control, pvt->info.mc_status, 520 pvt->i7core_dev->socket, pvt->info.mc_control,
521 pvt->info.max_dod, pvt->info.ch_map); 521 pvt->info.mc_status, pvt->info.max_dod, pvt->info.ch_map);
522 522
523 if (ECC_ENABLED(pvt)) { 523 if (ECC_ENABLED(pvt)) {
524 debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4); 524 edac_dbg(0, "ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
525 if (ECCx8(pvt)) 525 if (ECCx8(pvt))
526 mode = EDAC_S8ECD8ED; 526 mode = EDAC_S8ECD8ED;
527 else 527 else
528 mode = EDAC_S4ECD4ED; 528 mode = EDAC_S4ECD4ED;
529 } else { 529 } else {
530 debugf0("ECC disabled\n"); 530 edac_dbg(0, "ECC disabled\n");
531 mode = EDAC_NONE; 531 mode = EDAC_NONE;
532 } 532 }
533 533
534 /* FIXME: need to handle the error codes */ 534 /* FIXME: need to handle the error codes */
535 debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked " 535 edac_dbg(0, "DOD Max limits: DIMMS: %d, %d-ranked, %d-banked x%x x 0x%x\n",
536 "x%x x 0x%x\n", 536 numdimms(pvt->info.max_dod),
537 numdimms(pvt->info.max_dod), 537 numrank(pvt->info.max_dod >> 2),
538 numrank(pvt->info.max_dod >> 2), 538 numbank(pvt->info.max_dod >> 4),
539 numbank(pvt->info.max_dod >> 4), 539 numrow(pvt->info.max_dod >> 6),
540 numrow(pvt->info.max_dod >> 6), 540 numcol(pvt->info.max_dod >> 9));
541 numcol(pvt->info.max_dod >> 9));
542 541
543 for (i = 0; i < NUM_CHANS; i++) { 542 for (i = 0; i < NUM_CHANS; i++) {
544 u32 data, dimm_dod[3], value[8]; 543 u32 data, dimm_dod[3], value[8];
@@ -547,11 +546,11 @@ static int get_dimm_config(struct mem_ctl_info *mci)
547 continue; 546 continue;
548 547
549 if (!CH_ACTIVE(pvt, i)) { 548 if (!CH_ACTIVE(pvt, i)) {
550 debugf0("Channel %i is not active\n", i); 549 edac_dbg(0, "Channel %i is not active\n", i);
551 continue; 550 continue;
552 } 551 }
553 if (CH_DISABLED(pvt, i)) { 552 if (CH_DISABLED(pvt, i)) {
554 debugf0("Channel %i is disabled\n", i); 553 edac_dbg(0, "Channel %i is disabled\n", i);
555 continue; 554 continue;
556 } 555 }
557 556
@@ -582,15 +581,14 @@ static int get_dimm_config(struct mem_ctl_info *mci)
582 pci_read_config_dword(pvt->pci_ch[i][1], 581 pci_read_config_dword(pvt->pci_ch[i][1],
583 MC_DOD_CH_DIMM2, &dimm_dod[2]); 582 MC_DOD_CH_DIMM2, &dimm_dod[2]);
584 583
585 debugf0("Ch%d phy rd%d, wr%d (0x%08x): " 584 edac_dbg(0, "Ch%d phy rd%d, wr%d (0x%08x): %s%s%s%cDIMMs\n",
586 "%s%s%s%cDIMMs\n", 585 i,
587 i, 586 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
588 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i), 587 data,
589 data, 588 pvt->channel[i].is_3dimms_present ? "3DIMMS " : "",
590 pvt->channel[i].is_3dimms_present ? "3DIMMS " : "", 589 pvt->channel[i].is_3dimms_present ? "SINGLE_4R " : "",
591 pvt->channel[i].is_3dimms_present ? "SINGLE_4R " : "", 590 pvt->channel[i].has_4rank ? "HAS_4R " : "",
592 pvt->channel[i].has_4rank ? "HAS_4R " : "", 591 (data & REGISTERED_DIMM) ? 'R' : 'U');
593 (data & REGISTERED_DIMM) ? 'R' : 'U');
594 592
595 for (j = 0; j < 3; j++) { 593 for (j = 0; j < 3; j++) {
596 u32 banks, ranks, rows, cols; 594 u32 banks, ranks, rows, cols;
@@ -609,11 +607,10 @@ static int get_dimm_config(struct mem_ctl_info *mci)
609 /* DDR3 has 8 I/O banks */ 607 /* DDR3 has 8 I/O banks */
610 size = (rows * cols * banks * ranks) >> (20 - 3); 608 size = (rows * cols * banks * ranks) >> (20 - 3);
611 609
612 debugf0("\tdimm %d %d Mb offset: %x, " 610 edac_dbg(0, "\tdimm %d %d Mb offset: %x, bank: %d, rank: %d, row: %#x, col: %#x\n",
613 "bank: %d, rank: %d, row: %#x, col: %#x\n", 611 j, size,
614 j, size, 612 RANKOFFSET(dimm_dod[j]),
615 RANKOFFSET(dimm_dod[j]), 613 banks, ranks, rows, cols);
616 banks, ranks, rows, cols);
617 614
618 npages = MiB_TO_PAGES(size); 615 npages = MiB_TO_PAGES(size);
619 616
@@ -649,12 +646,12 @@ static int get_dimm_config(struct mem_ctl_info *mci)
649 pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]); 646 pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
650 pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]); 647 pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
651 pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]); 648 pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
652 debugf1("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i); 649 edac_dbg(1, "\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
653 for (j = 0; j < 8; j++) 650 for (j = 0; j < 8; j++)
654 debugf1("\t\t%#x\t%#x\t%#x\n", 651 edac_dbg(1, "\t\t%#x\t%#x\t%#x\n",
655 (value[j] >> 27) & 0x1, 652 (value[j] >> 27) & 0x1,
656 (value[j] >> 24) & 0x7, 653 (value[j] >> 24) & 0x7,
657 (value[j] & ((1 << 24) - 1))); 654 (value[j] & ((1 << 24) - 1)));
658 } 655 }
659 656
660 return 0; 657 return 0;
@@ -824,7 +821,7 @@ static ssize_t i7core_inject_store_##param( \
824 long value; \ 821 long value; \
825 int rc; \ 822 int rc; \
826 \ 823 \
827 debugf1("\n"); \ 824 edac_dbg(1, "\n"); \
828 pvt = mci->pvt_info; \ 825 pvt = mci->pvt_info; \
829 \ 826 \
830 if (pvt->inject.enable) \ 827 if (pvt->inject.enable) \
@@ -852,7 +849,7 @@ static ssize_t i7core_inject_show_##param( \
852 struct i7core_pvt *pvt; \ 849 struct i7core_pvt *pvt; \
853 \ 850 \
854 pvt = mci->pvt_info; \ 851 pvt = mci->pvt_info; \
855 debugf1("pvt=%p\n", pvt); \ 852 edac_dbg(1, "pvt=%p\n", pvt); \
856 if (pvt->inject.param < 0) \ 853 if (pvt->inject.param < 0) \
857 return sprintf(data, "any\n"); \ 854 return sprintf(data, "any\n"); \
858 else \ 855 else \
@@ -883,9 +880,9 @@ static int write_and_test(struct pci_dev *dev, const int where, const u32 val)
883 u32 read; 880 u32 read;
884 int count; 881 int count;
885 882
886 debugf0("setting pci %02x:%02x.%x reg=%02x value=%08x\n", 883 edac_dbg(0, "setting pci %02x:%02x.%x reg=%02x value=%08x\n",
887 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), 884 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
888 where, val); 885 where, val);
889 886
890 for (count = 0; count < 10; count++) { 887 for (count = 0; count < 10; count++) {
891 if (count) 888 if (count)
@@ -1020,9 +1017,8 @@ static ssize_t i7core_inject_enable_store(struct device *dev,
1020 pci_write_config_dword(pvt->pci_noncore, 1017 pci_write_config_dword(pvt->pci_noncore,
1021 MC_CFG_CONTROL, 8); 1018 MC_CFG_CONTROL, 8);
1022 1019
1023 debugf0("Error inject addr match 0x%016llx, ecc 0x%08x," 1020 edac_dbg(0, "Error inject addr match 0x%016llx, ecc 0x%08x, inject 0x%08x\n",
1024 " inject 0x%08x\n", 1021 mask, pvt->inject.eccmask, injectmask);
1025 mask, pvt->inject.eccmask, injectmask);
1026 1022
1027 1023
1028 return count; 1024 return count;
@@ -1042,7 +1038,7 @@ static ssize_t i7core_inject_enable_show(struct device *dev,
1042 pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0], 1038 pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
1043 MC_CHANNEL_ERROR_INJECT, &injectmask); 1039 MC_CHANNEL_ERROR_INJECT, &injectmask);
1044 1040
1045 debugf0("Inject error read: 0x%018x\n", injectmask); 1041 edac_dbg(0, "Inject error read: 0x%018x\n", injectmask);
1046 1042
1047 if (injectmask & 0x0c) 1043 if (injectmask & 0x0c)
1048 pvt->inject.enable = 1; 1044 pvt->inject.enable = 1;
@@ -1059,7 +1055,7 @@ static ssize_t i7core_show_counter_##param( \
1059 struct mem_ctl_info *mci = to_mci(dev); \ 1055 struct mem_ctl_info *mci = to_mci(dev); \
1060 struct i7core_pvt *pvt = mci->pvt_info; \ 1056 struct i7core_pvt *pvt = mci->pvt_info; \
1061 \ 1057 \
1062 debugf1("\n"); \ 1058 edac_dbg(1, "\n"); \
1063 if (!pvt->ce_count_available || (pvt->is_registered)) \ 1059 if (!pvt->ce_count_available || (pvt->is_registered)) \
1064 return sprintf(data, "data unavailable\n"); \ 1060 return sprintf(data, "data unavailable\n"); \
1065 return sprintf(data, "%lu\n", \ 1061 return sprintf(data, "%lu\n", \
@@ -1104,7 +1100,7 @@ static const struct attribute_group *addrmatch_groups[] = {
1104 1100
1105static void addrmatch_release(struct device *device) 1101static void addrmatch_release(struct device *device)
1106{ 1102{
1107 debugf1("Releasing device %s\n", dev_name(device)); 1103 edac_dbg(1, "Releasing device %s\n", dev_name(device));
1108 kfree(device); 1104 kfree(device);
1109} 1105}
1110 1106
@@ -1135,7 +1131,7 @@ static const struct attribute_group *all_channel_counts_groups[] = {
1135 1131
1136static void all_channel_counts_release(struct device *device) 1132static void all_channel_counts_release(struct device *device)
1137{ 1133{
1138 debugf1("Releasing device %s\n", dev_name(device)); 1134 edac_dbg(1, "Releasing device %s\n", dev_name(device));
1139 kfree(device); 1135 kfree(device);
1140} 1136}
1141 1137
@@ -1190,7 +1186,7 @@ static int i7core_create_sysfs_devices(struct mem_ctl_info *mci)
1190 dev_set_name(pvt->addrmatch_dev, "inject_addrmatch"); 1186 dev_set_name(pvt->addrmatch_dev, "inject_addrmatch");
1191 dev_set_drvdata(pvt->addrmatch_dev, mci); 1187 dev_set_drvdata(pvt->addrmatch_dev, mci);
1192 1188
1193 debugf1("creating %s\n", dev_name(pvt->addrmatch_dev)); 1189 edac_dbg(1, "creating %s\n", dev_name(pvt->addrmatch_dev));
1194 1190
1195 rc = device_add(pvt->addrmatch_dev); 1191 rc = device_add(pvt->addrmatch_dev);
1196 if (rc < 0) 1192 if (rc < 0)
@@ -1212,7 +1208,7 @@ static int i7core_create_sysfs_devices(struct mem_ctl_info *mci)
1212 dev_set_name(pvt->chancounts_dev, "all_channel_counts"); 1208 dev_set_name(pvt->chancounts_dev, "all_channel_counts");
1213 dev_set_drvdata(pvt->chancounts_dev, mci); 1209 dev_set_drvdata(pvt->chancounts_dev, mci);
1214 1210
1215 debugf1("creating %s\n", dev_name(pvt->chancounts_dev)); 1211 edac_dbg(1, "creating %s\n", dev_name(pvt->chancounts_dev));
1216 1212
1217 rc = device_add(pvt->chancounts_dev); 1213 rc = device_add(pvt->chancounts_dev);
1218 if (rc < 0) 1214 if (rc < 0)
@@ -1225,7 +1221,7 @@ static void i7core_delete_sysfs_devices(struct mem_ctl_info *mci)
1225{ 1221{
1226 struct i7core_pvt *pvt = mci->pvt_info; 1222 struct i7core_pvt *pvt = mci->pvt_info;
1227 1223
1228 debugf1("\n"); 1224 edac_dbg(1, "\n");
1229 1225
1230 device_remove_file(&mci->dev, &dev_attr_inject_section); 1226 device_remove_file(&mci->dev, &dev_attr_inject_section);
1231 device_remove_file(&mci->dev, &dev_attr_inject_type); 1227 device_remove_file(&mci->dev, &dev_attr_inject_type);
@@ -1252,14 +1248,14 @@ static void i7core_put_devices(struct i7core_dev *i7core_dev)
1252{ 1248{
1253 int i; 1249 int i;
1254 1250
1255 debugf0("\n"); 1251 edac_dbg(0, "\n");
1256 for (i = 0; i < i7core_dev->n_devs; i++) { 1252 for (i = 0; i < i7core_dev->n_devs; i++) {
1257 struct pci_dev *pdev = i7core_dev->pdev[i]; 1253 struct pci_dev *pdev = i7core_dev->pdev[i];
1258 if (!pdev) 1254 if (!pdev)
1259 continue; 1255 continue;
1260 debugf0("Removing dev %02x:%02x.%d\n", 1256 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
1261 pdev->bus->number, 1257 pdev->bus->number,
1262 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 1258 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1263 pci_dev_put(pdev); 1259 pci_dev_put(pdev);
1264 } 1260 }
1265} 1261}
@@ -1302,12 +1298,12 @@ static unsigned i7core_pci_lastbus(void)
1302 1298
1303 while ((b = pci_find_next_bus(b)) != NULL) { 1299 while ((b = pci_find_next_bus(b)) != NULL) {
1304 bus = b->number; 1300 bus = b->number;
1305 debugf0("Found bus %d\n", bus); 1301 edac_dbg(0, "Found bus %d\n", bus);
1306 if (bus > last_bus) 1302 if (bus > last_bus)
1307 last_bus = bus; 1303 last_bus = bus;
1308 } 1304 }
1309 1305
1310 debugf0("Last bus %d\n", last_bus); 1306 edac_dbg(0, "Last bus %d\n", last_bus);
1311 1307
1312 return last_bus; 1308 return last_bus;
1313} 1309}
@@ -1414,10 +1410,10 @@ static int i7core_get_onedevice(struct pci_dev **prev,
1414 return -ENODEV; 1410 return -ENODEV;
1415 } 1411 }
1416 1412
1417 debugf0("Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n", 1413 edac_dbg(0, "Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n",
1418 socket, bus, dev_descr->dev, 1414 socket, bus, dev_descr->dev,
1419 dev_descr->func, 1415 dev_descr->func,
1420 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); 1416 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1421 1417
1422 /* 1418 /*
1423 * As stated on drivers/pci/search.c, the reference count for 1419 * As stated on drivers/pci/search.c, the reference count for
@@ -1515,13 +1511,13 @@ static int mci_bind_devs(struct mem_ctl_info *mci,
1515 family = "unknown"; 1511 family = "unknown";
1516 pvt->enable_scrub = false; 1512 pvt->enable_scrub = false;
1517 } 1513 }
1518 debugf0("Detected a processor type %s\n", family); 1514 edac_dbg(0, "Detected a processor type %s\n", family);
1519 } else 1515 } else
1520 goto error; 1516 goto error;
1521 1517
1522 debugf0("Associated fn %d.%d, dev = %p, socket %d\n", 1518 edac_dbg(0, "Associated fn %d.%d, dev = %p, socket %d\n",
1523 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 1519 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1524 pdev, i7core_dev->socket); 1520 pdev, i7core_dev->socket);
1525 1521
1526 if (PCI_SLOT(pdev->devfn) == 3 && 1522 if (PCI_SLOT(pdev->devfn) == 3 &&
1527 PCI_FUNC(pdev->devfn) == 2) 1523 PCI_FUNC(pdev->devfn) == 2)
@@ -1618,8 +1614,8 @@ static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci)
1618 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5, 1614 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5,
1619 &rcv[2][1]); 1615 &rcv[2][1]);
1620 for (i = 0 ; i < 3; i++) { 1616 for (i = 0 ; i < 3; i++) {
1621 debugf3("MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n", 1617 edac_dbg(3, "MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n",
1622 (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]); 1618 (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]);
1623 /*if the channel has 3 dimms*/ 1619 /*if the channel has 3 dimms*/
1624 if (pvt->channel[i].dimms > 2) { 1620 if (pvt->channel[i].dimms > 2) {
1625 new0 = DIMM_BOT_COR_ERR(rcv[i][0]); 1621 new0 = DIMM_BOT_COR_ERR(rcv[i][0]);
@@ -1650,7 +1646,7 @@ static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci)
1650 int new0, new1, new2; 1646 int new0, new1, new2;
1651 1647
1652 if (!pvt->pci_mcr[4]) { 1648 if (!pvt->pci_mcr[4]) {
1653 debugf0("MCR registers not found\n"); 1649 edac_dbg(0, "MCR registers not found\n");
1654 return; 1650 return;
1655 } 1651 }
1656 1652
@@ -2188,7 +2184,7 @@ static void i7core_unregister_mci(struct i7core_dev *i7core_dev)
2188 struct i7core_pvt *pvt; 2184 struct i7core_pvt *pvt;
2189 2185
2190 if (unlikely(!mci || !mci->pvt_info)) { 2186 if (unlikely(!mci || !mci->pvt_info)) {
2191 debugf0("MC: dev = %p\n", &i7core_dev->pdev[0]->dev); 2187 edac_dbg(0, "MC: dev = %p\n", &i7core_dev->pdev[0]->dev);
2192 2188
2193 i7core_printk(KERN_ERR, "Couldn't find mci handler\n"); 2189 i7core_printk(KERN_ERR, "Couldn't find mci handler\n");
2194 return; 2190 return;
@@ -2196,7 +2192,7 @@ static void i7core_unregister_mci(struct i7core_dev *i7core_dev)
2196 2192
2197 pvt = mci->pvt_info; 2193 pvt = mci->pvt_info;
2198 2194
2199 debugf0("MC: mci = %p, dev = %p\n", mci, &i7core_dev->pdev[0]->dev); 2195 edac_dbg(0, "MC: mci = %p, dev = %p\n", mci, &i7core_dev->pdev[0]->dev);
2200 2196
2201 /* Disable scrubrate setting */ 2197 /* Disable scrubrate setting */
2202 if (pvt->enable_scrub) 2198 if (pvt->enable_scrub)
@@ -2211,7 +2207,7 @@ static void i7core_unregister_mci(struct i7core_dev *i7core_dev)
2211 i7core_delete_sysfs_devices(mci); 2207 i7core_delete_sysfs_devices(mci);
2212 edac_mc_del_mc(mci->pdev); 2208 edac_mc_del_mc(mci->pdev);
2213 2209
2214 debugf1("%s: free mci struct\n", mci->ctl_name); 2210 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
2215 kfree(mci->ctl_name); 2211 kfree(mci->ctl_name);
2216 edac_mc_free(mci); 2212 edac_mc_free(mci);
2217 i7core_dev->mci = NULL; 2213 i7core_dev->mci = NULL;
@@ -2237,7 +2233,7 @@ static int i7core_register_mci(struct i7core_dev *i7core_dev)
2237 if (unlikely(!mci)) 2233 if (unlikely(!mci))
2238 return -ENOMEM; 2234 return -ENOMEM;
2239 2235
2240 debugf0("MC: mci = %p, dev = %p\n", mci, &i7core_dev->pdev[0]->dev); 2236 edac_dbg(0, "MC: mci = %p, dev = %p\n", mci, &i7core_dev->pdev[0]->dev);
2241 2237
2242 pvt = mci->pvt_info; 2238 pvt = mci->pvt_info;
2243 memset(pvt, 0, sizeof(*pvt)); 2239 memset(pvt, 0, sizeof(*pvt));
@@ -2280,7 +2276,7 @@ static int i7core_register_mci(struct i7core_dev *i7core_dev)
2280 2276
2281 /* add this new MC control structure to EDAC's list of MCs */ 2277 /* add this new MC control structure to EDAC's list of MCs */
2282 if (unlikely(edac_mc_add_mc(mci))) { 2278 if (unlikely(edac_mc_add_mc(mci))) {
2283 debugf0("MC: failed edac_mc_add_mc()\n"); 2279 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
2284 /* FIXME: perhaps some code should go here that disables error 2280 /* FIXME: perhaps some code should go here that disables error
2285 * reporting if we just enabled it 2281 * reporting if we just enabled it
2286 */ 2282 */
@@ -2289,7 +2285,7 @@ static int i7core_register_mci(struct i7core_dev *i7core_dev)
2289 goto fail0; 2285 goto fail0;
2290 } 2286 }
2291 if (i7core_create_sysfs_devices(mci)) { 2287 if (i7core_create_sysfs_devices(mci)) {
2292 debugf0("MC: failed to create sysfs nodes\n"); 2288 edac_dbg(0, "MC: failed to create sysfs nodes\n");
2293 edac_mc_del_mc(mci->pdev); 2289 edac_mc_del_mc(mci->pdev);
2294 rc = -EINVAL; 2290 rc = -EINVAL;
2295 goto fail0; 2291 goto fail0;
@@ -2395,7 +2391,7 @@ static void __devexit i7core_remove(struct pci_dev *pdev)
2395{ 2391{
2396 struct i7core_dev *i7core_dev; 2392 struct i7core_dev *i7core_dev;
2397 2393
2398 debugf0("\n"); 2394 edac_dbg(0, "\n");
2399 2395
2400 /* 2396 /*
2401 * we have a trouble here: pdev value for removal will be wrong, since 2397 * we have a trouble here: pdev value for removal will be wrong, since
@@ -2444,7 +2440,7 @@ static int __init i7core_init(void)
2444{ 2440{
2445 int pci_rc; 2441 int pci_rc;
2446 2442
2447 debugf2("\n"); 2443 edac_dbg(2, "\n");
2448 2444
2449 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 2445 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
2450 opstate_init(); 2446 opstate_init();
@@ -2469,7 +2465,7 @@ static int __init i7core_init(void)
2469 */ 2465 */
2470static void __exit i7core_exit(void) 2466static void __exit i7core_exit(void)
2471{ 2467{
2472 debugf2("\n"); 2468 edac_dbg(2, "\n");
2473 pci_unregister_driver(&i7core_driver); 2469 pci_unregister_driver(&i7core_driver);
2474} 2470}
2475 2471
diff --git a/drivers/edac/i82443bxgx_edac.c b/drivers/edac/i82443bxgx_edac.c
index c43214fdf2d..475bde1c450 100644
--- a/drivers/edac/i82443bxgx_edac.c
+++ b/drivers/edac/i82443bxgx_edac.c
@@ -178,7 +178,7 @@ static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci)
178{ 178{
179 struct i82443bxgx_edacmc_error_info info; 179 struct i82443bxgx_edacmc_error_info info;
180 180
181 debugf1("MC%d\n", mci->mc_idx); 181 edac_dbg(1, "MC%d\n", mci->mc_idx);
182 i82443bxgx_edacmc_get_error_info(mci, &info); 182 i82443bxgx_edacmc_get_error_info(mci, &info);
183 i82443bxgx_edacmc_process_error_info(mci, &info, 1); 183 i82443bxgx_edacmc_process_error_info(mci, &info, 1);
184} 184}
@@ -201,14 +201,13 @@ static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
201 dimm = csrow->channels[0]->dimm; 201 dimm = csrow->channels[0]->dimm;
202 202
203 pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar); 203 pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar);
204 debugf1("MC%d: Row=%d DRB = %#0x\n", 204 edac_dbg(1, "MC%d: Row=%d DRB = %#0x\n",
205 mci->mc_idx,index, drbar); 205 mci->mc_idx, index, drbar);
206 row_high_limit = ((u32) drbar << 23); 206 row_high_limit = ((u32) drbar << 23);
207 /* find the DRAM Chip Select Base address and mask */ 207 /* find the DRAM Chip Select Base address and mask */
208 debugf1("MC%d: Row=%d, " 208 edac_dbg(1, "MC%d: Row=%d, Boundary Address=%#0x, Last = %#0x\n",
209 "Boundary Address=%#0x, Last = %#0x\n", 209 mci->mc_idx, index, row_high_limit,
210 mci->mc_idx, index, row_high_limit, 210 row_high_limit_last);
211 row_high_limit_last);
212 211
213 /* 440GX goes to 2GB, represented with a DRB of 0. */ 212 /* 440GX goes to 2GB, represented with a DRB of 0. */
214 if (row_high_limit_last && !row_high_limit) 213 if (row_high_limit_last && !row_high_limit)
@@ -241,7 +240,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
241 enum mem_type mtype; 240 enum mem_type mtype;
242 enum edac_type edac_mode; 241 enum edac_type edac_mode;
243 242
244 debugf0("MC: %s()\n", __FILE__); 243 edac_dbg(0, "MC:\n");
245 244
246 /* Something is really hosed if PCI config space reads from 245 /* Something is really hosed if PCI config space reads from
247 * the MC aren't working. 246 * the MC aren't working.
@@ -259,7 +258,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
259 if (mci == NULL) 258 if (mci == NULL)
260 return -ENOMEM; 259 return -ENOMEM;
261 260
262 debugf0("MC: %s(): mci = %p\n", __FILE__, mci); 261 edac_dbg(0, "MC: mci = %p\n", mci);
263 mci->pdev = &pdev->dev; 262 mci->pdev = &pdev->dev;
264 mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR; 263 mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR;
265 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; 264 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
@@ -275,8 +274,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
275 mtype = MEM_RDR; 274 mtype = MEM_RDR;
276 break; 275 break;
277 default: 276 default:
278 debugf0("Unknown/reserved DRAM type value " 277 edac_dbg(0, "Unknown/reserved DRAM type value in DRAMC register!\n");
279 "in DRAMC register!\n");
280 mtype = -MEM_UNKNOWN; 278 mtype = -MEM_UNKNOWN;
281 } 279 }
282 280
@@ -305,8 +303,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
305 edac_mode = EDAC_SECDED; 303 edac_mode = EDAC_SECDED;
306 break; 304 break;
307 default: 305 default:
308 debugf0("Unknown/reserved ECC state " 306 edac_dbg(0, "Unknown/reserved ECC state in NBXCFG register!\n");
309 "in NBXCFG register!\n");
310 edac_mode = EDAC_UNKNOWN; 307 edac_mode = EDAC_UNKNOWN;
311 break; 308 break;
312 } 309 }
@@ -330,7 +327,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
330 mci->ctl_page_to_phys = NULL; 327 mci->ctl_page_to_phys = NULL;
331 328
332 if (edac_mc_add_mc(mci)) { 329 if (edac_mc_add_mc(mci)) {
333 debugf3("failed edac_mc_add_mc()\n"); 330 edac_dbg(3, "failed edac_mc_add_mc()\n");
334 goto fail; 331 goto fail;
335 } 332 }
336 333
@@ -345,7 +342,7 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
345 __func__); 342 __func__);
346 } 343 }
347 344
348 debugf3("MC: %s(): success\n", __FILE__); 345 edac_dbg(3, "MC: success\n");
349 return 0; 346 return 0;
350 347
351fail: 348fail:
@@ -361,7 +358,7 @@ static int __devinit i82443bxgx_edacmc_init_one(struct pci_dev *pdev,
361{ 358{
362 int rc; 359 int rc;
363 360
364 debugf0("MC: %s()\n", __FILE__); 361 edac_dbg(0, "MC:\n");
365 362
366 /* don't need to call pci_enable_device() */ 363 /* don't need to call pci_enable_device() */
367 rc = i82443bxgx_edacmc_probe1(pdev, ent->driver_data); 364 rc = i82443bxgx_edacmc_probe1(pdev, ent->driver_data);
@@ -376,7 +373,7 @@ static void __devexit i82443bxgx_edacmc_remove_one(struct pci_dev *pdev)
376{ 373{
377 struct mem_ctl_info *mci; 374 struct mem_ctl_info *mci;
378 375
379 debugf0("%s()\n", __FILE__); 376 edac_dbg(0, "\n");
380 377
381 if (i82443bxgx_pci) 378 if (i82443bxgx_pci)
382 edac_pci_release_generic_ctl(i82443bxgx_pci); 379 edac_pci_release_generic_ctl(i82443bxgx_pci);
@@ -428,7 +425,7 @@ static int __init i82443bxgx_edacmc_init(void)
428 id = &i82443bxgx_pci_tbl[i]; 425 id = &i82443bxgx_pci_tbl[i];
429 } 426 }
430 if (!mci_pdev) { 427 if (!mci_pdev) {
431 debugf0("i82443bxgx pci_get_device fail\n"); 428 edac_dbg(0, "i82443bxgx pci_get_device fail\n");
432 pci_rc = -ENODEV; 429 pci_rc = -ENODEV;
433 goto fail1; 430 goto fail1;
434 } 431 }
@@ -436,7 +433,7 @@ static int __init i82443bxgx_edacmc_init(void)
436 pci_rc = i82443bxgx_edacmc_init_one(mci_pdev, i82443bxgx_pci_tbl); 433 pci_rc = i82443bxgx_edacmc_init_one(mci_pdev, i82443bxgx_pci_tbl);
437 434
438 if (pci_rc < 0) { 435 if (pci_rc < 0) {
439 debugf0("i82443bxgx init fail\n"); 436 edac_dbg(0, "i82443bxgx init fail\n");
440 pci_rc = -ENODEV; 437 pci_rc = -ENODEV;
441 goto fail1; 438 goto fail1;
442 } 439 }
diff --git a/drivers/edac/i82860_edac.c b/drivers/edac/i82860_edac.c
index d4ec21db22b..832e7dd2c5f 100644
--- a/drivers/edac/i82860_edac.c
+++ b/drivers/edac/i82860_edac.c
@@ -136,7 +136,7 @@ static void i82860_check(struct mem_ctl_info *mci)
136{ 136{
137 struct i82860_error_info info; 137 struct i82860_error_info info;
138 138
139 debugf1("MC%d\n", mci->mc_idx); 139 edac_dbg(1, "MC%d\n", mci->mc_idx);
140 i82860_get_error_info(mci, &info); 140 i82860_get_error_info(mci, &info);
141 i82860_process_error_info(mci, &info, 1); 141 i82860_process_error_info(mci, &info, 1);
142} 142}
@@ -167,8 +167,7 @@ static void i82860_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev)
167 pci_read_config_word(pdev, I82860_GBA + index * 2, &value); 167 pci_read_config_word(pdev, I82860_GBA + index * 2, &value);
168 cumul_size = (value & I82860_GBA_MASK) << 168 cumul_size = (value & I82860_GBA_MASK) <<
169 (I82860_GBA_SHIFT - PAGE_SHIFT); 169 (I82860_GBA_SHIFT - PAGE_SHIFT);
170 debugf3("(%d) cumul_size 0x%x\n", index, 170 edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
171 cumul_size);
172 171
173 if (cumul_size == last_cumul_size) 172 if (cumul_size == last_cumul_size)
174 continue; /* not populated */ 173 continue; /* not populated */
@@ -210,7 +209,7 @@ static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
210 if (!mci) 209 if (!mci)
211 return -ENOMEM; 210 return -ENOMEM;
212 211
213 debugf3("init mci\n"); 212 edac_dbg(3, "init mci\n");
214 mci->pdev = &pdev->dev; 213 mci->pdev = &pdev->dev;
215 mci->mtype_cap = MEM_FLAG_DDR; 214 mci->mtype_cap = MEM_FLAG_DDR;
216 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; 215 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
@@ -229,7 +228,7 @@ static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
229 * type of memory controller. The ID is therefore hardcoded to 0. 228 * type of memory controller. The ID is therefore hardcoded to 0.
230 */ 229 */
231 if (edac_mc_add_mc(mci)) { 230 if (edac_mc_add_mc(mci)) {
232 debugf3("failed edac_mc_add_mc()\n"); 231 edac_dbg(3, "failed edac_mc_add_mc()\n");
233 goto fail; 232 goto fail;
234 } 233 }
235 234
@@ -245,7 +244,7 @@ static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
245 } 244 }
246 245
247 /* get this far and it's successful */ 246 /* get this far and it's successful */
248 debugf3("success\n"); 247 edac_dbg(3, "success\n");
249 248
250 return 0; 249 return 0;
251 250
@@ -260,7 +259,7 @@ static int __devinit i82860_init_one(struct pci_dev *pdev,
260{ 259{
261 int rc; 260 int rc;
262 261
263 debugf0("\n"); 262 edac_dbg(0, "\n");
264 i82860_printk(KERN_INFO, "i82860 init one\n"); 263 i82860_printk(KERN_INFO, "i82860 init one\n");
265 264
266 if (pci_enable_device(pdev) < 0) 265 if (pci_enable_device(pdev) < 0)
@@ -278,7 +277,7 @@ static void __devexit i82860_remove_one(struct pci_dev *pdev)
278{ 277{
279 struct mem_ctl_info *mci; 278 struct mem_ctl_info *mci;
280 279
281 debugf0("\n"); 280 edac_dbg(0, "\n");
282 281
283 if (i82860_pci) 282 if (i82860_pci)
284 edac_pci_release_generic_ctl(i82860_pci); 283 edac_pci_release_generic_ctl(i82860_pci);
@@ -311,7 +310,7 @@ static int __init i82860_init(void)
311{ 310{
312 int pci_rc; 311 int pci_rc;
313 312
314 debugf3("\n"); 313 edac_dbg(3, "\n");
315 314
316 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 315 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
317 opstate_init(); 316 opstate_init();
@@ -324,7 +323,7 @@ static int __init i82860_init(void)
324 PCI_DEVICE_ID_INTEL_82860_0, NULL); 323 PCI_DEVICE_ID_INTEL_82860_0, NULL);
325 324
326 if (mci_pdev == NULL) { 325 if (mci_pdev == NULL) {
327 debugf0("860 pci_get_device fail\n"); 326 edac_dbg(0, "860 pci_get_device fail\n");
328 pci_rc = -ENODEV; 327 pci_rc = -ENODEV;
329 goto fail1; 328 goto fail1;
330 } 329 }
@@ -332,7 +331,7 @@ static int __init i82860_init(void)
332 pci_rc = i82860_init_one(mci_pdev, i82860_pci_tbl); 331 pci_rc = i82860_init_one(mci_pdev, i82860_pci_tbl);
333 332
334 if (pci_rc < 0) { 333 if (pci_rc < 0) {
335 debugf0("860 init fail\n"); 334 edac_dbg(0, "860 init fail\n");
336 pci_rc = -ENODEV; 335 pci_rc = -ENODEV;
337 goto fail1; 336 goto fail1;
338 } 337 }
@@ -352,7 +351,7 @@ fail0:
352 351
353static void __exit i82860_exit(void) 352static void __exit i82860_exit(void)
354{ 353{
355 debugf3("\n"); 354 edac_dbg(3, "\n");
356 355
357 pci_unregister_driver(&i82860_driver); 356 pci_unregister_driver(&i82860_driver);
358 357
diff --git a/drivers/edac/i82875p_edac.c b/drivers/edac/i82875p_edac.c
index 4ded498047f..db64bd74bc5 100644
--- a/drivers/edac/i82875p_edac.c
+++ b/drivers/edac/i82875p_edac.c
@@ -263,7 +263,7 @@ static void i82875p_check(struct mem_ctl_info *mci)
263{ 263{
264 struct i82875p_error_info info; 264 struct i82875p_error_info info;
265 265
266 debugf1("MC%d\n", mci->mc_idx); 266 edac_dbg(1, "MC%d\n", mci->mc_idx);
267 i82875p_get_error_info(mci, &info); 267 i82875p_get_error_info(mci, &info);
268 i82875p_process_error_info(mci, &info, 1); 268 i82875p_process_error_info(mci, &info, 1);
269} 269}
@@ -371,8 +371,7 @@ static void i82875p_init_csrows(struct mem_ctl_info *mci,
371 371
372 value = readb(ovrfl_window + I82875P_DRB + index); 372 value = readb(ovrfl_window + I82875P_DRB + index);
373 cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT); 373 cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT);
374 debugf3("(%d) cumul_size 0x%x\n", index, 374 edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
375 cumul_size);
376 if (cumul_size == last_cumul_size) 375 if (cumul_size == last_cumul_size)
377 continue; /* not populated */ 376 continue; /* not populated */
378 377
@@ -405,7 +404,7 @@ static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
405 u32 nr_chans; 404 u32 nr_chans;
406 struct i82875p_error_info discard; 405 struct i82875p_error_info discard;
407 406
408 debugf0("\n"); 407 edac_dbg(0, "\n");
409 408
410 ovrfl_pdev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL); 409 ovrfl_pdev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
411 410
@@ -426,7 +425,7 @@ static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
426 goto fail0; 425 goto fail0;
427 } 426 }
428 427
429 debugf3("init mci\n"); 428 edac_dbg(3, "init mci\n");
430 mci->pdev = &pdev->dev; 429 mci->pdev = &pdev->dev;
431 mci->mtype_cap = MEM_FLAG_DDR; 430 mci->mtype_cap = MEM_FLAG_DDR;
432 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; 431 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
@@ -437,7 +436,7 @@ static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
437 mci->dev_name = pci_name(pdev); 436 mci->dev_name = pci_name(pdev);
438 mci->edac_check = i82875p_check; 437 mci->edac_check = i82875p_check;
439 mci->ctl_page_to_phys = NULL; 438 mci->ctl_page_to_phys = NULL;
440 debugf3("init pvt\n"); 439 edac_dbg(3, "init pvt\n");
441 pvt = (struct i82875p_pvt *)mci->pvt_info; 440 pvt = (struct i82875p_pvt *)mci->pvt_info;
442 pvt->ovrfl_pdev = ovrfl_pdev; 441 pvt->ovrfl_pdev = ovrfl_pdev;
443 pvt->ovrfl_window = ovrfl_window; 442 pvt->ovrfl_window = ovrfl_window;
@@ -448,7 +447,7 @@ static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
448 * type of memory controller. The ID is therefore hardcoded to 0. 447 * type of memory controller. The ID is therefore hardcoded to 0.
449 */ 448 */
450 if (edac_mc_add_mc(mci)) { 449 if (edac_mc_add_mc(mci)) {
451 debugf3("failed edac_mc_add_mc()\n"); 450 edac_dbg(3, "failed edac_mc_add_mc()\n");
452 goto fail1; 451 goto fail1;
453 } 452 }
454 453
@@ -464,7 +463,7 @@ static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
464 } 463 }
465 464
466 /* get this far and it's successful */ 465 /* get this far and it's successful */
467 debugf3("success\n"); 466 edac_dbg(3, "success\n");
468 return 0; 467 return 0;
469 468
470fail1: 469fail1:
@@ -485,7 +484,7 @@ static int __devinit i82875p_init_one(struct pci_dev *pdev,
485{ 484{
486 int rc; 485 int rc;
487 486
488 debugf0("\n"); 487 edac_dbg(0, "\n");
489 i82875p_printk(KERN_INFO, "i82875p init one\n"); 488 i82875p_printk(KERN_INFO, "i82875p init one\n");
490 489
491 if (pci_enable_device(pdev) < 0) 490 if (pci_enable_device(pdev) < 0)
@@ -504,7 +503,7 @@ static void __devexit i82875p_remove_one(struct pci_dev *pdev)
504 struct mem_ctl_info *mci; 503 struct mem_ctl_info *mci;
505 struct i82875p_pvt *pvt = NULL; 504 struct i82875p_pvt *pvt = NULL;
506 505
507 debugf0("\n"); 506 edac_dbg(0, "\n");
508 507
509 if (i82875p_pci) 508 if (i82875p_pci)
510 edac_pci_release_generic_ctl(i82875p_pci); 509 edac_pci_release_generic_ctl(i82875p_pci);
@@ -550,7 +549,7 @@ static int __init i82875p_init(void)
550{ 549{
551 int pci_rc; 550 int pci_rc;
552 551
553 debugf3("\n"); 552 edac_dbg(3, "\n");
554 553
555 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 554 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
556 opstate_init(); 555 opstate_init();
@@ -565,7 +564,7 @@ static int __init i82875p_init(void)
565 PCI_DEVICE_ID_INTEL_82875_0, NULL); 564 PCI_DEVICE_ID_INTEL_82875_0, NULL);
566 565
567 if (!mci_pdev) { 566 if (!mci_pdev) {
568 debugf0("875p pci_get_device fail\n"); 567 edac_dbg(0, "875p pci_get_device fail\n");
569 pci_rc = -ENODEV; 568 pci_rc = -ENODEV;
570 goto fail1; 569 goto fail1;
571 } 570 }
@@ -573,7 +572,7 @@ static int __init i82875p_init(void)
573 pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl); 572 pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl);
574 573
575 if (pci_rc < 0) { 574 if (pci_rc < 0) {
576 debugf0("875p init fail\n"); 575 edac_dbg(0, "875p init fail\n");
577 pci_rc = -ENODEV; 576 pci_rc = -ENODEV;
578 goto fail1; 577 goto fail1;
579 } 578 }
@@ -593,7 +592,7 @@ fail0:
593 592
594static void __exit i82875p_exit(void) 593static void __exit i82875p_exit(void)
595{ 594{
596 debugf3("\n"); 595 edac_dbg(3, "\n");
597 596
598 i82875p_remove_one(mci_pdev); 597 i82875p_remove_one(mci_pdev);
599 pci_dev_put(mci_pdev); 598 pci_dev_put(mci_pdev);
diff --git a/drivers/edac/i82975x_edac.c b/drivers/edac/i82975x_edac.c
index 91b9e33fff2..974d1a2be37 100644
--- a/drivers/edac/i82975x_edac.c
+++ b/drivers/edac/i82975x_edac.c
@@ -331,7 +331,7 @@ static void i82975x_check(struct mem_ctl_info *mci)
331{ 331{
332 struct i82975x_error_info info; 332 struct i82975x_error_info info;
333 333
334 debugf1("MC%d\n", mci->mc_idx); 334 edac_dbg(1, "MC%d\n", mci->mc_idx);
335 i82975x_get_error_info(mci, &info); 335 i82975x_get_error_info(mci, &info);
336 i82975x_process_error_info(mci, &info, 1); 336 i82975x_process_error_info(mci, &info, 1);
337} 337}
@@ -406,8 +406,7 @@ static void i82975x_init_csrows(struct mem_ctl_info *mci,
406 */ 406 */
407 if (csrow->nr_channels > 1) 407 if (csrow->nr_channels > 1)
408 cumul_size <<= 1; 408 cumul_size <<= 1;
409 debugf3("(%d) cumul_size 0x%x\n", index, 409 edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
410 cumul_size);
411 410
412 nr_pages = cumul_size - last_cumul_size; 411 nr_pages = cumul_size - last_cumul_size;
413 if (!nr_pages) 412 if (!nr_pages)
@@ -489,11 +488,11 @@ static int i82975x_probe1(struct pci_dev *pdev, int dev_idx)
489 u8 c1drb[4]; 488 u8 c1drb[4];
490#endif 489#endif
491 490
492 debugf0("\n"); 491 edac_dbg(0, "\n");
493 492
494 pci_read_config_dword(pdev, I82975X_MCHBAR, &mchbar); 493 pci_read_config_dword(pdev, I82975X_MCHBAR, &mchbar);
495 if (!(mchbar & 1)) { 494 if (!(mchbar & 1)) {
496 debugf3("failed, MCHBAR disabled!\n"); 495 edac_dbg(3, "failed, MCHBAR disabled!\n");
497 goto fail0; 496 goto fail0;
498 } 497 }
499 mchbar &= 0xffffc000; /* bits 31:14 used for 16K window */ 498 mchbar &= 0xffffc000; /* bits 31:14 used for 16K window */
@@ -558,7 +557,7 @@ static int i82975x_probe1(struct pci_dev *pdev, int dev_idx)
558 goto fail1; 557 goto fail1;
559 } 558 }
560 559
561 debugf3("init mci\n"); 560 edac_dbg(3, "init mci\n");
562 mci->pdev = &pdev->dev; 561 mci->pdev = &pdev->dev;
563 mci->mtype_cap = MEM_FLAG_DDR2; 562 mci->mtype_cap = MEM_FLAG_DDR2;
564 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; 563 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
@@ -569,7 +568,7 @@ static int i82975x_probe1(struct pci_dev *pdev, int dev_idx)
569 mci->dev_name = pci_name(pdev); 568 mci->dev_name = pci_name(pdev);
570 mci->edac_check = i82975x_check; 569 mci->edac_check = i82975x_check;
571 mci->ctl_page_to_phys = NULL; 570 mci->ctl_page_to_phys = NULL;
572 debugf3("init pvt\n"); 571 edac_dbg(3, "init pvt\n");
573 pvt = (struct i82975x_pvt *) mci->pvt_info; 572 pvt = (struct i82975x_pvt *) mci->pvt_info;
574 pvt->mch_window = mch_window; 573 pvt->mch_window = mch_window;
575 i82975x_init_csrows(mci, pdev, mch_window); 574 i82975x_init_csrows(mci, pdev, mch_window);
@@ -578,12 +577,12 @@ static int i82975x_probe1(struct pci_dev *pdev, int dev_idx)
578 577
579 /* finalize this instance of memory controller with edac core */ 578 /* finalize this instance of memory controller with edac core */
580 if (edac_mc_add_mc(mci)) { 579 if (edac_mc_add_mc(mci)) {
581 debugf3("failed edac_mc_add_mc()\n"); 580 edac_dbg(3, "failed edac_mc_add_mc()\n");
582 goto fail2; 581 goto fail2;
583 } 582 }
584 583
585 /* get this far and it's successful */ 584 /* get this far and it's successful */
586 debugf3("success\n"); 585 edac_dbg(3, "success\n");
587 return 0; 586 return 0;
588 587
589fail2: 588fail2:
@@ -601,7 +600,7 @@ static int __devinit i82975x_init_one(struct pci_dev *pdev,
601{ 600{
602 int rc; 601 int rc;
603 602
604 debugf0("\n"); 603 edac_dbg(0, "\n");
605 604
606 if (pci_enable_device(pdev) < 0) 605 if (pci_enable_device(pdev) < 0)
607 return -EIO; 606 return -EIO;
@@ -619,7 +618,7 @@ static void __devexit i82975x_remove_one(struct pci_dev *pdev)
619 struct mem_ctl_info *mci; 618 struct mem_ctl_info *mci;
620 struct i82975x_pvt *pvt; 619 struct i82975x_pvt *pvt;
621 620
622 debugf0("\n"); 621 edac_dbg(0, "\n");
623 622
624 mci = edac_mc_del_mc(&pdev->dev); 623 mci = edac_mc_del_mc(&pdev->dev);
625 if (mci == NULL) 624 if (mci == NULL)
@@ -655,7 +654,7 @@ static int __init i82975x_init(void)
655{ 654{
656 int pci_rc; 655 int pci_rc;
657 656
658 debugf3("\n"); 657 edac_dbg(3, "\n");
659 658
660 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 659 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
661 opstate_init(); 660 opstate_init();
@@ -669,7 +668,7 @@ static int __init i82975x_init(void)
669 PCI_DEVICE_ID_INTEL_82975_0, NULL); 668 PCI_DEVICE_ID_INTEL_82975_0, NULL);
670 669
671 if (!mci_pdev) { 670 if (!mci_pdev) {
672 debugf0("i82975x pci_get_device fail\n"); 671 edac_dbg(0, "i82975x pci_get_device fail\n");
673 pci_rc = -ENODEV; 672 pci_rc = -ENODEV;
674 goto fail1; 673 goto fail1;
675 } 674 }
@@ -677,7 +676,7 @@ static int __init i82975x_init(void)
677 pci_rc = i82975x_init_one(mci_pdev, i82975x_pci_tbl); 676 pci_rc = i82975x_init_one(mci_pdev, i82975x_pci_tbl);
678 677
679 if (pci_rc < 0) { 678 if (pci_rc < 0) {
680 debugf0("i82975x init fail\n"); 679 edac_dbg(0, "i82975x init fail\n");
681 pci_rc = -ENODEV; 680 pci_rc = -ENODEV;
682 goto fail1; 681 goto fail1;
683 } 682 }
@@ -697,7 +696,7 @@ fail0:
697 696
698static void __exit i82975x_exit(void) 697static void __exit i82975x_exit(void)
699{ 698{
700 debugf3("\n"); 699 edac_dbg(3, "\n");
701 700
702 pci_unregister_driver(&i82975x_driver); 701 pci_unregister_driver(&i82975x_driver);
703 702
diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
index e01c678cb6a..64b47654324 100644
--- a/drivers/edac/mpc85xx_edac.c
+++ b/drivers/edac/mpc85xx_edac.c
@@ -280,7 +280,7 @@ static int __devinit mpc85xx_pci_err_probe(struct platform_device *op)
280 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0); 280 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0);
281 281
282 if (edac_pci_add_device(pci, pdata->edac_idx) > 0) { 282 if (edac_pci_add_device(pci, pdata->edac_idx) > 0) {
283 debugf3("failed edac_pci_add_device()\n"); 283 edac_dbg(3, "failed edac_pci_add_device()\n");
284 goto err; 284 goto err;
285 } 285 }
286 286
@@ -303,7 +303,7 @@ static int __devinit mpc85xx_pci_err_probe(struct platform_device *op)
303 } 303 }
304 304
305 devres_remove_group(&op->dev, mpc85xx_pci_err_probe); 305 devres_remove_group(&op->dev, mpc85xx_pci_err_probe);
306 debugf3("success\n"); 306 edac_dbg(3, "success\n");
307 printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n"); 307 printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n");
308 308
309 return 0; 309 return 0;
@@ -321,7 +321,7 @@ static int mpc85xx_pci_err_remove(struct platform_device *op)
321 struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev); 321 struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev);
322 struct mpc85xx_pci_pdata *pdata = pci->pvt_info; 322 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
323 323
324 debugf0("\n"); 324 edac_dbg(0, "\n");
325 325
326 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 326 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR,
327 orig_pci_err_cap_dr); 327 orig_pci_err_cap_dr);
@@ -582,7 +582,7 @@ static int __devinit mpc85xx_l2_err_probe(struct platform_device *op)
582 pdata->edac_idx = edac_dev_idx++; 582 pdata->edac_idx = edac_dev_idx++;
583 583
584 if (edac_device_add_device(edac_dev) > 0) { 584 if (edac_device_add_device(edac_dev) > 0) {
585 debugf3("failed edac_device_add_device()\n"); 585 edac_dbg(3, "failed edac_device_add_device()\n");
586 goto err; 586 goto err;
587 } 587 }
588 588
@@ -610,7 +610,7 @@ static int __devinit mpc85xx_l2_err_probe(struct platform_device *op)
610 610
611 devres_remove_group(&op->dev, mpc85xx_l2_err_probe); 611 devres_remove_group(&op->dev, mpc85xx_l2_err_probe);
612 612
613 debugf3("success\n"); 613 edac_dbg(3, "success\n");
614 printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n"); 614 printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n");
615 615
616 return 0; 616 return 0;
@@ -628,7 +628,7 @@ static int mpc85xx_l2_err_remove(struct platform_device *op)
628 struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev); 628 struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev);
629 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 629 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
630 630
631 debugf0("\n"); 631 edac_dbg(0, "\n");
632 632
633 if (edac_op_state == EDAC_OPSTATE_INT) { 633 if (edac_op_state == EDAC_OPSTATE_INT) {
634 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0); 634 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0);
@@ -1037,7 +1037,7 @@ static int __devinit mpc85xx_mc_err_probe(struct platform_device *op)
1037 goto err; 1037 goto err;
1038 } 1038 }
1039 1039
1040 debugf3("init mci\n"); 1040 edac_dbg(3, "init mci\n");
1041 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 | 1041 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 |
1042 MEM_FLAG_DDR | MEM_FLAG_DDR2; 1042 MEM_FLAG_DDR | MEM_FLAG_DDR2;
1043 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; 1043 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
@@ -1063,13 +1063,13 @@ static int __devinit mpc85xx_mc_err_probe(struct platform_device *op)
1063 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0); 1063 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0);
1064 1064
1065 if (edac_mc_add_mc(mci)) { 1065 if (edac_mc_add_mc(mci)) {
1066 debugf3("failed edac_mc_add_mc()\n"); 1066 edac_dbg(3, "failed edac_mc_add_mc()\n");
1067 goto err; 1067 goto err;
1068 } 1068 }
1069 1069
1070 if (mpc85xx_create_sysfs_attributes(mci)) { 1070 if (mpc85xx_create_sysfs_attributes(mci)) {
1071 edac_mc_del_mc(mci->pdev); 1071 edac_mc_del_mc(mci->pdev);
1072 debugf3("failed edac_mc_add_mc()\n"); 1072 edac_dbg(3, "failed edac_mc_add_mc()\n");
1073 goto err; 1073 goto err;
1074 } 1074 }
1075 1075
@@ -1103,7 +1103,7 @@ static int __devinit mpc85xx_mc_err_probe(struct platform_device *op)
1103 } 1103 }
1104 1104
1105 devres_remove_group(&op->dev, mpc85xx_mc_err_probe); 1105 devres_remove_group(&op->dev, mpc85xx_mc_err_probe);
1106 debugf3("success\n"); 1106 edac_dbg(3, "success\n");
1107 printk(KERN_INFO EDAC_MOD_STR " MC err registered\n"); 1107 printk(KERN_INFO EDAC_MOD_STR " MC err registered\n");
1108 1108
1109 return 0; 1109 return 0;
@@ -1121,7 +1121,7 @@ static int mpc85xx_mc_err_remove(struct platform_device *op)
1121 struct mem_ctl_info *mci = dev_get_drvdata(&op->dev); 1121 struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
1122 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 1122 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
1123 1123
1124 debugf0("\n"); 1124 edac_dbg(0, "\n");
1125 1125
1126 if (edac_op_state == EDAC_OPSTATE_INT) { 1126 if (edac_op_state == EDAC_OPSTATE_INT) {
1127 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0); 1127 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0);
diff --git a/drivers/edac/mv64x60_edac.c b/drivers/edac/mv64x60_edac.c
index 25851ef56b5..f54b3cb0a13 100644
--- a/drivers/edac/mv64x60_edac.c
+++ b/drivers/edac/mv64x60_edac.c
@@ -169,7 +169,7 @@ static int __devinit mv64x60_pci_err_probe(struct platform_device *pdev)
169 MV64X60_PCIx_ERR_MASK_VAL); 169 MV64X60_PCIx_ERR_MASK_VAL);
170 170
171 if (edac_pci_add_device(pci, pdata->edac_idx) > 0) { 171 if (edac_pci_add_device(pci, pdata->edac_idx) > 0) {
172 debugf3("failed edac_pci_add_device()\n"); 172 edac_dbg(3, "failed edac_pci_add_device()\n");
173 goto err; 173 goto err;
174 } 174 }
175 175
@@ -194,7 +194,7 @@ static int __devinit mv64x60_pci_err_probe(struct platform_device *pdev)
194 devres_remove_group(&pdev->dev, mv64x60_pci_err_probe); 194 devres_remove_group(&pdev->dev, mv64x60_pci_err_probe);
195 195
196 /* get this far and it's successful */ 196 /* get this far and it's successful */
197 debugf3("success\n"); 197 edac_dbg(3, "success\n");
198 198
199 return 0; 199 return 0;
200 200
@@ -210,7 +210,7 @@ static int mv64x60_pci_err_remove(struct platform_device *pdev)
210{ 210{
211 struct edac_pci_ctl_info *pci = platform_get_drvdata(pdev); 211 struct edac_pci_ctl_info *pci = platform_get_drvdata(pdev);
212 212
213 debugf0("\n"); 213 edac_dbg(0, "\n");
214 214
215 edac_pci_del_device(&pdev->dev); 215 edac_pci_del_device(&pdev->dev);
216 216
@@ -336,7 +336,7 @@ static int __devinit mv64x60_sram_err_probe(struct platform_device *pdev)
336 pdata->edac_idx = edac_dev_idx++; 336 pdata->edac_idx = edac_dev_idx++;
337 337
338 if (edac_device_add_device(edac_dev) > 0) { 338 if (edac_device_add_device(edac_dev) > 0) {
339 debugf3("failed edac_device_add_device()\n"); 339 edac_dbg(3, "failed edac_device_add_device()\n");
340 goto err; 340 goto err;
341 } 341 }
342 342
@@ -363,7 +363,7 @@ static int __devinit mv64x60_sram_err_probe(struct platform_device *pdev)
363 devres_remove_group(&pdev->dev, mv64x60_sram_err_probe); 363 devres_remove_group(&pdev->dev, mv64x60_sram_err_probe);
364 364
365 /* get this far and it's successful */ 365 /* get this far and it's successful */
366 debugf3("success\n"); 366 edac_dbg(3, "success\n");
367 367
368 return 0; 368 return 0;
369 369
@@ -379,7 +379,7 @@ static int mv64x60_sram_err_remove(struct platform_device *pdev)
379{ 379{
380 struct edac_device_ctl_info *edac_dev = platform_get_drvdata(pdev); 380 struct edac_device_ctl_info *edac_dev = platform_get_drvdata(pdev);
381 381
382 debugf0("\n"); 382 edac_dbg(0, "\n");
383 383
384 edac_device_del_device(&pdev->dev); 384 edac_device_del_device(&pdev->dev);
385 edac_device_free_ctl_info(edac_dev); 385 edac_device_free_ctl_info(edac_dev);
@@ -531,7 +531,7 @@ static int __devinit mv64x60_cpu_err_probe(struct platform_device *pdev)
531 pdata->edac_idx = edac_dev_idx++; 531 pdata->edac_idx = edac_dev_idx++;
532 532
533 if (edac_device_add_device(edac_dev) > 0) { 533 if (edac_device_add_device(edac_dev) > 0) {
534 debugf3("failed edac_device_add_device()\n"); 534 edac_dbg(3, "failed edac_device_add_device()\n");
535 goto err; 535 goto err;
536 } 536 }
537 537
@@ -558,7 +558,7 @@ static int __devinit mv64x60_cpu_err_probe(struct platform_device *pdev)
558 devres_remove_group(&pdev->dev, mv64x60_cpu_err_probe); 558 devres_remove_group(&pdev->dev, mv64x60_cpu_err_probe);
559 559
560 /* get this far and it's successful */ 560 /* get this far and it's successful */
561 debugf3("success\n"); 561 edac_dbg(3, "success\n");
562 562
563 return 0; 563 return 0;
564 564
@@ -574,7 +574,7 @@ static int mv64x60_cpu_err_remove(struct platform_device *pdev)
574{ 574{
575 struct edac_device_ctl_info *edac_dev = platform_get_drvdata(pdev); 575 struct edac_device_ctl_info *edac_dev = platform_get_drvdata(pdev);
576 576
577 debugf0("\n"); 577 edac_dbg(0, "\n");
578 578
579 edac_device_del_device(&pdev->dev); 579 edac_device_del_device(&pdev->dev);
580 edac_device_free_ctl_info(edac_dev); 580 edac_device_free_ctl_info(edac_dev);
@@ -766,7 +766,7 @@ static int __devinit mv64x60_mc_err_probe(struct platform_device *pdev)
766 goto err2; 766 goto err2;
767 } 767 }
768 768
769 debugf3("init mci\n"); 769 edac_dbg(3, "init mci\n");
770 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR; 770 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
771 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; 771 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
772 mci->edac_cap = EDAC_FLAG_SECDED; 772 mci->edac_cap = EDAC_FLAG_SECDED;
@@ -790,7 +790,7 @@ static int __devinit mv64x60_mc_err_probe(struct platform_device *pdev)
790 out_le32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ECC_CNTL, ctl); 790 out_le32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ECC_CNTL, ctl);
791 791
792 if (edac_mc_add_mc(mci)) { 792 if (edac_mc_add_mc(mci)) {
793 debugf3("failed edac_mc_add_mc()\n"); 793 edac_dbg(3, "failed edac_mc_add_mc()\n");
794 goto err; 794 goto err;
795 } 795 }
796 796
@@ -815,7 +815,7 @@ static int __devinit mv64x60_mc_err_probe(struct platform_device *pdev)
815 } 815 }
816 816
817 /* get this far and it's successful */ 817 /* get this far and it's successful */
818 debugf3("success\n"); 818 edac_dbg(3, "success\n");
819 819
820 return 0; 820 return 0;
821 821
@@ -831,7 +831,7 @@ static int mv64x60_mc_err_remove(struct platform_device *pdev)
831{ 831{
832 struct mem_ctl_info *mci = platform_get_drvdata(pdev); 832 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
833 833
834 debugf0("\n"); 834 edac_dbg(0, "\n");
835 835
836 edac_mc_del_mc(&pdev->dev); 836 edac_mc_del_mc(&pdev->dev);
837 edac_mc_free(mci); 837 edac_mc_free(mci);
diff --git a/drivers/edac/r82600_edac.c b/drivers/edac/r82600_edac.c
index 872c3b92803..b68e734398e 100644
--- a/drivers/edac/r82600_edac.c
+++ b/drivers/edac/r82600_edac.c
@@ -205,7 +205,7 @@ static void r82600_check(struct mem_ctl_info *mci)
205{ 205{
206 struct r82600_error_info info; 206 struct r82600_error_info info;
207 207
208 debugf1("MC%d\n", mci->mc_idx); 208 edac_dbg(1, "MC%d\n", mci->mc_idx);
209 r82600_get_error_info(mci, &info); 209 r82600_get_error_info(mci, &info);
210 r82600_process_error_info(mci, &info, 1); 210 r82600_process_error_info(mci, &info, 1);
211} 211}
@@ -236,13 +236,13 @@ static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
236 /* find the DRAM Chip Select Base address and mask */ 236 /* find the DRAM Chip Select Base address and mask */
237 pci_read_config_byte(pdev, R82600_DRBA + index, &drbar); 237 pci_read_config_byte(pdev, R82600_DRBA + index, &drbar);
238 238
239 debugf1("Row=%d DRBA = %#0x\n", index, drbar); 239 edac_dbg(1, "Row=%d DRBA = %#0x\n", index, drbar);
240 240
241 row_high_limit = ((u32) drbar << 24); 241 row_high_limit = ((u32) drbar << 24);
242/* row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */ 242/* row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */
243 243
244 debugf1("Row=%d, Boundary Address=%#0x, Last = %#0x\n", 244 edac_dbg(1, "Row=%d, Boundary Address=%#0x, Last = %#0x\n",
245 index, row_high_limit, row_high_limit_last); 245 index, row_high_limit, row_high_limit_last);
246 246
247 /* Empty row [p.57] */ 247 /* Empty row [p.57] */
248 if (row_high_limit == row_high_limit_last) 248 if (row_high_limit == row_high_limit_last)
@@ -277,13 +277,13 @@ static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
277 u32 sdram_refresh_rate; 277 u32 sdram_refresh_rate;
278 struct r82600_error_info discard; 278 struct r82600_error_info discard;
279 279
280 debugf0("\n"); 280 edac_dbg(0, "\n");
281 pci_read_config_byte(pdev, R82600_DRAMC, &dramcr); 281 pci_read_config_byte(pdev, R82600_DRAMC, &dramcr);
282 pci_read_config_dword(pdev, R82600_EAP, &eapr); 282 pci_read_config_dword(pdev, R82600_EAP, &eapr);
283 scrub_disabled = eapr & BIT(31); 283 scrub_disabled = eapr & BIT(31);
284 sdram_refresh_rate = dramcr & (BIT(0) | BIT(1)); 284 sdram_refresh_rate = dramcr & (BIT(0) | BIT(1));
285 debugf2("sdram refresh rate = %#0x\n", sdram_refresh_rate); 285 edac_dbg(2, "sdram refresh rate = %#0x\n", sdram_refresh_rate);
286 debugf2("DRAMC register = %#0x\n", dramcr); 286 edac_dbg(2, "DRAMC register = %#0x\n", dramcr);
287 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 287 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
288 layers[0].size = R82600_NR_CSROWS; 288 layers[0].size = R82600_NR_CSROWS;
289 layers[0].is_virt_csrow = true; 289 layers[0].is_virt_csrow = true;
@@ -294,7 +294,7 @@ static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
294 if (mci == NULL) 294 if (mci == NULL)
295 return -ENOMEM; 295 return -ENOMEM;
296 296
297 debugf0("mci = %p\n", mci); 297 edac_dbg(0, "mci = %p\n", mci);
298 mci->pdev = &pdev->dev; 298 mci->pdev = &pdev->dev;
299 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR; 299 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
300 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; 300 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
@@ -310,8 +310,8 @@ static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
310 310
311 if (ecc_enabled(dramcr)) { 311 if (ecc_enabled(dramcr)) {
312 if (scrub_disabled) 312 if (scrub_disabled)
313 debugf3("mci = %p - Scrubbing disabled! EAP: " 313 edac_dbg(3, "mci = %p - Scrubbing disabled! EAP: %#0x\n",
314 "%#0x\n", mci, eapr); 314 mci, eapr);
315 } else 315 } else
316 mci->edac_cap = EDAC_FLAG_NONE; 316 mci->edac_cap = EDAC_FLAG_NONE;
317 317
@@ -328,14 +328,14 @@ static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
328 * type of memory controller. The ID is therefore hardcoded to 0. 328 * type of memory controller. The ID is therefore hardcoded to 0.
329 */ 329 */
330 if (edac_mc_add_mc(mci)) { 330 if (edac_mc_add_mc(mci)) {
331 debugf3("failed edac_mc_add_mc()\n"); 331 edac_dbg(3, "failed edac_mc_add_mc()\n");
332 goto fail; 332 goto fail;
333 } 333 }
334 334
335 /* get this far and it's successful */ 335 /* get this far and it's successful */
336 336
337 if (disable_hardware_scrub) { 337 if (disable_hardware_scrub) {
338 debugf3("Disabling Hardware Scrub (scrub on error)\n"); 338 edac_dbg(3, "Disabling Hardware Scrub (scrub on error)\n");
339 pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31)); 339 pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31));
340 } 340 }
341 341
@@ -350,7 +350,7 @@ static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
350 __func__); 350 __func__);
351 } 351 }
352 352
353 debugf3("success\n"); 353 edac_dbg(3, "success\n");
354 return 0; 354 return 0;
355 355
356fail: 356fail:
@@ -362,7 +362,7 @@ fail:
362static int __devinit r82600_init_one(struct pci_dev *pdev, 362static int __devinit r82600_init_one(struct pci_dev *pdev,
363 const struct pci_device_id *ent) 363 const struct pci_device_id *ent)
364{ 364{
365 debugf0("\n"); 365 edac_dbg(0, "\n");
366 366
367 /* don't need to call pci_enable_device() */ 367 /* don't need to call pci_enable_device() */
368 return r82600_probe1(pdev, ent->driver_data); 368 return r82600_probe1(pdev, ent->driver_data);
@@ -372,7 +372,7 @@ static void __devexit r82600_remove_one(struct pci_dev *pdev)
372{ 372{
373 struct mem_ctl_info *mci; 373 struct mem_ctl_info *mci;
374 374
375 debugf0("\n"); 375 edac_dbg(0, "\n");
376 376
377 if (r82600_pci) 377 if (r82600_pci)
378 edac_pci_release_generic_ctl(r82600_pci); 378 edac_pci_release_generic_ctl(r82600_pci);
diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
index 96efa496db5..05955bfda84 100644
--- a/drivers/edac/sb_edac.c
+++ b/drivers/edac/sb_edac.c
@@ -381,8 +381,8 @@ static inline int numrank(u32 mtr)
381 int ranks = (1 << RANK_CNT_BITS(mtr)); 381 int ranks = (1 << RANK_CNT_BITS(mtr));
382 382
383 if (ranks > 4) { 383 if (ranks > 4) {
384 debugf0("Invalid number of ranks: %d (max = 4) raw value = %x (%04x)", 384 edac_dbg(0, "Invalid number of ranks: %d (max = 4) raw value = %x (%04x)\n",
385 ranks, (unsigned int)RANK_CNT_BITS(mtr), mtr); 385 ranks, (unsigned int)RANK_CNT_BITS(mtr), mtr);
386 return -EINVAL; 386 return -EINVAL;
387 } 387 }
388 388
@@ -394,8 +394,8 @@ static inline int numrow(u32 mtr)
394 int rows = (RANK_WIDTH_BITS(mtr) + 12); 394 int rows = (RANK_WIDTH_BITS(mtr) + 12);
395 395
396 if (rows < 13 || rows > 18) { 396 if (rows < 13 || rows > 18) {
397 debugf0("Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)", 397 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",
398 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr); 398 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
399 return -EINVAL; 399 return -EINVAL;
400 } 400 }
401 401
@@ -407,8 +407,8 @@ static inline int numcol(u32 mtr)
407 int cols = (COL_WIDTH_BITS(mtr) + 10); 407 int cols = (COL_WIDTH_BITS(mtr) + 10);
408 408
409 if (cols > 12) { 409 if (cols > 12) {
410 debugf0("Invalid number of cols: %d (max = 4) raw value = %x (%04x)", 410 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",
411 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr); 411 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
412 return -EINVAL; 412 return -EINVAL;
413 } 413 }
414 414
@@ -475,8 +475,8 @@ static struct pci_dev *get_pdev_slot_func(u8 bus, unsigned slot,
475 475
476 if (PCI_SLOT(sbridge_dev->pdev[i]->devfn) == slot && 476 if (PCI_SLOT(sbridge_dev->pdev[i]->devfn) == slot &&
477 PCI_FUNC(sbridge_dev->pdev[i]->devfn) == func) { 477 PCI_FUNC(sbridge_dev->pdev[i]->devfn) == func) {
478 debugf1("Associated %02x.%02x.%d with %p\n", 478 edac_dbg(1, "Associated %02x.%02x.%d with %p\n",
479 bus, slot, func, sbridge_dev->pdev[i]); 479 bus, slot, func, sbridge_dev->pdev[i]);
480 return sbridge_dev->pdev[i]; 480 return sbridge_dev->pdev[i];
481 } 481 }
482 } 482 }
@@ -523,45 +523,45 @@ static int get_dimm_config(struct mem_ctl_info *mci)
523 523
524 pci_read_config_dword(pvt->pci_br, SAD_CONTROL, &reg); 524 pci_read_config_dword(pvt->pci_br, SAD_CONTROL, &reg);
525 pvt->sbridge_dev->node_id = NODE_ID(reg); 525 pvt->sbridge_dev->node_id = NODE_ID(reg);
526 debugf0("mc#%d: Node ID: %d, source ID: %d\n", 526 edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
527 pvt->sbridge_dev->mc, 527 pvt->sbridge_dev->mc,
528 pvt->sbridge_dev->node_id, 528 pvt->sbridge_dev->node_id,
529 pvt->sbridge_dev->source_id); 529 pvt->sbridge_dev->source_id);
530 530
531 pci_read_config_dword(pvt->pci_ras, RASENABLES, &reg); 531 pci_read_config_dword(pvt->pci_ras, RASENABLES, &reg);
532 if (IS_MIRROR_ENABLED(reg)) { 532 if (IS_MIRROR_ENABLED(reg)) {
533 debugf0("Memory mirror is enabled\n"); 533 edac_dbg(0, "Memory mirror is enabled\n");
534 pvt->is_mirrored = true; 534 pvt->is_mirrored = true;
535 } else { 535 } else {
536 debugf0("Memory mirror is disabled\n"); 536 edac_dbg(0, "Memory mirror is disabled\n");
537 pvt->is_mirrored = false; 537 pvt->is_mirrored = false;
538 } 538 }
539 539
540 pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr); 540 pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr);
541 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) { 541 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
542 debugf0("Lockstep is enabled\n"); 542 edac_dbg(0, "Lockstep is enabled\n");
543 mode = EDAC_S8ECD8ED; 543 mode = EDAC_S8ECD8ED;
544 pvt->is_lockstep = true; 544 pvt->is_lockstep = true;
545 } else { 545 } else {
546 debugf0("Lockstep is disabled\n"); 546 edac_dbg(0, "Lockstep is disabled\n");
547 mode = EDAC_S4ECD4ED; 547 mode = EDAC_S4ECD4ED;
548 pvt->is_lockstep = false; 548 pvt->is_lockstep = false;
549 } 549 }
550 if (IS_CLOSE_PG(pvt->info.mcmtr)) { 550 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
551 debugf0("address map is on closed page mode\n"); 551 edac_dbg(0, "address map is on closed page mode\n");
552 pvt->is_close_pg = true; 552 pvt->is_close_pg = true;
553 } else { 553 } else {
554 debugf0("address map is on open page mode\n"); 554 edac_dbg(0, "address map is on open page mode\n");
555 pvt->is_close_pg = false; 555 pvt->is_close_pg = false;
556 } 556 }
557 557
558 pci_read_config_dword(pvt->pci_ta, RANK_CFG_A, &reg); 558 pci_read_config_dword(pvt->pci_ta, RANK_CFG_A, &reg);
559 if (IS_RDIMM_ENABLED(reg)) { 559 if (IS_RDIMM_ENABLED(reg)) {
560 /* FIXME: Can also be LRDIMM */ 560 /* FIXME: Can also be LRDIMM */
561 debugf0("Memory is registered\n"); 561 edac_dbg(0, "Memory is registered\n");
562 mtype = MEM_RDDR3; 562 mtype = MEM_RDDR3;
563 } else { 563 } else {
564 debugf0("Memory is unregistered\n"); 564 edac_dbg(0, "Memory is unregistered\n");
565 mtype = MEM_DDR3; 565 mtype = MEM_DDR3;
566 } 566 }
567 567
@@ -576,7 +576,7 @@ static int get_dimm_config(struct mem_ctl_info *mci)
576 i, j, 0); 576 i, j, 0);
577 pci_read_config_dword(pvt->pci_tad[i], 577 pci_read_config_dword(pvt->pci_tad[i],
578 mtr_regs[j], &mtr); 578 mtr_regs[j], &mtr);
579 debugf4("Channel #%d MTR%d = %x\n", i, j, mtr); 579 edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr);
580 if (IS_DIMM_PRESENT(mtr)) { 580 if (IS_DIMM_PRESENT(mtr)) {
581 pvt->channel[i].dimms++; 581 pvt->channel[i].dimms++;
582 582
@@ -588,10 +588,10 @@ static int get_dimm_config(struct mem_ctl_info *mci)
588 size = (rows * cols * banks * ranks) >> (20 - 3); 588 size = (rows * cols * banks * ranks) >> (20 - 3);
589 npages = MiB_TO_PAGES(size); 589 npages = MiB_TO_PAGES(size);
590 590
591 debugf0("mc#%d: channel %d, dimm %d, %d Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n", 591 edac_dbg(0, "mc#%d: channel %d, dimm %d, %d Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
592 pvt->sbridge_dev->mc, i, j, 592 pvt->sbridge_dev->mc, i, j,
593 size, npages, 593 size, npages,
594 banks, ranks, rows, cols); 594 banks, ranks, rows, cols);
595 595
596 dimm->nr_pages = npages; 596 dimm->nr_pages = npages;
597 dimm->grain = 32; 597 dimm->grain = 32;
@@ -629,8 +629,7 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
629 tmp_mb = (1 + pvt->tolm) >> 20; 629 tmp_mb = (1 + pvt->tolm) >> 20;
630 630
631 mb = div_u64_rem(tmp_mb, 1000, &kb); 631 mb = div_u64_rem(tmp_mb, 1000, &kb);
632 debugf0("TOLM: %u.%03u GB (0x%016Lx)\n", 632 edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n", mb, kb, (u64)pvt->tolm);
633 mb, kb, (u64)pvt->tolm);
634 633
635 /* Address range is already 45:25 */ 634 /* Address range is already 45:25 */
636 pci_read_config_dword(pvt->pci_sad1, TOHM, 635 pci_read_config_dword(pvt->pci_sad1, TOHM,
@@ -639,8 +638,7 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
639 tmp_mb = (1 + pvt->tohm) >> 20; 638 tmp_mb = (1 + pvt->tohm) >> 20;
640 639
641 mb = div_u64_rem(tmp_mb, 1000, &kb); 640 mb = div_u64_rem(tmp_mb, 1000, &kb);
642 debugf0("TOHM: %u.%03u GB (0x%016Lx)", 641 edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)", mb, kb, (u64)pvt->tohm);
643 mb, kb, (u64)pvt->tohm);
644 642
645 /* 643 /*
646 * Step 2) Get SAD range and SAD Interleave list 644 * Step 2) Get SAD range and SAD Interleave list
@@ -663,13 +661,13 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
663 661
664 tmp_mb = (limit + 1) >> 20; 662 tmp_mb = (limit + 1) >> 20;
665 mb = div_u64_rem(tmp_mb, 1000, &kb); 663 mb = div_u64_rem(tmp_mb, 1000, &kb);
666 debugf0("SAD#%d %s up to %u.%03u GB (0x%016Lx) %s reg=0x%08x\n", 664 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
667 n_sads, 665 n_sads,
668 get_dram_attr(reg), 666 get_dram_attr(reg),
669 mb, kb, 667 mb, kb,
670 ((u64)tmp_mb) << 20L, 668 ((u64)tmp_mb) << 20L,
671 INTERLEAVE_MODE(reg) ? "Interleave: 8:6" : "Interleave: [8:6]XOR[18:16]", 669 INTERLEAVE_MODE(reg) ? "8:6" : "[8:6]XOR[18:16]",
672 reg); 670 reg);
673 prv = limit; 671 prv = limit;
674 672
675 pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads], 673 pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads],
@@ -679,8 +677,8 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
679 if (j > 0 && sad_interl == sad_pkg(reg, j)) 677 if (j > 0 && sad_interl == sad_pkg(reg, j))
680 break; 678 break;
681 679
682 debugf0("SAD#%d, interleave #%d: %d\n", 680 edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
683 n_sads, j, sad_pkg(reg, j)); 681 n_sads, j, sad_pkg(reg, j));
684 } 682 }
685 } 683 }
686 684
@@ -697,16 +695,16 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
697 tmp_mb = (limit + 1) >> 20; 695 tmp_mb = (limit + 1) >> 20;
698 696
699 mb = div_u64_rem(tmp_mb, 1000, &kb); 697 mb = div_u64_rem(tmp_mb, 1000, &kb);
700 debugf0("TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n", 698 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
701 n_tads, mb, kb, 699 n_tads, mb, kb,
702 ((u64)tmp_mb) << 20L, 700 ((u64)tmp_mb) << 20L,
703 (u32)TAD_SOCK(reg), 701 (u32)TAD_SOCK(reg),
704 (u32)TAD_CH(reg), 702 (u32)TAD_CH(reg),
705 (u32)TAD_TGT0(reg), 703 (u32)TAD_TGT0(reg),
706 (u32)TAD_TGT1(reg), 704 (u32)TAD_TGT1(reg),
707 (u32)TAD_TGT2(reg), 705 (u32)TAD_TGT2(reg),
708 (u32)TAD_TGT3(reg), 706 (u32)TAD_TGT3(reg),
709 reg); 707 reg);
710 prv = limit; 708 prv = limit;
711 } 709 }
712 710
@@ -722,11 +720,11 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
722 &reg); 720 &reg);
723 tmp_mb = TAD_OFFSET(reg) >> 20; 721 tmp_mb = TAD_OFFSET(reg) >> 20;
724 mb = div_u64_rem(tmp_mb, 1000, &kb); 722 mb = div_u64_rem(tmp_mb, 1000, &kb);
725 debugf0("TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n", 723 edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
726 i, j, 724 i, j,
727 mb, kb, 725 mb, kb,
728 ((u64)tmp_mb) << 20L, 726 ((u64)tmp_mb) << 20L,
729 reg); 727 reg);
730 } 728 }
731 } 729 }
732 730
@@ -747,12 +745,12 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
747 tmp_mb = RIR_LIMIT(reg) >> 20; 745 tmp_mb = RIR_LIMIT(reg) >> 20;
748 rir_way = 1 << RIR_WAY(reg); 746 rir_way = 1 << RIR_WAY(reg);
749 mb = div_u64_rem(tmp_mb, 1000, &kb); 747 mb = div_u64_rem(tmp_mb, 1000, &kb);
750 debugf0("CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n", 748 edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
751 i, j, 749 i, j,
752 mb, kb, 750 mb, kb,
753 ((u64)tmp_mb) << 20L, 751 ((u64)tmp_mb) << 20L,
754 rir_way, 752 rir_way,
755 reg); 753 reg);
756 754
757 for (k = 0; k < rir_way; k++) { 755 for (k = 0; k < rir_way; k++) {
758 pci_read_config_dword(pvt->pci_tad[i], 756 pci_read_config_dword(pvt->pci_tad[i],
@@ -761,12 +759,12 @@ static void get_memory_layout(const struct mem_ctl_info *mci)
761 tmp_mb = RIR_OFFSET(reg) << 6; 759 tmp_mb = RIR_OFFSET(reg) << 6;
762 760
763 mb = div_u64_rem(tmp_mb, 1000, &kb); 761 mb = div_u64_rem(tmp_mb, 1000, &kb);
764 debugf0("CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n", 762 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
765 i, j, k, 763 i, j, k,
766 mb, kb, 764 mb, kb,
767 ((u64)tmp_mb) << 20L, 765 ((u64)tmp_mb) << 20L,
768 (u32)RIR_RNK_TGT(reg), 766 (u32)RIR_RNK_TGT(reg),
769 reg); 767 reg);
770 } 768 }
771 } 769 }
772 } 770 }
@@ -853,16 +851,16 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
853 if (sad_way > 0 && sad_interl == sad_pkg(reg, sad_way)) 851 if (sad_way > 0 && sad_interl == sad_pkg(reg, sad_way))
854 break; 852 break;
855 sad_interleave[sad_way] = sad_pkg(reg, sad_way); 853 sad_interleave[sad_way] = sad_pkg(reg, sad_way);
856 debugf0("SAD interleave #%d: %d\n", 854 edac_dbg(0, "SAD interleave #%d: %d\n",
857 sad_way, sad_interleave[sad_way]); 855 sad_way, sad_interleave[sad_way]);
858 } 856 }
859 debugf0("mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n", 857 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
860 pvt->sbridge_dev->mc, 858 pvt->sbridge_dev->mc,
861 n_sads, 859 n_sads,
862 addr, 860 addr,
863 limit, 861 limit,
864 sad_way + 7, 862 sad_way + 7,
865 interleave_mode ? "" : "XOR[18:16]"); 863 interleave_mode ? "" : "XOR[18:16]");
866 if (interleave_mode) 864 if (interleave_mode)
867 idx = ((addr >> 6) ^ (addr >> 16)) & 7; 865 idx = ((addr >> 6) ^ (addr >> 16)) & 7;
868 else 866 else
@@ -884,8 +882,8 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
884 return -EINVAL; 882 return -EINVAL;
885 } 883 }
886 *socket = sad_interleave[idx]; 884 *socket = sad_interleave[idx];
887 debugf0("SAD interleave index: %d (wayness %d) = CPU socket %d\n", 885 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
888 idx, sad_way, *socket); 886 idx, sad_way, *socket);
889 887
890 /* 888 /*
891 * Move to the proper node structure, in order to access the 889 * Move to the proper node structure, in order to access the
@@ -972,16 +970,16 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
972 970
973 offset = TAD_OFFSET(tad_offset); 971 offset = TAD_OFFSET(tad_offset);
974 972
975 debugf0("TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n", 973 edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
976 n_tads, 974 n_tads,
977 addr, 975 addr,
978 limit, 976 limit,
979 (u32)TAD_SOCK(reg), 977 (u32)TAD_SOCK(reg),
980 ch_way, 978 ch_way,
981 offset, 979 offset,
982 idx, 980 idx,
983 base_ch, 981 base_ch,
984 *channel_mask); 982 *channel_mask);
985 983
986 /* Calculate channel address */ 984 /* Calculate channel address */
987 /* Remove the TAD offset */ 985 /* Remove the TAD offset */
@@ -1017,11 +1015,11 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
1017 1015
1018 limit = RIR_LIMIT(reg); 1016 limit = RIR_LIMIT(reg);
1019 mb = div_u64_rem(limit >> 20, 1000, &kb); 1017 mb = div_u64_rem(limit >> 20, 1000, &kb);
1020 debugf0("RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n", 1018 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
1021 n_rir, 1019 n_rir,
1022 mb, kb, 1020 mb, kb,
1023 limit, 1021 limit,
1024 1 << RIR_WAY(reg)); 1022 1 << RIR_WAY(reg));
1025 if (ch_addr <= limit) 1023 if (ch_addr <= limit)
1026 break; 1024 break;
1027 } 1025 }
@@ -1042,12 +1040,12 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
1042 &reg); 1040 &reg);
1043 *rank = RIR_RNK_TGT(reg); 1041 *rank = RIR_RNK_TGT(reg);
1044 1042
1045 debugf0("RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n", 1043 edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
1046 n_rir, 1044 n_rir,
1047 ch_addr, 1045 ch_addr,
1048 limit, 1046 limit,
1049 rir_way, 1047 rir_way,
1050 idx); 1048 idx);
1051 1049
1052 return 0; 1050 return 0;
1053} 1051}
@@ -1064,14 +1062,14 @@ static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
1064{ 1062{
1065 int i; 1063 int i;
1066 1064
1067 debugf0("\n"); 1065 edac_dbg(0, "\n");
1068 for (i = 0; i < sbridge_dev->n_devs; i++) { 1066 for (i = 0; i < sbridge_dev->n_devs; i++) {
1069 struct pci_dev *pdev = sbridge_dev->pdev[i]; 1067 struct pci_dev *pdev = sbridge_dev->pdev[i];
1070 if (!pdev) 1068 if (!pdev)
1071 continue; 1069 continue;
1072 debugf0("Removing dev %02x:%02x.%d\n", 1070 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
1073 pdev->bus->number, 1071 pdev->bus->number,
1074 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 1072 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1075 pci_dev_put(pdev); 1073 pci_dev_put(pdev);
1076 } 1074 }
1077} 1075}
@@ -1177,10 +1175,9 @@ static int sbridge_get_onedevice(struct pci_dev **prev,
1177 return -ENODEV; 1175 return -ENODEV;
1178 } 1176 }
1179 1177
1180 debugf0("Detected dev %02x:%d.%d PCI ID %04x:%04x\n", 1178 edac_dbg(0, "Detected dev %02x:%d.%d PCI ID %04x:%04x\n",
1181 bus, dev_descr->dev, 1179 bus, dev_descr->dev, dev_descr->func,
1182 dev_descr->func, 1180 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1183 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1184 1181
1185 /* 1182 /*
1186 * As stated on drivers/pci/search.c, the reference count for 1183 * As stated on drivers/pci/search.c, the reference count for
@@ -1297,10 +1294,10 @@ static int mci_bind_devs(struct mem_ctl_info *mci,
1297 goto error; 1294 goto error;
1298 } 1295 }
1299 1296
1300 debugf0("Associated PCI %02x.%02d.%d with dev = %p\n", 1297 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
1301 sbridge_dev->bus, 1298 sbridge_dev->bus,
1302 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), 1299 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1303 pdev); 1300 pdev);
1304 } 1301 }
1305 1302
1306 /* Check if everything were registered */ 1303 /* Check if everything were registered */
@@ -1445,7 +1442,7 @@ static void sbridge_mce_output_error(struct mem_ctl_info *mci,
1445 channel_mask, 1442 channel_mask,
1446 rank); 1443 rank);
1447 1444
1448 debugf0("%s", msg); 1445 edac_dbg(0, "%s\n", msg);
1449 1446
1450 /* FIXME: need support for channel mask */ 1447 /* FIXME: need support for channel mask */
1451 1448
@@ -1592,7 +1589,7 @@ static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
1592 struct sbridge_pvt *pvt; 1589 struct sbridge_pvt *pvt;
1593 1590
1594 if (unlikely(!mci || !mci->pvt_info)) { 1591 if (unlikely(!mci || !mci->pvt_info)) {
1595 debugf0("MC: dev = %p\n", &sbridge_dev->pdev[0]->dev); 1592 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);
1596 1593
1597 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n"); 1594 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
1598 return; 1595 return;
@@ -1600,15 +1597,15 @@ static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
1600 1597
1601 pvt = mci->pvt_info; 1598 pvt = mci->pvt_info;
1602 1599
1603 debugf0("MC: mci = %p, dev = %p\n", 1600 edac_dbg(0, "MC: mci = %p, dev = %p\n",
1604 mci, &sbridge_dev->pdev[0]->dev); 1601 mci, &sbridge_dev->pdev[0]->dev);
1605 1602
1606 mce_unregister_decode_chain(&sbridge_mce_dec); 1603 mce_unregister_decode_chain(&sbridge_mce_dec);
1607 1604
1608 /* Remove MC sysfs nodes */ 1605 /* Remove MC sysfs nodes */
1609 edac_mc_del_mc(mci->pdev); 1606 edac_mc_del_mc(mci->pdev);
1610 1607
1611 debugf1("%s: free mci struct\n", mci->ctl_name); 1608 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
1612 kfree(mci->ctl_name); 1609 kfree(mci->ctl_name);
1613 edac_mc_free(mci); 1610 edac_mc_free(mci);
1614 sbridge_dev->mci = NULL; 1611 sbridge_dev->mci = NULL;
@@ -1639,8 +1636,8 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev)
1639 if (unlikely(!mci)) 1636 if (unlikely(!mci))
1640 return -ENOMEM; 1637 return -ENOMEM;
1641 1638
1642 debugf0("MC: mci = %p, dev = %p\n", 1639 edac_dbg(0, "MC: mci = %p, dev = %p\n",
1643 mci, &sbridge_dev->pdev[0]->dev); 1640 mci, &sbridge_dev->pdev[0]->dev);
1644 1641
1645 pvt = mci->pvt_info; 1642 pvt = mci->pvt_info;
1646 memset(pvt, 0, sizeof(*pvt)); 1643 memset(pvt, 0, sizeof(*pvt));
@@ -1675,7 +1672,7 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev)
1675 1672
1676 /* add this new MC control structure to EDAC's list of MCs */ 1673 /* add this new MC control structure to EDAC's list of MCs */
1677 if (unlikely(edac_mc_add_mc(mci))) { 1674 if (unlikely(edac_mc_add_mc(mci))) {
1678 debugf0("MC: failed edac_mc_add_mc()\n"); 1675 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
1679 rc = -EINVAL; 1676 rc = -EINVAL;
1680 goto fail0; 1677 goto fail0;
1681 } 1678 }
@@ -1723,7 +1720,8 @@ static int __devinit sbridge_probe(struct pci_dev *pdev,
1723 mc = 0; 1720 mc = 0;
1724 1721
1725 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { 1722 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1726 debugf0("Registering MC#%d (%d of %d)\n", mc, mc + 1, num_mc); 1723 edac_dbg(0, "Registering MC#%d (%d of %d)\n",
1724 mc, mc + 1, num_mc);
1727 sbridge_dev->mc = mc++; 1725 sbridge_dev->mc = mc++;
1728 rc = sbridge_register_mci(sbridge_dev); 1726 rc = sbridge_register_mci(sbridge_dev);
1729 if (unlikely(rc < 0)) 1727 if (unlikely(rc < 0))
@@ -1753,7 +1751,7 @@ static void __devexit sbridge_remove(struct pci_dev *pdev)
1753{ 1751{
1754 struct sbridge_dev *sbridge_dev; 1752 struct sbridge_dev *sbridge_dev;
1755 1753
1756 debugf0("\n"); 1754 edac_dbg(0, "\n");
1757 1755
1758 /* 1756 /*
1759 * we have a trouble here: pdev value for removal will be wrong, since 1757 * we have a trouble here: pdev value for removal will be wrong, since
@@ -1802,7 +1800,7 @@ static int __init sbridge_init(void)
1802{ 1800{
1803 int pci_rc; 1801 int pci_rc;
1804 1802
1805 debugf2("\n"); 1803 edac_dbg(2, "\n");
1806 1804
1807 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 1805 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1808 opstate_init(); 1806 opstate_init();
@@ -1824,7 +1822,7 @@ static int __init sbridge_init(void)
1824 */ 1822 */
1825static void __exit sbridge_exit(void) 1823static void __exit sbridge_exit(void)
1826{ 1824{
1827 debugf2("\n"); 1825 edac_dbg(2, "\n");
1828 pci_unregister_driver(&sbridge_driver); 1826 pci_unregister_driver(&sbridge_driver);
1829} 1827}
1830 1828
diff --git a/drivers/edac/x38_edac.c b/drivers/edac/x38_edac.c
index 70c745422fc..0e1581afada 100644
--- a/drivers/edac/x38_edac.c
+++ b/drivers/edac/x38_edac.c
@@ -103,10 +103,10 @@ static int how_many_channel(struct pci_dev *pdev)
103 103
104 pci_read_config_byte(pdev, X38_CAPID0 + 8, &capid0_8b); 104 pci_read_config_byte(pdev, X38_CAPID0 + 8, &capid0_8b);
105 if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */ 105 if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */
106 debugf0("In single channel mode.\n"); 106 edac_dbg(0, "In single channel mode\n");
107 x38_channel_num = 1; 107 x38_channel_num = 1;
108 } else { 108 } else {
109 debugf0("In dual channel mode.\n"); 109 edac_dbg(0, "In dual channel mode\n");
110 x38_channel_num = 2; 110 x38_channel_num = 2;
111 } 111 }
112 112
@@ -243,7 +243,7 @@ static void x38_check(struct mem_ctl_info *mci)
243{ 243{
244 struct x38_error_info info; 244 struct x38_error_info info;
245 245
246 debugf1("MC%d\n", mci->mc_idx); 246 edac_dbg(1, "MC%d\n", mci->mc_idx);
247 x38_get_and_clear_error_info(mci, &info); 247 x38_get_and_clear_error_info(mci, &info);
248 x38_process_error_info(mci, &info); 248 x38_process_error_info(mci, &info);
249} 249}
@@ -331,7 +331,7 @@ static int x38_probe1(struct pci_dev *pdev, int dev_idx)
331 bool stacked; 331 bool stacked;
332 void __iomem *window; 332 void __iomem *window;
333 333
334 debugf0("MC:\n"); 334 edac_dbg(0, "MC:\n");
335 335
336 window = x38_map_mchbar(pdev); 336 window = x38_map_mchbar(pdev);
337 if (!window) 337 if (!window)
@@ -352,7 +352,7 @@ static int x38_probe1(struct pci_dev *pdev, int dev_idx)
352 if (!mci) 352 if (!mci)
353 return -ENOMEM; 353 return -ENOMEM;
354 354
355 debugf3("MC: init mci\n"); 355 edac_dbg(3, "MC: init mci\n");
356 356
357 mci->pdev = &pdev->dev; 357 mci->pdev = &pdev->dev;
358 mci->mtype_cap = MEM_FLAG_DDR2; 358 mci->mtype_cap = MEM_FLAG_DDR2;
@@ -402,12 +402,12 @@ static int x38_probe1(struct pci_dev *pdev, int dev_idx)
402 402
403 rc = -ENODEV; 403 rc = -ENODEV;
404 if (edac_mc_add_mc(mci)) { 404 if (edac_mc_add_mc(mci)) {
405 debugf3("MC: failed edac_mc_add_mc()\n"); 405 edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
406 goto fail; 406 goto fail;
407 } 407 }
408 408
409 /* get this far and it's successful */ 409 /* get this far and it's successful */
410 debugf3("MC: success\n"); 410 edac_dbg(3, "MC: success\n");
411 return 0; 411 return 0;
412 412
413fail: 413fail:
@@ -423,7 +423,7 @@ static int __devinit x38_init_one(struct pci_dev *pdev,
423{ 423{
424 int rc; 424 int rc;
425 425
426 debugf0("MC:\n"); 426 edac_dbg(0, "MC:\n");
427 427
428 if (pci_enable_device(pdev) < 0) 428 if (pci_enable_device(pdev) < 0)
429 return -EIO; 429 return -EIO;
@@ -439,7 +439,7 @@ static void __devexit x38_remove_one(struct pci_dev *pdev)
439{ 439{
440 struct mem_ctl_info *mci; 440 struct mem_ctl_info *mci;
441 441
442 debugf0("\n"); 442 edac_dbg(0, "\n");
443 443
444 mci = edac_mc_del_mc(&pdev->dev); 444 mci = edac_mc_del_mc(&pdev->dev);
445 if (!mci) 445 if (!mci)
@@ -472,7 +472,7 @@ static int __init x38_init(void)
472{ 472{
473 int pci_rc; 473 int pci_rc;
474 474
475 debugf3("MC:\n"); 475 edac_dbg(3, "MC:\n");
476 476
477 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 477 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
478 opstate_init(); 478 opstate_init();
@@ -486,14 +486,14 @@ static int __init x38_init(void)
486 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 486 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
487 PCI_DEVICE_ID_INTEL_X38_HB, NULL); 487 PCI_DEVICE_ID_INTEL_X38_HB, NULL);
488 if (!mci_pdev) { 488 if (!mci_pdev) {
489 debugf0("x38 pci_get_device fail\n"); 489 edac_dbg(0, "x38 pci_get_device fail\n");
490 pci_rc = -ENODEV; 490 pci_rc = -ENODEV;
491 goto fail1; 491 goto fail1;
492 } 492 }
493 493
494 pci_rc = x38_init_one(mci_pdev, x38_pci_tbl); 494 pci_rc = x38_init_one(mci_pdev, x38_pci_tbl);
495 if (pci_rc < 0) { 495 if (pci_rc < 0) {
496 debugf0("x38 init fail\n"); 496 edac_dbg(0, "x38 init fail\n");
497 pci_rc = -ENODEV; 497 pci_rc = -ENODEV;
498 goto fail1; 498 goto fail1;
499 } 499 }
@@ -513,7 +513,7 @@ fail0:
513 513
514static void __exit x38_exit(void) 514static void __exit x38_exit(void)
515{ 515{
516 debugf3("MC:\n"); 516 edac_dbg(3, "MC:\n");
517 517
518 pci_unregister_driver(&x38_driver); 518 pci_unregister_driver(&x38_driver);
519 if (!x38_registered) { 519 if (!x38_registered) {
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 19:53:15 -0400