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-rw-r--r--drivers/mtd/maps/Kconfig8
-rw-r--r--drivers/mtd/maps/Makefile1
-rw-r--r--drivers/mtd/maps/epxa10db-flash.c179
-rw-r--r--drivers/net/arm/Kconfig13
-rw-r--r--drivers/net/arm/Makefile1
-rw-r--r--drivers/net/arm/ether00.c1017
-rw-r--r--drivers/serial/Kconfig23
-rw-r--r--drivers/serial/Makefile1
-rw-r--r--drivers/serial/uart00.c782
9 files changed, 0 insertions, 2025 deletions
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index b9b77cf39a1..7abd7fee0dd 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -473,14 +473,6 @@ config MTD_IXP2000
473 IXDP425 and Coyote. If you have an IXP2000 based board and 473 IXDP425 and Coyote. If you have an IXP2000 based board and
474 would like to use the flash chips on it, say 'Y'. 474 would like to use the flash chips on it, say 'Y'.
475 475
476config MTD_EPXA10DB
477 tristate "CFI Flash device mapped on Epxa10db"
478 depends on MTD_CFI && MTD_PARTITIONS && ARCH_CAMELOT
479 help
480 This enables support for the flash devices on the Altera
481 Excalibur XA10 Development Board. If you are building a kernel
482 for on of these boards then you should say 'Y' otherwise say 'N'.
483
484config MTD_FORTUNET 476config MTD_FORTUNET
485 tristate "CFI Flash device mapped on the FortuNet board" 477 tristate "CFI Flash device mapped on the FortuNet board"
486 depends on MTD_CFI && MTD_PARTITIONS && SA1100_FORTUNET 478 depends on MTD_CFI && MTD_PARTITIONS && SA1100_FORTUNET
diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
index 2f7e254912f..ab71f172eb7 100644
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -15,7 +15,6 @@ obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o
15obj-$(CONFIG_MTD_CSTM_MIPS_IXX) += cstm_mips_ixx.o 15obj-$(CONFIG_MTD_CSTM_MIPS_IXX) += cstm_mips_ixx.o
16obj-$(CONFIG_MTD_DC21285) += dc21285.o 16obj-$(CONFIG_MTD_DC21285) += dc21285.o
17obj-$(CONFIG_MTD_DILNETPC) += dilnetpc.o 17obj-$(CONFIG_MTD_DILNETPC) += dilnetpc.o
18obj-$(CONFIG_MTD_EPXA10DB) += epxa10db-flash.o
19obj-$(CONFIG_MTD_IQ80310) += iq80310.o 18obj-$(CONFIG_MTD_IQ80310) += iq80310.o
20obj-$(CONFIG_MTD_L440GX) += l440gx.o 19obj-$(CONFIG_MTD_L440GX) += l440gx.o
21obj-$(CONFIG_MTD_AMD76XROM) += amd76xrom.o 20obj-$(CONFIG_MTD_AMD76XROM) += amd76xrom.o
diff --git a/drivers/mtd/maps/epxa10db-flash.c b/drivers/mtd/maps/epxa10db-flash.c
deleted file mode 100644
index 265b079fe93..00000000000
--- a/drivers/mtd/maps/epxa10db-flash.c
+++ /dev/null
@@ -1,179 +0,0 @@
1/*
2 * Flash memory access on EPXA based devices
3 *
4 * (C) 2000 Nicolas Pitre <nico@cam.org>
5 * Copyright (C) 2001 Altera Corporation
6 * Copyright (C) 2001 Red Hat, Inc.
7 *
8 * $Id: epxa10db-flash.c,v 1.15 2005/11/07 11:14:27 gleixner Exp $
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25#include <linux/config.h>
26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/kernel.h>
29#include <linux/init.h>
30#include <linux/slab.h>
31
32#include <linux/mtd/mtd.h>
33#include <linux/mtd/map.h>
34#include <linux/mtd/partitions.h>
35
36#include <asm/io.h>
37#include <asm/hardware.h>
38
39#ifdef CONFIG_EPXA10DB
40#define BOARD_NAME "EPXA10DB"
41#else
42#define BOARD_NAME "EPXA1DB"
43#endif
44
45static int nr_parts = 0;
46static struct mtd_partition *parts;
47
48static struct mtd_info *mymtd;
49
50static int epxa_default_partitions(struct mtd_info *master, struct mtd_partition **pparts);
51
52
53static struct map_info epxa_map = {
54 .name = "EPXA flash",
55 .size = FLASH_SIZE,
56 .bankwidth = 2,
57 .phys = FLASH_START,
58};
59
60static const char *probes[] = { "RedBoot", "afs", NULL };
61
62static int __init epxa_mtd_init(void)
63{
64 int i;
65
66 printk(KERN_NOTICE "%s flash device: 0x%x at 0x%x\n", BOARD_NAME, FLASH_SIZE, FLASH_START);
67
68 epxa_map.virt = ioremap(FLASH_START, FLASH_SIZE);
69 if (!epxa_map.virt) {
70 printk("Failed to ioremap %s flash\n",BOARD_NAME);
71 return -EIO;
72 }
73 simple_map_init(&epxa_map);
74
75 mymtd = do_map_probe("cfi_probe", &epxa_map);
76 if (!mymtd) {
77 iounmap((void *)epxa_map.virt);
78 return -ENXIO;
79 }
80
81 mymtd->owner = THIS_MODULE;
82
83 /* Unlock the flash device. */
84 if(mymtd->unlock){
85 for (i=0; i<mymtd->numeraseregions;i++){
86 int j;
87 for(j=0;j<mymtd->eraseregions[i].numblocks;j++){
88 mymtd->unlock(mymtd,mymtd->eraseregions[i].offset + j * mymtd->eraseregions[i].erasesize,mymtd->eraseregions[i].erasesize);
89 }
90 }
91 }
92
93#ifdef CONFIG_MTD_PARTITIONS
94 nr_parts = parse_mtd_partitions(mymtd, probes, &parts, 0);
95
96 if (nr_parts > 0) {
97 add_mtd_partitions(mymtd, parts, nr_parts);
98 return 0;
99 }
100#endif
101 /* No recognised partitioning schemes found - use defaults */
102 nr_parts = epxa_default_partitions(mymtd, &parts);
103 if (nr_parts > 0) {
104 add_mtd_partitions(mymtd, parts, nr_parts);
105 return 0;
106 }
107
108 /* If all else fails... */
109 add_mtd_device(mymtd);
110 return 0;
111}
112
113static void __exit epxa_mtd_cleanup(void)
114{
115 if (mymtd) {
116 if (nr_parts)
117 del_mtd_partitions(mymtd);
118 else
119 del_mtd_device(mymtd);
120 map_destroy(mymtd);
121 }
122 if (epxa_map.virt) {
123 iounmap((void *)epxa_map.virt);
124 epxa_map.virt = 0;
125 }
126}
127
128
129/*
130 * This will do for now, once we decide which bootldr we're finally
131 * going to use then we'll remove this function and do it properly
132 *
133 * Partions are currently (as offsets from base of flash):
134 * 0x00000000 - 0x003FFFFF - bootloader (!)
135 * 0x00400000 - 0x00FFFFFF - Flashdisk
136 */
137
138static int __init epxa_default_partitions(struct mtd_info *master, struct mtd_partition **pparts)
139{
140 struct mtd_partition *parts;
141 int ret, i;
142 int npartitions = 0;
143 char *names;
144 const char *name = "jffs";
145
146 printk("Using default partitions for %s\n",BOARD_NAME);
147 npartitions=1;
148 parts = kmalloc(npartitions*sizeof(*parts)+strlen(name), GFP_KERNEL);
149 memzero(parts,npartitions*sizeof(*parts)+strlen(name));
150 if (!parts) {
151 ret = -ENOMEM;
152 goto out;
153 }
154 i=0;
155 names = (char *)&parts[npartitions];
156 parts[i].name = names;
157 names += strlen(name) + 1;
158 strcpy(parts[i].name, name);
159
160#ifdef CONFIG_EPXA10DB
161 parts[i].size = FLASH_SIZE-0x00400000;
162 parts[i].offset = 0x00400000;
163#else
164 parts[i].size = FLASH_SIZE-0x00180000;
165 parts[i].offset = 0x00180000;
166#endif
167
168 out:
169 *pparts = parts;
170 return npartitions;
171}
172
173
174module_init(epxa_mtd_init);
175module_exit(epxa_mtd_cleanup);
176
177MODULE_AUTHOR("Clive Davies");
178MODULE_DESCRIPTION("Altera epxa mtd flash map");
179MODULE_LICENSE("GPL");
diff --git a/drivers/net/arm/Kconfig b/drivers/net/arm/Kconfig
index 470364deded..625184b65e3 100644
--- a/drivers/net/arm/Kconfig
+++ b/drivers/net/arm/Kconfig
@@ -31,16 +31,3 @@ config ARM_ETHERH
31 help 31 help
32 If you have an Acorn system with one of these network cards, you 32 If you have an Acorn system with one of these network cards, you
33 should say Y to this option if you wish to use it with Linux. 33 should say Y to this option if you wish to use it with Linux.
34
35config ARM_ETHER00
36 tristate "Altera Ether00 support"
37 depends on NET_ETHERNET && ARM && ARCH_CAMELOT
38 help
39 This is the driver for Altera's ether00 ethernet mac IP core. Say
40 Y here if you want to build support for this into the kernel. It
41 is also available as a module (say M here) that can be inserted/
42 removed from the kernel at the same time as the PLD is configured.
43 If this driver is running on an epxa10 development board then it
44 will generate a suitable hw address based on the board serial
45 number (MTD support is required for this). Otherwise you will
46 need to set a suitable hw address using ifconfig.
diff --git a/drivers/net/arm/Makefile b/drivers/net/arm/Makefile
index b0d706834d8..bc263edf06a 100644
--- a/drivers/net/arm/Makefile
+++ b/drivers/net/arm/Makefile
@@ -4,7 +4,6 @@
4# 4#
5 5
6obj-$(CONFIG_ARM_AM79C961A) += am79c961a.o 6obj-$(CONFIG_ARM_AM79C961A) += am79c961a.o
7obj-$(CONFIG_ARM_ETHER00) += ether00.o
8obj-$(CONFIG_ARM_ETHERH) += etherh.o 7obj-$(CONFIG_ARM_ETHERH) += etherh.o
9obj-$(CONFIG_ARM_ETHER3) += ether3.o 8obj-$(CONFIG_ARM_ETHER3) += ether3.o
10obj-$(CONFIG_ARM_ETHER1) += ether1.o 9obj-$(CONFIG_ARM_ETHER1) += ether1.o
diff --git a/drivers/net/arm/ether00.c b/drivers/net/arm/ether00.c
deleted file mode 100644
index 4f1f4e31bda..00000000000
--- a/drivers/net/arm/ether00.c
+++ /dev/null
@@ -1,1017 +0,0 @@
1/*
2 * drivers/net/ether00.c
3 *
4 * Copyright (C) 2001 Altera Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/* includes */
22#include <linux/config.h>
23#include <linux/pci.h>
24#include <linux/sched.h>
25#include <linux/netdevice.h>
26#include <linux/skbuff.h>
27#include <linux/etherdevice.h>
28#include <linux/module.h>
29#include <linux/tqueue.h>
30#include <linux/mtd/mtd.h>
31#include <linux/pld/pld_hotswap.h>
32#include <asm/arch/excalibur.h>
33#include <asm/arch/hardware.h>
34#include <asm/irq.h>
35#include <asm/io.h>
36#include <asm/sizes.h>
37
38#include <asm/arch/ether00.h>
39#include <asm/arch/tdkphy.h>
40
41
42MODULE_AUTHOR("Clive Davies");
43MODULE_DESCRIPTION("Altera Ether00 IP core driver");
44MODULE_LICENSE("GPL");
45
46#define PKT_BUF_SZ 1540 /* Size of each rx buffer */
47#define ETH_NR 4 /* Number of MACs this driver supports */
48
49#define DEBUG(x)
50
51#define __dma_va(x) (unsigned int)((unsigned int)priv->dma_data+(((unsigned int)(x))&(EXC_SPSRAM_BLOCK0_SIZE-1)))
52#define __dma_pa(x) (unsigned int)(EXC_SPSRAM_BLOCK0_BASE+(((unsigned int)(x))-(unsigned int)priv->dma_data))
53
54#define ETHER00_BASE 0
55#define ETHER00_TYPE
56#define ETHER00_NAME "ether00"
57#define MAC_REG_SIZE 0x400 /* size of MAC register area */
58
59
60
61/* typedefs */
62
63/* The definition of the driver control structure */
64
65#define RX_NUM_BUFF 10
66#define RX_NUM_FDESC 10
67#define TX_NUM_FDESC 10
68
69struct tx_fda_ent{
70 FDA_DESC fd;
71 BUF_DESC bd;
72 BUF_DESC pad;
73};
74struct rx_fda_ent{
75 FDA_DESC fd;
76 BUF_DESC bd;
77 BUF_DESC pad;
78};
79struct rx_blist_ent{
80 FDA_DESC fd;
81 BUF_DESC bd;
82 BUF_DESC pad;
83};
84struct net_priv
85{
86 struct net_device_stats stats;
87 struct sk_buff* skb;
88 void* dma_data;
89 struct rx_blist_ent* rx_blist_vp;
90 struct rx_fda_ent* rx_fda_ptr;
91 struct tx_fda_ent* tx_fdalist_vp;
92 struct tq_struct tq_memupdate;
93 unsigned char memupdate_scheduled;
94 unsigned char rx_disabled;
95 unsigned char queue_stopped;
96 spinlock_t rx_lock;
97};
98
99static const char vendor_id[2]={0x07,0xed};
100
101#ifdef ETHER00_DEBUG
102
103/* Dump (most) registers for debugging puposes */
104
105static void dump_regs(struct net_device *dev){
106 struct net_priv* priv=dev->priv;
107 unsigned int* i;
108
109 printk("\n RX free descriptor area:\n");
110
111 for(i=(unsigned int*)priv->rx_fda_ptr;
112 i<((unsigned int*)(priv->rx_fda_ptr+RX_NUM_FDESC));){
113 printk("%#8x %#8x %#8x %#8x\n",*i,*(i+1),*(i+2),*(i+3));
114 i+=4;
115 }
116
117 printk("\n RX buffer list:\n");
118
119 for(i=(unsigned int*)priv->rx_blist_vp;
120 i<((unsigned int*)(priv->rx_blist_vp+RX_NUM_BUFF));){
121 printk("%#8x %#8x %#8x %#8x\n",*i,*(i+1),*(i+2),*(i+3));
122 i+=4;
123 }
124
125 printk("\n TX frame descriptor list:\n");
126
127 for(i=(unsigned int*)priv->tx_fdalist_vp;
128 i<((unsigned int*)(priv->tx_fdalist_vp+TX_NUM_FDESC));){
129 printk("%#8x %#8x %#8x %#8x\n",*i,*(i+1),*(i+2),*(i+3));
130 i+=4;
131 }
132
133 printk("\ndma ctl=%#x\n",readw(ETHER_DMA_CTL(dev->base_addr)));
134 printk("txfrmptr=%#x\n",readw(ETHER_TXFRMPTR(dev->base_addr)));
135 printk("txthrsh=%#x\n",readw(ETHER_TXTHRSH(dev->base_addr)));
136 printk("txpollctr=%#x\n",readw(ETHER_TXPOLLCTR(dev->base_addr)));
137 printk("blfrmptr=%#x\n",readw(ETHER_BLFRMPTR(dev->base_addr)));
138 printk("rxfragsize=%#x\n",readw(ETHER_RXFRAGSIZE(dev->base_addr)));
139 printk("tx_int_en=%#x\n",readw(ETHER_INT_EN(dev->base_addr)));
140 printk("fda_bas=%#x\n",readw(ETHER_FDA_BAS(dev->base_addr)));
141 printk("fda_lim=%#x\n",readw(ETHER_FDA_LIM(dev->base_addr)));
142 printk("int_src=%#x\n",readw(ETHER_INT_SRC(dev->base_addr)));
143 printk("pausecnt=%#x\n",readw(ETHER_PAUSECNT(dev->base_addr)));
144 printk("rempaucnt=%#x\n",readw(ETHER_REMPAUCNT(dev->base_addr)));
145 printk("txconfrmstat=%#x\n",readw(ETHER_TXCONFRMSTAT(dev->base_addr)));
146 printk("mac_ctl=%#x\n",readw(ETHER_MAC_CTL(dev->base_addr)));
147 printk("arc_ctl=%#x\n",readw(ETHER_ARC_CTL(dev->base_addr)));
148 printk("tx_ctl=%#x\n",readw(ETHER_TX_CTL(dev->base_addr)));
149}
150#endif /* ETHER00_DEBUG */
151
152
153static int ether00_write_phy(struct net_device *dev, short address, short value)
154{
155 volatile int count = 1024;
156 writew(value,ETHER_MD_DATA(dev->base_addr));
157 writew( ETHER_MD_CA_BUSY_MSK |
158 ETHER_MD_CA_WR_MSK |
159 (address & ETHER_MD_CA_ADDR_MSK),
160 ETHER_MD_CA(dev->base_addr));
161
162 /* Wait for the command to complete */
163 while((readw(ETHER_MD_CA(dev->base_addr)) & ETHER_MD_CA_BUSY_MSK)&&count){
164 count--;
165 }
166 if (!count){
167 printk("Write to phy failed, addr=%#x, data=%#x\n",address, value);
168 return -EIO;
169 }
170 return 0;
171}
172
173static int ether00_read_phy(struct net_device *dev, short address)
174{
175 volatile int count = 1024;
176 writew( ETHER_MD_CA_BUSY_MSK |
177 (address & ETHER_MD_CA_ADDR_MSK),
178 ETHER_MD_CA(dev->base_addr));
179
180 /* Wait for the command to complete */
181 while((readw(ETHER_MD_CA(dev->base_addr)) & ETHER_MD_CA_BUSY_MSK)&&count){
182 count--;
183 }
184 if (!count){
185 printk(KERN_WARNING "Read from phy timed out\n");
186 return -EIO;
187 }
188 return readw(ETHER_MD_DATA(dev->base_addr));
189}
190
191static void ether00_phy_int(int irq_num, void* dev_id, struct pt_regs* regs)
192{
193 struct net_device* dev=dev_id;
194 int irq_status;
195
196 irq_status=ether00_read_phy(dev, PHY_IRQ_CONTROL);
197
198 if(irq_status & PHY_IRQ_CONTROL_ANEG_COMP_INT_MSK){
199 /*
200 * Autonegotiation complete on epxa10db. The mac doesn't
201 * twig if we're in full duplex so we need to check the
202 * phy status register and configure the mac accordingly
203 */
204 if(ether00_read_phy(dev, PHY_STATUS)&(PHY_STATUS_10T_F_MSK|PHY_STATUS_100_X_F_MSK)){
205 int tmp;
206 tmp=readl(ETHER_MAC_CTL(dev->base_addr));
207 writel(tmp|ETHER_MAC_CTL_FULLDUP_MSK,ETHER_MAC_CTL(dev->base_addr));
208 }
209 }
210
211 if(irq_status&PHY_IRQ_CONTROL_LS_CHG_INT_MSK){
212
213 if(ether00_read_phy(dev, PHY_STATUS)& PHY_STATUS_LINK_MSK){
214 /* Link is up */
215 netif_carrier_on(dev);
216 //printk("Carrier on\n");
217 }else{
218 netif_carrier_off(dev);
219 //printk("Carrier off\n");
220
221 }
222 }
223
224}
225
226static void setup_blist_entry(struct sk_buff* skb,struct rx_blist_ent* blist_ent_ptr){
227 /* Make the buffer consistent with the cache as the mac is going to write
228 * directly into it*/
229 blist_ent_ptr->fd.FDSystem=(unsigned int)skb;
230 blist_ent_ptr->bd.BuffData=(char*)__pa(skb->data);
231 consistent_sync(skb->data,PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
232 /* align IP on 16 Byte (DMA_CTL set to skip 2 bytes) */
233 skb_reserve(skb,2);
234 blist_ent_ptr->bd.BuffLength=PKT_BUF_SZ-2;
235 blist_ent_ptr->fd.FDLength=1;
236 blist_ent_ptr->fd.FDCtl=FDCTL_COWNSFD_MSK;
237 blist_ent_ptr->bd.BDCtl=BDCTL_COWNSBD_MSK;
238}
239
240
241static int ether00_mem_init(struct net_device* dev)
242{
243 struct net_priv* priv=dev->priv;
244 struct tx_fda_ent *tx_fd_ptr,*tx_end_ptr;
245 struct rx_blist_ent* blist_ent_ptr;
246 int i;
247
248 /*
249 * Grab a block of on chip SRAM to contain the control stuctures for
250 * the ethernet MAC. This uncached becuase it needs to be accesses by both
251 * bus masters (cpu + mac). However, it shouldn't matter too much in terms
252 * of speed as its on chip memory
253 */
254 priv->dma_data=ioremap_nocache(EXC_SPSRAM_BLOCK0_BASE,EXC_SPSRAM_BLOCK0_SIZE );
255 if (!priv->dma_data)
256 return -ENOMEM;
257
258 priv->rx_fda_ptr=(struct rx_fda_ent*)priv->dma_data;
259 /*
260 * Now share it out amongst the Frame descriptors and the buffer list
261 */
262 priv->rx_blist_vp=(struct rx_blist_ent*)((unsigned int)priv->dma_data+RX_NUM_FDESC*sizeof(struct rx_fda_ent));
263
264 /*
265 *Initalise the FDA list
266 */
267 /* set ownership to the controller */
268 memset(priv->rx_fda_ptr,0x80,RX_NUM_FDESC*sizeof(struct rx_fda_ent));
269
270 /*
271 *Initialise the buffer list
272 */
273 blist_ent_ptr=priv->rx_blist_vp;
274 i=0;
275 while(blist_ent_ptr<(priv->rx_blist_vp+RX_NUM_BUFF)){
276 struct sk_buff *skb;
277 blist_ent_ptr->fd.FDLength=1;
278 skb=dev_alloc_skb(PKT_BUF_SZ);
279 if(skb){
280 setup_blist_entry(skb,blist_ent_ptr);
281 blist_ent_ptr->fd.FDNext=(FDA_DESC*)__dma_pa(blist_ent_ptr+1);
282 blist_ent_ptr->bd.BDStat=i++;
283 blist_ent_ptr++;
284 }
285 else
286 {
287 printk("Failed to initalise buffer list\n");
288 }
289
290 }
291 blist_ent_ptr--;
292 blist_ent_ptr->fd.FDNext=(FDA_DESC*)__dma_pa(priv->rx_blist_vp);
293
294 priv->tx_fdalist_vp=(struct tx_fda_ent*)(priv->rx_blist_vp+RX_NUM_BUFF);
295
296 /* Initialise the buffers to be a circular list. The mac will then go poll
297 * the list until it finds a frame ready to transmit */
298 tx_end_ptr=priv->tx_fdalist_vp+TX_NUM_FDESC;
299 for(tx_fd_ptr=priv->tx_fdalist_vp;tx_fd_ptr<tx_end_ptr;tx_fd_ptr++){
300 tx_fd_ptr->fd.FDNext=(FDA_DESC*)__dma_pa((tx_fd_ptr+1));
301 tx_fd_ptr->fd.FDCtl=1;
302 tx_fd_ptr->fd.FDStat=0;
303 tx_fd_ptr->fd.FDLength=1;
304
305 }
306 /* Change the last FDNext pointer to make a circular list */
307 tx_fd_ptr--;
308 tx_fd_ptr->fd.FDNext=(FDA_DESC*)__dma_pa(priv->tx_fdalist_vp);
309
310 /* Point the device at the chain of Rx and Tx Buffers */
311 writel((unsigned int)__dma_pa(priv->rx_fda_ptr),ETHER_FDA_BAS(dev->base_addr));
312 writel((RX_NUM_FDESC-1)*sizeof(struct rx_fda_ent),ETHER_FDA_LIM(dev->base_addr));
313 writel((unsigned int)__dma_pa(priv->rx_blist_vp),ETHER_BLFRMPTR(dev->base_addr));
314
315 writel((unsigned int)__dma_pa(priv->tx_fdalist_vp),ETHER_TXFRMPTR(dev->base_addr));
316
317 return 0;
318}
319
320
321void ether00_mem_update(void* dev_id)
322{
323 struct net_device* dev=dev_id;
324 struct net_priv* priv=dev->priv;
325 struct sk_buff* skb;
326 struct tx_fda_ent *fda_ptr=priv->tx_fdalist_vp;
327 struct rx_blist_ent* blist_ent_ptr;
328 unsigned long flags;
329
330 priv->tq_memupdate.sync=0;
331 //priv->tq_memupdate.list=
332 priv->memupdate_scheduled=0;
333
334 /* Transmit interrupt */
335 while(fda_ptr<(priv->tx_fdalist_vp+TX_NUM_FDESC)){
336 if(!(FDCTL_COWNSFD_MSK&fda_ptr->fd.FDCtl) && (ETHER_TX_STAT_COMP_MSK&fda_ptr->fd.FDStat)){
337 priv->stats.tx_packets++;
338 priv->stats.tx_bytes+=fda_ptr->bd.BuffLength;
339 skb=(struct sk_buff*)fda_ptr->fd.FDSystem;
340 //printk("%d:txcln:fda=%#x skb=%#x\n",jiffies,fda_ptr,skb);
341 dev_kfree_skb(skb);
342 fda_ptr->fd.FDSystem=0;
343 fda_ptr->fd.FDStat=0;
344 fda_ptr->fd.FDCtl=0;
345 }
346 fda_ptr++;
347 }
348 /* Fill in any missing buffers from the received queue */
349 spin_lock_irqsave(&priv->rx_lock,flags);
350 blist_ent_ptr=priv->rx_blist_vp;
351 while(blist_ent_ptr<(priv->rx_blist_vp+RX_NUM_BUFF)){
352 /* fd.FDSystem of 0 indicates we failed to allocate the buffer in the ISR */
353 if(!blist_ent_ptr->fd.FDSystem){
354 struct sk_buff *skb;
355 skb=dev_alloc_skb(PKT_BUF_SZ);
356 blist_ent_ptr->fd.FDSystem=(unsigned int)skb;
357 if(skb){
358 setup_blist_entry(skb,blist_ent_ptr);
359 }
360 else
361 {
362 break;
363 }
364 }
365 blist_ent_ptr++;
366 }
367 spin_unlock_irqrestore(&priv->rx_lock,flags);
368 if(priv->queue_stopped){
369 //printk("%d:cln:start q\n",jiffies);
370 netif_start_queue(dev);
371 }
372 if(priv->rx_disabled){
373 //printk("%d:enable_irq\n",jiffies);
374 priv->rx_disabled=0;
375 writel(ETHER_RX_CTL_RXEN_MSK,ETHER_RX_CTL(dev->base_addr));
376
377 }
378}
379
380
381static void ether00_int( int irq_num, void* dev_id, struct pt_regs* regs)
382{
383 struct net_device* dev=dev_id;
384 struct net_priv* priv=dev->priv;
385
386 unsigned int interruptValue;
387
388 interruptValue=readl(ETHER_INT_SRC(dev->base_addr));
389
390 //printk("INT_SRC=%x\n",interruptValue);
391
392 if(!(readl(ETHER_INT_SRC(dev->base_addr)) & ETHER_INT_SRC_IRQ_MSK))
393 {
394 return; /* Interrupt wasn't caused by us!! */
395 }
396
397 if(readl(ETHER_INT_SRC(dev->base_addr))&
398 (ETHER_INT_SRC_INTMACRX_MSK |
399 ETHER_INT_SRC_FDAEX_MSK |
400 ETHER_INT_SRC_BLEX_MSK)) {
401 struct rx_blist_ent* blist_ent_ptr;
402 struct rx_fda_ent* fda_ent_ptr;
403 struct sk_buff* skb;
404
405 fda_ent_ptr=priv->rx_fda_ptr;
406 spin_lock(&priv->rx_lock);
407 while(fda_ent_ptr<(priv->rx_fda_ptr+RX_NUM_FDESC)){
408 int result;
409
410 if(!(fda_ent_ptr->fd.FDCtl&FDCTL_COWNSFD_MSK))
411 {
412 /* This frame is ready for processing */
413 /*find the corresponding buffer in the bufferlist */
414 blist_ent_ptr=priv->rx_blist_vp+fda_ent_ptr->bd.BDStat;
415 skb=(struct sk_buff*)blist_ent_ptr->fd.FDSystem;
416
417 /* Pass this skb up the stack */
418 skb->dev=dev;
419 skb_put(skb,fda_ent_ptr->fd.FDLength);
420 skb->protocol=eth_type_trans(skb,dev);
421 skb->ip_summed=CHECKSUM_UNNECESSARY;
422 result=netif_rx(skb);
423 /* Update statistics */
424 priv->stats.rx_packets++;
425 priv->stats.rx_bytes+=fda_ent_ptr->fd.FDLength;
426
427 /* Free the FDA entry */
428 fda_ent_ptr->bd.BDStat=0xff;
429 fda_ent_ptr->fd.FDCtl=FDCTL_COWNSFD_MSK;
430
431 /* Allocate a new skb and point the bd entry to it */
432 blist_ent_ptr->fd.FDSystem=0;
433 skb=dev_alloc_skb(PKT_BUF_SZ);
434 //printk("allocskb=%#x\n",skb);
435 if(skb){
436 setup_blist_entry(skb,blist_ent_ptr);
437
438 }
439 else if(!priv->memupdate_scheduled){
440 int tmp;
441 /* There are no buffers at the moment, so schedule */
442 /* the background task to sort this out */
443 schedule_task(&priv->tq_memupdate);
444 priv->memupdate_scheduled=1;
445 printk(KERN_DEBUG "%s:No buffers",dev->name);
446 /* If this interrupt was due to a lack of buffers then
447 * we'd better stop the receiver too */
448 if(interruptValue&ETHER_INT_SRC_BLEX_MSK){
449 priv->rx_disabled=1;
450 tmp=readl(ETHER_INT_SRC(dev->base_addr));
451 writel(tmp&~ETHER_RX_CTL_RXEN_MSK,ETHER_RX_CTL(dev->base_addr));
452 printk(KERN_DEBUG "%s:Halting rx",dev->name);
453 }
454
455 }
456
457 }
458 fda_ent_ptr++;
459 }
460 spin_unlock(&priv->rx_lock);
461
462 /* Clear the interrupts */
463 writel(ETHER_INT_SRC_INTMACRX_MSK | ETHER_INT_SRC_FDAEX_MSK
464 | ETHER_INT_SRC_BLEX_MSK,ETHER_INT_SRC(dev->base_addr));
465
466 }
467
468 if(readl(ETHER_INT_SRC(dev->base_addr))&ETHER_INT_SRC_INTMACTX_MSK){
469
470 if(!priv->memupdate_scheduled){
471 schedule_task(&priv->tq_memupdate);
472 priv->memupdate_scheduled=1;
473 }
474 /* Clear the interrupt */
475 writel(ETHER_INT_SRC_INTMACTX_MSK,ETHER_INT_SRC(dev->base_addr));
476 }
477
478 if (readl(ETHER_INT_SRC(dev->base_addr)) & (ETHER_INT_SRC_SWINT_MSK|
479 ETHER_INT_SRC_INTEARNOT_MSK|
480 ETHER_INT_SRC_INTLINK_MSK|
481 ETHER_INT_SRC_INTEXBD_MSK|
482 ETHER_INT_SRC_INTTXCTLCMP_MSK))
483 {
484 /*
485 * Not using any of these so they shouldn't happen
486 *
487 * In the cased of INTEXBD - if you allocate more
488 * than 28 decsriptors you may need to think about this
489 */
490 printk("Not using this interrupt\n");
491 }
492
493 if (readl(ETHER_INT_SRC(dev->base_addr)) &
494 (ETHER_INT_SRC_INTSBUS_MSK |
495 ETHER_INT_SRC_INTNRABT_MSK
496 |ETHER_INT_SRC_DMPARERR_MSK))
497 {
498 /*
499 * Hardware errors, we can either ignore them and hope they go away
500 *or reset the device, I'll try the first for now to see if they happen
501 */
502 printk("Hardware error\n");
503 }
504}
505
506static void ether00_setup_ethernet_address(struct net_device* dev)
507{
508 int tmp;
509
510 dev->addr_len=6;
511 writew(0,ETHER_ARC_ADR(dev->base_addr));
512 writel((dev->dev_addr[0]<<24) |
513 (dev->dev_addr[1]<<16) |
514 (dev->dev_addr[2]<<8) |
515 dev->dev_addr[3],
516 ETHER_ARC_DATA(dev->base_addr));
517
518 writew(4,ETHER_ARC_ADR(dev->base_addr));
519 tmp=readl(ETHER_ARC_DATA(dev->base_addr));
520 tmp&=0xffff;
521 tmp|=(dev->dev_addr[4]<<24) | (dev->dev_addr[5]<<16);
522 writel(tmp, ETHER_ARC_DATA(dev->base_addr));
523 /* Enable this entry in the ARC */
524
525 writel(1,ETHER_ARC_ENA(dev->base_addr));
526
527 return;
528}
529
530
531static void ether00_reset(struct net_device *dev)
532{
533 /* reset the controller */
534 writew(ETHER_MAC_CTL_RESET_MSK,ETHER_MAC_CTL(dev->base_addr));
535
536 /*
537 * Make sure we're not going to send anything
538 */
539
540 writew(ETHER_TX_CTL_TXHALT_MSK,ETHER_TX_CTL(dev->base_addr));
541
542 /*
543 * Make sure we're not going to receive anything
544 */
545 writew(ETHER_RX_CTL_RXHALT_MSK,ETHER_RX_CTL(dev->base_addr));
546
547 /*
548 * Disable Interrupts for now, and set the burst size to 8 bytes
549 */
550
551 writel(ETHER_DMA_CTL_INTMASK_MSK |
552 ((8 << ETHER_DMA_CTL_DMBURST_OFST) & ETHER_DMA_CTL_DMBURST_MSK)
553 |(2<<ETHER_DMA_CTL_RXALIGN_OFST),
554 ETHER_DMA_CTL(dev->base_addr));
555
556
557 /*
558 * Set TxThrsh - start transmitting a packet after 1514
559 * bytes or when a packet is complete, whichever comes first
560 */
561 writew(1514,ETHER_TXTHRSH(dev->base_addr));
562
563 /*
564 * Set TxPollCtr. Each cycle is
565 * 61.44 microseconds with a 33 MHz bus
566 */
567 writew(1,ETHER_TXPOLLCTR(dev->base_addr));
568
569 /*
570 * Set Rx_Ctl - Turn off reception and let RxData turn it
571 * on later
572 */
573 writew(ETHER_RX_CTL_RXHALT_MSK,ETHER_RX_CTL(dev->base_addr));
574
575}
576
577
578static void ether00_set_multicast(struct net_device* dev)
579{
580 int count=dev->mc_count;
581
582 /* Set promiscuous mode if it's asked for. */
583
584 if (dev->flags&IFF_PROMISC){
585
586 writew( ETHER_ARC_CTL_COMPEN_MSK |
587 ETHER_ARC_CTL_BROADACC_MSK |
588 ETHER_ARC_CTL_GROUPACC_MSK |
589 ETHER_ARC_CTL_STATIONACC_MSK,
590 ETHER_ARC_CTL(dev->base_addr));
591 return;
592 }
593
594 /*
595 * Get all multicast packets if required, or if there are too
596 * many addresses to fit in hardware
597 */
598 if (dev->flags & IFF_ALLMULTI){
599 writew( ETHER_ARC_CTL_COMPEN_MSK |
600 ETHER_ARC_CTL_GROUPACC_MSK |
601 ETHER_ARC_CTL_BROADACC_MSK,
602 ETHER_ARC_CTL(dev->base_addr));
603 return;
604 }
605 if (dev->mc_count > (ETHER_ARC_SIZE - 1)){
606
607 printk(KERN_WARNING "Too many multicast addresses for hardware to filter - receiving all multicast packets\n");
608 writew( ETHER_ARC_CTL_COMPEN_MSK |
609 ETHER_ARC_CTL_GROUPACC_MSK |
610 ETHER_ARC_CTL_BROADACC_MSK,
611 ETHER_ARC_CTL(dev->base_addr));
612 return;
613 }
614
615 if(dev->mc_count){
616 struct dev_mc_list *mc_list_ent=dev->mc_list;
617 unsigned int temp,i;
618 DEBUG(printk("mc_count=%d mc_list=%#x\n",dev-> mc_count, dev->mc_list));
619 DEBUG(printk("mc addr=%02#x%02x%02x%02x%02x%02x\n",
620 mc_list_ent->dmi_addr[5],
621 mc_list_ent->dmi_addr[4],
622 mc_list_ent->dmi_addr[3],
623 mc_list_ent->dmi_addr[2],
624 mc_list_ent->dmi_addr[1],
625 mc_list_ent->dmi_addr[0]);)
626
627 /*
628 * The first 6 bytes are the MAC address, so
629 * don't change them!
630 */
631 writew(4,ETHER_ARC_ADR(dev->base_addr));
632 temp=readl(ETHER_ARC_DATA(dev->base_addr));
633 temp&=0xffff0000;
634
635 /* Disable the current multicast stuff */
636 writel(1,ETHER_ARC_ENA(dev->base_addr));
637
638 for(;;){
639 temp|=mc_list_ent->dmi_addr[1] |
640 mc_list_ent->dmi_addr[0]<<8;
641 writel(temp,ETHER_ARC_DATA(dev->base_addr));
642
643 i=readl(ETHER_ARC_ADR(dev->base_addr));
644 writew(i+4,ETHER_ARC_ADR(dev->base_addr));
645
646 temp=mc_list_ent->dmi_addr[5]|
647 mc_list_ent->dmi_addr[4]<<8 |
648 mc_list_ent->dmi_addr[3]<<16 |
649 mc_list_ent->dmi_addr[2]<<24;
650 writel(temp,ETHER_ARC_DATA(dev->base_addr));
651
652 count--;
653 if(!mc_list_ent->next || !count){
654 break;
655 }
656 DEBUG(printk("mc_list_next=%#x\n",mc_list_ent->next);)
657 mc_list_ent=mc_list_ent->next;
658
659
660 i=readl(ETHER_ARC_ADR(dev->base_addr));
661 writel(i+4,ETHER_ARC_ADR(dev->base_addr));
662
663 temp=mc_list_ent->dmi_addr[3]|
664 mc_list_ent->dmi_addr[2]<<8 |
665 mc_list_ent->dmi_addr[1]<<16 |
666 mc_list_ent->dmi_addr[0]<<24;
667 writel(temp,ETHER_ARC_DATA(dev->base_addr));
668
669 i=readl(ETHER_ARC_ADR(dev->base_addr));
670 writel(i+4,ETHER_ARC_ADR(dev->base_addr));
671
672 temp=mc_list_ent->dmi_addr[4]<<16 |
673 mc_list_ent->dmi_addr[5]<<24;
674
675 writel(temp,ETHER_ARC_DATA(dev->base_addr));
676
677 count--;
678 if(!mc_list_ent->next || !count){
679 break;
680 }
681 mc_list_ent=mc_list_ent->next;
682 }
683
684
685 if(count)
686 printk(KERN_WARNING "Multicast list size error\n");
687
688
689 writew( ETHER_ARC_CTL_BROADACC_MSK|
690 ETHER_ARC_CTL_COMPEN_MSK,
691 ETHER_ARC_CTL(dev->base_addr));
692
693 }
694
695 /* enable the active ARC enties */
696 writew((1<<(count+2))-1,ETHER_ARC_ENA(dev->base_addr));
697}
698
699
700static int ether00_open(struct net_device* dev)
701{
702 int result,tmp;
703 struct net_priv* priv;
704
705 if (!is_valid_ether_addr(dev->dev_addr))
706 return -EINVAL;
707
708 /* Install interrupt handlers */
709 result=request_irq(dev->irq,ether00_int,0,"ether00",dev);
710 if(result)
711 goto open_err1;
712
713 result=request_irq(2,ether00_phy_int,0,"ether00_phy",dev);
714 if(result)
715 goto open_err2;
716
717 ether00_reset(dev);
718 result=ether00_mem_init(dev);
719 if(result)
720 goto open_err3;
721
722
723 ether00_setup_ethernet_address(dev);
724
725 ether00_set_multicast(dev);
726
727 result=ether00_write_phy(dev,PHY_CONTROL, PHY_CONTROL_ANEGEN_MSK | PHY_CONTROL_RANEG_MSK);
728 if(result)
729 goto open_err4;
730 result=ether00_write_phy(dev,PHY_IRQ_CONTROL, PHY_IRQ_CONTROL_LS_CHG_IE_MSK |
731 PHY_IRQ_CONTROL_ANEG_COMP_IE_MSK);
732 if(result)
733 goto open_err4;
734
735 /* Start the device enable interrupts */
736 writew(ETHER_RX_CTL_RXEN_MSK
737// | ETHER_RX_CTL_STRIPCRC_MSK
738 | ETHER_RX_CTL_ENGOOD_MSK
739 | ETHER_RX_CTL_ENRXPAR_MSK| ETHER_RX_CTL_ENLONGERR_MSK
740 | ETHER_RX_CTL_ENOVER_MSK| ETHER_RX_CTL_ENCRCERR_MSK,
741 ETHER_RX_CTL(dev->base_addr));
742
743 writew(ETHER_TX_CTL_TXEN_MSK|
744 ETHER_TX_CTL_ENEXDEFER_MSK|
745 ETHER_TX_CTL_ENLCARR_MSK|
746 ETHER_TX_CTL_ENEXCOLL_MSK|
747 ETHER_TX_CTL_ENLATECOLL_MSK|
748 ETHER_TX_CTL_ENTXPAR_MSK|
749 ETHER_TX_CTL_ENCOMP_MSK,
750 ETHER_TX_CTL(dev->base_addr));
751
752 tmp=readl(ETHER_DMA_CTL(dev->base_addr));
753 writel(tmp&~ETHER_DMA_CTL_INTMASK_MSK,ETHER_DMA_CTL(dev->base_addr));
754
755 return 0;
756
757 open_err4:
758 ether00_reset(dev);
759 open_err3:
760 free_irq(2,dev);
761 open_err2:
762 free_irq(dev->irq,dev);
763 open_err1:
764 return result;
765
766}
767
768
769static int ether00_tx(struct sk_buff* skb, struct net_device* dev)
770{
771 struct net_priv *priv=dev->priv;
772 struct tx_fda_ent *fda_ptr;
773 int i;
774
775
776 /*
777 * Find an empty slot in which to stick the frame
778 */
779 fda_ptr=(struct tx_fda_ent*)__dma_va(readl(ETHER_TXFRMPTR(dev->base_addr)));
780 i=0;
781 while(i<TX_NUM_FDESC){
782 if (fda_ptr->fd.FDStat||(fda_ptr->fd.FDCtl & FDCTL_COWNSFD_MSK)){
783 fda_ptr =(struct tx_fda_ent*) __dma_va((struct tx_fda_ent*)fda_ptr->fd.FDNext);
784 }
785 else {
786 break;
787 }
788 i++;
789 }
790
791 /* Write the skb data from the cache*/
792 consistent_sync(skb->data,skb->len,PCI_DMA_TODEVICE);
793 fda_ptr->bd.BuffData=(char*)__pa(skb->data);
794 fda_ptr->bd.BuffLength=(unsigned short)skb->len;
795 /* Save the pointer to the skb for freeing later */
796 fda_ptr->fd.FDSystem=(unsigned int)skb;
797 fda_ptr->fd.FDStat=0;
798 /* Pass ownership of the buffers to the controller */
799 fda_ptr->fd.FDCtl=1;
800 fda_ptr->fd.FDCtl|=FDCTL_COWNSFD_MSK;
801
802 /* If the next buffer in the list is full, stop the queue */
803 fda_ptr=(struct tx_fda_ent*)__dma_va(fda_ptr->fd.FDNext);
804 if ((fda_ptr->fd.FDStat)||(fda_ptr->fd.FDCtl & FDCTL_COWNSFD_MSK)){
805 netif_stop_queue(dev);
806 priv->queue_stopped=1;
807 }
808
809 return 0;
810}
811
812static struct net_device_stats *ether00_stats(struct net_device* dev)
813{
814 struct net_priv *priv=dev->priv;
815 return &priv->stats;
816}
817
818
819static int ether00_stop(struct net_device* dev)
820{
821 struct net_priv *priv=dev->priv;
822 int tmp;
823
824 /* Stop/disable the device. */
825 tmp=readw(ETHER_RX_CTL(dev->base_addr));
826 tmp&=~(ETHER_RX_CTL_RXEN_MSK | ETHER_RX_CTL_ENGOOD_MSK);
827 tmp|=ETHER_RX_CTL_RXHALT_MSK;
828 writew(tmp,ETHER_RX_CTL(dev->base_addr));
829
830 tmp=readl(ETHER_TX_CTL(dev->base_addr));
831 tmp&=~ETHER_TX_CTL_TXEN_MSK;
832 tmp|=ETHER_TX_CTL_TXHALT_MSK;
833 writel(tmp,ETHER_TX_CTL(dev->base_addr));
834
835 /* Free up system resources */
836 free_irq(dev->irq,dev);
837 free_irq(2,dev);
838 iounmap(priv->dma_data);
839
840 return 0;
841}
842
843
844static void ether00_get_ethernet_address(struct net_device* dev)
845{
846 struct mtd_info *mymtd=NULL;
847 int i;
848 size_t retlen;
849
850 /*
851 * For the Epxa10 dev board (camelot), the ethernet MAC
852 * address is of the form 00:aa:aa:00:xx:xx where
853 * 00:aa:aa is the Altera vendor ID and xx:xx is the
854 * last 2 bytes of the board serial number, as programmed
855 * into the OTP area of the flash device on EBI1. If this
856 * isn't an expa10 dev board, or there's no mtd support to
857 * read the serial number from flash then we'll force the
858 * use to set their own mac address using ifconfig.
859 */
860
861#ifdef CONFIG_ARCH_CAMELOT
862#ifdef CONFIG_MTD
863 /* get the mtd_info structure for the first mtd device*/
864 for(i=0;i<MAX_MTD_DEVICES;i++){
865 mymtd=get_mtd_device(NULL,i);
866 if(!mymtd||!strcmp(mymtd->name,"EPXA10DB flash"))
867 break;
868 }
869
870 if(!mymtd || !mymtd->read_user_prot_reg){
871 printk(KERN_WARNING "%s: Failed to read MAC address from flash\n",dev->name);
872 }else{
873 mymtd->read_user_prot_reg(mymtd,2,1,&retlen,&dev->dev_addr[5]);
874 mymtd->read_user_prot_reg(mymtd,3,1,&retlen,&dev->dev_addr[4]);
875 dev->dev_addr[3]=0;
876 dev->dev_addr[2]=vendor_id[1];
877 dev->dev_addr[1]=vendor_id[0];
878 dev->dev_addr[0]=0;
879 }
880#else
881 printk(KERN_WARNING "%s: MTD support required to read MAC address from EPXA10 dev board\n", dev->name);
882#endif
883#endif
884
885 if (!is_valid_ether_addr(dev->dev_addr))
886 printk("%s: Invalid ethernet MAC address. Please set using "
887 "ifconfig\n", dev->name);
888
889}
890
891/*
892 * Keep a mapping of dev_info addresses -> port lines to use when
893 * removing ports dev==NULL indicates unused entry
894 */
895
896
897static struct net_device* dev_list[ETH_NR];
898
899static int ether00_add_device(struct pldhs_dev_info* dev_info,void* dev_ps_data)
900{
901 struct net_device *dev;
902 struct net_priv *priv;
903 void *map_addr;
904 int result;
905 int i;
906
907 i=0;
908 while(dev_list[i] && i < ETH_NR)
909 i++;
910
911 if(i==ETH_NR){
912 printk(KERN_WARNING "ether00: Maximum number of ports reached\n");
913 return 0;
914 }
915
916
917 if (!request_mem_region(dev_info->base_addr, MAC_REG_SIZE, "ether00"))
918 return -EBUSY;
919
920 dev = alloc_etherdev(sizeof(struct net_priv));
921 if(!dev) {
922 result = -ENOMEM;
923 goto out_release;
924 }
925 priv = dev->priv;
926
927 priv->tq_memupdate.routine=ether00_mem_update;
928 priv->tq_memupdate.data=(void*) dev;
929
930 spin_lock_init(&priv->rx_lock);
931
932 map_addr=ioremap_nocache(dev_info->base_addr,SZ_4K);
933 if(!map_addr){
934 result = -ENOMEM;
935 out_kfree;
936 }
937
938 dev->open=ether00_open;
939 dev->stop=ether00_stop;
940 dev->set_multicast_list=ether00_set_multicast;
941 dev->hard_start_xmit=ether00_tx;
942 dev->get_stats=ether00_stats;
943
944 ether00_get_ethernet_address(dev);
945
946 SET_MODULE_OWNER(dev);
947
948 dev->base_addr=(unsigned int)map_addr;
949 dev->irq=dev_info->irq;
950 dev->features=NETIF_F_DYNALLOC | NETIF_F_HW_CSUM;
951
952 result=register_netdev(dev);
953 if(result){
954 printk("Ether00: Error %i registering driver\n",result);
955 goto out_unmap;
956 }
957 printk("registered ether00 device at %#x\n",dev_info->base_addr);
958
959 dev_list[i]=dev;
960
961 return result;
962
963 out_unmap:
964 iounmap(map_addr);
965 out_kfree:
966 free_netdev(dev);
967 out_release:
968 release_mem_region(dev_info->base_addr, MAC_REG_SIZE);
969 return result;
970}
971
972
973static int ether00_remove_devices(void)
974{
975 int i;
976
977 for(i=0;i<ETH_NR;i++){
978 if(dev_list[i]){
979 netif_device_detach(dev_list[i]);
980 unregister_netdev(dev_list[i]);
981 iounmap((void*)dev_list[i]->base_addr);
982 release_mem_region(dev_list[i]->base_addr, MAC_REG_SIZE);
983 free_netdev(dev_list[i]);
984 dev_list[i]=0;
985 }
986 }
987 return 0;
988}
989
990static struct pld_hotswap_ops ether00_pldhs_ops={
991 .name = ETHER00_NAME,
992 .add_device = ether00_add_device,
993 .remove_devices = ether00_remove_devices,
994};
995
996
997static void __exit ether00_cleanup_module(void)
998{
999 int result;
1000 result=ether00_remove_devices();
1001 if(result)
1002 printk(KERN_WARNING "ether00: failed to remove all devices\n");
1003
1004 pldhs_unregister_driver(ETHER00_NAME);
1005}
1006module_exit(ether00_cleanup_module);
1007
1008
1009static int __init ether00_mod_init(void)
1010{
1011 printk("mod init\n");
1012 return pldhs_register_driver(&ether00_pldhs_ops);
1013
1014}
1015
1016module_init(ether00_mod_init);
1017
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 812bae62c8e..47ea8338c03 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -359,29 +359,6 @@ config SERIAL_21285_CONSOLE
359 your boot loader (lilo or loadlin) about how to pass options to the 359 your boot loader (lilo or loadlin) about how to pass options to the
360 kernel at boot time.) 360 kernel at boot time.)
361 361
362config SERIAL_UART00
363 bool "Excalibur serial port (uart00) support"
364 depends on ARM && ARCH_CAMELOT
365 select SERIAL_CORE
366 help
367 Say Y here if you want to use the hard logic uart on Excalibur. This
368 driver also supports soft logic implementations of this uart core.
369
370config SERIAL_UART00_CONSOLE
371 bool "Support for console on Excalibur serial port"
372 depends on SERIAL_UART00
373 select SERIAL_CORE_CONSOLE
374 help
375 Say Y here if you want to support a serial console on an Excalibur
376 hard logic uart or uart00 IP core.
377
378 Even if you say Y here, the currently visible virtual console
379 (/dev/tty0) will still be used as the system console by default, but
380 you can alter that using a kernel command line option such as
381 "console=ttyS1". (Try "man bootparam" or see the documentation of
382 your boot loader (lilo or loadlin) about how to pass options to the
383 kernel at boot time.)
384
385config SERIAL_MPSC 362config SERIAL_MPSC
386 bool "Marvell MPSC serial port support" 363 bool "Marvell MPSC serial port support"
387 depends on PPC32 && MV64X60 364 depends on PPC32 && MV64X60
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index d7c7c7180e3..137148bba4f 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -29,7 +29,6 @@ obj-$(CONFIG_SERIAL_CLPS711X) += clps711x.o
29obj-$(CONFIG_SERIAL_PXA) += pxa.o 29obj-$(CONFIG_SERIAL_PXA) += pxa.o
30obj-$(CONFIG_SERIAL_SA1100) += sa1100.o 30obj-$(CONFIG_SERIAL_SA1100) += sa1100.o
31obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o 31obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o
32obj-$(CONFIG_SERIAL_UART00) += uart00.o
33obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o 32obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o
34obj-$(CONFIG_SERIAL_SUNZILOG) += sunzilog.o 33obj-$(CONFIG_SERIAL_SUNZILOG) += sunzilog.o
35obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o 34obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o
diff --git a/drivers/serial/uart00.c b/drivers/serial/uart00.c
deleted file mode 100644
index 47b504ff38b..00000000000
--- a/drivers/serial/uart00.c
+++ /dev/null
@@ -1,782 +0,0 @@
1/*
2 * linux/drivers/serial/uart00.c
3 *
4 * Driver for UART00 serial ports
5 *
6 * Based on drivers/char/serial_amba.c, by ARM Limited &
7 * Deep Blue Solutions Ltd.
8 * Copyright 2001 Altera Corporation
9 *
10 * Update for 2.6.4 by Dirk Behme <dirk.behme@de.bosch.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * $Id: uart00.c,v 1.35 2002/07/28 10:03:28 rmk Exp $
27 *
28 */
29#include <linux/config.h>
30
31#if defined(CONFIG_SERIAL_UART00_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
32#define SUPPORT_SYSRQ
33#endif
34
35#include <linux/module.h>
36#include <linux/ioport.h>
37#include <linux/init.h>
38#include <linux/console.h>
39#include <linux/sysrq.h>
40#include <linux/tty.h>
41#include <linux/tty_flip.h>
42#include <linux/serial_core.h>
43#include <linux/serial.h>
44
45#include <asm/io.h>
46#include <asm/irq.h>
47#include <asm/sizes.h>
48
49#include <asm/arch/excalibur.h>
50#define UART00_TYPE (volatile unsigned int*)
51#include <asm/arch/uart00.h>
52#include <asm/arch/int_ctrl00.h>
53
54#define UART_NR 2
55
56#define SERIAL_UART00_NAME "ttyUA"
57#define SERIAL_UART00_MAJOR 204
58#define SERIAL_UART00_MINOR 16 /* Temporary - will change in future */
59#define SERIAL_UART00_NR UART_NR
60#define UART_PORT_SIZE 0x50
61
62#define UART00_ISR_PASS_LIMIT 256
63
64/*
65 * Access macros for the UART00 UARTs
66 */
67#define UART_GET_INT_STATUS(p) inl(UART_ISR((p)->membase))
68#define UART_PUT_IES(p, c) outl(c,UART_IES((p)->membase))
69#define UART_GET_IES(p) inl(UART_IES((p)->membase))
70#define UART_PUT_IEC(p, c) outl(c,UART_IEC((p)->membase))
71#define UART_GET_IEC(p) inl(UART_IEC((p)->membase))
72#define UART_PUT_CHAR(p, c) outl(c,UART_TD((p)->membase))
73#define UART_GET_CHAR(p) inl(UART_RD((p)->membase))
74#define UART_GET_RSR(p) inl(UART_RSR((p)->membase))
75#define UART_GET_RDS(p) inl(UART_RDS((p)->membase))
76#define UART_GET_MSR(p) inl(UART_MSR((p)->membase))
77#define UART_GET_MCR(p) inl(UART_MCR((p)->membase))
78#define UART_PUT_MCR(p, c) outl(c,UART_MCR((p)->membase))
79#define UART_GET_MC(p) inl(UART_MC((p)->membase))
80#define UART_PUT_MC(p, c) outl(c,UART_MC((p)->membase))
81#define UART_GET_TSR(p) inl(UART_TSR((p)->membase))
82#define UART_GET_DIV_HI(p) inl(UART_DIV_HI((p)->membase))
83#define UART_PUT_DIV_HI(p,c) outl(c,UART_DIV_HI((p)->membase))
84#define UART_GET_DIV_LO(p) inl(UART_DIV_LO((p)->membase))
85#define UART_PUT_DIV_LO(p,c) outl(c,UART_DIV_LO((p)->membase))
86#define UART_RX_DATA(s) ((s) & UART_RSR_RX_LEVEL_MSK)
87#define UART_TX_READY(s) (((s) & UART_TSR_TX_LEVEL_MSK) < 15)
88//#define UART_TX_EMPTY(p) ((UART_GET_FR(p) & UART00_UARTFR_TMSK) == 0)
89
90static void uart00_stop_tx(struct uart_port *port)
91{
92 UART_PUT_IEC(port, UART_IEC_TIE_MSK);
93}
94
95static void uart00_stop_rx(struct uart_port *port)
96{
97 UART_PUT_IEC(port, UART_IEC_RE_MSK);
98}
99
100static void uart00_enable_ms(struct uart_port *port)
101{
102 UART_PUT_IES(port, UART_IES_ME_MSK);
103}
104
105static void
106uart00_rx_chars(struct uart_port *port, struct pt_regs *regs)
107{
108 struct tty_struct *tty = port->info->tty;
109 unsigned int status, ch, rds, flg, ignored = 0;
110
111 status = UART_GET_RSR(port);
112 while (UART_RX_DATA(status)) {
113 /*
114 * We need to read rds before reading the
115 * character from the fifo
116 */
117 rds = UART_GET_RDS(port);
118 ch = UART_GET_CHAR(port);
119 port->icount.rx++;
120
121 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
122 goto ignore_char;
123
124 flg = TTY_NORMAL;
125
126 /*
127 * Note that the error handling code is
128 * out of the main execution path
129 */
130 if (rds & (UART_RDS_BI_MSK |UART_RDS_FE_MSK|
131 UART_RDS_PE_MSK |UART_RDS_PE_MSK))
132 goto handle_error;
133 if (uart_handle_sysrq_char(port, ch, regs))
134 goto ignore_char;
135
136 error_return:
137 tty_insert_flip_char(tty, ch, flg);
138
139 ignore_char:
140 status = UART_GET_RSR(port);
141 }
142 out:
143 tty_flip_buffer_push(tty);
144 return;
145
146 handle_error:
147 if (rds & UART_RDS_BI_MSK) {
148 status &= ~(UART_RDS_FE_MSK | UART_RDS_PE_MSK);
149 port->icount.brk++;
150 if (uart_handle_break(port))
151 goto ignore_char;
152 } else if (rds & UART_RDS_PE_MSK)
153 port->icount.parity++;
154 else if (rds & UART_RDS_FE_MSK)
155 port->icount.frame++;
156 if (rds & UART_RDS_OE_MSK)
157 port->icount.overrun++;
158
159 if (rds & port->ignore_status_mask) {
160 if (++ignored > 100)
161 goto out;
162 goto ignore_char;
163 }
164 rds &= port->read_status_mask;
165
166 if (rds & UART_RDS_BI_MSK)
167 flg = TTY_BREAK;
168 else if (rds & UART_RDS_PE_MSK)
169 flg = TTY_PARITY;
170 else if (rds & UART_RDS_FE_MSK)
171 flg = TTY_FRAME;
172
173 if (rds & UART_RDS_OE_MSK) {
174 /*
175 * CHECK: does overrun affect the current character?
176 * ASSUMPTION: it does not.
177 */
178 tty_insert_flip_char(tty, ch, flg);
179 ch = 0;
180 flg = TTY_OVERRUN;
181 }
182#ifdef SUPPORT_SYSRQ
183 port->sysrq = 0;
184#endif
185 goto error_return;
186}
187
188static void uart00_tx_chars(struct uart_port *port)
189{
190 struct circ_buf *xmit = &port->info->xmit;
191 int count;
192
193 if (port->x_char) {
194 while ((UART_GET_TSR(port) & UART_TSR_TX_LEVEL_MSK) == 15)
195 barrier();
196 UART_PUT_CHAR(port, port->x_char);
197 port->icount.tx++;
198 port->x_char = 0;
199 return;
200 }
201 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
202 uart00_stop_tx(port);
203 return;
204 }
205
206 count = port->fifosize >> 1;
207 do {
208 while ((UART_GET_TSR(port) & UART_TSR_TX_LEVEL_MSK) == 15)
209 barrier();
210 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
211 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
212 port->icount.tx++;
213 if (uart_circ_empty(xmit))
214 break;
215 } while (--count > 0);
216
217 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
218 uart_write_wakeup(port);
219
220 if (uart_circ_empty(xmit))
221 uart00_stop_tx(port);
222}
223
224static void uart00_start_tx(struct uart_port *port)
225{
226 UART_PUT_IES(port, UART_IES_TIE_MSK);
227 uart00_tx_chars(port);
228}
229
230static void uart00_modem_status(struct uart_port *port)
231{
232 unsigned int status;
233
234 status = UART_GET_MSR(port);
235
236 if (!(status & (UART_MSR_DCTS_MSK | UART_MSR_DDSR_MSK |
237 UART_MSR_TERI_MSK | UART_MSR_DDCD_MSK)))
238 return;
239
240 if (status & UART_MSR_DDCD_MSK)
241 uart_handle_dcd_change(port, status & UART_MSR_DCD_MSK);
242
243 if (status & UART_MSR_DDSR_MSK)
244 port->icount.dsr++;
245
246 if (status & UART_MSR_DCTS_MSK)
247 uart_handle_cts_change(port, status & UART_MSR_CTS_MSK);
248
249 wake_up_interruptible(&port->info->delta_msr_wait);
250}
251
252static irqreturn_t uart00_int(int irq, void *dev_id, struct pt_regs *regs)
253{
254 struct uart_port *port = dev_id;
255 unsigned int status, pass_counter = 0;
256
257 status = UART_GET_INT_STATUS(port);
258 do {
259 if (status & UART_ISR_RI_MSK)
260 uart00_rx_chars(port, regs);
261 if (status & UART_ISR_MI_MSK)
262 uart00_modem_status(port);
263 if (status & (UART_ISR_TI_MSK | UART_ISR_TII_MSK))
264 uart00_tx_chars(port);
265 if (pass_counter++ > UART00_ISR_PASS_LIMIT)
266 break;
267
268 status = UART_GET_INT_STATUS(port);
269 } while (status);
270
271 return IRQ_HANDLED;
272}
273
274static unsigned int uart00_tx_empty(struct uart_port *port)
275{
276 return UART_GET_TSR(port) & UART_TSR_TX_LEVEL_MSK? 0 : TIOCSER_TEMT;
277}
278
279static unsigned int uart00_get_mctrl(struct uart_port *port)
280{
281 unsigned int result = 0;
282 unsigned int status;
283
284 status = UART_GET_MSR(port);
285 if (status & UART_MSR_DCD_MSK)
286 result |= TIOCM_CAR;
287 if (status & UART_MSR_DSR_MSK)
288 result |= TIOCM_DSR;
289 if (status & UART_MSR_CTS_MSK)
290 result |= TIOCM_CTS;
291 if (status & UART_MSR_RI_MSK)
292 result |= TIOCM_RI;
293
294 return result;
295}
296
297static void uart00_set_mctrl_null(struct uart_port *port, unsigned int mctrl)
298{
299}
300
301static void uart00_break_ctl(struct uart_port *port, int break_state)
302{
303 unsigned long flags;
304 unsigned int mcr;
305
306 spin_lock_irqsave(&port->lock, flags);
307 mcr = UART_GET_MCR(port);
308 if (break_state == -1)
309 mcr |= UART_MCR_BR_MSK;
310 else
311 mcr &= ~UART_MCR_BR_MSK;
312 UART_PUT_MCR(port, mcr);
313 spin_unlock_irqrestore(&port->lock, flags);
314}
315
316static void
317uart00_set_termios(struct uart_port *port, struct termios *termios,
318 struct termios *old)
319{
320 unsigned int uart_mc, old_ies, baud, quot;
321 unsigned long flags;
322
323 /*
324 * We don't support CREAD (yet)
325 */
326 termios->c_cflag |= CREAD;
327
328 /*
329 * Ask the core to calculate the divisor for us.
330 */
331 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
332 quot = uart_get_divisor(port, baud);
333
334 /* byte size and parity */
335 switch (termios->c_cflag & CSIZE) {
336 case CS5:
337 uart_mc = UART_MC_CLS_CHARLEN_5;
338 break;
339 case CS6:
340 uart_mc = UART_MC_CLS_CHARLEN_6;
341 break;
342 case CS7:
343 uart_mc = UART_MC_CLS_CHARLEN_7;
344 break;
345 default: // CS8
346 uart_mc = UART_MC_CLS_CHARLEN_8;
347 break;
348 }
349 if (termios->c_cflag & CSTOPB)
350 uart_mc|= UART_MC_ST_TWO;
351 if (termios->c_cflag & PARENB) {
352 uart_mc |= UART_MC_PE_MSK;
353 if (!(termios->c_cflag & PARODD))
354 uart_mc |= UART_MC_EP_MSK;
355 }
356
357 spin_lock_irqsave(&port->lock, flags);
358
359 /*
360 * Update the per-port timeout.
361 */
362 uart_update_timeout(port, termios->c_cflag, baud);
363
364 port->read_status_mask = UART_RDS_OE_MSK;
365 if (termios->c_iflag & INPCK)
366 port->read_status_mask |= UART_RDS_FE_MSK | UART_RDS_PE_MSK;
367 if (termios->c_iflag & (BRKINT | PARMRK))
368 port->read_status_mask |= UART_RDS_BI_MSK;
369
370 /*
371 * Characters to ignore
372 */
373 port->ignore_status_mask = 0;
374 if (termios->c_iflag & IGNPAR)
375 port->ignore_status_mask |= UART_RDS_FE_MSK | UART_RDS_PE_MSK;
376 if (termios->c_iflag & IGNBRK) {
377 port->ignore_status_mask |= UART_RDS_BI_MSK;
378 /*
379 * If we're ignoring parity and break indicators,
380 * ignore overruns to (for real raw support).
381 */
382 if (termios->c_iflag & IGNPAR)
383 port->ignore_status_mask |= UART_RDS_OE_MSK;
384 }
385
386 /* first, disable everything */
387 old_ies = UART_GET_IES(port);
388
389 if (UART_ENABLE_MS(port, termios->c_cflag))
390 old_ies |= UART_IES_ME_MSK;
391
392 /* Set baud rate */
393 UART_PUT_DIV_LO(port, (quot & 0xff));
394 UART_PUT_DIV_HI(port, ((quot & 0xf00) >> 8));
395
396 UART_PUT_MC(port, uart_mc);
397 UART_PUT_IES(port, old_ies);
398
399 spin_unlock_irqrestore(&port->lock, flags);
400}
401
402static int uart00_startup(struct uart_port *port)
403{
404 int result;
405
406 /*
407 * Allocate the IRQ
408 */
409 result = request_irq(port->irq, uart00_int, 0, "uart00", port);
410 if (result) {
411 printk(KERN_ERR "Request of irq %d failed\n", port->irq);
412 return result;
413 }
414
415 /*
416 * Finally, enable interrupts. Use the TII interrupt to minimise
417 * the number of interrupts generated. If higher performance is
418 * needed, consider using the TI interrupt with a suitable FIFO
419 * threshold
420 */
421 UART_PUT_IES(port, UART_IES_RE_MSK | UART_IES_TIE_MSK);
422
423 return 0;
424}
425
426static void uart00_shutdown(struct uart_port *port)
427{
428 /*
429 * disable all interrupts, disable the port
430 */
431 UART_PUT_IEC(port, 0xff);
432
433 /* disable break condition and fifos */
434 UART_PUT_MCR(port, UART_GET_MCR(port) &~UART_MCR_BR_MSK);
435
436 /*
437 * Free the interrupt
438 */
439 free_irq(port->irq, port);
440}
441
442static const char *uart00_type(struct uart_port *port)
443{
444 return port->type == PORT_UART00 ? "Altera UART00" : NULL;
445}
446
447/*
448 * Release the memory region(s) being used by 'port'
449 */
450static void uart00_release_port(struct uart_port *port)
451{
452 release_mem_region(port->mapbase, UART_PORT_SIZE);
453
454#ifdef CONFIG_ARCH_CAMELOT
455 if (port->membase != (void*)IO_ADDRESS(EXC_UART00_BASE)) {
456 iounmap(port->membase);
457 }
458#endif
459}
460
461/*
462 * Request the memory region(s) being used by 'port'
463 */
464static int uart00_request_port(struct uart_port *port)
465{
466 return request_mem_region(port->mapbase, UART_PORT_SIZE, "serial_uart00")
467 != NULL ? 0 : -EBUSY;
468}
469
470/*
471 * Configure/autoconfigure the port.
472 */
473static void uart00_config_port(struct uart_port *port, int flags)
474{
475
476 /*
477 * Map the io memory if this is a soft uart
478 */
479 if (!port->membase)
480 port->membase = ioremap_nocache(port->mapbase,SZ_4K);
481
482 if (!port->membase)
483 printk(KERN_ERR "serial00: cannot map io memory\n");
484 else
485 port->type = PORT_UART00;
486
487}
488
489/*
490 * verify the new serial_struct (for TIOCSSERIAL).
491 */
492static int uart00_verify_port(struct uart_port *port, struct serial_struct *ser)
493{
494 int ret = 0;
495 if (ser->type != PORT_UNKNOWN && ser->type != PORT_UART00)
496 ret = -EINVAL;
497 if (ser->irq < 0 || ser->irq >= NR_IRQS)
498 ret = -EINVAL;
499 if (ser->baud_base < 9600)
500 ret = -EINVAL;
501 return ret;
502}
503
504static struct uart_ops uart00_pops = {
505 .tx_empty = uart00_tx_empty,
506 .set_mctrl = uart00_set_mctrl_null,
507 .get_mctrl = uart00_get_mctrl,
508 .stop_tx = uart00_stop_tx,
509 .start_tx = uart00_start_tx,
510 .stop_rx = uart00_stop_rx,
511 .enable_ms = uart00_enable_ms,
512 .break_ctl = uart00_break_ctl,
513 .startup = uart00_startup,
514 .shutdown = uart00_shutdown,
515 .set_termios = uart00_set_termios,
516 .type = uart00_type,
517 .release_port = uart00_release_port,
518 .request_port = uart00_request_port,
519 .config_port = uart00_config_port,
520 .verify_port = uart00_verify_port,
521};
522
523
524#ifdef CONFIG_ARCH_CAMELOT
525static struct uart_port epxa10db_port = {
526 .membase = (void*)IO_ADDRESS(EXC_UART00_BASE),
527 .mapbase = EXC_UART00_BASE,
528 .iotype = SERIAL_IO_MEM,
529 .irq = IRQ_UART,
530 .uartclk = EXC_AHB2_CLK_FREQUENCY,
531 .fifosize = 16,
532 .ops = &uart00_pops,
533 .flags = ASYNC_BOOT_AUTOCONF,
534};
535#endif
536
537
538#ifdef CONFIG_SERIAL_UART00_CONSOLE
539static void uart00_console_write(struct console *co, const char *s, unsigned count)
540{
541#ifdef CONFIG_ARCH_CAMELOT
542 struct uart_port *port = &epxa10db_port;
543 unsigned int status, old_ies;
544 int i;
545
546 /*
547 * First save the CR then disable the interrupts
548 */
549 old_ies = UART_GET_IES(port);
550 UART_PUT_IEC(port,0xff);
551
552 /*
553 * Now, do each character
554 */
555 for (i = 0; i < count; i++) {
556 do {
557 status = UART_GET_TSR(port);
558 } while (!UART_TX_READY(status));
559 UART_PUT_CHAR(port, s[i]);
560 if (s[i] == '\n') {
561 do {
562 status = UART_GET_TSR(port);
563 } while (!UART_TX_READY(status));
564 UART_PUT_CHAR(port, '\r');
565 }
566 }
567
568 /*
569 * Finally, wait for transmitter to become empty
570 * and restore the IES
571 */
572 do {
573 status = UART_GET_TSR(port);
574 } while (status & UART_TSR_TX_LEVEL_MSK);
575 UART_PUT_IES(port, old_ies);
576#endif
577}
578
579static void __init
580uart00_console_get_options(struct uart_port *port, int *baud,
581 int *parity, int *bits)
582{
583 unsigned int uart_mc, quot;
584
585 uart_mc = UART_GET_MC(port);
586
587 *parity = 'n';
588 if (uart_mc & UART_MC_PE_MSK) {
589 if (uart_mc & UART_MC_EP_MSK)
590 *parity = 'e';
591 else
592 *parity = 'o';
593 }
594
595 switch (uart_mc & UART_MC_CLS_MSK) {
596 case UART_MC_CLS_CHARLEN_5:
597 *bits = 5;
598 break;
599 case UART_MC_CLS_CHARLEN_6:
600 *bits = 6;
601 break;
602 case UART_MC_CLS_CHARLEN_7:
603 *bits = 7;
604 break;
605 case UART_MC_CLS_CHARLEN_8:
606 *bits = 8;
607 break;
608 }
609 quot = UART_GET_DIV_LO(port) | (UART_GET_DIV_HI(port) << 8);
610 *baud = port->uartclk / (16 *quot );
611}
612
613static int __init uart00_console_setup(struct console *co, char *options)
614{
615 struct uart_port *port;
616 int baud = 115200;
617 int bits = 8;
618 int parity = 'n';
619 int flow = 'n';
620
621#ifdef CONFIG_ARCH_CAMELOT
622 port = &epxa10db_port; ;
623#else
624 return -ENODEV;
625#endif
626 if (options)
627 uart_parse_options(options, &baud, &parity, &bits, &flow);
628 else
629 uart00_console_get_options(port, &baud, &parity, &bits);
630
631 return uart_set_options(port, co, baud, parity, bits, flow);
632}
633
634extern struct uart_driver uart00_reg;
635static struct console uart00_console = {
636 .name = SERIAL_UART00_NAME,
637 .write = uart00_console_write,
638 .device = uart_console_device,
639 .setup = uart00_console_setup,
640 .flags = CON_PRINTBUFFER,
641 .index = 0,
642 .data = &uart00_reg,
643};
644
645static int __init uart00_console_init(void)
646{
647 register_console(&uart00_console);
648 return 0;
649}
650console_initcall(uart00_console_init);
651
652#define UART00_CONSOLE &uart00_console
653#else
654#define UART00_CONSOLE NULL
655#endif
656
657static struct uart_driver uart00_reg = {
658 .owner = NULL,
659 .driver_name = SERIAL_UART00_NAME,
660 .dev_name = SERIAL_UART00_NAME,
661 .major = SERIAL_UART00_MAJOR,
662 .minor = SERIAL_UART00_MINOR,
663 .nr = UART_NR,
664 .cons = UART00_CONSOLE,
665};
666
667struct dev_port_entry{
668 unsigned int base_addr;
669 struct uart_port *port;
670};
671
672#ifdef CONFIG_PLD_HOTSWAP
673
674static struct dev_port_entry dev_port_map[UART_NR];
675
676/*
677 * Keep a mapping of dev_info addresses -> port lines to use when
678 * removing ports dev==NULL indicates unused entry
679 */
680
681struct uart00_ps_data{
682 unsigned int clk;
683 unsigned int fifosize;
684};
685
686int uart00_add_device(struct pldhs_dev_info* dev_info, void* dev_ps_data)
687{
688 struct uart00_ps_data* dev_ps=dev_ps_data;
689 struct uart_port * port;
690 int i,result;
691
692 i=0;
693 while(dev_port_map[i].port)
694 i++;
695
696 if(i==UART_NR){
697 printk(KERN_WARNING "uart00: Maximum number of ports reached\n");
698 return 0;
699 }
700
701 port=kmalloc(sizeof(struct uart_port),GFP_KERNEL);
702 if(!port)
703 return -ENOMEM;
704
705 printk("clk=%d fifo=%d\n",dev_ps->clk,dev_ps->fifosize);
706 port->membase=0;
707 port->mapbase=dev_info->base_addr;
708 port->iotype=SERIAL_IO_MEM;
709 port->irq=dev_info->irq;
710 port->uartclk=dev_ps->clk;
711 port->fifosize=dev_ps->fifosize;
712 port->ops=&uart00_pops;
713 port->line=i;
714 port->flags=ASYNC_BOOT_AUTOCONF;
715
716 result=uart_add_one_port(&uart00_reg, port);
717 if(result){
718 printk("uart_add_one_port returned %d\n",result);
719 return result;
720 }
721 dev_port_map[i].base_addr=dev_info->base_addr;
722 dev_port_map[i].port=port;
723 printk("uart00: added device at %x as ttyUA%d\n",dev_port_map[i].base_addr,i);
724 return 0;
725
726}
727
728int uart00_remove_devices(void)
729{
730 int i,result;
731
732
733 result=0;
734 for(i=1;i<UART_NR;i++){
735 if(dev_port_map[i].base_addr){
736 result=uart_remove_one_port(&uart00_reg, dev_port_map[i].port);
737 if(result)
738 return result;
739
740 /* port removed sucessfully, so now tidy up */
741 kfree(dev_port_map[i].port);
742 dev_port_map[i].base_addr=0;
743 dev_port_map[i].port=NULL;
744 }
745 }
746 return 0;
747
748}
749
750struct pld_hotswap_ops uart00_pldhs_ops={
751 .name = "uart00",
752 .add_device = uart00_add_device,
753 .remove_devices = uart00_remove_devices,
754};
755
756#endif
757
758static int __init uart00_init(void)
759{
760 int result;
761
762 printk(KERN_INFO "Serial: UART00 driver $Revision: 1.35 $\n");
763
764 printk(KERN_WARNING "serial_uart00:Using temporary major/minor pairs"
765 " - these WILL change in the future\n");
766
767 result = uart_register_driver(&uart00_reg);
768 if (result)
769 return result;
770#ifdef CONFIG_ARCH_CAMELOT
771 result = uart_add_one_port(&uart00_reg,&epxa10db_port);
772#endif
773 if (result)
774 uart_unregister_driver(&uart00_reg);
775
776#ifdef CONFIG_PLD_HOTSWAP
777 pldhs_register_driver(&uart00_pldhs_ops);
778#endif
779 return result;
780}
781
782__initcall(uart00_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-20 22:24:50 -0400