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-rw-r--r--drivers/video/via/Makefile2
-rw-r--r--drivers/video/via/chip.h11
-rw-r--r--drivers/video/via/dvi.c233
-rw-r--r--drivers/video/via/dvi.h7
-rw-r--r--drivers/video/via/global.c5
-rw-r--r--drivers/video/via/global.h3
-rw-r--r--drivers/video/via/hw.c330
-rw-r--r--drivers/video/via/hw.h17
-rw-r--r--drivers/video/via/iface.c78
-rw-r--r--drivers/video/via/iface.h38
-rw-r--r--drivers/video/via/lcd.c640
-rw-r--r--drivers/video/via/share.h56
-rw-r--r--drivers/video/via/via_utility.c12
-rw-r--r--drivers/video/via/via_utility.h1
-rw-r--r--drivers/video/via/viafbdev.c518
-rw-r--r--drivers/video/via/viafbdev.h6
-rw-r--r--drivers/video/via/viamode.c180
-rw-r--r--drivers/video/via/viamode.h8
18 files changed, 511 insertions, 1634 deletions
diff --git a/drivers/video/via/Makefile b/drivers/video/via/Makefile
index e533b4b6aba..eeed238ad6a 100644
--- a/drivers/video/via/Makefile
+++ b/drivers/video/via/Makefile
@@ -4,4 +4,4 @@
4 4
5obj-$(CONFIG_FB_VIA) += viafb.o 5obj-$(CONFIG_FB_VIA) += viafb.o
6 6
7viafb-y :=viafbdev.o hw.o iface.o via_i2c.o dvi.o lcd.o ioctl.o accel.o via_utility.o vt1636.o global.o tblDPASetting.o viamode.o tbl1636.o 7viafb-y :=viafbdev.o hw.o via_i2c.o dvi.o lcd.o ioctl.o accel.o via_utility.o vt1636.o global.o tblDPASetting.o viamode.o tbl1636.o
diff --git a/drivers/video/via/chip.h b/drivers/video/via/chip.h
index 474f428aea9..8c06bd3c0b4 100644
--- a/drivers/video/via/chip.h
+++ b/drivers/video/via/chip.h
@@ -107,7 +107,6 @@
107struct tmds_chip_information { 107struct tmds_chip_information {
108 int tmds_chip_name; 108 int tmds_chip_name;
109 int tmds_chip_slave_addr; 109 int tmds_chip_slave_addr;
110 int dvi_panel_id;
111 int data_mode; 110 int data_mode;
112 int output_interface; 111 int output_interface;
113 int i2c_port; 112 int i2c_port;
@@ -142,14 +141,9 @@ struct tmds_setting_information {
142 int iga_path; 141 int iga_path;
143 int h_active; 142 int h_active;
144 int v_active; 143 int v_active;
145 int bpp;
146 int refresh_rate;
147 int get_dvi_size_method;
148 int max_pixel_clock; 144 int max_pixel_clock;
149 int dvi_panel_size; 145 int max_hres;
150 int dvi_panel_hres; 146 int max_vres;
151 int dvi_panel_vres;
152 int native_size;
153}; 147};
154 148
155struct lvds_setting_information { 149struct lvds_setting_information {
@@ -160,7 +154,6 @@ struct lvds_setting_information {
160 int refresh_rate; 154 int refresh_rate;
161 int get_lcd_size_method; 155 int get_lcd_size_method;
162 int lcd_panel_id; 156 int lcd_panel_id;
163 int lcd_panel_size;
164 int lcd_panel_hres; 157 int lcd_panel_hres;
165 int lcd_panel_vres; 158 int lcd_panel_vres;
166 int display_method; 159 int display_method;
diff --git a/drivers/video/via/dvi.c b/drivers/video/via/dvi.c
index 67b36932212..abe59b8c7a0 100644
--- a/drivers/video/via/dvi.c
+++ b/drivers/video/via/dvi.c
@@ -23,11 +23,10 @@
23static void tmds_register_write(int index, u8 data); 23static void tmds_register_write(int index, u8 data);
24static int tmds_register_read(int index); 24static int tmds_register_read(int index);
25static int tmds_register_read_bytes(int index, u8 *buff, int buff_len); 25static int tmds_register_read_bytes(int index, u8 *buff, int buff_len);
26static int check_reduce_blanking_mode(int mode_index, 26static void dvi_get_panel_size_from_DDCv1(struct tmds_chip_information
27 int refresh_rate); 27 *tmds_chip, struct tmds_setting_information *tmds_setting);
28static int dvi_get_panel_size_from_DDCv1(void); 28static void dvi_get_panel_size_from_DDCv2(struct tmds_chip_information
29static int dvi_get_panel_size_from_DDCv2(void); 29 *tmds_chip, struct tmds_setting_information *tmds_setting);
30static unsigned char dvi_get_panel_info(void);
31static int viafb_dvi_query_EDID(void); 30static int viafb_dvi_query_EDID(void);
32 31
33static int check_tmds_chip(int device_id_subaddr, int device_id) 32static int check_tmds_chip(int device_id_subaddr, int device_id)
@@ -38,23 +37,24 @@ static int check_tmds_chip(int device_id_subaddr, int device_id)
38 return FAIL; 37 return FAIL;
39} 38}
40 39
41void viafb_init_dvi_size(void) 40void viafb_init_dvi_size(struct tmds_chip_information *tmds_chip,
41 struct tmds_setting_information *tmds_setting)
42{ 42{
43 DEBUG_MSG(KERN_INFO "viafb_init_dvi_size()\n"); 43 DEBUG_MSG(KERN_INFO "viafb_init_dvi_size()\n");
44 DEBUG_MSG(KERN_INFO
45 "viaparinfo->tmds_setting_info->get_dvi_size_method %d\n",
46 viaparinfo->tmds_setting_info->get_dvi_size_method);
47 44
48 switch (viaparinfo->tmds_setting_info->get_dvi_size_method) { 45 viafb_dvi_sense();
49 case GET_DVI_SIZE_BY_SYSTEM_BIOS: 46 switch (viafb_dvi_query_EDID()) {
47 case 1:
48 dvi_get_panel_size_from_DDCv1(tmds_chip, tmds_setting);
50 break; 49 break;
51 case GET_DVI_SZIE_BY_HW_STRAPPING: 50 case 2:
51 dvi_get_panel_size_from_DDCv2(tmds_chip, tmds_setting);
52 break; 52 break;
53 case GET_DVI_SIZE_BY_VGA_BIOS:
54 default: 53 default:
55 dvi_get_panel_info(); 54 printk(KERN_WARNING "viafb_init_dvi_size: DVI panel size undetected!\n");
56 break; 55 break;
57 } 56 }
57
58 return; 58 return;
59} 59}
60 60
@@ -189,42 +189,14 @@ static int tmds_register_read_bytes(int index, u8 *buff, int buff_len)
189 return 0; 189 return 0;
190} 190}
191 191
192static int check_reduce_blanking_mode(int mode_index,
193 int refresh_rate)
194{
195 if (refresh_rate != 60)
196 return false;
197
198 switch (mode_index) {
199 /* Following modes have reduce blanking mode. */
200 case VIA_RES_1360X768:
201 case VIA_RES_1400X1050:
202 case VIA_RES_1440X900:
203 case VIA_RES_1600X900:
204 case VIA_RES_1680X1050:
205 case VIA_RES_1920X1080:
206 case VIA_RES_1920X1200:
207 break;
208
209 default:
210 DEBUG_MSG(KERN_INFO
211 "This dvi mode %d have no reduce blanking mode!\n",
212 mode_index);
213 return false;
214 }
215
216 return true;
217}
218
219/* DVI Set Mode */ 192/* DVI Set Mode */
220void viafb_dvi_set_mode(int video_index, int mode_bpp, int set_iga) 193void viafb_dvi_set_mode(struct VideoModeTable *mode, int mode_bpp,
194 int set_iga)
221{ 195{
222 struct VideoModeTable *videoMode = NULL; 196 struct VideoModeTable *rb_mode;
223 struct crt_mode_table *pDviTiming; 197 struct crt_mode_table *pDviTiming;
224 unsigned long desirePixelClock, maxPixelClock; 198 unsigned long desirePixelClock, maxPixelClock;
225 int status = 0; 199 pDviTiming = mode->crtc;
226 videoMode = viafb_get_modetbl_pointer(video_index);
227 pDviTiming = videoMode->crtc;
228 desirePixelClock = pDviTiming->clk / 1000000; 200 desirePixelClock = pDviTiming->clk / 1000000;
229 maxPixelClock = (unsigned long)viaparinfo-> 201 maxPixelClock = (unsigned long)viaparinfo->
230 tmds_setting_info->max_pixel_clock; 202 tmds_setting_info->max_pixel_clock;
@@ -232,20 +204,14 @@ void viafb_dvi_set_mode(int video_index, int mode_bpp, int set_iga)
232 DEBUG_MSG(KERN_INFO "\nDVI_set_mode!!\n"); 204 DEBUG_MSG(KERN_INFO "\nDVI_set_mode!!\n");
233 205
234 if ((maxPixelClock != 0) && (desirePixelClock > maxPixelClock)) { 206 if ((maxPixelClock != 0) && (desirePixelClock > maxPixelClock)) {
235 /*Check if reduce-blanking mode is exist */ 207 rb_mode = viafb_get_rb_mode(mode->crtc[0].crtc.hor_addr,
236 status = 208 mode->crtc[0].crtc.ver_addr);
237 check_reduce_blanking_mode(video_index, 209 if (rb_mode) {
238 pDviTiming->refresh_rate); 210 mode = rb_mode;
239 if (status) { 211 pDviTiming = rb_mode->crtc;
240 video_index += 100; /*Use reduce-blanking mode */
241 videoMode = viafb_get_modetbl_pointer(video_index);
242 pDviTiming = videoMode->crtc;
243 DEBUG_MSG(KERN_INFO
244 "DVI use reduce blanking mode %d!!\n",
245 video_index);
246 } 212 }
247 } 213 }
248 viafb_fill_crtc_timing(pDviTiming, video_index, mode_bpp / 8, set_iga); 214 viafb_fill_crtc_timing(pDviTiming, mode, mode_bpp / 8, set_iga);
249 viafb_set_output_path(DEVICE_DVI, set_iga, 215 viafb_set_output_path(DEVICE_DVI, set_iga,
250 viaparinfo->chip_info->tmds_chip_info.output_interface); 216 viaparinfo->chip_info->tmds_chip_info.output_interface);
251} 217}
@@ -350,25 +316,18 @@ static int viafb_dvi_query_EDID(void)
350 return false; 316 return false;
351} 317}
352 318
353/* 319/* Get Panel Size Using EDID1 Table */
354 * 320static void dvi_get_panel_size_from_DDCv1(struct tmds_chip_information
355 * int dvi_get_panel_size_from_DDCv1(void) 321 *tmds_chip, struct tmds_setting_information *tmds_setting)
356 *
357 * - Get Panel Size Using EDID1 Table
358 *
359 * Return Type: int
360 *
361 */
362static int dvi_get_panel_size_from_DDCv1(void)
363{ 322{
364 int i, max_h = 0, max_v = 0, tmp, restore; 323 int i, max_h = 0, tmp, restore;
365 unsigned char rData; 324 unsigned char rData;
366 unsigned char EDID_DATA[18]; 325 unsigned char EDID_DATA[18];
367 326
368 DEBUG_MSG(KERN_INFO "\n dvi_get_panel_size_from_DDCv1 \n"); 327 DEBUG_MSG(KERN_INFO "\n dvi_get_panel_size_from_DDCv1 \n");
369 328
370 restore = viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr; 329 restore = tmds_chip->tmds_chip_slave_addr;
371 viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = 0xA0; 330 tmds_chip->tmds_chip_slave_addr = 0xA0;
372 331
373 rData = tmds_register_read(0x23); 332 rData = tmds_register_read(0x23);
374 if (rData & 0x3C) 333 if (rData & 0x3C)
@@ -414,8 +373,8 @@ static int dvi_get_panel_size_from_DDCv1(void)
414 /* The first two byte must be zero. */ 373 /* The first two byte must be zero. */
415 if (EDID_DATA[3] == 0xFD) { 374 if (EDID_DATA[3] == 0xFD) {
416 /* To get max pixel clock. */ 375 /* To get max pixel clock. */
417 viaparinfo->tmds_setting_info-> 376 tmds_setting->max_pixel_clock =
418 max_pixel_clock = EDID_DATA[9] * 10; 377 EDID_DATA[9] * 10;
419 } 378 }
420 } 379 }
421 break; 380 break;
@@ -425,154 +384,88 @@ static int dvi_get_panel_size_from_DDCv1(void)
425 } 384 }
426 } 385 }
427 386
387 tmds_setting->max_hres = max_h;
428 switch (max_h) { 388 switch (max_h) {
429 case 640: 389 case 640:
430 viaparinfo->tmds_setting_info->dvi_panel_size = 390 tmds_setting->max_vres = 480;
431 VIA_RES_640X480;
432 break; 391 break;
433 case 800: 392 case 800:
434 viaparinfo->tmds_setting_info->dvi_panel_size = 393 tmds_setting->max_vres = 600;
435 VIA_RES_800X600;
436 break; 394 break;
437 case 1024: 395 case 1024:
438 viaparinfo->tmds_setting_info->dvi_panel_size = 396 tmds_setting->max_vres = 768;
439 VIA_RES_1024X768;
440 break; 397 break;
441 case 1280: 398 case 1280:
442 viaparinfo->tmds_setting_info->dvi_panel_size = 399 tmds_setting->max_vres = 1024;
443 VIA_RES_1280X1024;
444 break; 400 break;
445 case 1400: 401 case 1400:
446 viaparinfo->tmds_setting_info->dvi_panel_size = 402 tmds_setting->max_vres = 1050;
447 VIA_RES_1400X1050;
448 break; 403 break;
449 case 1440: 404 case 1440:
450 viaparinfo->tmds_setting_info->dvi_panel_size = 405 tmds_setting->max_vres = 1050;
451 VIA_RES_1440X1050;
452 break; 406 break;
453 case 1600: 407 case 1600:
454 viaparinfo->tmds_setting_info->dvi_panel_size = 408 tmds_setting->max_vres = 1200;
455 VIA_RES_1600X1200;
456 break; 409 break;
457 case 1920: 410 case 1920:
458 if (max_v == 1200) { 411 tmds_setting->max_vres = 1080;
459 viaparinfo->tmds_setting_info->dvi_panel_size =
460 VIA_RES_1920X1200;
461 } else {
462 viaparinfo->tmds_setting_info->dvi_panel_size =
463 VIA_RES_1920X1080;
464 }
465
466 break; 412 break;
467 default: 413 default:
468 viaparinfo->tmds_setting_info->dvi_panel_size = 414 DEBUG_MSG(KERN_INFO "Unknown panel size max resolution = %d ! "
469 VIA_RES_1024X768; 415 "set default panel size.\n", max_h);
470 DEBUG_MSG(KERN_INFO "Unknown panel size max resolution = %d !\
471 set default panel size.\n", max_h);
472 break; 416 break;
473 } 417 }
474 418
475 DEBUG_MSG(KERN_INFO "DVI max pixelclock = %d\n", 419 DEBUG_MSG(KERN_INFO "DVI max pixelclock = %d\n",
476 viaparinfo->tmds_setting_info->max_pixel_clock); 420 tmds_setting->max_pixel_clock);
477 viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = restore; 421 tmds_chip->tmds_chip_slave_addr = restore;
478 return viaparinfo->tmds_setting_info->dvi_panel_size;
479} 422}
480 423
481/* 424/* Get Panel Size Using EDID2 Table */
482 * 425static void dvi_get_panel_size_from_DDCv2(struct tmds_chip_information
483 * int dvi_get_panel_size_from_DDCv2(void) 426 *tmds_chip, struct tmds_setting_information *tmds_setting)
484 *
485 * - Get Panel Size Using EDID2 Table
486 *
487 * Return Type: int
488 *
489 */
490static int dvi_get_panel_size_from_DDCv2(void)
491{ 427{
492 int HSize = 0, restore; 428 int restore;
493 unsigned char R_Buffer[2]; 429 unsigned char R_Buffer[2];
494 430
495 DEBUG_MSG(KERN_INFO "\n dvi_get_panel_size_from_DDCv2 \n"); 431 DEBUG_MSG(KERN_INFO "\n dvi_get_panel_size_from_DDCv2 \n");
496 432
497 restore = viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr; 433 restore = tmds_chip->tmds_chip_slave_addr;
498 viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = 0xA2; 434 tmds_chip->tmds_chip_slave_addr = 0xA2;
499 435
500 /* Horizontal: 0x76, 0x77 */ 436 /* Horizontal: 0x76, 0x77 */
501 tmds_register_read_bytes(0x76, R_Buffer, 2); 437 tmds_register_read_bytes(0x76, R_Buffer, 2);
502 HSize = R_Buffer[0]; 438 tmds_setting->max_hres = R_Buffer[0] + (R_Buffer[1] << 8);
503 HSize += R_Buffer[1] << 8;
504 439
505 switch (HSize) { 440 switch (tmds_setting->max_hres) {
506 case 640: 441 case 640:
507 viaparinfo->tmds_setting_info->dvi_panel_size = 442 tmds_setting->max_vres = 480;
508 VIA_RES_640X480;
509 break; 443 break;
510 case 800: 444 case 800:
511 viaparinfo->tmds_setting_info->dvi_panel_size = 445 tmds_setting->max_vres = 600;
512 VIA_RES_800X600;
513 break; 446 break;
514 case 1024: 447 case 1024:
515 viaparinfo->tmds_setting_info->dvi_panel_size = 448 tmds_setting->max_vres = 768;
516 VIA_RES_1024X768;
517 break; 449 break;
518 case 1280: 450 case 1280:
519 viaparinfo->tmds_setting_info->dvi_panel_size = 451 tmds_setting->max_vres = 1024;
520 VIA_RES_1280X1024;
521 break; 452 break;
522 case 1400: 453 case 1400:
523 viaparinfo->tmds_setting_info->dvi_panel_size = 454 tmds_setting->max_vres = 1050;
524 VIA_RES_1400X1050;
525 break; 455 break;
526 case 1440: 456 case 1440:
527 viaparinfo->tmds_setting_info->dvi_panel_size = 457 tmds_setting->max_vres = 1050;
528 VIA_RES_1440X1050;
529 break; 458 break;
530 case 1600: 459 case 1600:
531 viaparinfo->tmds_setting_info->dvi_panel_size = 460 tmds_setting->max_vres = 1200;
532 VIA_RES_1600X1200;
533 break;
534 default:
535 viaparinfo->tmds_setting_info->dvi_panel_size =
536 VIA_RES_1024X768;
537 DEBUG_MSG(KERN_INFO "Unknown panel size max resolution = %d!\
538 set default panel size.\n", HSize);
539 break;
540 }
541
542 viaparinfo->chip_info->tmds_chip_info.tmds_chip_slave_addr = restore;
543 return viaparinfo->tmds_setting_info->dvi_panel_size;
544}
545
546/*
547 *
548 * unsigned char dvi_get_panel_info(void)
549 *
550 * - Get Panel Size
551 *
552 * Return Type: unsigned char
553 */
554static unsigned char dvi_get_panel_info(void)
555{
556 unsigned char dvipanelsize;
557 DEBUG_MSG(KERN_INFO "dvi_get_panel_info! \n");
558
559 viafb_dvi_sense();
560 switch (viafb_dvi_query_EDID()) {
561 case 1:
562 dvi_get_panel_size_from_DDCv1();
563 break;
564 case 2:
565 dvi_get_panel_size_from_DDCv2();
566 break; 461 break;
567 default: 462 default:
463 DEBUG_MSG(KERN_INFO "Unknown panel size max resolution = %d! "
464 "set default panel size.\n", tmds_setting->max_hres);
568 break; 465 break;
569 } 466 }
570 467
571 DEBUG_MSG(KERN_INFO "dvi panel size is %2d \n", 468 tmds_chip->tmds_chip_slave_addr = restore;
572 viaparinfo->tmds_setting_info->dvi_panel_size);
573 dvipanelsize = (unsigned char)(viaparinfo->
574 tmds_setting_info->dvi_panel_size);
575 return dvipanelsize;
576} 469}
577 470
578/* If Disable DVI, turn off pad */ 471/* If Disable DVI, turn off pad */
diff --git a/drivers/video/via/dvi.h b/drivers/video/via/dvi.h
index e1ec37fb0dc..0dffcfd395f 100644
--- a/drivers/video/via/dvi.h
+++ b/drivers/video/via/dvi.h
@@ -53,12 +53,13 @@
53#define DEV_CONNECT_DVI 0x01 53#define DEV_CONNECT_DVI 0x01
54#define DEV_CONNECT_HDMI 0x02 54#define DEV_CONNECT_HDMI 0x02
55 55
56struct VideoModeTable *viafb_get_cea_mode_tbl_pointer(int Index);
57int viafb_dvi_sense(void); 56int viafb_dvi_sense(void);
58void viafb_dvi_disable(void); 57void viafb_dvi_disable(void);
59void viafb_dvi_enable(void); 58void viafb_dvi_enable(void);
60int viafb_tmds_trasmitter_identify(void); 59int viafb_tmds_trasmitter_identify(void);
61void viafb_init_dvi_size(void); 60void viafb_init_dvi_size(struct tmds_chip_information *tmds_chip,
62void viafb_dvi_set_mode(int video_index, int mode_bpp, int set_iga); 61 struct tmds_setting_information *tmds_setting);
62void viafb_dvi_set_mode(struct VideoModeTable *videoMode, int mode_bpp,
63 int set_iga);
63 64
64#endif /* __DVI_H__ */ 65#endif /* __DVI_H__ */
diff --git a/drivers/video/via/global.c b/drivers/video/via/global.c
index b675cdbb03a..1ee511b7330 100644
--- a/drivers/video/via/global.c
+++ b/drivers/video/via/global.c
@@ -23,15 +23,12 @@ int viafb_platform_epia_dvi = STATE_OFF;
23int viafb_device_lcd_dualedge = STATE_OFF; 23int viafb_device_lcd_dualedge = STATE_OFF;
24int viafb_bus_width = 12; 24int viafb_bus_width = 12;
25int viafb_display_hardware_layout = HW_LAYOUT_LCD_DVI; 25int viafb_display_hardware_layout = HW_LAYOUT_LCD_DVI;
26int viafb_memsize;
27int viafb_DeviceStatus = CRT_Device; 26int viafb_DeviceStatus = CRT_Device;
28int viafb_hotplug; 27int viafb_hotplug;
29int viafb_refresh = 60; 28int viafb_refresh = 60;
30int viafb_refresh1 = 60; 29int viafb_refresh1 = 60;
31int viafb_lcd_dsp_method = LCD_EXPANDSION; 30int viafb_lcd_dsp_method = LCD_EXPANDSION;
32int viafb_lcd_mode = LCD_OPENLDI; 31int viafb_lcd_mode = LCD_OPENLDI;
33int viafb_bpp = 32;
34int viafb_bpp1 = 32;
35int viafb_CRT_ON = 1; 32int viafb_CRT_ON = 1;
36int viafb_DVI_ON; 33int viafb_DVI_ON;
37int viafb_LCD_ON ; 34int viafb_LCD_ON ;
@@ -42,8 +39,6 @@ int viafb_hotplug_Xres = 640;
42int viafb_hotplug_Yres = 480; 39int viafb_hotplug_Yres = 480;
43int viafb_hotplug_bpp = 32; 40int viafb_hotplug_bpp = 32;
44int viafb_hotplug_refresh = 60; 41int viafb_hotplug_refresh = 60;
45unsigned int viafb_second_offset;
46int viafb_second_size;
47int viafb_primary_dev = None_Device; 42int viafb_primary_dev = None_Device;
48unsigned int viafb_second_xres = 640; 43unsigned int viafb_second_xres = 640;
49unsigned int viafb_second_yres = 480; 44unsigned int viafb_second_yres = 480;
diff --git a/drivers/video/via/global.h b/drivers/video/via/global.h
index d69d0ca99c2..8d95d5fd138 100644
--- a/drivers/video/via/global.h
+++ b/drivers/video/via/global.h
@@ -35,7 +35,6 @@
35 35
36#include "debug.h" 36#include "debug.h"
37 37
38#include "iface.h"
39#include "viafbdev.h" 38#include "viafbdev.h"
40#include "chip.h" 39#include "chip.h"
41#include "accel.h" 40#include "accel.h"
@@ -68,8 +67,6 @@ extern int viafb_refresh;
68extern int viafb_refresh1; 67extern int viafb_refresh1;
69extern int viafb_lcd_dsp_method; 68extern int viafb_lcd_dsp_method;
70extern int viafb_lcd_mode; 69extern int viafb_lcd_mode;
71extern int viafb_bpp;
72extern int viafb_bpp1;
73 70
74extern int viafb_CRT_ON; 71extern int viafb_CRT_ON;
75extern int viafb_hotplug_Xres; 72extern int viafb_hotplug_Xres;
diff --git a/drivers/video/via/hw.c b/drivers/video/via/hw.c
index 3e083ff67ae..f2583b1b527 100644
--- a/drivers/video/via/hw.c
+++ b/drivers/video/via/hw.c
@@ -524,7 +524,6 @@ static void dvi_patch_skew_dvp1(void);
524static void dvi_patch_skew_dvp_low(void); 524static void dvi_patch_skew_dvp_low(void);
525static void set_dvi_output_path(int set_iga, int output_interface); 525static void set_dvi_output_path(int set_iga, int output_interface);
526static void set_lcd_output_path(int set_iga, int output_interface); 526static void set_lcd_output_path(int set_iga, int output_interface);
527static int search_mode_setting(int ModeInfoIndex);
528static void load_fix_bit_crtc_reg(void); 527static void load_fix_bit_crtc_reg(void);
529static void init_gfx_chip_info(struct pci_dev *pdev, 528static void init_gfx_chip_info(struct pci_dev *pdev,
530 const struct pci_device_id *pdi); 529 const struct pci_device_id *pdi);
@@ -686,6 +685,84 @@ void viafb_set_secondary_pitch(u32 pitch)
686 viafb_write_reg_mask(0x71, VIACR, (pitch >> (10 - 7)) & 0x80, 0x80); 685 viafb_write_reg_mask(0x71, VIACR, (pitch >> (10 - 7)) & 0x80, 0x80);
687} 686}
688 687
688void viafb_set_primary_color_depth(u8 depth)
689{
690 u8 value;
691
692 DEBUG_MSG(KERN_DEBUG "viafb_set_primary_color_depth(%d)\n", depth);
693 switch (depth) {
694 case 8:
695 value = 0x00;
696 break;
697 case 15:
698 value = 0x04;
699 break;
700 case 16:
701 value = 0x14;
702 break;
703 case 24:
704 value = 0x0C;
705 break;
706 case 30:
707 value = 0x08;
708 break;
709 default:
710 printk(KERN_WARNING "viafb_set_primary_color_depth: "
711 "Unsupported depth: %d\n", depth);
712 return;
713 }
714
715 viafb_write_reg_mask(0x15, VIASR, value, 0x1C);
716}
717
718void viafb_set_secondary_color_depth(u8 depth)
719{
720 u8 value;
721
722 DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_color_depth(%d)\n", depth);
723 switch (depth) {
724 case 8:
725 value = 0x00;
726 break;
727 case 16:
728 value = 0x40;
729 break;
730 case 24:
731 value = 0xC0;
732 break;
733 case 30:
734 value = 0x80;
735 break;
736 default:
737 printk(KERN_WARNING "viafb_set_secondary_color_depth: "
738 "Unsupported depth: %d\n", depth);
739 return;
740 }
741
742 viafb_write_reg_mask(0x67, VIACR, value, 0xC0);
743}
744
745static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
746{
747 outb(0xFF, 0x3C6); /* bit mask of palette */
748 outb(index, 0x3C8);
749 outb(red, 0x3C9);
750 outb(green, 0x3C9);
751 outb(blue, 0x3C9);
752}
753
754void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue)
755{
756 viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);
757 set_color_register(index, red, green, blue);
758}
759
760void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue)
761{
762 viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);
763 set_color_register(index, red, green, blue);
764}
765
689void viafb_set_output_path(int device, int set_iga, int output_interface) 766void viafb_set_output_path(int device, int set_iga, int output_interface)
690{ 767{
691 switch (device) { 768 switch (device) {
@@ -710,11 +787,8 @@ static void set_crt_output_path(int set_iga)
710 viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6); 787 viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6);
711 break; 788 break;
712 case IGA2: 789 case IGA2:
713 case IGA1_IGA2:
714 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7); 790 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
715 viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6); 791 viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6);
716 if (set_iga == IGA1_IGA2)
717 viafb_write_reg_mask(CR6B, VIACR, 0x08, BIT3);
718 break; 792 break;
719 } 793 }
720} 794}
@@ -904,13 +978,6 @@ static void set_lcd_output_path(int set_iga, int output_interface)
904 978
905 enable_second_display_channel(); 979 enable_second_display_channel();
906 break; 980 break;
907
908 case IGA1_IGA2:
909 viafb_write_reg_mask(CR6B, VIACR, 0x08, BIT3);
910 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
911
912 disable_second_display_channel();
913 break;
914 } 981 }
915 982
916 switch (output_interface) { 983 switch (output_interface) {
@@ -987,49 +1054,6 @@ static void set_lcd_output_path(int set_iga, int output_interface)
987 } 1054 }
988} 1055}
989 1056
990/* Search Mode Index */
991static int search_mode_setting(int ModeInfoIndex)
992{
993 int i = 0;
994
995 while ((i < NUM_TOTAL_MODETABLE) &&
996 (ModeInfoIndex != CLE266Modes[i].ModeIndex))
997 i++;
998 if (i >= NUM_TOTAL_MODETABLE)
999 i = 0;
1000 return i;
1001
1002}
1003
1004struct VideoModeTable *viafb_get_modetbl_pointer(int Index)
1005{
1006 struct VideoModeTable *TmpTbl = NULL;
1007 TmpTbl = &CLE266Modes[search_mode_setting(Index)];
1008 return TmpTbl;
1009}
1010
1011struct VideoModeTable *viafb_get_cea_mode_tbl_pointer(int Index)
1012{
1013 struct VideoModeTable *TmpTbl = NULL;
1014 int i = 0;
1015 while ((i < NUM_TOTAL_CEA_MODES) &&
1016 (Index != CEA_HDMI_Modes[i].ModeIndex))
1017 i++;
1018 if ((i < NUM_TOTAL_CEA_MODES))
1019 TmpTbl = &CEA_HDMI_Modes[i];
1020 else {
1021 /*Still use general timing if don't find CEA timing */
1022 i = 0;
1023 while ((i < NUM_TOTAL_MODETABLE) &&
1024 (Index != CLE266Modes[i].ModeIndex))
1025 i++;
1026 if (i >= NUM_TOTAL_MODETABLE)
1027 i = 0;
1028 TmpTbl = &CLE266Modes[i];
1029 }
1030 return TmpTbl;
1031}
1032
1033static void load_fix_bit_crtc_reg(void) 1057static void load_fix_bit_crtc_reg(void)
1034{ 1058{
1035 /* always set to 1 */ 1059 /* always set to 1 */
@@ -1121,15 +1145,13 @@ void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1121 struct io_register *reg = NULL; 1145 struct io_register *reg = NULL;
1122 1146
1123 switch (set_iga) { 1147 switch (set_iga) {
1124 case IGA1_IGA2:
1125 case IGA1: 1148 case IGA1:
1126 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte); 1149 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1127 viafb_load_reg_num = fetch_count_reg. 1150 viafb_load_reg_num = fetch_count_reg.
1128 iga1_fetch_count_reg.reg_num; 1151 iga1_fetch_count_reg.reg_num;
1129 reg = fetch_count_reg.iga1_fetch_count_reg.reg; 1152 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1130 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); 1153 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1131 if (set_iga == IGA1) 1154 break;
1132 break;
1133 case IGA2: 1155 case IGA2:
1134 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte); 1156 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1135 viafb_load_reg_num = fetch_count_reg. 1157 viafb_load_reg_num = fetch_count_reg.
@@ -1499,7 +1521,7 @@ void viafb_set_vclock(u32 CLK, int set_iga)
1499 /* H.W. Reset : ON */ 1521 /* H.W. Reset : ON */
1500 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7); 1522 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1501 1523
1502 if ((set_iga == IGA1) || (set_iga == IGA1_IGA2)) { 1524 if (set_iga == IGA1) {
1503 /* Change D,N FOR VCLK */ 1525 /* Change D,N FOR VCLK */
1504 switch (viaparinfo->chip_info->gfx_chip_name) { 1526 switch (viaparinfo->chip_info->gfx_chip_name) {
1505 case UNICHROME_CLE266: 1527 case UNICHROME_CLE266:
@@ -1528,7 +1550,7 @@ void viafb_set_vclock(u32 CLK, int set_iga)
1528 } 1550 }
1529 } 1551 }
1530 1552
1531 if ((set_iga == IGA2) || (set_iga == IGA1_IGA2)) { 1553 if (set_iga == IGA2) {
1532 /* Change D,N FOR LCK */ 1554 /* Change D,N FOR LCK */
1533 switch (viaparinfo->chip_info->gfx_chip_name) { 1555 switch (viaparinfo->chip_info->gfx_chip_name) {
1534 case UNICHROME_CLE266: 1556 case UNICHROME_CLE266:
@@ -1557,12 +1579,12 @@ void viafb_set_vclock(u32 CLK, int set_iga)
1557 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7); 1579 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1558 1580
1559 /* Reset PLL */ 1581 /* Reset PLL */
1560 if ((set_iga == IGA1) || (set_iga == IGA1_IGA2)) { 1582 if (set_iga == IGA1) {
1561 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1); 1583 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1562 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1); 1584 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1563 } 1585 }
1564 1586
1565 if ((set_iga == IGA2) || (set_iga == IGA1_IGA2)) { 1587 if (set_iga == IGA2) {
1566 viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0); 1588 viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0);
1567 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0); 1589 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0);
1568 } 1590 }
@@ -1805,47 +1827,15 @@ void viafb_load_crtc_timing(struct display_timing device_timing,
1805 viafb_lock_crt(); 1827 viafb_lock_crt();
1806} 1828}
1807 1829
1808void viafb_set_color_depth(int bpp_byte, int set_iga)
1809{
1810 if (set_iga == IGA1) {
1811 switch (bpp_byte) {
1812 case MODE_8BPP:
1813 viafb_write_reg_mask(SR15, VIASR, 0x22, 0x7E);
1814 break;
1815 case MODE_16BPP:
1816 viafb_write_reg_mask(SR15, VIASR, 0xB6, 0xFE);
1817 break;
1818 case MODE_32BPP:
1819 viafb_write_reg_mask(SR15, VIASR, 0xAE, 0xFE);
1820 break;
1821 }
1822 } else {
1823 switch (bpp_byte) {
1824 case MODE_8BPP:
1825 viafb_write_reg_mask(CR67, VIACR, 0x00, BIT6 + BIT7);
1826 break;
1827 case MODE_16BPP:
1828 viafb_write_reg_mask(CR67, VIACR, 0x40, BIT6 + BIT7);
1829 break;
1830 case MODE_32BPP:
1831 viafb_write_reg_mask(CR67, VIACR, 0xC0, BIT6 + BIT7);
1832 break;
1833 }
1834 }
1835}
1836
1837void viafb_fill_crtc_timing(struct crt_mode_table *crt_table, 1830void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1838 int mode_index, int bpp_byte, int set_iga) 1831 struct VideoModeTable *video_mode, int bpp_byte, int set_iga)
1839{ 1832{
1840 struct VideoModeTable *video_mode;
1841 struct display_timing crt_reg; 1833 struct display_timing crt_reg;
1842 int i; 1834 int i;
1843 int index = 0; 1835 int index = 0;
1844 int h_addr, v_addr; 1836 int h_addr, v_addr;
1845 u32 pll_D_N; 1837 u32 pll_D_N;
1846 1838
1847 video_mode = &CLE266Modes[search_mode_setting(mode_index)];
1848
1849 for (i = 0; i < video_mode->mode_array; i++) { 1839 for (i = 0; i < video_mode->mode_array; i++) {
1850 index = i; 1840 index = i;
1851 1841
@@ -1858,8 +1848,10 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1858 1848
1859 /* Mode 640x480 has border, but LCD/DFP didn't have border. */ 1849 /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1860 /* So we would delete border. */ 1850 /* So we would delete border. */
1861 if ((viafb_LCD_ON | viafb_DVI_ON) && (mode_index == VIA_RES_640X480) 1851 if ((viafb_LCD_ON | viafb_DVI_ON)
1862 && (viaparinfo->crt_setting_info->refresh_rate == 60)) { 1852 && video_mode->crtc[0].crtc.hor_addr == 640
1853 && video_mode->crtc[0].crtc.ver_addr == 480
1854 && viaparinfo->crt_setting_info->refresh_rate == 60) {
1863 /* The border is 8 pixels. */ 1855 /* The border is 8 pixels. */
1864 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8; 1856 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
1865 1857
@@ -1912,9 +1904,6 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1912 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400)) 1904 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1913 viafb_load_FIFO_reg(set_iga, h_addr, v_addr); 1905 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
1914 1906
1915 /* load SR Register About Memory and Color part */
1916 viafb_set_color_depth(bpp_byte, set_iga);
1917
1918 pll_D_N = viafb_get_clk_value(crt_table[index].clk); 1907 pll_D_N = viafb_get_clk_value(crt_table[index].clk);
1919 DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N); 1908 DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
1920 viafb_set_vclock(pll_D_N, set_iga); 1909 viafb_set_vclock(pll_D_N, set_iga);
@@ -1956,9 +1945,6 @@ void viafb_update_device_setting(int hres, int vres,
1956 1945
1957 viaparinfo->tmds_setting_info->h_active = hres; 1946 viaparinfo->tmds_setting_info->h_active = hres;
1958 viaparinfo->tmds_setting_info->v_active = vres; 1947 viaparinfo->tmds_setting_info->v_active = vres;
1959 viaparinfo->tmds_setting_info->bpp = bpp;
1960 viaparinfo->tmds_setting_info->refresh_rate =
1961 vmode_refresh;
1962 1948
1963 viaparinfo->lvds_setting_info->h_active = hres; 1949 viaparinfo->lvds_setting_info->h_active = hres;
1964 viaparinfo->lvds_setting_info->v_active = vres; 1950 viaparinfo->lvds_setting_info->v_active = vres;
@@ -1975,9 +1961,6 @@ void viafb_update_device_setting(int hres, int vres,
1975 if (viaparinfo->tmds_setting_info->iga_path == IGA2) { 1961 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
1976 viaparinfo->tmds_setting_info->h_active = hres; 1962 viaparinfo->tmds_setting_info->h_active = hres;
1977 viaparinfo->tmds_setting_info->v_active = vres; 1963 viaparinfo->tmds_setting_info->v_active = vres;
1978 viaparinfo->tmds_setting_info->bpp = bpp;
1979 viaparinfo->tmds_setting_info->refresh_rate =
1980 vmode_refresh;
1981 } 1964 }
1982 1965
1983 if (viaparinfo->lvds_setting_info->iga_path == IGA2) { 1966 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
@@ -2076,9 +2059,8 @@ static void init_tmds_chip_info(void)
2076 2059
2077 DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n", 2060 DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
2078 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name); 2061 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
2079 viaparinfo->tmds_setting_info->get_dvi_size_method = 2062 viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info,
2080 GET_DVI_SIZE_BY_VGA_BIOS; 2063 &viaparinfo->shared->tmds_setting_info);
2081 viafb_init_dvi_size();
2082} 2064}
2083 2065
2084static void init_lvds_chip_info(void) 2066static void init_lvds_chip_info(void)
@@ -2195,28 +2177,19 @@ static void set_display_channel(void)
2195 } 2177 }
2196} 2178}
2197 2179
2198int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp, 2180int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
2199 int vmode_index1, int hor_res1, int ver_res1, int video_bpp1) 2181 struct VideoModeTable *vmode_tbl1, int video_bpp1)
2200{ 2182{
2201 int i, j; 2183 int i, j;
2202 int port; 2184 int port;
2203 u8 value, index, mask; 2185 u8 value, index, mask;
2204 struct VideoModeTable *vmode_tbl;
2205 struct crt_mode_table *crt_timing; 2186 struct crt_mode_table *crt_timing;
2206 struct VideoModeTable *vmode_tbl1 = NULL;
2207 struct crt_mode_table *crt_timing1 = NULL; 2187 struct crt_mode_table *crt_timing1 = NULL;
2208 2188
2209 DEBUG_MSG(KERN_INFO "Set Mode!!\n");
2210 DEBUG_MSG(KERN_INFO
2211 "vmode_index=%d hor_res=%d ver_res=%d video_bpp=%d\n",
2212 vmode_index, hor_res, ver_res, video_bpp);
2213
2214 device_screen_off(); 2189 device_screen_off();
2215 vmode_tbl = &CLE266Modes[search_mode_setting(vmode_index)];
2216 crt_timing = vmode_tbl->crtc; 2190 crt_timing = vmode_tbl->crtc;
2217 2191
2218 if (viafb_SAMM_ON == 1) { 2192 if (viafb_SAMM_ON == 1) {
2219 vmode_tbl1 = &CLE266Modes[search_mode_setting(vmode_index1)];
2220 crt_timing1 = vmode_tbl1->crtc; 2193 crt_timing1 = vmode_tbl1->crtc;
2221 } 2194 }
2222 2195
@@ -2267,12 +2240,11 @@ int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp,
2267 outb(VPIT.SR[i - 1], VIASR + 1); 2240 outb(VPIT.SR[i - 1], VIASR + 1);
2268 } 2241 }
2269 2242
2270 viafb_set_primary_address(0); 2243 viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);
2271 viafb_set_secondary_address(viafb_SAMM_ON ? viafb_second_offset : 0);
2272 viafb_set_iga_path(); 2244 viafb_set_iga_path();
2273 2245
2274 /* Write CRTC */ 2246 /* Write CRTC */
2275 viafb_fill_crtc_timing(crt_timing, vmode_index, video_bpp / 8, IGA1); 2247 viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1);
2276 2248
2277 /* Write Graphic Controller */ 2249 /* Write Graphic Controller */
2278 for (i = 0; i < StdGR; i++) { 2250 for (i = 0; i < StdGR; i++) {
@@ -2292,65 +2264,25 @@ int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp,
2292 2264
2293 /* Update Patch Register */ 2265 /* Update Patch Register */
2294 2266
2295 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) 2267 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266
2296 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)) { 2268 || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)
2297 for (i = 0; i < NUM_TOTAL_PATCH_MODE; i++) { 2269 && vmode_tbl->crtc[0].crtc.hor_addr == 1024
2298 if (res_patch_table[i].mode_index == vmode_index) { 2270 && vmode_tbl->crtc[0].crtc.ver_addr == 768) {
2299 for (j = 0; 2271 for (j = 0; j < res_patch_table[0].table_length; j++) {
2300 j < res_patch_table[i].table_length; j++) { 2272 index = res_patch_table[0].io_reg_table[j].index;
2301 index = 2273 port = res_patch_table[0].io_reg_table[j].port;
2302 res_patch_table[i]. 2274 value = res_patch_table[0].io_reg_table[j].value;
2303 io_reg_table[j].index; 2275 mask = res_patch_table[0].io_reg_table[j].mask;
2304 port = 2276 viafb_write_reg_mask(index, port, value, mask);
2305 res_patch_table[i].
2306 io_reg_table[j].port;
2307 value =
2308 res_patch_table[i].
2309 io_reg_table[j].value;
2310 mask =
2311 res_patch_table[i].
2312 io_reg_table[j].mask;
2313 viafb_write_reg_mask(index, port, value,
2314 mask);
2315 }
2316 }
2317 }
2318 }
2319
2320 if (viafb_SAMM_ON == 1) {
2321 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
2322 || (viaparinfo->chip_info->gfx_chip_name ==
2323 UNICHROME_K400)) {
2324 for (i = 0; i < NUM_TOTAL_PATCH_MODE; i++) {
2325 if (res_patch_table[i].mode_index ==
2326 vmode_index1) {
2327 for (j = 0;
2328 j <
2329 res_patch_table[i].
2330 table_length; j++) {
2331 index =
2332 res_patch_table[i].
2333 io_reg_table[j].index;
2334 port =
2335 res_patch_table[i].
2336 io_reg_table[j].port;
2337 value =
2338 res_patch_table[i].
2339 io_reg_table[j].value;
2340 mask =
2341 res_patch_table[i].
2342 io_reg_table[j].mask;
2343 viafb_write_reg_mask(index,
2344 port, value, mask);
2345 }
2346 }
2347 }
2348 } 2277 }
2349 } 2278 }
2350 2279
2351 viafb_set_primary_pitch(viafbinfo->fix.line_length); 2280 viafb_set_primary_pitch(viafbinfo->fix.line_length);
2352 viafb_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length 2281 viafb_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2353 : viafbinfo->fix.line_length); 2282 : viafbinfo->fix.line_length);
2283 viafb_set_primary_color_depth(viaparinfo->depth);
2284 viafb_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth
2285 : viaparinfo->depth);
2354 /* Update Refresh Rate Setting */ 2286 /* Update Refresh Rate Setting */
2355 2287
2356 /* Clear On Screen */ 2288 /* Clear On Screen */
@@ -2359,11 +2291,11 @@ int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp,
2359 if (viafb_CRT_ON) { 2291 if (viafb_CRT_ON) {
2360 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path == 2292 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2361 IGA2)) { 2293 IGA2)) {
2362 viafb_fill_crtc_timing(crt_timing1, vmode_index1, 2294 viafb_fill_crtc_timing(crt_timing1, vmode_tbl1,
2363 video_bpp1 / 8, 2295 video_bpp1 / 8,
2364 viaparinfo->crt_setting_info->iga_path); 2296 viaparinfo->crt_setting_info->iga_path);
2365 } else { 2297 } else {
2366 viafb_fill_crtc_timing(crt_timing, vmode_index, 2298 viafb_fill_crtc_timing(crt_timing, vmode_tbl,
2367 video_bpp / 8, 2299 video_bpp / 8,
2368 viaparinfo->crt_setting_info->iga_path); 2300 viaparinfo->crt_setting_info->iga_path);
2369 } 2301 }
@@ -2373,7 +2305,7 @@ int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp,
2373 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode 2305 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2374 to 8 alignment (1368),there is several pixels (2 pixels) 2306 to 8 alignment (1368),there is several pixels (2 pixels)
2375 on right side of screen. */ 2307 on right side of screen. */
2376 if (hor_res % 8) { 2308 if (vmode_tbl->crtc[0].crtc.hor_addr % 8) {
2377 viafb_unlock_crt(); 2309 viafb_unlock_crt();
2378 viafb_write_reg(CR02, VIACR, 2310 viafb_write_reg(CR02, VIACR,
2379 viafb_read_reg(VIACR, CR02) - 1); 2311 viafb_read_reg(VIACR, CR02) - 1);
@@ -2384,14 +2316,14 @@ int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp,
2384 if (viafb_DVI_ON) { 2316 if (viafb_DVI_ON) {
2385 if (viafb_SAMM_ON && 2317 if (viafb_SAMM_ON &&
2386 (viaparinfo->tmds_setting_info->iga_path == IGA2)) { 2318 (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2387 viafb_dvi_set_mode(viafb_get_mode_index 2319 viafb_dvi_set_mode(viafb_get_mode
2388 (viaparinfo->tmds_setting_info->h_active, 2320 (viaparinfo->tmds_setting_info->h_active,
2389 viaparinfo->tmds_setting_info-> 2321 viaparinfo->tmds_setting_info->
2390 v_active), 2322 v_active),
2391 video_bpp1, viaparinfo-> 2323 video_bpp1, viaparinfo->
2392 tmds_setting_info->iga_path); 2324 tmds_setting_info->iga_path);
2393 } else { 2325 } else {
2394 viafb_dvi_set_mode(viafb_get_mode_index 2326 viafb_dvi_set_mode(viafb_get_mode
2395 (viaparinfo->tmds_setting_info->h_active, 2327 (viaparinfo->tmds_setting_info->h_active,
2396 viaparinfo-> 2328 viaparinfo->
2397 tmds_setting_info->v_active), 2329 tmds_setting_info->v_active),
@@ -2445,8 +2377,8 @@ int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp,
2445 2377
2446 /* If set mode normally, save resolution information for hot-plug . */ 2378 /* If set mode normally, save resolution information for hot-plug . */
2447 if (!viafb_hotplug) { 2379 if (!viafb_hotplug) {
2448 viafb_hotplug_Xres = hor_res; 2380 viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr;
2449 viafb_hotplug_Yres = ver_res; 2381 viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr;
2450 viafb_hotplug_bpp = video_bpp; 2382 viafb_hotplug_bpp = video_bpp;
2451 viafb_hotplug_refresh = viafb_refresh; 2383 viafb_hotplug_refresh = viafb_refresh;
2452 2384
@@ -2706,13 +2638,11 @@ void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2706 2638
2707/*According var's xres, yres fill var's other timing information*/ 2639/*According var's xres, yres fill var's other timing information*/
2708void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh, 2640void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2709 int mode_index) 2641 struct VideoModeTable *vmode_tbl)
2710{ 2642{
2711 struct VideoModeTable *vmode_tbl = NULL;
2712 struct crt_mode_table *crt_timing = NULL; 2643 struct crt_mode_table *crt_timing = NULL;
2713 struct display_timing crt_reg; 2644 struct display_timing crt_reg;
2714 int i = 0, index = 0; 2645 int i = 0, index = 0;
2715 vmode_tbl = &CLE266Modes[search_mode_setting(mode_index)];
2716 crt_timing = vmode_tbl->crtc; 2646 crt_timing = vmode_tbl->crtc;
2717 for (i = 0; i < vmode_tbl->mode_array; i++) { 2647 for (i = 0; i < vmode_tbl->mode_array; i++) {
2718 index = i; 2648 index = i;
@@ -2721,36 +2651,6 @@ void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2721 } 2651 }
2722 2652
2723 crt_reg = crt_timing[index].crtc; 2653 crt_reg = crt_timing[index].crtc;
2724 switch (var->bits_per_pixel) {
2725 case 8:
2726 var->red.offset = 0;
2727 var->green.offset = 0;
2728 var->blue.offset = 0;
2729 var->red.length = 6;
2730 var->green.length = 6;
2731 var->blue.length = 6;
2732 break;
2733 case 16:
2734 var->red.offset = 11;
2735 var->green.offset = 5;
2736 var->blue.offset = 0;
2737 var->red.length = 5;
2738 var->green.length = 6;
2739 var->blue.length = 5;
2740 break;
2741 case 32:
2742 var->red.offset = 16;
2743 var->green.offset = 8;
2744 var->blue.offset = 0;
2745 var->red.length = 8;
2746 var->green.length = 8;
2747 var->blue.length = 8;
2748 break;
2749 default:
2750 /* never happed, put here to keep consistent */
2751 break;
2752 }
2753
2754 var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh); 2654 var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2755 var->left_margin = 2655 var->left_margin =
2756 crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end); 2656 crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
diff --git a/drivers/video/via/hw.h b/drivers/video/via/hw.h
index b874d952b44..12ef32d334c 100644
--- a/drivers/video/via/hw.h
+++ b/drivers/video/via/hw.h
@@ -22,6 +22,7 @@
22#ifndef __HW_H__ 22#ifndef __HW_H__
23#define __HW_H__ 23#define __HW_H__
24 24
25#include "viamode.h"
25#include "global.h" 26#include "global.h"
26 27
27/*************************************************** 28/***************************************************
@@ -862,8 +863,6 @@ struct pci_device_id_info {
862}; 863};
863 864
864extern unsigned int viafb_second_virtual_xres; 865extern unsigned int viafb_second_virtual_xres;
865extern unsigned int viafb_second_offset;
866extern int viafb_second_size;
867extern int viafb_SAMM_ON; 866extern int viafb_SAMM_ON;
868extern int viafb_dual_fb; 867extern int viafb_dual_fb;
869extern int viafb_LCD2_ON; 868extern int viafb_LCD2_ON;
@@ -874,8 +873,9 @@ extern int viafb_hotplug;
874void viafb_write_reg_mask(u8 index, int io_port, u8 data, u8 mask); 873void viafb_write_reg_mask(u8 index, int io_port, u8 data, u8 mask);
875void viafb_set_output_path(int device, int set_iga, 874void viafb_set_output_path(int device, int set_iga,
876 int output_interface); 875 int output_interface);
876
877void viafb_fill_crtc_timing(struct crt_mode_table *crt_table, 877void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
878 int mode_index, int bpp_byte, int set_iga); 878 struct VideoModeTable *video_mode, int bpp_byte, int set_iga);
879 879
880void viafb_set_vclock(u32 CLK, int set_iga); 880void viafb_set_vclock(u32 CLK, int set_iga);
881void viafb_load_reg(int timing_value, int viafb_load_reg_num, 881void viafb_load_reg(int timing_value, int viafb_load_reg_num,
@@ -891,16 +891,15 @@ void viafb_lock_crt(void);
891void viafb_unlock_crt(void); 891void viafb_unlock_crt(void);
892void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga); 892void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga);
893void viafb_write_regx(struct io_reg RegTable[], int ItemNum); 893void viafb_write_regx(struct io_reg RegTable[], int ItemNum);
894struct VideoModeTable *viafb_get_modetbl_pointer(int Index);
895u32 viafb_get_clk_value(int clk); 894u32 viafb_get_clk_value(int clk);
896void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active); 895void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active);
897void viafb_set_color_depth(int bpp_byte, int set_iga);
898void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\ 896void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
899 *p_gfx_dpa_setting); 897 *p_gfx_dpa_setting);
900 898
901int viafb_setmode(int vmode_index, int hor_res, int ver_res, 899int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
902 int video_bpp, int vmode_index1, int hor_res1, 900 struct VideoModeTable *vmode_tbl1, int video_bpp1);
903 int ver_res1, int video_bpp1); 901void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
902 struct VideoModeTable *vmode_tbl);
904void viafb_init_chip_info(struct pci_dev *pdev, 903void viafb_init_chip_info(struct pci_dev *pdev,
905 const struct pci_device_id *pdi); 904 const struct pci_device_id *pdi);
906void viafb_init_dac(int set_iga); 905void viafb_init_dac(int set_iga);
@@ -915,6 +914,8 @@ void viafb_set_primary_address(u32 addr);
915void viafb_set_secondary_address(u32 addr); 914void viafb_set_secondary_address(u32 addr);
916void viafb_set_primary_pitch(u32 pitch); 915void viafb_set_primary_pitch(u32 pitch);
917void viafb_set_secondary_pitch(u32 pitch); 916void viafb_set_secondary_pitch(u32 pitch);
917void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue);
918void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue);
918void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len); 919void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len);
919 920
920#endif /* __HW_H__ */ 921#endif /* __HW_H__ */
diff --git a/drivers/video/via/iface.c b/drivers/video/via/iface.c
deleted file mode 100644
index 1570636c8d5..00000000000
--- a/drivers/video/via/iface.c
+++ /dev/null
@@ -1,78 +0,0 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "global.h"
23
24/* Get frame buffer size from VGA BIOS */
25
26unsigned int viafb_get_memsize(void)
27{
28 unsigned int m;
29
30 /* If memory size provided by user */
31 if (viafb_memsize)
32 m = viafb_memsize * Mb;
33 else {
34 m = (unsigned int)viafb_read_reg(VIASR, SR39);
35 m = m * (4 * Mb);
36
37 if ((m < (16 * Mb)) || (m > (64 * Mb)))
38 m = 16 * Mb;
39 }
40 DEBUG_MSG(KERN_INFO "framebuffer size = %d Mb\n", m / Mb);
41 return m;
42}
43
44/* Get Video Buffer Starting Physical Address(back door)*/
45
46unsigned long viafb_get_videobuf_addr(void)
47{
48 struct pci_dev *pdev = NULL;
49 unsigned char sys_mem;
50 unsigned char video_mem;
51 unsigned long sys_mem_size;
52 unsigned long video_mem_size;
53 /*system memory = 256 MB, video memory 64 MB */
54 unsigned long vmem_starting_adr = 0x0C000000;
55
56 pdev =
57 (struct pci_dev *)pci_get_device(VIA_K800_BRIDGE_VID,
58 VIA_K800_BRIDGE_DID, NULL);
59 if (pdev != NULL) {
60 pci_read_config_byte(pdev, VIA_K800_SYSTEM_MEMORY_REG,
61 &sys_mem);
62 pci_read_config_byte(pdev, VIA_K800_VIDEO_MEMORY_REG,
63 &video_mem);
64 video_mem = (video_mem & 0x70) >> 4;
65 sys_mem_size = ((unsigned long)sys_mem) << 24;
66 if (video_mem != 0)
67 video_mem_size = (1 << (video_mem)) * 1024 * 1024;
68 else
69 video_mem_size = 0;
70
71 vmem_starting_adr = sys_mem_size - video_mem_size;
72 pci_dev_put(pdev);
73 }
74
75 DEBUG_MSG(KERN_INFO "Video Memory Starting Address = %lx \n",
76 vmem_starting_adr);
77 return vmem_starting_adr;
78}
diff --git a/drivers/video/via/iface.h b/drivers/video/via/iface.h
deleted file mode 100644
index 790ec3e3aea..00000000000
--- a/drivers/video/via/iface.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef __IFACE_H__
23#define __IFACE_H__
24
25#define Kb (1024)
26#define Mb (Kb*Kb)
27
28#define VIA_K800_BRIDGE_VID 0x1106
29#define VIA_K800_BRIDGE_DID 0x3204
30
31#define VIA_K800_SYSTEM_MEMORY_REG 0x47
32#define VIA_K800_VIDEO_MEMORY_REG 0xA1
33
34extern int viafb_memsize;
35unsigned int viafb_get_memsize(void);
36unsigned long viafb_get_videobuf_addr(void);
37
38#endif /* __IFACE_H__ */
diff --git a/drivers/video/via/lcd.c b/drivers/video/via/lcd.c
index 09353e2b92f..1b1ccdc2d83 100644
--- a/drivers/video/via/lcd.c
+++ b/drivers/video/via/lcd.c
@@ -22,25 +22,7 @@
22#include "global.h" 22#include "global.h"
23#include "lcdtbl.h" 23#include "lcdtbl.h"
24 24
25static struct iga2_shadow_crtc_timing iga2_shadow_crtc_reg = { 25#define viafb_compact_res(x, y) (((x)<<16)|(y))
26 /* IGA2 Shadow Horizontal Total */
27 {IGA2_SHADOW_HOR_TOTAL_REG_NUM, {{CR6D, 0, 7}, {CR71, 3, 3} } },
28 /* IGA2 Shadow Horizontal Blank End */
29 {IGA2_SHADOW_HOR_BLANK_END_REG_NUM, {{CR6E, 0, 7} } },
30 /* IGA2 Shadow Vertical Total */
31 {IGA2_SHADOW_VER_TOTAL_REG_NUM, {{CR6F, 0, 7}, {CR71, 0, 2} } },
32 /* IGA2 Shadow Vertical Addressable Video */
33 {IGA2_SHADOW_VER_ADDR_REG_NUM, {{CR70, 0, 7}, {CR71, 4, 6} } },
34 /* IGA2 Shadow Vertical Blank Start */
35 {IGA2_SHADOW_VER_BLANK_START_REG_NUM,
36 {{CR72, 0, 7}, {CR74, 4, 6} } },
37 /* IGA2 Shadow Vertical Blank End */
38 {IGA2_SHADOW_VER_BLANK_END_REG_NUM, {{CR73, 0, 7}, {CR74, 0, 2} } },
39 /* IGA2 Shadow Vertical Sync Start */
40 {IGA2_SHADOW_VER_SYNC_START_REG_NUM, {{CR75, 0, 7}, {CR76, 4, 6} } },
41 /* IGA2 Shadow Vertical Sync End */
42 {IGA2_SHADOW_VER_SYNC_END_REG_NUM, {{CR76, 0, 3} } }
43};
44 26
45static struct _lcd_scaling_factor lcd_scaling_factor = { 27static struct _lcd_scaling_factor lcd_scaling_factor = {
46 /* LCD Horizontal Scaling Factor Register */ 28 /* LCD Horizontal Scaling Factor Register */
@@ -59,16 +41,10 @@ static struct _lcd_scaling_factor lcd_scaling_factor_CLE = {
59 41
60static int check_lvds_chip(int device_id_subaddr, int device_id); 42static int check_lvds_chip(int device_id_subaddr, int device_id);
61static bool lvds_identify_integratedlvds(void); 43static bool lvds_identify_integratedlvds(void);
62static int fp_id_to_vindex(int panel_id); 44static void fp_id_to_vindex(int panel_id);
63static int lvds_register_read(int index); 45static int lvds_register_read(int index);
64static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres, 46static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
65 int panel_vres); 47 int panel_vres);
66static void load_lcd_k400_patch_tbl(int set_hres, int set_vres,
67 int panel_id);
68static void load_lcd_p880_patch_tbl(int set_hres, int set_vres,
69 int panel_id);
70static void load_lcd_patch_regs(int set_hres, int set_vres,
71 int panel_id, int set_iga);
72static void via_pitch_alignment_patch_lcd( 48static void via_pitch_alignment_patch_lcd(
73 struct lvds_setting_information *plvds_setting_info, 49 struct lvds_setting_information *plvds_setting_info,
74 struct lvds_chip_information 50 struct lvds_chip_information
@@ -98,8 +74,6 @@ static void check_diport_of_integrated_lvds(
98static struct display_timing lcd_centering_timging(struct display_timing 74static struct display_timing lcd_centering_timging(struct display_timing
99 mode_crt_reg, 75 mode_crt_reg,
100 struct display_timing panel_crt_reg); 76 struct display_timing panel_crt_reg);
101static void load_crtc_shadow_timing(struct display_timing mode_timing,
102 struct display_timing panel_timing);
103static void viafb_load_scaling_factor_for_p4m900(int set_hres, 77static void viafb_load_scaling_factor_for_p4m900(int set_hres,
104 int set_vres, int panel_hres, int panel_vres); 78 int set_vres, int panel_hres, int panel_vres);
105 79
@@ -125,33 +99,24 @@ void viafb_init_lcd_size(void)
125 break; 99 break;
126 case GET_LCD_SIZE_BY_VGA_BIOS: 100 case GET_LCD_SIZE_BY_VGA_BIOS:
127 DEBUG_MSG(KERN_INFO "Get LCD Size method by VGA BIOS !!\n"); 101 DEBUG_MSG(KERN_INFO "Get LCD Size method by VGA BIOS !!\n");
128 viaparinfo->lvds_setting_info->lcd_panel_size = 102 fp_id_to_vindex(viafb_lcd_panel_id);
129 fp_id_to_vindex(viafb_lcd_panel_id);
130 DEBUG_MSG(KERN_INFO "LCD Panel_ID = %d\n", 103 DEBUG_MSG(KERN_INFO "LCD Panel_ID = %d\n",
131 viaparinfo->lvds_setting_info->lcd_panel_id); 104 viaparinfo->lvds_setting_info->lcd_panel_id);
132 DEBUG_MSG(KERN_INFO "LCD Panel Size = %d\n",
133 viaparinfo->lvds_setting_info->lcd_panel_size);
134 break; 105 break;
135 case GET_LCD_SIZE_BY_USER_SETTING: 106 case GET_LCD_SIZE_BY_USER_SETTING:
136 DEBUG_MSG(KERN_INFO "Get LCD Size method by user setting !!\n"); 107 DEBUG_MSG(KERN_INFO "Get LCD Size method by user setting !!\n");
137 viaparinfo->lvds_setting_info->lcd_panel_size = 108 fp_id_to_vindex(viafb_lcd_panel_id);
138 fp_id_to_vindex(viafb_lcd_panel_id);
139 DEBUG_MSG(KERN_INFO "LCD Panel_ID = %d\n", 109 DEBUG_MSG(KERN_INFO "LCD Panel_ID = %d\n",
140 viaparinfo->lvds_setting_info->lcd_panel_id); 110 viaparinfo->lvds_setting_info->lcd_panel_id);
141 DEBUG_MSG(KERN_INFO "LCD Panel Size = %d\n",
142 viaparinfo->lvds_setting_info->lcd_panel_size);
143 break; 111 break;
144 default: 112 default:
145 DEBUG_MSG(KERN_INFO "viafb_init_lcd_size fail\n"); 113 DEBUG_MSG(KERN_INFO "viafb_init_lcd_size fail\n");
146 viaparinfo->lvds_setting_info->lcd_panel_id = 114 viaparinfo->lvds_setting_info->lcd_panel_id =
147 LCD_PANEL_ID1_800X600; 115 LCD_PANEL_ID1_800X600;
148 viaparinfo->lvds_setting_info->lcd_panel_size = 116 fp_id_to_vindex(LCD_PANEL_ID1_800X600);
149 fp_id_to_vindex(LCD_PANEL_ID1_800X600);
150 } 117 }
151 viaparinfo->lvds_setting_info2->lcd_panel_id = 118 viaparinfo->lvds_setting_info2->lcd_panel_id =
152 viaparinfo->lvds_setting_info->lcd_panel_id; 119 viaparinfo->lvds_setting_info->lcd_panel_id;
153 viaparinfo->lvds_setting_info2->lcd_panel_size =
154 viaparinfo->lvds_setting_info->lcd_panel_size;
155 viaparinfo->lvds_setting_info2->lcd_panel_hres = 120 viaparinfo->lvds_setting_info2->lcd_panel_hres =
156 viaparinfo->lvds_setting_info->lcd_panel_hres; 121 viaparinfo->lvds_setting_info->lcd_panel_hres;
157 viaparinfo->lvds_setting_info2->lcd_panel_vres = 122 viaparinfo->lvds_setting_info2->lcd_panel_vres =
@@ -171,13 +136,13 @@ static bool lvds_identify_integratedlvds(void)
171 if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) { 136 if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
172 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name = 137 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
173 INTEGRATED_LVDS; 138 INTEGRATED_LVDS;
174 DEBUG_MSG(KERN_INFO "Support two dual channel LVDS!\ 139 DEBUG_MSG(KERN_INFO "Support two dual channel LVDS! "
175 (Internal LVDS + External LVDS)\n"); 140 "(Internal LVDS + External LVDS)\n");
176 } else { 141 } else {
177 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name = 142 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
178 INTEGRATED_LVDS; 143 INTEGRATED_LVDS;
179 DEBUG_MSG(KERN_INFO "Not found external LVDS,\ 144 DEBUG_MSG(KERN_INFO "Not found external LVDS, "
180 so can't support two dual channel LVDS!\n"); 145 "so can't support two dual channel LVDS!\n");
181 } 146 }
182 } else if (viafb_display_hardware_layout == HW_LAYOUT_LCD1_LCD2) { 147 } else if (viafb_display_hardware_layout == HW_LAYOUT_LCD1_LCD2) {
183 /* Two single channel LCD (Internal LVDS + Internal LVDS): */ 148 /* Two single channel LCD (Internal LVDS + Internal LVDS): */
@@ -185,8 +150,8 @@ static bool lvds_identify_integratedlvds(void)
185 INTEGRATED_LVDS; 150 INTEGRATED_LVDS;
186 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name = 151 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
187 INTEGRATED_LVDS; 152 INTEGRATED_LVDS;
188 DEBUG_MSG(KERN_INFO "Support two single channel LVDS!\ 153 DEBUG_MSG(KERN_INFO "Support two single channel LVDS! "
189 (Internal LVDS + Internal LVDS)\n"); 154 "(Internal LVDS + Internal LVDS)\n");
190 } else if (viafb_display_hardware_layout != HW_LAYOUT_DVI_ONLY) { 155 } else if (viafb_display_hardware_layout != HW_LAYOUT_DVI_ONLY) {
191 /* If we have found external LVDS, just use it, 156 /* If we have found external LVDS, just use it,
192 otherwise, we will use internal LVDS as default. */ 157 otherwise, we will use internal LVDS as default. */
@@ -248,7 +213,7 @@ int viafb_lvds_trasmitter_identify(void)
248 return FAIL; 213 return FAIL;
249} 214}
250 215
251static int fp_id_to_vindex(int panel_id) 216static void fp_id_to_vindex(int panel_id)
252{ 217{
253 DEBUG_MSG(KERN_INFO "fp_get_panel_id()\n"); 218 DEBUG_MSG(KERN_INFO "fp_get_panel_id()\n");
254 219
@@ -264,7 +229,6 @@ static int fp_id_to_vindex(int panel_id)
264 LCD_PANEL_ID0_640X480; 229 LCD_PANEL_ID0_640X480;
265 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 230 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
266 viaparinfo->lvds_setting_info->LCDDithering = 1; 231 viaparinfo->lvds_setting_info->LCDDithering = 1;
267 return VIA_RES_640X480;
268 break; 232 break;
269 case 0x1: 233 case 0x1:
270 viaparinfo->lvds_setting_info->lcd_panel_hres = 800; 234 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
@@ -273,7 +237,6 @@ static int fp_id_to_vindex(int panel_id)
273 LCD_PANEL_ID1_800X600; 237 LCD_PANEL_ID1_800X600;
274 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 238 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
275 viaparinfo->lvds_setting_info->LCDDithering = 1; 239 viaparinfo->lvds_setting_info->LCDDithering = 1;
276 return VIA_RES_800X600;
277 break; 240 break;
278 case 0x2: 241 case 0x2:
279 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024; 242 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
@@ -282,7 +245,6 @@ static int fp_id_to_vindex(int panel_id)
282 LCD_PANEL_ID2_1024X768; 245 LCD_PANEL_ID2_1024X768;
283 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 246 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
284 viaparinfo->lvds_setting_info->LCDDithering = 1; 247 viaparinfo->lvds_setting_info->LCDDithering = 1;
285 return VIA_RES_1024X768;
286 break; 248 break;
287 case 0x3: 249 case 0x3:
288 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280; 250 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
@@ -291,7 +253,6 @@ static int fp_id_to_vindex(int panel_id)
291 LCD_PANEL_ID3_1280X768; 253 LCD_PANEL_ID3_1280X768;
292 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 254 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
293 viaparinfo->lvds_setting_info->LCDDithering = 1; 255 viaparinfo->lvds_setting_info->LCDDithering = 1;
294 return VIA_RES_1280X768;
295 break; 256 break;
296 case 0x4: 257 case 0x4:
297 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280; 258 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
@@ -300,7 +261,6 @@ static int fp_id_to_vindex(int panel_id)
300 LCD_PANEL_ID4_1280X1024; 261 LCD_PANEL_ID4_1280X1024;
301 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1; 262 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
302 viaparinfo->lvds_setting_info->LCDDithering = 1; 263 viaparinfo->lvds_setting_info->LCDDithering = 1;
303 return VIA_RES_1280X1024;
304 break; 264 break;
305 case 0x5: 265 case 0x5:
306 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400; 266 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
@@ -309,7 +269,6 @@ static int fp_id_to_vindex(int panel_id)
309 LCD_PANEL_ID5_1400X1050; 269 LCD_PANEL_ID5_1400X1050;
310 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1; 270 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
311 viaparinfo->lvds_setting_info->LCDDithering = 1; 271 viaparinfo->lvds_setting_info->LCDDithering = 1;
312 return VIA_RES_1400X1050;
313 break; 272 break;
314 case 0x6: 273 case 0x6:
315 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600; 274 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
@@ -318,7 +277,6 @@ static int fp_id_to_vindex(int panel_id)
318 LCD_PANEL_ID6_1600X1200; 277 LCD_PANEL_ID6_1600X1200;
319 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1; 278 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
320 viaparinfo->lvds_setting_info->LCDDithering = 1; 279 viaparinfo->lvds_setting_info->LCDDithering = 1;
321 return VIA_RES_1600X1200;
322 break; 280 break;
323 case 0x8: 281 case 0x8:
324 viaparinfo->lvds_setting_info->lcd_panel_hres = 800; 282 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
@@ -327,7 +285,6 @@ static int fp_id_to_vindex(int panel_id)
327 LCD_PANEL_IDA_800X480; 285 LCD_PANEL_IDA_800X480;
328 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 286 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
329 viaparinfo->lvds_setting_info->LCDDithering = 1; 287 viaparinfo->lvds_setting_info->LCDDithering = 1;
330 return VIA_RES_800X480;
331 break; 288 break;
332 case 0x9: 289 case 0x9:
333 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024; 290 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
@@ -336,7 +293,6 @@ static int fp_id_to_vindex(int panel_id)
336 LCD_PANEL_ID2_1024X768; 293 LCD_PANEL_ID2_1024X768;
337 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1; 294 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
338 viaparinfo->lvds_setting_info->LCDDithering = 1; 295 viaparinfo->lvds_setting_info->LCDDithering = 1;
339 return VIA_RES_1024X768;
340 break; 296 break;
341 case 0xA: 297 case 0xA:
342 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024; 298 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
@@ -345,7 +301,6 @@ static int fp_id_to_vindex(int panel_id)
345 LCD_PANEL_ID2_1024X768; 301 LCD_PANEL_ID2_1024X768;
346 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 302 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
347 viaparinfo->lvds_setting_info->LCDDithering = 0; 303 viaparinfo->lvds_setting_info->LCDDithering = 0;
348 return VIA_RES_1024X768;
349 break; 304 break;
350 case 0xB: 305 case 0xB:
351 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024; 306 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
@@ -354,7 +309,6 @@ static int fp_id_to_vindex(int panel_id)
354 LCD_PANEL_ID2_1024X768; 309 LCD_PANEL_ID2_1024X768;
355 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1; 310 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
356 viaparinfo->lvds_setting_info->LCDDithering = 0; 311 viaparinfo->lvds_setting_info->LCDDithering = 0;
357 return VIA_RES_1024X768;
358 break; 312 break;
359 case 0xC: 313 case 0xC:
360 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280; 314 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
@@ -363,7 +317,6 @@ static int fp_id_to_vindex(int panel_id)
363 LCD_PANEL_ID3_1280X768; 317 LCD_PANEL_ID3_1280X768;
364 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 318 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
365 viaparinfo->lvds_setting_info->LCDDithering = 0; 319 viaparinfo->lvds_setting_info->LCDDithering = 0;
366 return VIA_RES_1280X768;
367 break; 320 break;
368 case 0xD: 321 case 0xD:
369 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280; 322 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
@@ -372,7 +325,6 @@ static int fp_id_to_vindex(int panel_id)
372 LCD_PANEL_ID4_1280X1024; 325 LCD_PANEL_ID4_1280X1024;
373 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1; 326 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
374 viaparinfo->lvds_setting_info->LCDDithering = 0; 327 viaparinfo->lvds_setting_info->LCDDithering = 0;
375 return VIA_RES_1280X1024;
376 break; 328 break;
377 case 0xE: 329 case 0xE:
378 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400; 330 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
@@ -381,7 +333,6 @@ static int fp_id_to_vindex(int panel_id)
381 LCD_PANEL_ID5_1400X1050; 333 LCD_PANEL_ID5_1400X1050;
382 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1; 334 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
383 viaparinfo->lvds_setting_info->LCDDithering = 0; 335 viaparinfo->lvds_setting_info->LCDDithering = 0;
384 return VIA_RES_1400X1050;
385 break; 336 break;
386 case 0xF: 337 case 0xF:
387 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600; 338 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
@@ -390,7 +341,6 @@ static int fp_id_to_vindex(int panel_id)
390 LCD_PANEL_ID6_1600X1200; 341 LCD_PANEL_ID6_1600X1200;
391 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1; 342 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
392 viaparinfo->lvds_setting_info->LCDDithering = 0; 343 viaparinfo->lvds_setting_info->LCDDithering = 0;
393 return VIA_RES_1600X1200;
394 break; 344 break;
395 case 0x10: 345 case 0x10:
396 viaparinfo->lvds_setting_info->lcd_panel_hres = 1366; 346 viaparinfo->lvds_setting_info->lcd_panel_hres = 1366;
@@ -399,7 +349,6 @@ static int fp_id_to_vindex(int panel_id)
399 LCD_PANEL_ID7_1366X768; 349 LCD_PANEL_ID7_1366X768;
400 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 350 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
401 viaparinfo->lvds_setting_info->LCDDithering = 0; 351 viaparinfo->lvds_setting_info->LCDDithering = 0;
402 return VIA_RES_1368X768;
403 break; 352 break;
404 case 0x11: 353 case 0x11:
405 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024; 354 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
@@ -408,7 +357,6 @@ static int fp_id_to_vindex(int panel_id)
408 LCD_PANEL_ID8_1024X600; 357 LCD_PANEL_ID8_1024X600;
409 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 358 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
410 viaparinfo->lvds_setting_info->LCDDithering = 1; 359 viaparinfo->lvds_setting_info->LCDDithering = 1;
411 return VIA_RES_1024X600;
412 break; 360 break;
413 case 0x12: 361 case 0x12:
414 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280; 362 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
@@ -417,7 +365,6 @@ static int fp_id_to_vindex(int panel_id)
417 LCD_PANEL_ID3_1280X768; 365 LCD_PANEL_ID3_1280X768;
418 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1; 366 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
419 viaparinfo->lvds_setting_info->LCDDithering = 1; 367 viaparinfo->lvds_setting_info->LCDDithering = 1;
420 return VIA_RES_1280X768;
421 break; 368 break;
422 case 0x13: 369 case 0x13:
423 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280; 370 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
@@ -426,7 +373,6 @@ static int fp_id_to_vindex(int panel_id)
426 LCD_PANEL_ID9_1280X800; 373 LCD_PANEL_ID9_1280X800;
427 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 374 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
428 viaparinfo->lvds_setting_info->LCDDithering = 1; 375 viaparinfo->lvds_setting_info->LCDDithering = 1;
429 return VIA_RES_1280X800;
430 break; 376 break;
431 case 0x14: 377 case 0x14:
432 viaparinfo->lvds_setting_info->lcd_panel_hres = 1360; 378 viaparinfo->lvds_setting_info->lcd_panel_hres = 1360;
@@ -435,7 +381,6 @@ static int fp_id_to_vindex(int panel_id)
435 LCD_PANEL_IDB_1360X768; 381 LCD_PANEL_IDB_1360X768;
436 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 382 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
437 viaparinfo->lvds_setting_info->LCDDithering = 0; 383 viaparinfo->lvds_setting_info->LCDDithering = 0;
438 return VIA_RES_1360X768;
439 break; 384 break;
440 case 0x15: 385 case 0x15:
441 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280; 386 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
@@ -444,7 +389,6 @@ static int fp_id_to_vindex(int panel_id)
444 LCD_PANEL_ID3_1280X768; 389 LCD_PANEL_ID3_1280X768;
445 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1; 390 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
446 viaparinfo->lvds_setting_info->LCDDithering = 0; 391 viaparinfo->lvds_setting_info->LCDDithering = 0;
447 return VIA_RES_1280X768;
448 break; 392 break;
449 case 0x16: 393 case 0x16:
450 viaparinfo->lvds_setting_info->lcd_panel_hres = 480; 394 viaparinfo->lvds_setting_info->lcd_panel_hres = 480;
@@ -453,7 +397,6 @@ static int fp_id_to_vindex(int panel_id)
453 LCD_PANEL_IDC_480X640; 397 LCD_PANEL_IDC_480X640;
454 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 398 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
455 viaparinfo->lvds_setting_info->LCDDithering = 1; 399 viaparinfo->lvds_setting_info->LCDDithering = 1;
456 return VIA_RES_480X640;
457 break; 400 break;
458 default: 401 default:
459 viaparinfo->lvds_setting_info->lcd_panel_hres = 800; 402 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
@@ -462,7 +405,6 @@ static int fp_id_to_vindex(int panel_id)
462 LCD_PANEL_ID1_800X600; 405 LCD_PANEL_ID1_800X600;
463 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0; 406 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
464 viaparinfo->lvds_setting_info->LCDDithering = 1; 407 viaparinfo->lvds_setting_info->LCDDithering = 1;
465 return VIA_RES_800X600;
466 } 408 }
467} 409}
468 410
@@ -573,284 +515,6 @@ static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
573 } 515 }
574} 516}
575 517
576static void load_lcd_k400_patch_tbl(int set_hres, int set_vres,
577 int panel_id)
578{
579 int vmode_index;
580 int reg_num = 0;
581 struct io_reg *lcd_patch_reg = NULL;
582
583 vmode_index = viafb_get_mode_index(set_hres, set_vres);
584 switch (panel_id) {
585 /* LCD 800x600 */
586 case LCD_PANEL_ID1_800X600:
587 switch (vmode_index) {
588 case VIA_RES_640X400:
589 case VIA_RES_640X480:
590 reg_num = NUM_TOTAL_K400_LCD_RES_6X4_8X6;
591 lcd_patch_reg = K400_LCD_RES_6X4_8X6;
592 break;
593 case VIA_RES_720X480:
594 case VIA_RES_720X576:
595 reg_num = NUM_TOTAL_K400_LCD_RES_7X4_8X6;
596 lcd_patch_reg = K400_LCD_RES_7X4_8X6;
597 break;
598 }
599 break;
600
601 /* LCD 1024x768 */
602 case LCD_PANEL_ID2_1024X768:
603 switch (vmode_index) {
604 case VIA_RES_640X400:
605 case VIA_RES_640X480:
606 reg_num = NUM_TOTAL_K400_LCD_RES_6X4_10X7;
607 lcd_patch_reg = K400_LCD_RES_6X4_10X7;
608 break;
609 case VIA_RES_720X480:
610 case VIA_RES_720X576:
611 reg_num = NUM_TOTAL_K400_LCD_RES_7X4_10X7;
612 lcd_patch_reg = K400_LCD_RES_7X4_10X7;
613 break;
614 case VIA_RES_800X600:
615 reg_num = NUM_TOTAL_K400_LCD_RES_8X6_10X7;
616 lcd_patch_reg = K400_LCD_RES_8X6_10X7;
617 break;
618 }
619 break;
620
621 /* LCD 1280x1024 */
622 case LCD_PANEL_ID4_1280X1024:
623 switch (vmode_index) {
624 case VIA_RES_640X400:
625 case VIA_RES_640X480:
626 reg_num = NUM_TOTAL_K400_LCD_RES_6X4_12X10;
627 lcd_patch_reg = K400_LCD_RES_6X4_12X10;
628 break;
629 case VIA_RES_720X480:
630 case VIA_RES_720X576:
631 reg_num = NUM_TOTAL_K400_LCD_RES_7X4_12X10;
632 lcd_patch_reg = K400_LCD_RES_7X4_12X10;
633 break;
634 case VIA_RES_800X600:
635 reg_num = NUM_TOTAL_K400_LCD_RES_8X6_12X10;
636 lcd_patch_reg = K400_LCD_RES_8X6_12X10;
637 break;
638 case VIA_RES_1024X768:
639 reg_num = NUM_TOTAL_K400_LCD_RES_10X7_12X10;
640 lcd_patch_reg = K400_LCD_RES_10X7_12X10;
641 break;
642
643 }
644 break;
645
646 /* LCD 1400x1050 */
647 case LCD_PANEL_ID5_1400X1050:
648 switch (vmode_index) {
649 case VIA_RES_640X480:
650 reg_num = NUM_TOTAL_K400_LCD_RES_6X4_14X10;
651 lcd_patch_reg = K400_LCD_RES_6X4_14X10;
652 break;
653 case VIA_RES_800X600:
654 reg_num = NUM_TOTAL_K400_LCD_RES_8X6_14X10;
655 lcd_patch_reg = K400_LCD_RES_8X6_14X10;
656 break;
657 case VIA_RES_1024X768:
658 reg_num = NUM_TOTAL_K400_LCD_RES_10X7_14X10;
659 lcd_patch_reg = K400_LCD_RES_10X7_14X10;
660 break;
661 case VIA_RES_1280X768:
662 case VIA_RES_1280X800:
663 case VIA_RES_1280X960:
664 case VIA_RES_1280X1024:
665 reg_num = NUM_TOTAL_K400_LCD_RES_12X10_14X10;
666 lcd_patch_reg = K400_LCD_RES_12X10_14X10;
667 break;
668 }
669 break;
670
671 /* LCD 1600x1200 */
672 case LCD_PANEL_ID6_1600X1200:
673 switch (vmode_index) {
674 case VIA_RES_640X400:
675 case VIA_RES_640X480:
676 reg_num = NUM_TOTAL_K400_LCD_RES_6X4_16X12;
677 lcd_patch_reg = K400_LCD_RES_6X4_16X12;
678 break;
679 case VIA_RES_720X480:
680 case VIA_RES_720X576:
681 reg_num = NUM_TOTAL_K400_LCD_RES_7X4_16X12;
682 lcd_patch_reg = K400_LCD_RES_7X4_16X12;
683 break;
684 case VIA_RES_800X600:
685 reg_num = NUM_TOTAL_K400_LCD_RES_8X6_16X12;
686 lcd_patch_reg = K400_LCD_RES_8X6_16X12;
687 break;
688 case VIA_RES_1024X768:
689 reg_num = NUM_TOTAL_K400_LCD_RES_10X7_16X12;
690 lcd_patch_reg = K400_LCD_RES_10X7_16X12;
691 break;
692 case VIA_RES_1280X768:
693 case VIA_RES_1280X800:
694 case VIA_RES_1280X960:
695 case VIA_RES_1280X1024:
696 reg_num = NUM_TOTAL_K400_LCD_RES_12X10_16X12;
697 lcd_patch_reg = K400_LCD_RES_12X10_16X12;
698 break;
699 }
700 break;
701
702 /* LCD 1366x768 */
703 case LCD_PANEL_ID7_1366X768:
704 switch (vmode_index) {
705 case VIA_RES_640X480:
706 reg_num = NUM_TOTAL_K400_LCD_RES_6X4_1366X7;
707 lcd_patch_reg = K400_LCD_RES_6X4_1366X7;
708 break;
709 case VIA_RES_720X480:
710 case VIA_RES_720X576:
711 reg_num = NUM_TOTAL_K400_LCD_RES_7X4_1366X7;
712 lcd_patch_reg = K400_LCD_RES_7X4_1366X7;
713 break;
714 case VIA_RES_800X600:
715 reg_num = NUM_TOTAL_K400_LCD_RES_8X6_1366X7;
716 lcd_patch_reg = K400_LCD_RES_8X6_1366X7;
717 break;
718 case VIA_RES_1024X768:
719 reg_num = NUM_TOTAL_K400_LCD_RES_10X7_1366X7;
720 lcd_patch_reg = K400_LCD_RES_10X7_1366X7;
721 break;
722 case VIA_RES_1280X768:
723 case VIA_RES_1280X800:
724 case VIA_RES_1280X960:
725 case VIA_RES_1280X1024:
726 reg_num = NUM_TOTAL_K400_LCD_RES_12X10_1366X7;
727 lcd_patch_reg = K400_LCD_RES_12X10_1366X7;
728 break;
729 }
730 break;
731
732 /* LCD 1360x768 */
733 case LCD_PANEL_IDB_1360X768:
734 break;
735 }
736 if (reg_num != 0) {
737 /* H.W. Reset : ON */
738 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
739
740 viafb_write_regx(lcd_patch_reg, reg_num);
741
742 /* H.W. Reset : OFF */
743 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
744
745 /* Reset PLL */
746 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
747 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
748
749 /* Fire! */
750 outb(inb(VIARMisc) | (BIT2 + BIT3), VIAWMisc);
751 }
752}
753
754static void load_lcd_p880_patch_tbl(int set_hres, int set_vres,
755 int panel_id)
756{
757 int vmode_index;
758 int reg_num = 0;
759 struct io_reg *lcd_patch_reg = NULL;
760
761 vmode_index = viafb_get_mode_index(set_hres, set_vres);
762
763 switch (panel_id) {
764 case LCD_PANEL_ID5_1400X1050:
765 switch (vmode_index) {
766 case VIA_RES_640X480:
767 reg_num = NUM_TOTAL_P880_LCD_RES_6X4_14X10;
768 lcd_patch_reg = P880_LCD_RES_6X4_14X10;
769 break;
770 case VIA_RES_800X600:
771 reg_num = NUM_TOTAL_P880_LCD_RES_8X6_14X10;
772 lcd_patch_reg = P880_LCD_RES_8X6_14X10;
773 break;
774 }
775 break;
776 case LCD_PANEL_ID6_1600X1200:
777 switch (vmode_index) {
778 case VIA_RES_640X400:
779 case VIA_RES_640X480:
780 reg_num = NUM_TOTAL_P880_LCD_RES_6X4_16X12;
781 lcd_patch_reg = P880_LCD_RES_6X4_16X12;
782 break;
783 case VIA_RES_720X480:
784 case VIA_RES_720X576:
785 reg_num = NUM_TOTAL_P880_LCD_RES_7X4_16X12;
786 lcd_patch_reg = P880_LCD_RES_7X4_16X12;
787 break;
788 case VIA_RES_800X600:
789 reg_num = NUM_TOTAL_P880_LCD_RES_8X6_16X12;
790 lcd_patch_reg = P880_LCD_RES_8X6_16X12;
791 break;
792 case VIA_RES_1024X768:
793 reg_num = NUM_TOTAL_P880_LCD_RES_10X7_16X12;
794 lcd_patch_reg = P880_LCD_RES_10X7_16X12;
795 break;
796 case VIA_RES_1280X768:
797 case VIA_RES_1280X960:
798 case VIA_RES_1280X1024:
799 reg_num = NUM_TOTAL_P880_LCD_RES_12X10_16X12;
800 lcd_patch_reg = P880_LCD_RES_12X10_16X12;
801 break;
802 }
803 break;
804
805 }
806 if (reg_num != 0) {
807 /* H.W. Reset : ON */
808 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
809
810 viafb_write_regx(lcd_patch_reg, reg_num);
811
812 /* H.W. Reset : OFF */
813 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
814
815 /* Reset PLL */
816 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
817 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
818
819 /* Fire! */
820 outb(inb(VIARMisc) | (BIT2 + BIT3), VIAWMisc);
821 }
822}
823
824static void load_lcd_patch_regs(int set_hres, int set_vres,
825 int panel_id, int set_iga)
826{
827 int vmode_index;
828
829 vmode_index = viafb_get_mode_index(set_hres, set_vres);
830
831 viafb_unlock_crt();
832
833 /* Patch for simultaneous & Expansion */
834 if ((set_iga == IGA1_IGA2) &&
835 (viaparinfo->lvds_setting_info->display_method ==
836 LCD_EXPANDSION)) {
837 switch (viaparinfo->chip_info->gfx_chip_name) {
838 case UNICHROME_CLE266:
839 case UNICHROME_K400:
840 load_lcd_k400_patch_tbl(set_hres, set_vres, panel_id);
841 break;
842 case UNICHROME_K800:
843 break;
844 case UNICHROME_PM800:
845 case UNICHROME_CN700:
846 case UNICHROME_CX700:
847 load_lcd_p880_patch_tbl(set_hres, set_vres, panel_id);
848 }
849 }
850
851 viafb_lock_crt();
852}
853
854static void via_pitch_alignment_patch_lcd( 518static void via_pitch_alignment_patch_lcd(
855 struct lvds_setting_information *plvds_setting_info, 519 struct lvds_setting_information *plvds_setting_info,
856 struct lvds_chip_information 520 struct lvds_chip_information
@@ -949,29 +613,25 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
949 struct lvds_setting_information *plvds_setting_info, 613 struct lvds_setting_information *plvds_setting_info,
950 struct lvds_chip_information *plvds_chip_info) 614 struct lvds_chip_information *plvds_chip_info)
951{ 615{
952 int video_index = plvds_setting_info->lcd_panel_size;
953 int set_iga = plvds_setting_info->iga_path; 616 int set_iga = plvds_setting_info->iga_path;
954 int mode_bpp = plvds_setting_info->bpp; 617 int mode_bpp = plvds_setting_info->bpp;
955 int set_hres, set_vres; 618 int set_hres = plvds_setting_info->h_active;
956 int panel_hres, panel_vres; 619 int set_vres = plvds_setting_info->v_active;
620 int panel_hres = plvds_setting_info->lcd_panel_hres;
621 int panel_vres = plvds_setting_info->lcd_panel_vres;
957 u32 pll_D_N; 622 u32 pll_D_N;
958 int offset;
959 struct display_timing mode_crt_reg, panel_crt_reg; 623 struct display_timing mode_crt_reg, panel_crt_reg;
960 struct crt_mode_table *panel_crt_table = NULL; 624 struct crt_mode_table *panel_crt_table = NULL;
961 struct VideoModeTable *vmode_tbl = NULL; 625 struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres,
626 panel_vres);
962 627
963 DEBUG_MSG(KERN_INFO "viafb_lcd_set_mode!!\n"); 628 DEBUG_MSG(KERN_INFO "viafb_lcd_set_mode!!\n");
964 /* Get mode table */ 629 /* Get mode table */
965 mode_crt_reg = mode_crt_table->crtc; 630 mode_crt_reg = mode_crt_table->crtc;
966 /* Get panel table Pointer */ 631 /* Get panel table Pointer */
967 vmode_tbl = viafb_get_modetbl_pointer(video_index);
968 panel_crt_table = vmode_tbl->crtc; 632 panel_crt_table = vmode_tbl->crtc;
969 panel_crt_reg = panel_crt_table->crtc; 633 panel_crt_reg = panel_crt_table->crtc;
970 DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n"); 634 DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");
971 set_hres = plvds_setting_info->h_active;
972 set_vres = plvds_setting_info->v_active;
973 panel_hres = plvds_setting_info->lcd_panel_hres;
974 panel_vres = plvds_setting_info->lcd_panel_vres;
975 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) 635 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)
976 viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info); 636 viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
977 plvds_setting_info->vclk = panel_crt_table->clk; 637 plvds_setting_info->vclk = panel_crt_table->clk;
@@ -1001,54 +661,12 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
1001 } 661 }
1002 } 662 }
1003 663
1004 if (set_iga == IGA1_IGA2) { 664 /* Fetch count for IGA2 only */
1005 load_crtc_shadow_timing(mode_crt_reg, panel_crt_reg); 665 viafb_load_fetch_count_reg(set_hres, mode_bpp / 8, set_iga);
1006 /* Fill shadow registers */
1007
1008 switch (plvds_setting_info->lcd_panel_id) {
1009 case LCD_PANEL_ID0_640X480:
1010 offset = 80;
1011 break;
1012 case LCD_PANEL_ID1_800X600:
1013 case LCD_PANEL_IDA_800X480:
1014 offset = 110;
1015 break;
1016 case LCD_PANEL_ID2_1024X768:
1017 offset = 150;
1018 break;
1019 case LCD_PANEL_ID3_1280X768:
1020 case LCD_PANEL_ID4_1280X1024:
1021 case LCD_PANEL_ID5_1400X1050:
1022 case LCD_PANEL_ID9_1280X800:
1023 offset = 190;
1024 break;
1025 case LCD_PANEL_ID6_1600X1200:
1026 offset = 250;
1027 break;
1028 case LCD_PANEL_ID7_1366X768:
1029 case LCD_PANEL_IDB_1360X768:
1030 offset = 212;
1031 break;
1032 default:
1033 offset = 140;
1034 break;
1035 }
1036
1037 /* Offset for simultaneous */
1038 viafb_set_secondary_pitch(offset << 3);
1039 DEBUG_MSG(KERN_INFO "viafb_load_reg!!\n");
1040 viafb_load_fetch_count_reg(set_hres, 4, IGA2);
1041 /* Fetch count for simultaneous */
1042 } else { /* SAMM */
1043 /* Fetch count for IGA2 only */
1044 viafb_load_fetch_count_reg(set_hres, mode_bpp / 8, set_iga);
1045
1046 if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1047 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1048 viafb_load_FIFO_reg(set_iga, set_hres, set_vres);
1049 666
1050 viafb_set_color_depth(mode_bpp / 8, set_iga); 667 if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1051 } 668 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
669 viafb_load_FIFO_reg(set_iga, set_hres, set_vres);
1052 670
1053 fill_lcd_format(); 671 fill_lcd_format();
1054 672
@@ -1065,11 +683,6 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
1065 || (UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)) 683 || (UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name))
1066 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0); 684 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);
1067 685
1068 load_lcd_patch_regs(set_hres, set_vres,
1069 plvds_setting_info->lcd_panel_id, set_iga);
1070
1071 DEBUG_MSG(KERN_INFO "load_lcd_patch_regs!!\n");
1072
1073 /* Patch for non 32bit alignment mode */ 686 /* Patch for non 32bit alignment mode */
1074 via_pitch_alignment_patch_lcd(plvds_setting_info, plvds_chip_info); 687 via_pitch_alignment_patch_lcd(plvds_setting_info, plvds_chip_info);
1075} 688}
@@ -1283,8 +896,7 @@ void viafb_lcd_enable(void)
1283 viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48); 896 viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48);
1284 } 897 }
1285 898
1286 if ((viaparinfo->lvds_setting_info->iga_path == IGA1) 899 if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
1287 || (viaparinfo->lvds_setting_info->iga_path == IGA1_IGA2)) {
1288 /* CRT path set to IGA2 */ 900 /* CRT path set to IGA2 */
1289 viafb_write_reg_mask(SR16, VIASR, 0x40, 0x40); 901 viafb_write_reg_mask(SR16, VIASR, 0x40, 0x40);
1290 /* IGA2 path disabled */ 902 /* IGA2 path disabled */
@@ -1476,210 +1088,6 @@ static struct display_timing lcd_centering_timging(struct display_timing
1476 return crt_reg; 1088 return crt_reg;
1477} 1089}
1478 1090
1479static void load_crtc_shadow_timing(struct display_timing mode_timing,
1480 struct display_timing panel_timing)
1481{
1482 struct io_register *reg = NULL;
1483 int i;
1484 int viafb_load_reg_Num = 0;
1485 int reg_value = 0;
1486
1487 if (viaparinfo->lvds_setting_info->display_method == LCD_EXPANDSION) {
1488 /* Expansion */
1489 for (i = 12; i < 20; i++) {
1490 switch (i) {
1491 case H_TOTAL_SHADOW_INDEX:
1492 reg_value =
1493 IGA2_HOR_TOTAL_SHADOW_FORMULA
1494 (panel_timing.hor_total);
1495 viafb_load_reg_Num =
1496 iga2_shadow_crtc_reg.hor_total_shadow.
1497 reg_num;
1498 reg = iga2_shadow_crtc_reg.hor_total_shadow.reg;
1499 break;
1500 case H_BLANK_END_SHADOW_INDEX:
1501 reg_value =
1502 IGA2_HOR_BLANK_END_SHADOW_FORMULA
1503 (panel_timing.hor_blank_start,
1504 panel_timing.hor_blank_end);
1505 viafb_load_reg_Num =
1506 iga2_shadow_crtc_reg.
1507 hor_blank_end_shadow.reg_num;
1508 reg =
1509 iga2_shadow_crtc_reg.
1510 hor_blank_end_shadow.reg;
1511 break;
1512 case V_TOTAL_SHADOW_INDEX:
1513 reg_value =
1514 IGA2_VER_TOTAL_SHADOW_FORMULA
1515 (panel_timing.ver_total);
1516 viafb_load_reg_Num =
1517 iga2_shadow_crtc_reg.ver_total_shadow.
1518 reg_num;
1519 reg = iga2_shadow_crtc_reg.ver_total_shadow.reg;
1520 break;
1521 case V_ADDR_SHADOW_INDEX:
1522 reg_value =
1523 IGA2_VER_ADDR_SHADOW_FORMULA
1524 (panel_timing.ver_addr);
1525 viafb_load_reg_Num =
1526 iga2_shadow_crtc_reg.ver_addr_shadow.
1527 reg_num;
1528 reg = iga2_shadow_crtc_reg.ver_addr_shadow.reg;
1529 break;
1530 case V_BLANK_SATRT_SHADOW_INDEX:
1531 reg_value =
1532 IGA2_VER_BLANK_START_SHADOW_FORMULA
1533 (panel_timing.ver_blank_start);
1534 viafb_load_reg_Num =
1535 iga2_shadow_crtc_reg.
1536 ver_blank_start_shadow.reg_num;
1537 reg =
1538 iga2_shadow_crtc_reg.
1539 ver_blank_start_shadow.reg;
1540 break;
1541 case V_BLANK_END_SHADOW_INDEX:
1542 reg_value =
1543 IGA2_VER_BLANK_END_SHADOW_FORMULA
1544 (panel_timing.ver_blank_start,
1545 panel_timing.ver_blank_end);
1546 viafb_load_reg_Num =
1547 iga2_shadow_crtc_reg.
1548 ver_blank_end_shadow.reg_num;
1549 reg =
1550 iga2_shadow_crtc_reg.
1551 ver_blank_end_shadow.reg;
1552 break;
1553 case V_SYNC_SATRT_SHADOW_INDEX:
1554 reg_value =
1555 IGA2_VER_SYNC_START_SHADOW_FORMULA
1556 (panel_timing.ver_sync_start);
1557 viafb_load_reg_Num =
1558 iga2_shadow_crtc_reg.
1559 ver_sync_start_shadow.reg_num;
1560 reg =
1561 iga2_shadow_crtc_reg.
1562 ver_sync_start_shadow.reg;
1563 break;
1564 case V_SYNC_END_SHADOW_INDEX:
1565 reg_value =
1566 IGA2_VER_SYNC_END_SHADOW_FORMULA
1567 (panel_timing.ver_sync_start,
1568 panel_timing.ver_sync_end);
1569 viafb_load_reg_Num =
1570 iga2_shadow_crtc_reg.
1571 ver_sync_end_shadow.reg_num;
1572 reg =
1573 iga2_shadow_crtc_reg.
1574 ver_sync_end_shadow.reg;
1575 break;
1576 }
1577 viafb_load_reg(reg_value,
1578 viafb_load_reg_Num, reg, VIACR);
1579 }
1580 } else { /* Centering */
1581 for (i = 12; i < 20; i++) {
1582 switch (i) {
1583 case H_TOTAL_SHADOW_INDEX:
1584 reg_value =
1585 IGA2_HOR_TOTAL_SHADOW_FORMULA
1586 (panel_timing.hor_total);
1587 viafb_load_reg_Num =
1588 iga2_shadow_crtc_reg.hor_total_shadow.
1589 reg_num;
1590 reg = iga2_shadow_crtc_reg.hor_total_shadow.reg;
1591 break;
1592 case H_BLANK_END_SHADOW_INDEX:
1593 reg_value =
1594 IGA2_HOR_BLANK_END_SHADOW_FORMULA
1595 (panel_timing.hor_blank_start,
1596 panel_timing.hor_blank_end);
1597 viafb_load_reg_Num =
1598 iga2_shadow_crtc_reg.
1599 hor_blank_end_shadow.reg_num;
1600 reg =
1601 iga2_shadow_crtc_reg.
1602 hor_blank_end_shadow.reg;
1603 break;
1604 case V_TOTAL_SHADOW_INDEX:
1605 reg_value =
1606 IGA2_VER_TOTAL_SHADOW_FORMULA
1607 (panel_timing.ver_total);
1608 viafb_load_reg_Num =
1609 iga2_shadow_crtc_reg.ver_total_shadow.
1610 reg_num;
1611 reg = iga2_shadow_crtc_reg.ver_total_shadow.reg;
1612 break;
1613 case V_ADDR_SHADOW_INDEX:
1614 reg_value =
1615 IGA2_VER_ADDR_SHADOW_FORMULA
1616 (mode_timing.ver_addr);
1617 viafb_load_reg_Num =
1618 iga2_shadow_crtc_reg.ver_addr_shadow.
1619 reg_num;
1620 reg = iga2_shadow_crtc_reg.ver_addr_shadow.reg;
1621 break;
1622 case V_BLANK_SATRT_SHADOW_INDEX:
1623 reg_value =
1624 IGA2_VER_BLANK_START_SHADOW_FORMULA
1625 (mode_timing.ver_blank_start);
1626 viafb_load_reg_Num =
1627 iga2_shadow_crtc_reg.
1628 ver_blank_start_shadow.reg_num;
1629 reg =
1630 iga2_shadow_crtc_reg.
1631 ver_blank_start_shadow.reg;
1632 break;
1633 case V_BLANK_END_SHADOW_INDEX:
1634 reg_value =
1635 IGA2_VER_BLANK_END_SHADOW_FORMULA
1636 (panel_timing.ver_blank_start,
1637 panel_timing.ver_blank_end);
1638 viafb_load_reg_Num =
1639 iga2_shadow_crtc_reg.
1640 ver_blank_end_shadow.reg_num;
1641 reg =
1642 iga2_shadow_crtc_reg.
1643 ver_blank_end_shadow.reg;
1644 break;
1645 case V_SYNC_SATRT_SHADOW_INDEX:
1646 reg_value =
1647 IGA2_VER_SYNC_START_SHADOW_FORMULA(
1648 (panel_timing.ver_sync_start -
1649 panel_timing.ver_blank_start) +
1650 (panel_timing.ver_addr -
1651 mode_timing.ver_addr) / 2 +
1652 mode_timing.ver_addr);
1653 viafb_load_reg_Num =
1654 iga2_shadow_crtc_reg.ver_sync_start_shadow.
1655 reg_num;
1656 reg =
1657 iga2_shadow_crtc_reg.ver_sync_start_shadow.
1658 reg;
1659 break;
1660 case V_SYNC_END_SHADOW_INDEX:
1661 reg_value =
1662 IGA2_VER_SYNC_END_SHADOW_FORMULA(
1663 (panel_timing.ver_sync_start -
1664 panel_timing.ver_blank_start) +
1665 (panel_timing.ver_addr -
1666 mode_timing.ver_addr) / 2 +
1667 mode_timing.ver_addr,
1668 panel_timing.ver_sync_end);
1669 viafb_load_reg_Num =
1670 iga2_shadow_crtc_reg.ver_sync_end_shadow.
1671 reg_num;
1672 reg =
1673 iga2_shadow_crtc_reg.ver_sync_end_shadow.
1674 reg;
1675 break;
1676 }
1677 viafb_load_reg(reg_value,
1678 viafb_load_reg_Num, reg, VIACR);
1679 }
1680 }
1681}
1682
1683bool viafb_lcd_get_mobile_state(bool *mobile) 1091bool viafb_lcd_get_mobile_state(bool *mobile)
1684{ 1092{
1685 unsigned char *romptr, *tableptr; 1093 unsigned char *romptr, *tableptr;
diff --git a/drivers/video/via/share.h b/drivers/video/via/share.h
index 7cd03e2a127..d55aaa7b912 100644
--- a/drivers/video/via/share.h
+++ b/drivers/video/via/share.h
@@ -43,61 +43,6 @@
43/* Video Memory Size */ 43/* Video Memory Size */
44#define VIDEO_MEMORY_SIZE_16M 0x1000000 44#define VIDEO_MEMORY_SIZE_16M 0x1000000
45 45
46/* Definition Mode Index
47*/
48#define VIA_RES_640X480 0
49#define VIA_RES_800X600 1
50#define VIA_RES_1024X768 2
51#define VIA_RES_1152X864 3
52#define VIA_RES_1280X1024 4
53#define VIA_RES_1600X1200 5
54#define VIA_RES_1440X1050 6
55#define VIA_RES_1280X768 7
56#define VIA_RES_1280X960 8
57#define VIA_RES_1920X1440 9
58#define VIA_RES_848X480 10
59#define VIA_RES_1400X1050 11
60#define VIA_RES_720X480 12
61#define VIA_RES_720X576 13
62#define VIA_RES_1024X512 14
63#define VIA_RES_856X480 15
64#define VIA_RES_1024X576 16
65#define VIA_RES_640X400 17
66#define VIA_RES_1280X720 18
67#define VIA_RES_1920X1080 19
68#define VIA_RES_800X480 20
69#define VIA_RES_1368X768 21
70#define VIA_RES_1024X600 22
71#define VIA_RES_1280X800 23
72#define VIA_RES_1680X1050 24
73#define VIA_RES_960X600 25
74#define VIA_RES_1000X600 26
75#define VIA_RES_1088X612 27
76#define VIA_RES_1152X720 28
77#define VIA_RES_1200X720 29
78#define VIA_RES_1280X600 30
79#define VIA_RES_1360X768 31
80#define VIA_RES_1366X768 32
81#define VIA_RES_1440X900 33
82#define VIA_RES_1600X900 34
83#define VIA_RES_1600X1024 35
84#define VIA_RES_1792X1344 36
85#define VIA_RES_1856X1392 37
86#define VIA_RES_1920X1200 38
87#define VIA_RES_2048X1536 39
88#define VIA_RES_480X640 40
89
90/*Reduce Blanking*/
91#define VIA_RES_1360X768_RB 131
92#define VIA_RES_1440X900_RB 133
93#define VIA_RES_1400X1050_RB 111
94#define VIA_RES_1600X900_RB 134
95#define VIA_RES_1680X1050_RB 124
96#define VIA_RES_1920X1080_RB 119
97#define VIA_RES_1920X1200_RB 138
98
99#define VIA_RES_INVALID 255
100
101/* standard VGA IO port 46/* standard VGA IO port
102*/ 47*/
103#define VIARMisc 0x3CC 48#define VIARMisc 0x3CC
@@ -118,7 +63,6 @@
118/* Display path */ 63/* Display path */
119#define IGA1 1 64#define IGA1 1
120#define IGA2 2 65#define IGA2 2
121#define IGA1_IGA2 3
122 66
123/* Define Color Depth */ 67/* Define Color Depth */
124#define MODE_8BPP 1 68#define MODE_8BPP 1
diff --git a/drivers/video/via/via_utility.c b/drivers/video/via/via_utility.c
index d53c3d54ed8..aefdeeec89b 100644
--- a/drivers/video/via/via_utility.c
+++ b/drivers/video/via/via_utility.c
@@ -239,15 +239,3 @@ void viafb_get_gamma_support_state(int bpp, unsigned int *support_state)
239 else 239 else
240 *support_state = CRT_Device | DVI_Device | LCD_Device; 240 *support_state = CRT_Device | DVI_Device | LCD_Device;
241} 241}
242
243int viafb_input_parameter_converter(int parameter_value)
244{
245 int result;
246
247 if (parameter_value >= 1 && parameter_value <= 9)
248 result = 1 << (parameter_value - 1);
249 else
250 result = 1;
251
252 return result;
253}
diff --git a/drivers/video/via/via_utility.h b/drivers/video/via/via_utility.h
index 2fd455202eb..1670ba82143 100644
--- a/drivers/video/via/via_utility.h
+++ b/drivers/video/via/via_utility.h
@@ -30,6 +30,5 @@ bool viafb_lcd_get_support_expand_state(u32 xres, u32 yres);
30void viafb_set_gamma_table(int bpp, unsigned int *gamma_table); 30void viafb_set_gamma_table(int bpp, unsigned int *gamma_table);
31void viafb_get_gamma_table(unsigned int *gamma_table); 31void viafb_get_gamma_table(unsigned int *gamma_table);
32void viafb_get_gamma_support_state(int bpp, unsigned int *support_state); 32void viafb_get_gamma_support_state(int bpp, unsigned int *support_state);
33int viafb_input_parameter_converter(int parameter_value);
34 33
35#endif /* __VIAUTILITY_H__ */ 34#endif /* __VIAUTILITY_H__ */
diff --git a/drivers/video/via/viafbdev.c b/drivers/video/via/viafbdev.c
index 3028e7ddc3b..ce7783b63f6 100644
--- a/drivers/video/via/viafbdev.c
+++ b/drivers/video/via/viafbdev.c
@@ -26,18 +26,22 @@
26 26
27#include "global.h" 27#include "global.h"
28 28
29static struct fb_var_screeninfo default_var;
30static char *viafb_name = "Via"; 29static char *viafb_name = "Via";
31static u32 pseudo_pal[17]; 30static u32 pseudo_pal[17];
32 31
33/* video mode */ 32/* video mode */
34static char *viafb_mode = "640x480"; 33static char *viafb_mode;
35static char *viafb_mode1 = "640x480"; 34static char *viafb_mode1;
35static int viafb_bpp = 32;
36static int viafb_bpp1 = 32;
37
38static unsigned int viafb_second_offset;
39static int viafb_second_size;
36 40
37static int viafb_accel = 1; 41static int viafb_accel = 1;
38 42
39/* Added for specifying active devices.*/ 43/* Added for specifying active devices.*/
40char *viafb_active_dev = ""; 44char *viafb_active_dev;
41 45
42/*Added for specify lcd output port*/ 46/*Added for specify lcd output port*/
43char *viafb_lcd_port = ""; 47char *viafb_lcd_port = "";
@@ -50,18 +54,78 @@ static void apply_second_mode_setting(struct fb_var_screeninfo
50 *sec_var); 54 *sec_var);
51static void retrieve_device_setting(struct viafb_ioctl_setting 55static void retrieve_device_setting(struct viafb_ioctl_setting
52 *setting_info); 56 *setting_info);
57static int viafb_pan_display(struct fb_var_screeninfo *var,
58 struct fb_info *info);
53 59
54static struct fb_ops viafb_ops; 60static struct fb_ops viafb_ops;
55 61
56 62
63static void viafb_fill_var_color_info(struct fb_var_screeninfo *var, u8 depth)
64{
65 var->grayscale = 0;
66 var->red.msb_right = 0;
67 var->green.msb_right = 0;
68 var->blue.msb_right = 0;
69 var->transp.offset = 0;
70 var->transp.length = 0;
71 var->transp.msb_right = 0;
72 var->nonstd = 0;
73 switch (depth) {
74 case 8:
75 var->bits_per_pixel = 8;
76 var->red.offset = 0;
77 var->green.offset = 0;
78 var->blue.offset = 0;
79 var->red.length = 8;
80 var->green.length = 8;
81 var->blue.length = 8;
82 break;
83 case 15:
84 var->bits_per_pixel = 16;
85 var->red.offset = 10;
86 var->green.offset = 5;
87 var->blue.offset = 0;
88 var->red.length = 5;
89 var->green.length = 5;
90 var->blue.length = 5;
91 break;
92 case 16:
93 var->bits_per_pixel = 16;
94 var->red.offset = 11;
95 var->green.offset = 5;
96 var->blue.offset = 0;
97 var->red.length = 5;
98 var->green.length = 6;
99 var->blue.length = 5;
100 break;
101 case 24:
102 var->bits_per_pixel = 32;
103 var->red.offset = 16;
104 var->green.offset = 8;
105 var->blue.offset = 0;
106 var->red.length = 8;
107 var->green.length = 8;
108 var->blue.length = 8;
109 break;
110 case 30:
111 var->bits_per_pixel = 32;
112 var->red.offset = 20;
113 var->green.offset = 10;
114 var->blue.offset = 0;
115 var->red.length = 10;
116 var->green.length = 10;
117 var->blue.length = 10;
118 break;
119 }
120}
121
57static void viafb_update_fix(struct fb_info *info) 122static void viafb_update_fix(struct fb_info *info)
58{ 123{
59 u32 bpp = info->var.bits_per_pixel; 124 u32 bpp = info->var.bits_per_pixel;
60 125
61 info->fix.visual = 126 info->fix.visual =
62 bpp == 8 ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; 127 bpp == 8 ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
63 info->fix.line_length = 128 info->fix.line_length = (info->var.xres_virtual * bpp / 8 + 7) & ~7;
64 ((info->var.xres_virtual + 7) & ~7) * bpp / 8;
65} 129}
66 130
67static void viafb_setup_fixinfo(struct fb_fix_screeninfo *fix, 131static void viafb_setup_fixinfo(struct fb_fix_screeninfo *fix,
@@ -75,6 +139,7 @@ static void viafb_setup_fixinfo(struct fb_fix_screeninfo *fix,
75 139
76 fix->type = FB_TYPE_PACKED_PIXELS; 140 fix->type = FB_TYPE_PACKED_PIXELS;
77 fix->type_aux = 0; 141 fix->type_aux = 0;
142 fix->visual = FB_VISUAL_TRUECOLOR;
78 143
79 fix->xpanstep = fix->ywrapstep = 0; 144 fix->xpanstep = fix->ywrapstep = 0;
80 fix->ypanstep = 1; 145 fix->ypanstep = 1;
@@ -97,9 +162,10 @@ static int viafb_release(struct fb_info *info, int user)
97static int viafb_check_var(struct fb_var_screeninfo *var, 162static int viafb_check_var(struct fb_var_screeninfo *var,
98 struct fb_info *info) 163 struct fb_info *info)
99{ 164{
100 int vmode_index, htotal, vtotal; 165 int htotal, vtotal, depth;
166 struct VideoModeTable *vmode_entry;
101 struct viafb_par *ppar = info->par; 167 struct viafb_par *ppar = info->par;
102 u32 long_refresh; 168 u32 long_refresh, line;
103 169
104 DEBUG_MSG(KERN_INFO "viafb_check_var!\n"); 170 DEBUG_MSG(KERN_INFO "viafb_check_var!\n");
105 /* Sanity check */ 171 /* Sanity check */
@@ -107,26 +173,36 @@ static int viafb_check_var(struct fb_var_screeninfo *var,
107 if (var->vmode & FB_VMODE_INTERLACED || var->vmode & FB_VMODE_DOUBLE) 173 if (var->vmode & FB_VMODE_INTERLACED || var->vmode & FB_VMODE_DOUBLE)
108 return -EINVAL; 174 return -EINVAL;
109 175
110 vmode_index = viafb_get_mode_index(var->xres, var->yres); 176 vmode_entry = viafb_get_mode(var->xres, var->yres);
111 if (vmode_index == VIA_RES_INVALID) { 177 if (!vmode_entry) {
112 DEBUG_MSG(KERN_INFO 178 DEBUG_MSG(KERN_INFO
113 "viafb: Mode %dx%dx%d not supported!!\n", 179 "viafb: Mode %dx%dx%d not supported!!\n",
114 var->xres, var->yres, var->bits_per_pixel); 180 var->xres, var->yres, var->bits_per_pixel);
115 return -EINVAL; 181 return -EINVAL;
116 } 182 }
117 183
118 if (24 == var->bits_per_pixel) 184 depth = fb_get_color_depth(var, &info->fix);
119 var->bits_per_pixel = 32; 185 if (!depth)
186 depth = var->bits_per_pixel;
120 187
121 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 && 188 if (depth < 0 || depth > 32)
122 var->bits_per_pixel != 32)
123 return -EINVAL; 189 return -EINVAL;
190 else if (!depth)
191 depth = 24;
192 else if (depth == 15 && viafb_dual_fb && ppar->iga_path == IGA1)
193 depth = 15;
194 else if (depth == 30)
195 depth = 30;
196 else if (depth <= 8)
197 depth = 8;
198 else if (depth <= 16)
199 depth = 16;
200 else
201 depth = 24;
124 202
125 if ((var->xres_virtual * (var->bits_per_pixel >> 3)) & 0x1F) 203 viafb_fill_var_color_info(var, depth);
126 /*32 pixel alignment */ 204 line = (var->xres_virtual * var->bits_per_pixel / 8 + 7) & ~7;
127 var->xres_virtual = (var->xres_virtual + 31) & ~31; 205 if (line * var->yres_virtual > ppar->memsize)
128 if (var->xres_virtual * var->yres_virtual * var->bits_per_pixel / 8 >
129 ppar->memsize)
130 return -EINVAL; 206 return -EINVAL;
131 207
132 /* Based on var passed in to calculate the refresh, 208 /* Based on var passed in to calculate the refresh,
@@ -142,7 +218,7 @@ static int viafb_check_var(struct fb_var_screeninfo *var,
142 viafb_refresh = viafb_get_refresh(var->xres, var->yres, long_refresh); 218 viafb_refresh = viafb_get_refresh(var->xres, var->yres, long_refresh);
143 219
144 /* Adjust var according to our driver's own table */ 220 /* Adjust var according to our driver's own table */
145 viafb_fill_var_timing_info(var, viafb_refresh, vmode_index); 221 viafb_fill_var_timing_info(var, viafb_refresh, vmode_entry);
146 if (info->var.accel_flags & FB_ACCELF_TEXT && 222 if (info->var.accel_flags & FB_ACCELF_TEXT &&
147 !ppar->shared->engine_mmio) 223 !ppar->shared->engine_mmio)
148 info->var.accel_flags = 0; 224 info->var.accel_flags = 0;
@@ -153,39 +229,45 @@ static int viafb_check_var(struct fb_var_screeninfo *var,
153static int viafb_set_par(struct fb_info *info) 229static int viafb_set_par(struct fb_info *info)
154{ 230{
155 struct viafb_par *viapar = info->par; 231 struct viafb_par *viapar = info->par;
156 int vmode_index; 232 struct VideoModeTable *vmode_entry, *vmode_entry1 = NULL;
157 int vmode_index1 = 0;
158 DEBUG_MSG(KERN_INFO "viafb_set_par!\n"); 233 DEBUG_MSG(KERN_INFO "viafb_set_par!\n");
159 234
160 viapar->depth = fb_get_color_depth(&info->var, &info->fix); 235 viapar->depth = fb_get_color_depth(&info->var, &info->fix);
161 viafb_update_device_setting(info->var.xres, info->var.yres, 236 viafb_update_device_setting(viafbinfo->var.xres, viafbinfo->var.yres,
162 info->var.bits_per_pixel, viafb_refresh, 0); 237 viafbinfo->var.bits_per_pixel, viafb_refresh, 0);
163 238
164 vmode_index = viafb_get_mode_index(info->var.xres, info->var.yres); 239 vmode_entry = viafb_get_mode(viafbinfo->var.xres, viafbinfo->var.yres);
165 240 if (viafb_dual_fb) {
166 if (viafb_SAMM_ON == 1) { 241 vmode_entry1 = viafb_get_mode(viafbinfo1->var.xres,
242 viafbinfo1->var.yres);
243 viafb_update_device_setting(viafbinfo1->var.xres,
244 viafbinfo1->var.yres, viafbinfo1->var.bits_per_pixel,
245 viafb_refresh1, 1);
246 } else if (viafb_SAMM_ON == 1) {
167 DEBUG_MSG(KERN_INFO 247 DEBUG_MSG(KERN_INFO
168 "viafb_second_xres = %d, viafb_second_yres = %d, bpp = %d\n", 248 "viafb_second_xres = %d, viafb_second_yres = %d, bpp = %d\n",
169 viafb_second_xres, viafb_second_yres, viafb_bpp1); 249 viafb_second_xres, viafb_second_yres, viafb_bpp1);
170 vmode_index1 = viafb_get_mode_index(viafb_second_xres, 250 vmode_entry1 = viafb_get_mode(viafb_second_xres,
171 viafb_second_yres); 251 viafb_second_yres);
172 DEBUG_MSG(KERN_INFO "->viafb_SAMM_ON: index=%d\n",
173 vmode_index1);
174 252
175 viafb_update_device_setting(viafb_second_xres, 253 viafb_update_device_setting(viafb_second_xres,
176 viafb_second_yres, viafb_bpp1, viafb_refresh1, 1); 254 viafb_second_yres, viafb_bpp1, viafb_refresh1, 1);
177 } 255 }
178 256
179 if (vmode_index != VIA_RES_INVALID) { 257 if (vmode_entry) {
180 viafb_update_fix(info); 258 viafb_update_fix(info);
181 viafb_bpp = info->var.bits_per_pixel; 259 if (viafb_dual_fb && viapar->iga_path == IGA2)
260 viafb_bpp1 = info->var.bits_per_pixel;
261 else
262 viafb_bpp = info->var.bits_per_pixel;
263
182 if (info->var.accel_flags & FB_ACCELF_TEXT) 264 if (info->var.accel_flags & FB_ACCELF_TEXT)
183 info->flags &= ~FBINFO_HWACCEL_DISABLED; 265 info->flags &= ~FBINFO_HWACCEL_DISABLED;
184 else 266 else
185 info->flags |= FBINFO_HWACCEL_DISABLED; 267 info->flags |= FBINFO_HWACCEL_DISABLED;
186 viafb_setmode(vmode_index, info->var.xres, info->var.yres, 268 viafb_setmode(vmode_entry, info->var.bits_per_pixel,
187 info->var.bits_per_pixel, vmode_index1, 269 vmode_entry1, viafb_bpp1);
188 viafb_second_xres, viafb_second_yres, viafb_bpp1); 270 viafb_pan_display(&info->var, info);
189 } 271 }
190 272
191 return 0; 273 return 0;
@@ -195,234 +277,52 @@ static int viafb_set_par(struct fb_info *info)
195static int viafb_setcolreg(unsigned regno, unsigned red, unsigned green, 277static int viafb_setcolreg(unsigned regno, unsigned red, unsigned green,
196unsigned blue, unsigned transp, struct fb_info *info) 278unsigned blue, unsigned transp, struct fb_info *info)
197{ 279{
198 u8 sr1a, sr1b, cr67, cr6a, rev = 0, shift = 10; 280 struct viafb_par *viapar = info->par;
199 unsigned cmap_entries = (info->var.bits_per_pixel == 8) ? 256 : 16; 281 u32 r, g, b;
200 DEBUG_MSG(KERN_INFO "viafb_setcolreg!\n");
201 if (regno >= cmap_entries)
202 return 1;
203 if (UNICHROME_CLE266 == viaparinfo->chip_info->gfx_chip_name) {
204 /*
205 * Read PCI bus 0,dev 0,function 0,index 0xF6 to get chip rev.
206 */
207 outl(0x80000000 | (0xf6 & ~3), (unsigned long)0xCF8);
208 rev = (inl((unsigned long)0xCFC) >> ((0xf6 & 3) * 8)) & 0xff;
209 }
210 switch (info->var.bits_per_pixel) {
211 case 8:
212 outb(0x1A, 0x3C4);
213 sr1a = inb(0x3C5);
214 outb(0x1B, 0x3C4);
215 sr1b = inb(0x3C5);
216 outb(0x67, 0x3D4);
217 cr67 = inb(0x3D5);
218 outb(0x6A, 0x3D4);
219 cr6a = inb(0x3D5);
220
221 /* Map the 3C6/7/8/9 to the IGA2 */
222 outb(0x1A, 0x3C4);
223 outb(sr1a | 0x01, 0x3C5);
224 /* Second Display Engine colck always on */
225 outb(0x1B, 0x3C4);
226 outb(sr1b | 0x80, 0x3C5);
227 /* Second Display Color Depth 8 */
228 outb(0x67, 0x3D4);
229 outb(cr67 & 0x3F, 0x3D5);
230 outb(0x6A, 0x3D4);
231 /* Second Display Channel Reset CR6A[6]) */
232 outb(cr6a & 0xBF, 0x3D5);
233 /* Second Display Channel Enable CR6A[7] */
234 outb(cr6a | 0x80, 0x3D5);
235 /* Second Display Channel stop reset) */
236 outb(cr6a | 0x40, 0x3D5);
237
238 /* Bit mask of palette */
239 outb(0xFF, 0x3c6);
240 /* Write one register of IGA2 */
241 outb(regno, 0x3C8);
242 if (UNICHROME_CLE266 == viaparinfo->chip_info->gfx_chip_name &&
243 rev >= 15) {
244 shift = 8;
245 viafb_write_reg_mask(CR6A, VIACR, BIT5, BIT5);
246 viafb_write_reg_mask(SR15, VIASR, BIT7, BIT7);
247 } else {
248 shift = 10;
249 viafb_write_reg_mask(CR6A, VIACR, 0, BIT5);
250 viafb_write_reg_mask(SR15, VIASR, 0, BIT7);
251 }
252 outb(red >> shift, 0x3C9);
253 outb(green >> shift, 0x3C9);
254 outb(blue >> shift, 0x3C9);
255
256 /* Map the 3C6/7/8/9 to the IGA1 */
257 outb(0x1A, 0x3C4);
258 outb(sr1a & 0xFE, 0x3C5);
259 /* Bit mask of palette */
260 outb(0xFF, 0x3c6);
261 /* Write one register of IGA1 */
262 outb(regno, 0x3C8);
263 outb(red >> shift, 0x3C9);
264 outb(green >> shift, 0x3C9);
265 outb(blue >> shift, 0x3C9);
266
267 outb(0x1A, 0x3C4);
268 outb(sr1a, 0x3C5);
269 outb(0x1B, 0x3C4);
270 outb(sr1b, 0x3C5);
271 outb(0x67, 0x3D4);
272 outb(cr67, 0x3D5);
273 outb(0x6A, 0x3D4);
274 outb(cr6a, 0x3D5);
275 break;
276 case 16:
277 ((u32 *) info->pseudo_palette)[regno] = (red & 0xF800) |
278 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
279 break;
280 case 32:
281 ((u32 *) info->pseudo_palette)[regno] =
282 ((transp & 0xFF00) << 16) |
283 ((red & 0xFF00) << 8) |
284 ((green & 0xFF00)) | ((blue & 0xFF00) >> 8);
285 break;
286 }
287
288 return 0;
289 282
290} 283 if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
284 if (regno > 255)
285 return -EINVAL;
291 286
292/*CALLED BY: fb_set_cmap */ 287 if (!viafb_dual_fb || viapar->iga_path == IGA1)
293/* fb_set_var, pass 256 colors */ 288 viafb_set_primary_color_register(regno, red >> 8,
294/*CALLED BY: fb_set_cmap */ 289 green >> 8, blue >> 8);
295/* fbcon_set_palette, pass 16 colors */
296static int viafb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
297{
298 u32 len = cmap->len;
299 u32 i;
300 u16 *pred = cmap->red;
301 u16 *pgreen = cmap->green;
302 u16 *pblue = cmap->blue;
303 u16 *ptransp = cmap->transp;
304 u8 sr1a, sr1b, cr67, cr6a, rev = 0, shift = 10;
305 if (len > 256)
306 return 1;
307 if (UNICHROME_CLE266 == viaparinfo->chip_info->gfx_chip_name) {
308 /*
309 * Read PCI bus 0, dev 0, function 0, index 0xF6 to get chip
310 * rev.
311 */
312 outl(0x80000000 | (0xf6 & ~3), (unsigned long)0xCF8);
313 rev = (inl((unsigned long)0xCFC) >> ((0xf6 & 3) * 8)) & 0xff;
314 }
315 switch (info->var.bits_per_pixel) {
316 case 8:
317 outb(0x1A, 0x3C4);
318 sr1a = inb(0x3C5);
319 outb(0x1B, 0x3C4);
320 sr1b = inb(0x3C5);
321 outb(0x67, 0x3D4);
322 cr67 = inb(0x3D5);
323 outb(0x6A, 0x3D4);
324 cr6a = inb(0x3D5);
325 /* Map the 3C6/7/8/9 to the IGA2 */
326 outb(0x1A, 0x3C4);
327 outb(sr1a | 0x01, 0x3C5);
328 outb(0x1B, 0x3C4);
329 /* Second Display Engine colck always on */
330 outb(sr1b | 0x80, 0x3C5);
331 outb(0x67, 0x3D4);
332 /* Second Display Color Depth 8 */
333 outb(cr67 & 0x3F, 0x3D5);
334 outb(0x6A, 0x3D4);
335 /* Second Display Channel Reset CR6A[6]) */
336 outb(cr6a & 0xBF, 0x3D5);
337 /* Second Display Channel Enable CR6A[7] */
338 outb(cr6a | 0x80, 0x3D5);
339 /* Second Display Channel stop reset) */
340 outb(cr6a | 0xC0, 0x3D5);
341
342 /* Bit mask of palette */
343 outb(0xFF, 0x3c6);
344 outb(0x00, 0x3C8);
345 if (UNICHROME_CLE266 == viaparinfo->chip_info->gfx_chip_name &&
346 rev >= 15) {
347 shift = 8;
348 viafb_write_reg_mask(CR6A, VIACR, BIT5, BIT5);
349 viafb_write_reg_mask(SR15, VIASR, BIT7, BIT7);
350 } else {
351 shift = 10;
352 viafb_write_reg_mask(CR6A, VIACR, 0, BIT5);
353 viafb_write_reg_mask(SR15, VIASR, 0, BIT7);
354 }
355 for (i = 0; i < len; i++) {
356 outb((*(pred + i)) >> shift, 0x3C9);
357 outb((*(pgreen + i)) >> shift, 0x3C9);
358 outb((*(pblue + i)) >> shift, 0x3C9);
359 }
360 290
361 outb(0x1A, 0x3C4); 291 if (!viafb_dual_fb || viapar->iga_path == IGA2)
362 /* Map the 3C6/7/8/9 to the IGA1 */ 292 viafb_set_secondary_color_register(regno, red >> 8,
363 outb(sr1a & 0xFE, 0x3C5); 293 green >> 8, blue >> 8);
364 /* Bit mask of palette */ 294 } else {
365 outb(0xFF, 0x3c6); 295 if (regno > 15)
366 outb(0x00, 0x3C8); 296 return -EINVAL;
367 for (i = 0; i < len; i++) {
368 outb((*(pred + i)) >> shift, 0x3C9);
369 outb((*(pgreen + i)) >> shift, 0x3C9);
370 outb((*(pblue + i)) >> shift, 0x3C9);
371 }
372 297
373 outb(0x1A, 0x3C4); 298 r = (red >> (16 - info->var.red.length))
374 outb(sr1a, 0x3C5); 299 << info->var.red.offset;
375 outb(0x1B, 0x3C4); 300 b = (blue >> (16 - info->var.blue.length))
376 outb(sr1b, 0x3C5); 301 << info->var.blue.offset;
377 outb(0x67, 0x3D4); 302 g = (green >> (16 - info->var.green.length))
378 outb(cr67, 0x3D5); 303 << info->var.green.offset;
379 outb(0x6A, 0x3D4); 304 ((u32 *) info->pseudo_palette)[regno] = r | g | b;
380 outb(cr6a, 0x3D5);
381 break;
382 case 16:
383 if (len > 17)
384 return 0; /* Because static u32 pseudo_pal[17]; */
385 for (i = 0; i < len; i++)
386 ((u32 *) info->pseudo_palette)[i] =
387 (*(pred + i) & 0xF800) |
388 ((*(pgreen + i) & 0xFC00) >> 5) |
389 ((*(pblue + i) & 0xF800) >> 11);
390 break;
391 case 32:
392 if (len > 17)
393 return 0;
394 if (ptransp) {
395 for (i = 0; i < len; i++)
396 ((u32 *) info->pseudo_palette)[i] =
397 ((*(ptransp + i) & 0xFF00) << 16) |
398 ((*(pred + i) & 0xFF00) << 8) |
399 ((*(pgreen + i) & 0xFF00)) |
400 ((*(pblue + i) & 0xFF00) >> 8);
401 } else {
402 for (i = 0; i < len; i++)
403 ((u32 *) info->pseudo_palette)[i] =
404 0x00000000 |
405 ((*(pred + i) & 0xFF00) << 8) |
406 ((*(pgreen + i) & 0xFF00)) |
407 ((*(pblue + i) & 0xFF00) >> 8);
408 }
409 break;
410 } 305 }
306
411 return 0; 307 return 0;
412} 308}
413 309
414static int viafb_pan_display(struct fb_var_screeninfo *var, 310static int viafb_pan_display(struct fb_var_screeninfo *var,
415 struct fb_info *info) 311 struct fb_info *info)
416{ 312{
417 unsigned int offset; 313 struct viafb_par *viapar = info->par;
418 314 u32 vram_addr = (var->yoffset * var->xres_virtual + var->xoffset)
419 DEBUG_MSG(KERN_INFO "viafb_pan_display!\n"); 315 * (var->bits_per_pixel / 8) + viapar->vram_addr;
420 316
421 offset = (var->xoffset + (var->yoffset * var->xres_virtual)) * 317 DEBUG_MSG(KERN_DEBUG "viafb_pan_display, address = %d\n", vram_addr);
422 var->bits_per_pixel / 16; 318 if (!viafb_dual_fb) {
319 viafb_set_primary_address(vram_addr);
320 viafb_set_secondary_address(vram_addr);
321 } else if (viapar->iga_path == IGA1)
322 viafb_set_primary_address(vram_addr);
323 else
324 viafb_set_secondary_address(vram_addr);
423 325
424 DEBUG_MSG(KERN_INFO "\nviafb_pan_display,offset =%d ", offset);
425 viafb_set_primary_address(offset);
426 return 0; 326 return 0;
427} 327}
428 328
@@ -476,6 +376,7 @@ static int viafb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
476 u32 gpu32; 376 u32 gpu32;
477 377
478 DEBUG_MSG(KERN_INFO "viafb_ioctl: 0x%X !!\n", cmd); 378 DEBUG_MSG(KERN_INFO "viafb_ioctl: 0x%X !!\n", cmd);
379 printk(KERN_WARNING "viafb_ioctl: Please avoid this interface as it is unstable and might change or vanish at any time!\n");
479 memset(&u, 0, sizeof(u)); 380 memset(&u, 0, sizeof(u));
480 381
481 switch (cmd) { 382 switch (cmd) {
@@ -1015,23 +916,6 @@ static int viafb_sync(struct fb_info *info)
1015 return 0; 916 return 0;
1016} 917}
1017 918
1018int viafb_get_mode_index(int hres, int vres)
1019{
1020 u32 i;
1021 DEBUG_MSG(KERN_INFO "viafb_get_mode_index!\n");
1022
1023 for (i = 0; i < NUM_TOTAL_MODETABLE; i++)
1024 if (CLE266Modes[i].mode_array &&
1025 CLE266Modes[i].crtc[0].crtc.hor_addr == hres &&
1026 CLE266Modes[i].crtc[0].crtc.ver_addr == vres)
1027 break;
1028
1029 if (i == NUM_TOTAL_MODETABLE)
1030 return VIA_RES_INVALID;
1031
1032 return CLE266Modes[i].ModeIndex;
1033}
1034
1035static void check_available_device_to_enable(int device_id) 919static void check_available_device_to_enable(int device_id)
1036{ 920{
1037 int device_num = 0; 921 int device_num = 0;
@@ -1330,7 +1214,7 @@ static void retrieve_device_setting(struct viafb_ioctl_setting
1330 setting_info->lcd_attributes.lcd_mode = viafb_lcd_mode; 1214 setting_info->lcd_attributes.lcd_mode = viafb_lcd_mode;
1331} 1215}
1332 1216
1333static void parse_active_dev(void) 1217static int parse_active_dev(void)
1334{ 1218{
1335 viafb_CRT_ON = STATE_OFF; 1219 viafb_CRT_ON = STATE_OFF;
1336 viafb_DVI_ON = STATE_OFF; 1220 viafb_DVI_ON = STATE_OFF;
@@ -1341,60 +1225,63 @@ static void parse_active_dev(void)
1341 IGA path to devices in SAMM case. */ 1225 IGA path to devices in SAMM case. */
1342 /* Note: The previous of active_dev is primary device, 1226 /* Note: The previous of active_dev is primary device,
1343 and the following is secondary device. */ 1227 and the following is secondary device. */
1344 if (!strncmp(viafb_active_dev, "CRT+DVI", 7)) { 1228 if (!viafb_active_dev) {
1229 viafb_CRT_ON = STATE_ON;
1230 viafb_SAMM_ON = STATE_OFF;
1231 } else if (!strcmp(viafb_active_dev, "CRT+DVI")) {
1345 /* CRT+DVI */ 1232 /* CRT+DVI */
1346 viafb_CRT_ON = STATE_ON; 1233 viafb_CRT_ON = STATE_ON;
1347 viafb_DVI_ON = STATE_ON; 1234 viafb_DVI_ON = STATE_ON;
1348 viafb_primary_dev = CRT_Device; 1235 viafb_primary_dev = CRT_Device;
1349 } else if (!strncmp(viafb_active_dev, "DVI+CRT", 7)) { 1236 } else if (!strcmp(viafb_active_dev, "DVI+CRT")) {
1350 /* DVI+CRT */ 1237 /* DVI+CRT */
1351 viafb_CRT_ON = STATE_ON; 1238 viafb_CRT_ON = STATE_ON;
1352 viafb_DVI_ON = STATE_ON; 1239 viafb_DVI_ON = STATE_ON;
1353 viafb_primary_dev = DVI_Device; 1240 viafb_primary_dev = DVI_Device;
1354 } else if (!strncmp(viafb_active_dev, "CRT+LCD", 7)) { 1241 } else if (!strcmp(viafb_active_dev, "CRT+LCD")) {
1355 /* CRT+LCD */ 1242 /* CRT+LCD */
1356 viafb_CRT_ON = STATE_ON; 1243 viafb_CRT_ON = STATE_ON;
1357 viafb_LCD_ON = STATE_ON; 1244 viafb_LCD_ON = STATE_ON;
1358 viafb_primary_dev = CRT_Device; 1245 viafb_primary_dev = CRT_Device;
1359 } else if (!strncmp(viafb_active_dev, "LCD+CRT", 7)) { 1246 } else if (!strcmp(viafb_active_dev, "LCD+CRT")) {
1360 /* LCD+CRT */ 1247 /* LCD+CRT */
1361 viafb_CRT_ON = STATE_ON; 1248 viafb_CRT_ON = STATE_ON;
1362 viafb_LCD_ON = STATE_ON; 1249 viafb_LCD_ON = STATE_ON;
1363 viafb_primary_dev = LCD_Device; 1250 viafb_primary_dev = LCD_Device;
1364 } else if (!strncmp(viafb_active_dev, "DVI+LCD", 7)) { 1251 } else if (!strcmp(viafb_active_dev, "DVI+LCD")) {
1365 /* DVI+LCD */ 1252 /* DVI+LCD */
1366 viafb_DVI_ON = STATE_ON; 1253 viafb_DVI_ON = STATE_ON;
1367 viafb_LCD_ON = STATE_ON; 1254 viafb_LCD_ON = STATE_ON;
1368 viafb_primary_dev = DVI_Device; 1255 viafb_primary_dev = DVI_Device;
1369 } else if (!strncmp(viafb_active_dev, "LCD+DVI", 7)) { 1256 } else if (!strcmp(viafb_active_dev, "LCD+DVI")) {
1370 /* LCD+DVI */ 1257 /* LCD+DVI */
1371 viafb_DVI_ON = STATE_ON; 1258 viafb_DVI_ON = STATE_ON;
1372 viafb_LCD_ON = STATE_ON; 1259 viafb_LCD_ON = STATE_ON;
1373 viafb_primary_dev = LCD_Device; 1260 viafb_primary_dev = LCD_Device;
1374 } else if (!strncmp(viafb_active_dev, "LCD+LCD2", 8)) { 1261 } else if (!strcmp(viafb_active_dev, "LCD+LCD2")) {
1375 viafb_LCD_ON = STATE_ON; 1262 viafb_LCD_ON = STATE_ON;
1376 viafb_LCD2_ON = STATE_ON; 1263 viafb_LCD2_ON = STATE_ON;
1377 viafb_primary_dev = LCD_Device; 1264 viafb_primary_dev = LCD_Device;
1378 } else if (!strncmp(viafb_active_dev, "LCD2+LCD", 8)) { 1265 } else if (!strcmp(viafb_active_dev, "LCD2+LCD")) {
1379 viafb_LCD_ON = STATE_ON; 1266 viafb_LCD_ON = STATE_ON;
1380 viafb_LCD2_ON = STATE_ON; 1267 viafb_LCD2_ON = STATE_ON;
1381 viafb_primary_dev = LCD2_Device; 1268 viafb_primary_dev = LCD2_Device;
1382 } else if (!strncmp(viafb_active_dev, "CRT", 3)) { 1269 } else if (!strcmp(viafb_active_dev, "CRT")) {
1383 /* CRT only */ 1270 /* CRT only */
1384 viafb_CRT_ON = STATE_ON; 1271 viafb_CRT_ON = STATE_ON;
1385 viafb_SAMM_ON = STATE_OFF; 1272 viafb_SAMM_ON = STATE_OFF;
1386 } else if (!strncmp(viafb_active_dev, "DVI", 3)) { 1273 } else if (!strcmp(viafb_active_dev, "DVI")) {
1387 /* DVI only */ 1274 /* DVI only */
1388 viafb_DVI_ON = STATE_ON; 1275 viafb_DVI_ON = STATE_ON;
1389 viafb_SAMM_ON = STATE_OFF; 1276 viafb_SAMM_ON = STATE_OFF;
1390 } else if (!strncmp(viafb_active_dev, "LCD", 3)) { 1277 } else if (!strcmp(viafb_active_dev, "LCD")) {
1391 /* LCD only */ 1278 /* LCD only */
1392 viafb_LCD_ON = STATE_ON; 1279 viafb_LCD_ON = STATE_ON;
1393 viafb_SAMM_ON = STATE_OFF; 1280 viafb_SAMM_ON = STATE_OFF;
1394 } else { 1281 } else
1395 viafb_CRT_ON = STATE_ON; 1282 return -EINVAL;
1396 viafb_SAMM_ON = STATE_OFF; 1283
1397 } 1284 return 0;
1398} 1285}
1399 1286
1400static int parse_port(char *opt_str, int *output_interface) 1287static int parse_port(char *opt_str, int *output_interface)
@@ -1823,35 +1710,37 @@ static void viafb_remove_proc(struct proc_dir_entry *viafb_entry)
1823 remove_proc_entry("viafb", NULL); 1710 remove_proc_entry("viafb", NULL);
1824} 1711}
1825 1712
1826static void parse_mode(const char *str, u32 *xres, u32 *yres) 1713static int parse_mode(const char *str, u32 *xres, u32 *yres)
1827{ 1714{
1828 char *ptr; 1715 char *ptr;
1829 1716
1717 if (!str) {
1718 *xres = 640;
1719 *yres = 480;
1720 return 0;
1721 }
1722
1830 *xres = simple_strtoul(str, &ptr, 10); 1723 *xres = simple_strtoul(str, &ptr, 10);
1831 if (ptr[0] != 'x') 1724 if (ptr[0] != 'x')
1832 goto out_default; 1725 return -EINVAL;
1833 1726
1834 *yres = simple_strtoul(&ptr[1], &ptr, 10); 1727 *yres = simple_strtoul(&ptr[1], &ptr, 10);
1835 if (ptr[0]) 1728 if (ptr[0])
1836 goto out_default; 1729 return -EINVAL;
1837
1838 return;
1839 1730
1840out_default: 1731 return 0;
1841 printk(KERN_WARNING "viafb received invalid mode string: %s\n", str);
1842 *xres = 640;
1843 *yres = 480;
1844} 1732}
1845 1733
1846static int __devinit via_pci_probe(struct pci_dev *pdev, 1734static int __devinit via_pci_probe(struct pci_dev *pdev,
1847 const struct pci_device_id *ent) 1735 const struct pci_device_id *ent)
1848{ 1736{
1849 u32 default_xres, default_yres; 1737 u32 default_xres, default_yres;
1850 int vmode_index; 1738 struct VideoModeTable *vmode_entry;
1739 struct fb_var_screeninfo default_var;
1851 u32 viafb_par_length; 1740 u32 viafb_par_length;
1852 1741
1853 DEBUG_MSG(KERN_INFO "VIAFB PCI Probe!!\n"); 1742 DEBUG_MSG(KERN_INFO "VIAFB PCI Probe!!\n");
1854 1743 memset(&default_var, 0, sizeof(default_var));
1855 viafb_par_length = ALIGN(sizeof(struct viafb_par), BITS_PER_LONG/8); 1744 viafb_par_length = ALIGN(sizeof(struct viafb_par), BITS_PER_LONG/8);
1856 1745
1857 /* Allocate fb_info and ***_par here, also including some other needed 1746 /* Allocate fb_info and ***_par here, also including some other needed
@@ -1877,7 +1766,6 @@ static int __devinit via_pci_probe(struct pci_dev *pdev,
1877 1766
1878 if (viafb_dual_fb) 1767 if (viafb_dual_fb)
1879 viafb_SAMM_ON = 1; 1768 viafb_SAMM_ON = 1;
1880 parse_active_dev();
1881 parse_lcd_port(); 1769 parse_lcd_port();
1882 parse_dvi_port(); 1770 parse_dvi_port();
1883 1771
@@ -1926,9 +1814,7 @@ static int __devinit via_pci_probe(struct pci_dev *pdev,
1926 } 1814 }
1927 1815
1928 parse_mode(viafb_mode, &default_xres, &default_yres); 1816 parse_mode(viafb_mode, &default_xres, &default_yres);
1929 vmode_index = viafb_get_mode_index(default_xres, default_yres); 1817 vmode_entry = viafb_get_mode(default_xres, default_yres);
1930 DEBUG_MSG(KERN_INFO "0->index=%d\n", vmode_index);
1931
1932 if (viafb_SAMM_ON == 1) { 1818 if (viafb_SAMM_ON == 1) {
1933 parse_mode(viafb_mode1, &viafb_second_xres, 1819 parse_mode(viafb_mode1, &viafb_second_xres,
1934 &viafb_second_yres); 1820 &viafb_second_yres);
@@ -1947,19 +1833,6 @@ static int __devinit via_pci_probe(struct pci_dev *pdev,
1947 viafb_second_virtual_yres = viafb_second_yres; 1833 viafb_second_virtual_yres = viafb_second_yres;
1948 } 1834 }
1949 1835
1950 switch (viafb_bpp) {
1951 case 0 ... 8:
1952 viafb_bpp = 8;
1953 break;
1954 case 9 ... 16:
1955 viafb_bpp = 16;
1956 break;
1957 case 17 ... 32:
1958 viafb_bpp = 32;
1959 break;
1960 default:
1961 viafb_bpp = 8;
1962 }
1963 default_var.xres = default_xres; 1836 default_var.xres = default_xres;
1964 default_var.yres = default_yres; 1837 default_var.yres = default_yres;
1965 switch (default_xres) { 1838 switch (default_xres) {
@@ -1972,8 +1845,6 @@ static int __devinit via_pci_probe(struct pci_dev *pdev,
1972 } 1845 }
1973 default_var.yres_virtual = default_yres; 1846 default_var.yres_virtual = default_yres;
1974 default_var.bits_per_pixel = viafb_bpp; 1847 default_var.bits_per_pixel = viafb_bpp;
1975 if (default_var.bits_per_pixel == 15)
1976 default_var.bits_per_pixel = 16;
1977 default_var.pixclock = 1848 default_var.pixclock =
1978 viafb_get_pixclock(default_xres, default_yres, viafb_refresh); 1849 viafb_get_pixclock(default_xres, default_yres, viafb_refresh);
1979 default_var.left_margin = (default_xres >> 3) & 0xf8; 1850 default_var.left_margin = (default_xres >> 3) & 0xf8;
@@ -1982,6 +1853,8 @@ static int __devinit via_pci_probe(struct pci_dev *pdev,
1982 default_var.lower_margin = 4; 1853 default_var.lower_margin = 4;
1983 default_var.hsync_len = default_var.left_margin; 1854 default_var.hsync_len = default_var.left_margin;
1984 default_var.vsync_len = 4; 1855 default_var.vsync_len = 4;
1856 viafb_setup_fixinfo(&viafbinfo->fix, viaparinfo);
1857 viafbinfo->var = default_var;
1985 1858
1986 if (viafb_dual_fb) { 1859 if (viafb_dual_fb) {
1987 viafbinfo1 = framebuffer_alloc(viafb_par_length, &pdev->dev); 1860 viafbinfo1 = framebuffer_alloc(viafb_par_length, &pdev->dev);
@@ -2016,8 +1889,6 @@ static int __devinit via_pci_probe(struct pci_dev *pdev,
2016 default_var.yres = viafb_second_yres; 1889 default_var.yres = viafb_second_yres;
2017 default_var.xres_virtual = viafb_second_virtual_xres; 1890 default_var.xres_virtual = viafb_second_virtual_xres;
2018 default_var.yres_virtual = viafb_second_virtual_yres; 1891 default_var.yres_virtual = viafb_second_virtual_yres;
2019 if (viafb_bpp1 != viafb_bpp)
2020 viafb_bpp1 = viafb_bpp;
2021 default_var.bits_per_pixel = viafb_bpp1; 1892 default_var.bits_per_pixel = viafb_bpp1;
2022 default_var.pixclock = 1893 default_var.pixclock =
2023 viafb_get_pixclock(viafb_second_xres, viafb_second_yres, 1894 viafb_get_pixclock(viafb_second_xres, viafb_second_yres,
@@ -2037,9 +1908,7 @@ static int __devinit via_pci_probe(struct pci_dev *pdev,
2037 &viafbinfo1->fix); 1908 &viafbinfo1->fix);
2038 } 1909 }
2039 1910
2040 viafb_setup_fixinfo(&viafbinfo->fix, viaparinfo); 1911 viafb_check_var(&viafbinfo->var, viafbinfo);
2041 viafb_check_var(&default_var, viafbinfo);
2042 viafbinfo->var = default_var;
2043 viafb_update_fix(viafbinfo); 1912 viafb_update_fix(viafbinfo);
2044 viaparinfo->depth = fb_get_color_depth(&viafbinfo->var, 1913 viaparinfo->depth = fb_get_color_depth(&viafbinfo->var,
2045 &viafbinfo->fix); 1914 &viafbinfo->fix);
@@ -2197,12 +2066,20 @@ static struct pci_driver viafb_driver = {
2197 2066
2198static int __init viafb_init(void) 2067static int __init viafb_init(void)
2199{ 2068{
2069 u32 dummy;
2200#ifndef MODULE 2070#ifndef MODULE
2201 char *option = NULL; 2071 char *option = NULL;
2202 if (fb_get_options("viafb", &option)) 2072 if (fb_get_options("viafb", &option))
2203 return -ENODEV; 2073 return -ENODEV;
2204 viafb_setup(option); 2074 viafb_setup(option);
2205#endif 2075#endif
2076 if (parse_mode(viafb_mode, &dummy, &dummy)
2077 || parse_mode(viafb_mode1, &dummy, &dummy)
2078 || viafb_bpp < 0 || viafb_bpp > 32
2079 || viafb_bpp1 < 0 || viafb_bpp1 > 32
2080 || parse_active_dev())
2081 return -EINVAL;
2082
2206 printk(KERN_INFO 2083 printk(KERN_INFO
2207 "VIA Graphics Intergration Chipset framebuffer %d.%d initializing\n", 2084 "VIA Graphics Intergration Chipset framebuffer %d.%d initializing\n",
2208 VERSION_MAJOR, VERSION_MINOR); 2085 VERSION_MAJOR, VERSION_MINOR);
@@ -2230,15 +2107,12 @@ static struct fb_ops viafb_ops = {
2230 .fb_cursor = viafb_cursor, 2107 .fb_cursor = viafb_cursor,
2231 .fb_ioctl = viafb_ioctl, 2108 .fb_ioctl = viafb_ioctl,
2232 .fb_sync = viafb_sync, 2109 .fb_sync = viafb_sync,
2233 .fb_setcmap = viafb_setcmap,
2234}; 2110};
2235 2111
2236module_init(viafb_init); 2112module_init(viafb_init);
2237module_exit(viafb_exit); 2113module_exit(viafb_exit);
2238 2114
2239#ifdef MODULE 2115#ifdef MODULE
2240module_param(viafb_memsize, int, S_IRUSR);
2241
2242module_param(viafb_mode, charp, S_IRUSR); 2116module_param(viafb_mode, charp, S_IRUSR);
2243MODULE_PARM_DESC(viafb_mode, "Set resolution (default=640x480)"); 2117MODULE_PARM_DESC(viafb_mode, "Set resolution (default=640x480)");
2244 2118
diff --git a/drivers/video/via/viafbdev.h b/drivers/video/via/viafbdev.h
index 0c94d244192..61b5953cd15 100644
--- a/drivers/video/via/viafbdev.h
+++ b/drivers/video/via/viafbdev.h
@@ -83,22 +83,16 @@ struct viafb_par {
83 83
84extern unsigned int viafb_second_virtual_yres; 84extern unsigned int viafb_second_virtual_yres;
85extern unsigned int viafb_second_virtual_xres; 85extern unsigned int viafb_second_virtual_xres;
86extern unsigned int viafb_second_offset;
87extern int viafb_second_size;
88extern int viafb_SAMM_ON; 86extern int viafb_SAMM_ON;
89extern int viafb_dual_fb; 87extern int viafb_dual_fb;
90extern int viafb_LCD2_ON; 88extern int viafb_LCD2_ON;
91extern int viafb_LCD_ON; 89extern int viafb_LCD_ON;
92extern int viafb_DVI_ON; 90extern int viafb_DVI_ON;
93extern int viafb_hotplug; 91extern int viafb_hotplug;
94extern int viafb_memsize;
95 92
96extern int strict_strtoul(const char *cp, unsigned int base, 93extern int strict_strtoul(const char *cp, unsigned int base,
97 unsigned long *res); 94 unsigned long *res);
98 95
99void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
100 int mode_index);
101int viafb_get_mode_index(int hres, int vres);
102u8 viafb_gpio_i2c_read_lvds(struct lvds_setting_information 96u8 viafb_gpio_i2c_read_lvds(struct lvds_setting_information
103 *plvds_setting_info, struct lvds_chip_information 97 *plvds_setting_info, struct lvds_chip_information
104 *plvds_chip_info, u8 index); 98 *plvds_chip_info, u8 index);
diff --git a/drivers/video/via/viamode.c b/drivers/video/via/viamode.c
index b74f8a67923..af50e244016 100644
--- a/drivers/video/via/viamode.c
+++ b/drivers/video/via/viamode.c
@@ -412,7 +412,7 @@ struct io_reg PM1024x768[] = { {VIASR, 0x16, 0xBF, 0x0C},
412}; 412};
413 413
414struct patch_table res_patch_table[] = { 414struct patch_table res_patch_table[] = {
415 {VIA_RES_1024X768, ARRAY_SIZE(PM1024x768), PM1024x768} 415 {ARRAY_SIZE(PM1024x768), PM1024x768}
416}; 416};
417 417
418/* struct VPITTable { 418/* struct VPITTable {
@@ -879,169 +879,151 @@ struct crt_mode_table CRTM2048x1536[] = {
879 {2800, 2048, 2048, 752, 2200, 224, 1592, 1536, 1536, 56, 1539, 4} } 879 {2800, 2048, 2048, 752, 2200, 224, 1592, 1536, 1536, 56, 1539, 4} }
880}; 880};
881 881
882/* Video Mode Table */ 882struct VideoModeTable viafb_modes[] = {
883/* struct VideoModeTable {*/
884/* int ModeIndex;*/
885/* struct crt_mode_table *crtc;*/
886/* int mode_array;*/
887/* };*/
888struct VideoModeTable CLE266Modes[] = {
889 /* Display : 480x640 (GTF) */ 883 /* Display : 480x640 (GTF) */
890 {VIA_RES_480X640, CRTM480x640, ARRAY_SIZE(CRTM480x640)}, 884 {CRTM480x640, ARRAY_SIZE(CRTM480x640)},
891 885
892 /* Display : 640x480 */ 886 /* Display : 640x480 */
893 {VIA_RES_640X480, CRTM640x480, ARRAY_SIZE(CRTM640x480)}, 887 {CRTM640x480, ARRAY_SIZE(CRTM640x480)},
894 888
895 /* Display : 720x480 (GTF) */ 889 /* Display : 720x480 (GTF) */
896 {VIA_RES_720X480, CRTM720x480, ARRAY_SIZE(CRTM720x480)}, 890 {CRTM720x480, ARRAY_SIZE(CRTM720x480)},
897 891
898 /* Display : 720x576 (GTF) */ 892 /* Display : 720x576 (GTF) */
899 {VIA_RES_720X576, CRTM720x576, ARRAY_SIZE(CRTM720x576)}, 893 {CRTM720x576, ARRAY_SIZE(CRTM720x576)},
900 894
901 /* Display : 800x600 */ 895 /* Display : 800x600 */
902 {VIA_RES_800X600, CRTM800x600, ARRAY_SIZE(CRTM800x600)}, 896 {CRTM800x600, ARRAY_SIZE(CRTM800x600)},
903 897
904 /* Display : 800x480 (CVT) */ 898 /* Display : 800x480 (CVT) */
905 {VIA_RES_800X480, CRTM800x480, ARRAY_SIZE(CRTM800x480)}, 899 {CRTM800x480, ARRAY_SIZE(CRTM800x480)},
906 900
907 /* Display : 848x480 (CVT) */ 901 /* Display : 848x480 (CVT) */
908 {VIA_RES_848X480, CRTM848x480, ARRAY_SIZE(CRTM848x480)}, 902 {CRTM848x480, ARRAY_SIZE(CRTM848x480)},
909 903
910 /* Display : 852x480 (GTF) */ 904 /* Display : 852x480 (GTF) */
911 {VIA_RES_856X480, CRTM852x480, ARRAY_SIZE(CRTM852x480)}, 905 {CRTM852x480, ARRAY_SIZE(CRTM852x480)},
912 906
913 /* Display : 1024x512 (GTF) */ 907 /* Display : 1024x512 (GTF) */
914 {VIA_RES_1024X512, CRTM1024x512, ARRAY_SIZE(CRTM1024x512)}, 908 {CRTM1024x512, ARRAY_SIZE(CRTM1024x512)},
915 909
916 /* Display : 1024x600 */ 910 /* Display : 1024x600 */
917 {VIA_RES_1024X600, CRTM1024x600, ARRAY_SIZE(CRTM1024x600)}, 911 {CRTM1024x600, ARRAY_SIZE(CRTM1024x600)},
918
919 /* Display : 1024x576 (GTF) */
920 /*{ VIA_RES_1024X576, CRTM1024x576, ARRAY_SIZE(CRTM1024x576)}, */
921 912
922 /* Display : 1024x768 */ 913 /* Display : 1024x768 */
923 {VIA_RES_1024X768, CRTM1024x768, ARRAY_SIZE(CRTM1024x768)}, 914 {CRTM1024x768, ARRAY_SIZE(CRTM1024x768)},
924 915
925 /* Display : 1152x864 */ 916 /* Display : 1152x864 */
926 {VIA_RES_1152X864, CRTM1152x864, ARRAY_SIZE(CRTM1152x864)}, 917 {CRTM1152x864, ARRAY_SIZE(CRTM1152x864)},
927 918
928 /* Display : 1280x768 (GTF) */ 919 /* Display : 1280x768 (GTF) */
929 {VIA_RES_1280X768, CRTM1280x768, ARRAY_SIZE(CRTM1280x768)}, 920 {CRTM1280x768, ARRAY_SIZE(CRTM1280x768)},
930 921
931 /* Display : 960x600 (CVT) */ 922 /* Display : 960x600 (CVT) */
932 {VIA_RES_960X600, CRTM960x600, ARRAY_SIZE(CRTM960x600)}, 923 {CRTM960x600, ARRAY_SIZE(CRTM960x600)},
933 924
934 /* Display : 1000x600 (GTF) */ 925 /* Display : 1000x600 (GTF) */
935 {VIA_RES_1000X600, CRTM1000x600, ARRAY_SIZE(CRTM1000x600)}, 926 {CRTM1000x600, ARRAY_SIZE(CRTM1000x600)},
936 927
937 /* Display : 1024x576 (GTF) */ 928 /* Display : 1024x576 (GTF) */
938 {VIA_RES_1024X576, CRTM1024x576, ARRAY_SIZE(CRTM1024x576)}, 929 {CRTM1024x576, ARRAY_SIZE(CRTM1024x576)},
939 930
940 /* Display : 1088x612 (GTF) */ 931 /* Display : 1088x612 (GTF) */
941 {VIA_RES_1088X612, CRTM1088x612, ARRAY_SIZE(CRTM1088x612)}, 932 {CRTM1088x612, ARRAY_SIZE(CRTM1088x612)},
942 933
943 /* Display : 1152x720 (CVT) */ 934 /* Display : 1152x720 (CVT) */
944 {VIA_RES_1152X720, CRTM1152x720, ARRAY_SIZE(CRTM1152x720)}, 935 {CRTM1152x720, ARRAY_SIZE(CRTM1152x720)},
945 936
946 /* Display : 1200x720 (GTF) */ 937 /* Display : 1200x720 (GTF) */
947 {VIA_RES_1200X720, CRTM1200x720, ARRAY_SIZE(CRTM1200x720)}, 938 {CRTM1200x720, ARRAY_SIZE(CRTM1200x720)},
948 939
949 /* Display : 1280x600 (GTF) */ 940 /* Display : 1280x600 (GTF) */
950 {VIA_RES_1280X600, CRTM1280x600, ARRAY_SIZE(CRTM1280x600)}, 941 {CRTM1280x600, ARRAY_SIZE(CRTM1280x600)},
951 942
952 /* Display : 1280x800 (CVT) */ 943 /* Display : 1280x800 (CVT) */
953 {VIA_RES_1280X800, CRTM1280x800, ARRAY_SIZE(CRTM1280x800)}, 944 {CRTM1280x800, ARRAY_SIZE(CRTM1280x800)},
954
955 /* Display : 1280x800 (GTF) */
956 /*{ M1280x800, CRTM1280x800, ARRAY_SIZE(CRTM1280x800)}, */
957 945
958 /* Display : 1280x960 */ 946 /* Display : 1280x960 */
959 {VIA_RES_1280X960, CRTM1280x960, ARRAY_SIZE(CRTM1280x960)}, 947 {CRTM1280x960, ARRAY_SIZE(CRTM1280x960)},
960 948
961 /* Display : 1280x1024 */ 949 /* Display : 1280x1024 */
962 {VIA_RES_1280X1024, CRTM1280x1024, ARRAY_SIZE(CRTM1280x1024)}, 950 {CRTM1280x1024, ARRAY_SIZE(CRTM1280x1024)},
963 951
964 /* Display : 1360x768 (CVT) */ 952 /* Display : 1360x768 (CVT) */
965 {VIA_RES_1360X768, CRTM1360x768, ARRAY_SIZE(CRTM1360x768)}, 953 {CRTM1360x768, ARRAY_SIZE(CRTM1360x768)},
966
967 /* Display : 1360x768 (CVT Reduce Blanking) */
968 {VIA_RES_1360X768_RB, CRTM1360x768_RB,
969 ARRAY_SIZE(CRTM1360x768_RB)},
970 954
971 /* Display : 1366x768 */ 955 /* Display : 1366x768 */
972 {VIA_RES_1366X768, CRTM1366x768, ARRAY_SIZE(CRTM1366x768)}, 956 {CRTM1366x768, ARRAY_SIZE(CRTM1366x768)},
973 957
974 /* Display : 1368x768 (GTF) */ 958 /* Display : 1368x768 (GTF) */
975 /*{ M1368x768,CRTM1368x768,ARRAY_SIZE(CRTM1368x768)}, */ 959 {CRTM1368x768, ARRAY_SIZE(CRTM1368x768)},
976 /* Display : 1368x768 (GTF) */
977 {VIA_RES_1368X768, CRTM1368x768, ARRAY_SIZE(CRTM1368x768)},
978 960
979 /* Display : 1440x900 (CVT) */ 961 /* Display : 1440x900 (CVT) */
980 {VIA_RES_1440X900, CRTM1440x900, ARRAY_SIZE(CRTM1440x900)}, 962 {CRTM1440x900, ARRAY_SIZE(CRTM1440x900)},
981
982 /* Display : 1440x900 (CVT Reduce Blanking) */
983 {VIA_RES_1440X900_RB, CRTM1440x900_RB,
984 ARRAY_SIZE(CRTM1440x900_RB)},
985 963
986 /* Display : 1440x1050 (GTF) */ 964 /* Display : 1440x1050 (GTF) */
987 {VIA_RES_1440X1050, CRTM1440x1050, ARRAY_SIZE(CRTM1440x1050)}, 965 {CRTM1440x1050, ARRAY_SIZE(CRTM1440x1050)},
988
989 /* Display : 1400x1050 (CVT Reduce Blanking) */
990 {VIA_RES_1400X1050_RB, CRTM1400x1050_RB,
991 ARRAY_SIZE(CRTM1400x1050_RB)},
992 966
993 /* Display : 1600x900 (CVT) */ 967 /* Display : 1600x900 (CVT) */
994 {VIA_RES_1600X900, CRTM1600x900, ARRAY_SIZE(CRTM1600x900)}, 968 {CRTM1600x900, ARRAY_SIZE(CRTM1600x900)},
995
996 /* Display : 1600x900 (CVT Reduce Blanking) */
997 {VIA_RES_1600X900_RB, CRTM1600x900_RB,
998 ARRAY_SIZE(CRTM1600x900_RB)},
999 969
1000 /* Display : 1600x1024 (GTF) */ 970 /* Display : 1600x1024 (GTF) */
1001 {VIA_RES_1600X1024, CRTM1600x1024, ARRAY_SIZE(CRTM1600x1024)}, 971 {CRTM1600x1024, ARRAY_SIZE(CRTM1600x1024)},
1002 972
1003 /* Display : 1600x1200 */ 973 /* Display : 1600x1200 */
1004 {VIA_RES_1600X1200, CRTM1600x1200, ARRAY_SIZE(CRTM1600x1200)}, 974 {CRTM1600x1200, ARRAY_SIZE(CRTM1600x1200)},
1005 975
1006 /* Display : 1680x1050 (CVT) */ 976 /* Display : 1680x1050 (CVT) */
1007 {VIA_RES_1680X1050, CRTM1680x1050, ARRAY_SIZE(CRTM1680x1050)}, 977 {CRTM1680x1050, ARRAY_SIZE(CRTM1680x1050)},
1008
1009 /* Display : 1680x1050 (CVT Reduce Blanking) */
1010 {VIA_RES_1680X1050_RB, CRTM1680x1050_RB,
1011 ARRAY_SIZE(CRTM1680x1050_RB)},
1012 978
1013 /* Display : 1792x1344 (DMT) */ 979 /* Display : 1792x1344 (DMT) */
1014 {VIA_RES_1792X1344, CRTM1792x1344, ARRAY_SIZE(CRTM1792x1344)}, 980 {CRTM1792x1344, ARRAY_SIZE(CRTM1792x1344)},
1015 981
1016 /* Display : 1856x1392 (DMT) */ 982 /* Display : 1856x1392 (DMT) */
1017 {VIA_RES_1856X1392, CRTM1856x1392, ARRAY_SIZE(CRTM1856x1392)}, 983 {CRTM1856x1392, ARRAY_SIZE(CRTM1856x1392)},
1018 984
1019 /* Display : 1920x1440 */ 985 /* Display : 1920x1440 */
1020 {VIA_RES_1920X1440, CRTM1920x1440, ARRAY_SIZE(CRTM1920x1440)}, 986 {CRTM1920x1440, ARRAY_SIZE(CRTM1920x1440)},
1021 987
1022 /* Display : 2048x1536 */ 988 /* Display : 2048x1536 */
1023 {VIA_RES_2048X1536, CRTM2048x1536, ARRAY_SIZE(CRTM2048x1536)}, 989 {CRTM2048x1536, ARRAY_SIZE(CRTM2048x1536)},
1024 990
1025 /* Display : 1280x720 */ 991 /* Display : 1280x720 */
1026 {VIA_RES_1280X720, CRTM1280x720, ARRAY_SIZE(CRTM1280x720)}, 992 {CRTM1280x720, ARRAY_SIZE(CRTM1280x720)},
1027 993
1028 /* Display : 1920x1080 (CVT) */ 994 /* Display : 1920x1080 (CVT) */
1029 {VIA_RES_1920X1080, CRTM1920x1080, ARRAY_SIZE(CRTM1920x1080)}, 995 {CRTM1920x1080, ARRAY_SIZE(CRTM1920x1080)},
1030
1031 /* Display : 1920x1080 (CVT Reduce Blanking) */
1032 {VIA_RES_1920X1080_RB, CRTM1920x1080_RB,
1033 ARRAY_SIZE(CRTM1920x1080_RB)},
1034 996
1035 /* Display : 1920x1200 (CVT) */ 997 /* Display : 1920x1200 (CVT) */
1036 {VIA_RES_1920X1200, CRTM1920x1200, ARRAY_SIZE(CRTM1920x1200)}, 998 {CRTM1920x1200, ARRAY_SIZE(CRTM1920x1200)},
1037
1038 /* Display : 1920x1200 (CVT Reduce Blanking) */
1039 {VIA_RES_1920X1200_RB, CRTM1920x1200_RB,
1040 ARRAY_SIZE(CRTM1920x1200_RB)},
1041 999
1042 /* Display : 1400x1050 (CVT) */ 1000 /* Display : 1400x1050 (CVT) */
1043 {VIA_RES_1400X1050, CRTM1400x1050, ARRAY_SIZE(CRTM1400x1050)} 1001 {CRTM1400x1050, ARRAY_SIZE(CRTM1400x1050)}
1044}; 1002};
1003
1004struct VideoModeTable viafb_rb_modes[] = {
1005 /* Display : 1360x768 (CVT Reduce Blanking) */
1006 {CRTM1360x768_RB, ARRAY_SIZE(CRTM1360x768_RB)},
1007
1008 /* Display : 1440x900 (CVT Reduce Blanking) */
1009 {CRTM1440x900_RB, ARRAY_SIZE(CRTM1440x900_RB)},
1010
1011 /* Display : 1400x1050 (CVT Reduce Blanking) */
1012 {CRTM1400x1050_RB, ARRAY_SIZE(CRTM1400x1050_RB)},
1013
1014 /* Display : 1600x900 (CVT Reduce Blanking) */
1015 {CRTM1600x900_RB, ARRAY_SIZE(CRTM1600x900_RB)},
1016
1017 /* Display : 1680x1050 (CVT Reduce Blanking) */
1018 {CRTM1680x1050_RB, ARRAY_SIZE(CRTM1680x1050_RB)},
1019
1020 /* Display : 1920x1080 (CVT Reduce Blanking) */
1021 {CRTM1920x1080_RB, ARRAY_SIZE(CRTM1920x1080_RB)},
1022
1023 /* Display : 1920x1200 (CVT Reduce Blanking) */
1024 {CRTM1920x1200_RB, ARRAY_SIZE(CRTM1920x1200_RB)}
1025};
1026
1045struct crt_mode_table CEAM1280x720[] = { 1027struct crt_mode_table CEAM1280x720[] = {
1046 {REFRESH_60, CLK_74_270M, M1280X720_CEA_R60_HSP, 1028 {REFRESH_60, CLK_74_270M, M1280X720_CEA_R60_HSP,
1047 M1280X720_CEA_R60_VSP, 1029 M1280X720_CEA_R60_VSP,
@@ -1056,8 +1038,8 @@ struct crt_mode_table CEAM1920x1080[] = {
1056}; 1038};
1057struct VideoModeTable CEA_HDMI_Modes[] = { 1039struct VideoModeTable CEA_HDMI_Modes[] = {
1058 /* Display : 1280x720 */ 1040 /* Display : 1280x720 */
1059 {VIA_RES_1280X720, CEAM1280x720, ARRAY_SIZE(CEAM1280x720)}, 1041 {CEAM1280x720, ARRAY_SIZE(CEAM1280x720)},
1060 {VIA_RES_1920X1080, CEAM1920x1080, ARRAY_SIZE(CEAM1920x1080)} 1042 {CEAM1920x1080, ARRAY_SIZE(CEAM1920x1080)}
1061}; 1043};
1062 1044
1063int NUM_TOTAL_RES_MAP_REFRESH = ARRAY_SIZE(res_map_refresh_tbl); 1045int NUM_TOTAL_RES_MAP_REFRESH = ARRAY_SIZE(res_map_refresh_tbl);
@@ -1069,4 +1051,28 @@ int NUM_TOTAL_CX700_ModeXregs = ARRAY_SIZE(CX700_ModeXregs);
1069int NUM_TOTAL_VX855_ModeXregs = ARRAY_SIZE(VX855_ModeXregs); 1051int NUM_TOTAL_VX855_ModeXregs = ARRAY_SIZE(VX855_ModeXregs);
1070int NUM_TOTAL_CLE266_ModeXregs = ARRAY_SIZE(CLE266_ModeXregs); 1052int NUM_TOTAL_CLE266_ModeXregs = ARRAY_SIZE(CLE266_ModeXregs);
1071int NUM_TOTAL_PATCH_MODE = ARRAY_SIZE(res_patch_table); 1053int NUM_TOTAL_PATCH_MODE = ARRAY_SIZE(res_patch_table);
1072int NUM_TOTAL_MODETABLE = ARRAY_SIZE(CLE266Modes); 1054
1055
1056struct VideoModeTable *viafb_get_mode(int hres, int vres)
1057{
1058 u32 i;
1059 for (i = 0; i < ARRAY_SIZE(viafb_modes); i++)
1060 if (viafb_modes[i].mode_array &&
1061 viafb_modes[i].crtc[0].crtc.hor_addr == hres &&
1062 viafb_modes[i].crtc[0].crtc.ver_addr == vres)
1063 return &viafb_modes[i];
1064
1065 return NULL;
1066}
1067
1068struct VideoModeTable *viafb_get_rb_mode(int hres, int vres)
1069{
1070 u32 i;
1071 for (i = 0; i < ARRAY_SIZE(viafb_rb_modes); i++)
1072 if (viafb_rb_modes[i].mode_array &&
1073 viafb_rb_modes[i].crtc[0].crtc.hor_addr == hres &&
1074 viafb_rb_modes[i].crtc[0].crtc.ver_addr == vres)
1075 return &viafb_rb_modes[i];
1076
1077 return NULL;
1078}
diff --git a/drivers/video/via/viamode.h b/drivers/video/via/viamode.h
index a9d6554fabd..5b1ced86514 100644
--- a/drivers/video/via/viamode.h
+++ b/drivers/video/via/viamode.h
@@ -32,13 +32,11 @@ struct VPITTable {
32}; 32};
33 33
34struct VideoModeTable { 34struct VideoModeTable {
35 int ModeIndex;
36 struct crt_mode_table *crtc; 35 struct crt_mode_table *crtc;
37 int mode_array; 36 int mode_array;
38}; 37};
39 38
40struct patch_table { 39struct patch_table {
41 int mode_index;
42 int table_length; 40 int table_length;
43 struct io_reg *io_reg_table; 41 struct io_reg *io_reg_table;
44}; 42};
@@ -59,13 +57,11 @@ extern int NUM_TOTAL_CX700_ModeXregs;
59extern int NUM_TOTAL_VX855_ModeXregs; 57extern int NUM_TOTAL_VX855_ModeXregs;
60extern int NUM_TOTAL_CLE266_ModeXregs; 58extern int NUM_TOTAL_CLE266_ModeXregs;
61extern int NUM_TOTAL_PATCH_MODE; 59extern int NUM_TOTAL_PATCH_MODE;
62extern int NUM_TOTAL_MODETABLE;
63 60
64/********************/ 61/********************/
65/* Mode Table */ 62/* Mode Table */
66/********************/ 63/********************/
67 64
68extern struct VideoModeTable CLE266Modes[];
69extern struct crt_mode_table CEAM1280x720[]; 65extern struct crt_mode_table CEAM1280x720[];
70extern struct crt_mode_table CEAM1920x1080[]; 66extern struct crt_mode_table CEAM1920x1080[];
71extern struct VideoModeTable CEA_HDMI_Modes[]; 67extern struct VideoModeTable CEA_HDMI_Modes[];
@@ -81,4 +77,8 @@ extern struct io_reg CLE266_ModeXregs[];
81extern struct io_reg PM1024x768[]; 77extern struct io_reg PM1024x768[];
82extern struct patch_table res_patch_table[]; 78extern struct patch_table res_patch_table[];
83extern struct VPITTable VPIT; 79extern struct VPITTable VPIT;
80
81struct VideoModeTable *viafb_get_mode(int hres, int vres);
82struct VideoModeTable *viafb_get_rb_mode(int hres, int vres);
83
84#endif /* __VIAMODE_H__ */ 84#endif /* __VIAMODE_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-18 20:45:52 -0400