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path: root/drivers/usb/host/ehci-fsl.c
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Diffstat (limited to 'drivers/usb/host/ehci-fsl.c')
-rw-r--r--drivers/usb/host/ehci-fsl.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index fd9b5424b86..d81d2fcbff1 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -230,7 +230,7 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
230 230
231 switch (phy_mode) { 231 switch (phy_mode) {
232 case FSL_USB2_PHY_ULPI: 232 case FSL_USB2_PHY_ULPI:
233 if (pdata->controller_ver) { 233 if (pdata->have_sysif_regs && pdata->controller_ver) {
234 /* controller version 1.6 or above */ 234 /* controller version 1.6 or above */
235 setbits32(non_ehci + FSL_SOC_USB_CTRL, 235 setbits32(non_ehci + FSL_SOC_USB_CTRL,
236 ULPI_PHY_CLK_SEL); 236 ULPI_PHY_CLK_SEL);
@@ -251,7 +251,7 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
251 portsc |= PORT_PTS_PTW; 251 portsc |= PORT_PTS_PTW;
252 /* fall through */ 252 /* fall through */
253 case FSL_USB2_PHY_UTMI: 253 case FSL_USB2_PHY_UTMI:
254 if (pdata->controller_ver) { 254 if (pdata->have_sysif_regs && pdata->controller_ver) {
255 /* controller version 1.6 or above */ 255 /* controller version 1.6 or above */
256 setbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN); 256 setbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);
257 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to 257 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to
@@ -267,7 +267,8 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
267 break; 267 break;
268 } 268 }
269 269
270 if (pdata->controller_ver && (phy_mode == FSL_USB2_PHY_ULPI)) { 270 if (pdata->have_sysif_regs && pdata->controller_ver &&
271 (phy_mode == FSL_USB2_PHY_ULPI)) {
271 /* check PHY_CLK_VALID to get phy clk valid */ 272 /* check PHY_CLK_VALID to get phy clk valid */
272 if (!spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) & 273 if (!spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) &
273 PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0)) { 274 PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0)) {
@@ -278,7 +279,7 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
278 279
279 ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]); 280 ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
280 281
281 if (phy_mode != FSL_USB2_PHY_ULPI) 282 if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs)
282 setbits32(non_ehci + FSL_SOC_USB_CTRL, USB_CTRL_USB_EN); 283 setbits32(non_ehci + FSL_SOC_USB_CTRL, USB_CTRL_USB_EN);
283 284
284 return 0; 285 return 0;