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Diffstat (limited to 'drivers/usb/gadget/s3c-hsotg.c')
-rw-r--r--drivers/usb/gadget/s3c-hsotg.c1644
1 files changed, 942 insertions, 702 deletions
diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index 69295ba9d99..f4abb0ed987 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -1,4 +1,5 @@
1/* linux/drivers/usb/gadget/s3c-hsotg.c 1/**
2 * linux/drivers/usb/gadget/s3c-hsotg.c
2 * 3 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 5 * http://www.samsung.com
@@ -13,7 +14,7 @@
13 * This program is free software; you can redistribute it and/or modify 14 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as 15 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation. 16 * published by the Free Software Foundation.
16*/ 17 */
17 18
18#include <linux/kernel.h> 19#include <linux/kernel.h>
19#include <linux/module.h> 20#include <linux/module.h>
@@ -27,21 +28,25 @@
27#include <linux/io.h> 28#include <linux/io.h>
28#include <linux/slab.h> 29#include <linux/slab.h>
29#include <linux/clk.h> 30#include <linux/clk.h>
31#include <linux/regulator/consumer.h>
30 32
31#include <linux/usb/ch9.h> 33#include <linux/usb/ch9.h>
32#include <linux/usb/gadget.h> 34#include <linux/usb/gadget.h>
35#include <linux/platform_data/s3c-hsotg.h>
33 36
34#include <mach/map.h> 37#include <mach/map.h>
35 38
36#include <plat/regs-usb-hsotg-phy.h> 39#include "s3c-hsotg.h"
37#include <plat/regs-usb-hsotg.h>
38#include <mach/regs-sys.h>
39#include <plat/udc-hs.h>
40#include <plat/cpu.h>
41 40
42#define DMA_ADDR_INVALID (~((dma_addr_t)0)) 41#define DMA_ADDR_INVALID (~((dma_addr_t)0))
43 42
44/* EP0_MPS_LIMIT 43static const char * const s3c_hsotg_supply_names[] = {
44 "vusb_d", /* digital USB supply, 1.2V */
45 "vusb_a", /* analog USB supply, 1.1V */
46};
47
48/*
49 * EP0_MPS_LIMIT
45 * 50 *
46 * Unfortunately there seems to be a limit of the amount of data that can 51 * Unfortunately there seems to be a limit of the amount of data that can
47 * be transferred by IN transactions on EP0. This is either 127 bytes or 3 52 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
@@ -125,8 +130,6 @@ struct s3c_hsotg_ep {
125 char name[10]; 130 char name[10];
126}; 131};
127 132
128#define S3C_HSOTG_EPS (8+1) /* limit to 9 for the moment */
129
130/** 133/**
131 * struct s3c_hsotg - driver state. 134 * struct s3c_hsotg - driver state.
132 * @dev: The parent device supplied to the probe function 135 * @dev: The parent device supplied to the probe function
@@ -135,7 +138,9 @@ struct s3c_hsotg_ep {
135 * @regs: The memory area mapped for accessing registers. 138 * @regs: The memory area mapped for accessing registers.
136 * @regs_res: The resource that was allocated when claiming register space. 139 * @regs_res: The resource that was allocated when claiming register space.
137 * @irq: The IRQ number we are using 140 * @irq: The IRQ number we are using
141 * @supplies: Definition of USB power supplies
138 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 142 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
143 * @num_of_eps: Number of available EPs (excluding EP0)
139 * @debug_root: root directrory for debugfs. 144 * @debug_root: root directrory for debugfs.
140 * @debug_file: main status file for debugfs. 145 * @debug_file: main status file for debugfs.
141 * @debug_fifo: FIFO status file for debugfs. 146 * @debug_fifo: FIFO status file for debugfs.
@@ -143,6 +148,8 @@ struct s3c_hsotg_ep {
143 * @ep0_buff: Buffer for EP0 reply data, if needed. 148 * @ep0_buff: Buffer for EP0 reply data, if needed.
144 * @ctrl_buff: Buffer for EP0 control requests. 149 * @ctrl_buff: Buffer for EP0 control requests.
145 * @ctrl_req: Request for EP0 control packets. 150 * @ctrl_req: Request for EP0 control packets.
151 * @setup: NAK management for EP0 SETUP
152 * @last_rst: Time of last reset
146 * @eps: The endpoints being supplied to the gadget framework 153 * @eps: The endpoints being supplied to the gadget framework
147 */ 154 */
148struct s3c_hsotg { 155struct s3c_hsotg {
@@ -155,7 +162,10 @@ struct s3c_hsotg {
155 int irq; 162 int irq;
156 struct clk *clk; 163 struct clk *clk;
157 164
165 struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsotg_supply_names)];
166
158 unsigned int dedicated_fifos:1; 167 unsigned int dedicated_fifos:1;
168 unsigned char num_of_eps;
159 169
160 struct dentry *debug_root; 170 struct dentry *debug_root;
161 struct dentry *debug_file; 171 struct dentry *debug_file;
@@ -167,7 +177,9 @@ struct s3c_hsotg {
167 u8 ctrl_buff[8]; 177 u8 ctrl_buff[8];
168 178
169 struct usb_gadget gadget; 179 struct usb_gadget gadget;
170 struct s3c_hsotg_ep eps[]; 180 unsigned int setup;
181 unsigned long last_rst;
182 struct s3c_hsotg_ep *eps;
171}; 183};
172 184
173/** 185/**
@@ -244,14 +256,14 @@ static inline bool using_dma(struct s3c_hsotg *hsotg)
244 */ 256 */
245static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints) 257static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
246{ 258{
247 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK); 259 u32 gsintmsk = readl(hsotg->regs + GINTMSK);
248 u32 new_gsintmsk; 260 u32 new_gsintmsk;
249 261
250 new_gsintmsk = gsintmsk | ints; 262 new_gsintmsk = gsintmsk | ints;
251 263
252 if (new_gsintmsk != gsintmsk) { 264 if (new_gsintmsk != gsintmsk) {
253 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); 265 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
254 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK); 266 writel(new_gsintmsk, hsotg->regs + GINTMSK);
255 } 267 }
256} 268}
257 269
@@ -262,13 +274,13 @@ static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
262 */ 274 */
263static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints) 275static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
264{ 276{
265 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK); 277 u32 gsintmsk = readl(hsotg->regs + GINTMSK);
266 u32 new_gsintmsk; 278 u32 new_gsintmsk;
267 279
268 new_gsintmsk = gsintmsk & ~ints; 280 new_gsintmsk = gsintmsk & ~ints;
269 281
270 if (new_gsintmsk != gsintmsk) 282 if (new_gsintmsk != gsintmsk)
271 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK); 283 writel(new_gsintmsk, hsotg->regs + GINTMSK);
272} 284}
273 285
274/** 286/**
@@ -293,12 +305,12 @@ static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
293 bit <<= 16; 305 bit <<= 16;
294 306
295 local_irq_save(flags); 307 local_irq_save(flags);
296 daint = readl(hsotg->regs + S3C_DAINTMSK); 308 daint = readl(hsotg->regs + DAINTMSK);
297 if (en) 309 if (en)
298 daint |= bit; 310 daint |= bit;
299 else 311 else
300 daint &= ~bit; 312 daint &= ~bit;
301 writel(daint, hsotg->regs + S3C_DAINTMSK); 313 writel(daint, hsotg->regs + DAINTMSK);
302 local_irq_restore(flags); 314 local_irq_restore(flags);
303} 315}
304 316
@@ -314,52 +326,51 @@ static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
314 int timeout; 326 int timeout;
315 u32 val; 327 u32 val;
316 328
317 /* the ryu 2.6.24 release ahs
318 writel(0x1C0, hsotg->regs + S3C_GRXFSIZ);
319 writel(S3C_GNPTXFSIZ_NPTxFStAddr(0x200) |
320 S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
321 hsotg->regs + S3C_GNPTXFSIZ);
322 */
323
324 /* set FIFO sizes to 2048/1024 */ 329 /* set FIFO sizes to 2048/1024 */
325 330
326 writel(2048, hsotg->regs + S3C_GRXFSIZ); 331 writel(2048, hsotg->regs + GRXFSIZ);
327 writel(S3C_GNPTXFSIZ_NPTxFStAddr(2048) | 332 writel(GNPTXFSIZ_NPTxFStAddr(2048) |
328 S3C_GNPTXFSIZ_NPTxFDep(1024), 333 GNPTXFSIZ_NPTxFDep(1024),
329 hsotg->regs + S3C_GNPTXFSIZ); 334 hsotg->regs + GNPTXFSIZ);
330 335
331 /* arange all the rest of the TX FIFOs, as some versions of this 336 /*
337 * arange all the rest of the TX FIFOs, as some versions of this
332 * block have overlapping default addresses. This also ensures 338 * block have overlapping default addresses. This also ensures
333 * that if the settings have been changed, then they are set to 339 * that if the settings have been changed, then they are set to
334 * known values. */ 340 * known values.
341 */
335 342
336 /* start at the end of the GNPTXFSIZ, rounded up */ 343 /* start at the end of the GNPTXFSIZ, rounded up */
337 addr = 2048 + 1024; 344 addr = 2048 + 1024;
338 size = 768; 345 size = 768;
339 346
340 /* currently we allocate TX FIFOs for all possible endpoints, 347 /*
341 * and assume that they are all the same size. */ 348 * currently we allocate TX FIFOs for all possible endpoints,
349 * and assume that they are all the same size.
350 */
342 351
343 for (ep = 0; ep <= 15; ep++) { 352 for (ep = 1; ep <= 15; ep++) {
344 val = addr; 353 val = addr;
345 val |= size << S3C_DPTXFSIZn_DPTxFSize_SHIFT; 354 val |= size << DPTXFSIZn_DPTxFSize_SHIFT;
346 addr += size; 355 addr += size;
347 356
348 writel(val, hsotg->regs + S3C_DPTXFSIZn(ep)); 357 writel(val, hsotg->regs + DPTXFSIZn(ep));
349 } 358 }
350 359
351 /* according to p428 of the design guide, we need to ensure that 360 /*
352 * all fifos are flushed before continuing */ 361 * according to p428 of the design guide, we need to ensure that
362 * all fifos are flushed before continuing
363 */
353 364
354 writel(S3C_GRSTCTL_TxFNum(0x10) | S3C_GRSTCTL_TxFFlsh | 365 writel(GRSTCTL_TxFNum(0x10) | GRSTCTL_TxFFlsh |
355 S3C_GRSTCTL_RxFFlsh, hsotg->regs + S3C_GRSTCTL); 366 GRSTCTL_RxFFlsh, hsotg->regs + GRSTCTL);
356 367
357 /* wait until the fifos are both flushed */ 368 /* wait until the fifos are both flushed */
358 timeout = 100; 369 timeout = 100;
359 while (1) { 370 while (1) {
360 val = readl(hsotg->regs + S3C_GRSTCTL); 371 val = readl(hsotg->regs + GRSTCTL);
361 372
362 if ((val & (S3C_GRSTCTL_TxFFlsh | S3C_GRSTCTL_RxFFlsh)) == 0) 373 if ((val & (GRSTCTL_TxFFlsh | GRSTCTL_RxFFlsh)) == 0)
363 break; 374 break;
364 375
365 if (--timeout == 0) { 376 if (--timeout == 0) {
@@ -415,7 +426,7 @@ static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
415 * 426 *
416 * This is the reverse of s3c_hsotg_map_dma(), called for the completion 427 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
417 * of a request to ensure the buffer is ready for access by the caller. 428 * of a request to ensure the buffer is ready for access by the caller.
418*/ 429 */
419static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg, 430static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
420 struct s3c_hsotg_ep *hs_ep, 431 struct s3c_hsotg_ep *hs_ep,
421 struct s3c_hsotg_req *hs_req) 432 struct s3c_hsotg_req *hs_req)
@@ -456,13 +467,13 @@ static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
456 * otherwise -ENOSPC is returned if the FIFO space was used up. 467 * otherwise -ENOSPC is returned if the FIFO space was used up.
457 * 468 *
458 * This routine is only needed for PIO 469 * This routine is only needed for PIO
459*/ 470 */
460static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg, 471static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
461 struct s3c_hsotg_ep *hs_ep, 472 struct s3c_hsotg_ep *hs_ep,
462 struct s3c_hsotg_req *hs_req) 473 struct s3c_hsotg_req *hs_req)
463{ 474{
464 bool periodic = is_ep_periodic(hs_ep); 475 bool periodic = is_ep_periodic(hs_ep);
465 u32 gnptxsts = readl(hsotg->regs + S3C_GNPTXSTS); 476 u32 gnptxsts = readl(hsotg->regs + GNPTXSTS);
466 int buf_pos = hs_req->req.actual; 477 int buf_pos = hs_req->req.actual;
467 int to_write = hs_ep->size_loaded; 478 int to_write = hs_ep->size_loaded;
468 void *data; 479 void *data;
@@ -476,20 +487,23 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
476 return 0; 487 return 0;
477 488
478 if (periodic && !hsotg->dedicated_fifos) { 489 if (periodic && !hsotg->dedicated_fifos) {
479 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index)); 490 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
480 int size_left; 491 int size_left;
481 int size_done; 492 int size_done;
482 493
483 /* work out how much data was loaded so we can calculate 494 /*
484 * how much data is left in the fifo. */ 495 * work out how much data was loaded so we can calculate
496 * how much data is left in the fifo.
497 */
485 498
486 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize); 499 size_left = DxEPTSIZ_XferSize_GET(epsize);
487 500
488 /* if shared fifo, we cannot write anything until the 501 /*
502 * if shared fifo, we cannot write anything until the
489 * previous data has been completely sent. 503 * previous data has been completely sent.
490 */ 504 */
491 if (hs_ep->fifo_load != 0) { 505 if (hs_ep->fifo_load != 0) {
492 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp); 506 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTxFEmp);
493 return -ENOSPC; 507 return -ENOSPC;
494 } 508 }
495 509
@@ -510,47 +524,50 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
510 __func__, can_write); 524 __func__, can_write);
511 525
512 if (can_write <= 0) { 526 if (can_write <= 0) {
513 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp); 527 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTxFEmp);
514 return -ENOSPC; 528 return -ENOSPC;
515 } 529 }
516 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { 530 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
517 can_write = readl(hsotg->regs + S3C_DTXFSTS(hs_ep->index)); 531 can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index));
518 532
519 can_write &= 0xffff; 533 can_write &= 0xffff;
520 can_write *= 4; 534 can_write *= 4;
521 } else { 535 } else {
522 if (S3C_GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) { 536 if (GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
523 dev_dbg(hsotg->dev, 537 dev_dbg(hsotg->dev,
524 "%s: no queue slots available (0x%08x)\n", 538 "%s: no queue slots available (0x%08x)\n",
525 __func__, gnptxsts); 539 __func__, gnptxsts);
526 540
527 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_NPTxFEmp); 541 s3c_hsotg_en_gsint(hsotg, GINTSTS_NPTxFEmp);
528 return -ENOSPC; 542 return -ENOSPC;
529 } 543 }
530 544
531 can_write = S3C_GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts); 545 can_write = GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
532 can_write *= 4; /* fifo size is in 32bit quantities. */ 546 can_write *= 4; /* fifo size is in 32bit quantities. */
533 } 547 }
534 548
535 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n", 549 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
536 __func__, gnptxsts, can_write, to_write, hs_ep->ep.maxpacket); 550 __func__, gnptxsts, can_write, to_write, hs_ep->ep.maxpacket);
537 551
538 /* limit to 512 bytes of data, it seems at least on the non-periodic 552 /*
553 * limit to 512 bytes of data, it seems at least on the non-periodic
539 * FIFO, requests of >512 cause the endpoint to get stuck with a 554 * FIFO, requests of >512 cause the endpoint to get stuck with a
540 * fragment of the end of the transfer in it. 555 * fragment of the end of the transfer in it.
541 */ 556 */
542 if (can_write > 512) 557 if (can_write > 512)
543 can_write = 512; 558 can_write = 512;
544 559
545 /* limit the write to one max-packet size worth of data, but allow 560 /*
561 * limit the write to one max-packet size worth of data, but allow
546 * the transfer to return that it did not run out of fifo space 562 * the transfer to return that it did not run out of fifo space
547 * doing it. */ 563 * doing it.
564 */
548 if (to_write > hs_ep->ep.maxpacket) { 565 if (to_write > hs_ep->ep.maxpacket) {
549 to_write = hs_ep->ep.maxpacket; 566 to_write = hs_ep->ep.maxpacket;
550 567
551 s3c_hsotg_en_gsint(hsotg, 568 s3c_hsotg_en_gsint(hsotg,
552 periodic ? S3C_GINTSTS_PTxFEmp : 569 periodic ? GINTSTS_PTxFEmp :
553 S3C_GINTSTS_NPTxFEmp); 570 GINTSTS_NPTxFEmp);
554 } 571 }
555 572
556 /* see if we can write data */ 573 /* see if we can write data */
@@ -559,8 +576,8 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
559 to_write = can_write; 576 to_write = can_write;
560 pkt_round = to_write % hs_ep->ep.maxpacket; 577 pkt_round = to_write % hs_ep->ep.maxpacket;
561 578
562 /* Not sure, but we probably shouldn't be writing partial 579 /*
563 * packets into the FIFO, so round the write down to an 580 * Round the write down to an
564 * exact number of packets. 581 * exact number of packets.
565 * 582 *
566 * Note, we do not currently check to see if we can ever 583 * Note, we do not currently check to see if we can ever
@@ -570,12 +587,14 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
570 if (pkt_round) 587 if (pkt_round)
571 to_write -= pkt_round; 588 to_write -= pkt_round;
572 589
573 /* enable correct FIFO interrupt to alert us when there 590 /*
574 * is more room left. */ 591 * enable correct FIFO interrupt to alert us when there
592 * is more room left.
593 */
575 594
576 s3c_hsotg_en_gsint(hsotg, 595 s3c_hsotg_en_gsint(hsotg,
577 periodic ? S3C_GINTSTS_PTxFEmp : 596 periodic ? GINTSTS_PTxFEmp :
578 S3C_GINTSTS_NPTxFEmp); 597 GINTSTS_NPTxFEmp);
579 } 598 }
580 599
581 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", 600 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
@@ -593,7 +612,7 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
593 to_write = DIV_ROUND_UP(to_write, 4); 612 to_write = DIV_ROUND_UP(to_write, 4);
594 data = hs_req->req.buf + buf_pos; 613 data = hs_req->req.buf + buf_pos;
595 614
596 writesl(hsotg->regs + S3C_EPFIFO(hs_ep->index), data, to_write); 615 writesl(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
597 616
598 return (to_write >= can_write) ? -ENOSPC : 0; 617 return (to_write >= can_write) ? -ENOSPC : 0;
599} 618}
@@ -612,12 +631,12 @@ static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
612 unsigned maxpkt; 631 unsigned maxpkt;
613 632
614 if (index != 0) { 633 if (index != 0) {
615 maxsize = S3C_DxEPTSIZ_XferSize_LIMIT + 1; 634 maxsize = DxEPTSIZ_XferSize_LIMIT + 1;
616 maxpkt = S3C_DxEPTSIZ_PktCnt_LIMIT + 1; 635 maxpkt = DxEPTSIZ_PktCnt_LIMIT + 1;
617 } else { 636 } else {
618 maxsize = 64+64; 637 maxsize = 64+64;
619 if (hs_ep->dir_in) 638 if (hs_ep->dir_in)
620 maxpkt = S3C_DIEPTSIZ0_PktCnt_LIMIT + 1; 639 maxpkt = DIEPTSIZ0_PktCnt_LIMIT + 1;
621 else 640 else
622 maxpkt = 2; 641 maxpkt = 2;
623 } 642 }
@@ -626,8 +645,10 @@ static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
626 maxpkt--; 645 maxpkt--;
627 maxsize--; 646 maxsize--;
628 647
629 /* constrain by packet count if maxpkts*pktsize is greater 648 /*
630 * than the length register size. */ 649 * constrain by packet count if maxpkts*pktsize is greater
650 * than the length register size.
651 */
631 652
632 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize) 653 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
633 maxsize = maxpkt * hs_ep->ep.maxpacket; 654 maxsize = maxpkt * hs_ep->ep.maxpacket;
@@ -674,8 +695,8 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
674 } 695 }
675 } 696 }
676 697
677 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index); 698 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
678 epsize_reg = dir_in ? S3C_DIEPTSIZ(index) : S3C_DOEPTSIZ(index); 699 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
679 700
680 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", 701 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
681 __func__, readl(hsotg->regs + epctrl_reg), index, 702 __func__, readl(hsotg->regs + epctrl_reg), index,
@@ -684,13 +705,14 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
684 /* If endpoint is stalled, we will restart request later */ 705 /* If endpoint is stalled, we will restart request later */
685 ctrl = readl(hsotg->regs + epctrl_reg); 706 ctrl = readl(hsotg->regs + epctrl_reg);
686 707
687 if (ctrl & S3C_DxEPCTL_Stall) { 708 if (ctrl & DxEPCTL_Stall) {
688 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); 709 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
689 return; 710 return;
690 } 711 }
691 712
692 length = ureq->length - ureq->actual; 713 length = ureq->length - ureq->actual;
693 714 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
715 ureq->length, ureq->actual);
694 if (0) 716 if (0)
695 dev_dbg(hsotg->dev, 717 dev_dbg(hsotg->dev,
696 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n", 718 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
@@ -717,20 +739,22 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
717 packets = 1; /* send one packet if length is zero. */ 739 packets = 1; /* send one packet if length is zero. */
718 740
719 if (dir_in && index != 0) 741 if (dir_in && index != 0)
720 epsize = S3C_DxEPTSIZ_MC(1); 742 epsize = DxEPTSIZ_MC(1);
721 else 743 else
722 epsize = 0; 744 epsize = 0;
723 745
724 if (index != 0 && ureq->zero) { 746 if (index != 0 && ureq->zero) {
725 /* test for the packets being exactly right for the 747 /*
726 * transfer */ 748 * test for the packets being exactly right for the
749 * transfer
750 */
727 751
728 if (length == (packets * hs_ep->ep.maxpacket)) 752 if (length == (packets * hs_ep->ep.maxpacket))
729 packets++; 753 packets++;
730 } 754 }
731 755
732 epsize |= S3C_DxEPTSIZ_PktCnt(packets); 756 epsize |= DxEPTSIZ_PktCnt(packets);
733 epsize |= S3C_DxEPTSIZ_XferSize(length); 757 epsize |= DxEPTSIZ_XferSize(length);
734 758
735 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", 759 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
736 __func__, packets, length, ureq->length, epsize, epsize_reg); 760 __func__, packets, length, ureq->length, epsize, epsize_reg);
@@ -741,29 +765,41 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
741 /* write size / packets */ 765 /* write size / packets */
742 writel(epsize, hsotg->regs + epsize_reg); 766 writel(epsize, hsotg->regs + epsize_reg);
743 767
744 if (using_dma(hsotg)) { 768 if (using_dma(hsotg) && !continuing) {
745 unsigned int dma_reg; 769 unsigned int dma_reg;
746 770
747 /* write DMA address to control register, buffer already 771 /*
748 * synced by s3c_hsotg_ep_queue(). */ 772 * write DMA address to control register, buffer already
773 * synced by s3c_hsotg_ep_queue().
774 */
749 775
750 dma_reg = dir_in ? S3C_DIEPDMA(index) : S3C_DOEPDMA(index); 776 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
751 writel(ureq->dma, hsotg->regs + dma_reg); 777 writel(ureq->dma, hsotg->regs + dma_reg);
752 778
753 dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n", 779 dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n",
754 __func__, ureq->dma, dma_reg); 780 __func__, ureq->dma, dma_reg);
755 } 781 }
756 782
757 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */ 783 ctrl |= DxEPCTL_EPEna; /* ensure ep enabled */
758 ctrl |= S3C_DxEPCTL_USBActEp; 784 ctrl |= DxEPCTL_USBActEp;
759 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */ 785
786 dev_dbg(hsotg->dev, "setup req:%d\n", hsotg->setup);
787
788 /* For Setup request do not clear NAK */
789 if (hsotg->setup && index == 0)
790 hsotg->setup = 0;
791 else
792 ctrl |= DxEPCTL_CNAK; /* clear NAK set by core */
793
760 794
761 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); 795 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
762 writel(ctrl, hsotg->regs + epctrl_reg); 796 writel(ctrl, hsotg->regs + epctrl_reg);
763 797
764 /* set these, it seems that DMA support increments past the end 798 /*
799 * set these, it seems that DMA support increments past the end
765 * of the packet buffer so we need to calculate the length from 800 * of the packet buffer so we need to calculate the length from
766 * this information. */ 801 * this information.
802 */
767 hs_ep->size_loaded = length; 803 hs_ep->size_loaded = length;
768 hs_ep->last_load = ureq->actual; 804 hs_ep->last_load = ureq->actual;
769 805
@@ -774,17 +810,21 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
774 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req); 810 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
775 } 811 }
776 812
777 /* clear the INTknTXFEmpMsk when we start request, more as a aide 813 /*
778 * to debugging to see what is going on. */ 814 * clear the INTknTXFEmpMsk when we start request, more as a aide
815 * to debugging to see what is going on.
816 */
779 if (dir_in) 817 if (dir_in)
780 writel(S3C_DIEPMSK_INTknTXFEmpMsk, 818 writel(DIEPMSK_INTknTXFEmpMsk,
781 hsotg->regs + S3C_DIEPINT(index)); 819 hsotg->regs + DIEPINT(index));
782 820
783 /* Note, trying to clear the NAK here causes problems with transmit 821 /*
784 * on the S3C6400 ending up with the TXFIFO becoming full. */ 822 * Note, trying to clear the NAK here causes problems with transmit
823 * on the S3C6400 ending up with the TXFIFO becoming full.
824 */
785 825
786 /* check ep is enabled */ 826 /* check ep is enabled */
787 if (!(readl(hsotg->regs + epctrl_reg) & S3C_DxEPCTL_EPEna)) 827 if (!(readl(hsotg->regs + epctrl_reg) & DxEPCTL_EPEna))
788 dev_warn(hsotg->dev, 828 dev_warn(hsotg->dev,
789 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n", 829 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
790 index, readl(hsotg->regs + epctrl_reg)); 830 index, readl(hsotg->regs + epctrl_reg));
@@ -804,7 +844,7 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
804 * then ensure the buffer has been synced to memory. If our buffer has no 844 * then ensure the buffer has been synced to memory. If our buffer has no
805 * DMA memory, then we map the memory and mark our request to allow us to 845 * DMA memory, then we map the memory and mark our request to allow us to
806 * cleanup on completion. 846 * cleanup on completion.
807*/ 847 */
808static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg, 848static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg,
809 struct s3c_hsotg_ep *hs_ep, 849 struct s3c_hsotg_ep *hs_ep,
810 struct usb_request *req) 850 struct usb_request *req)
@@ -922,7 +962,7 @@ static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
922 * 962 *
923 * Convert the given wIndex into a pointer to an driver endpoint 963 * Convert the given wIndex into a pointer to an driver endpoint
924 * structure, or return NULL if it is not a valid endpoint. 964 * structure, or return NULL if it is not a valid endpoint.
925*/ 965 */
926static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg, 966static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
927 u32 windex) 967 u32 windex)
928{ 968{
@@ -933,7 +973,7 @@ static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
933 if (windex >= 0x100) 973 if (windex >= 0x100)
934 return NULL; 974 return NULL;
935 975
936 if (idx > S3C_HSOTG_EPS) 976 if (idx > hsotg->num_of_eps)
937 return NULL; 977 return NULL;
938 978
939 if (idx && ep->dir_in != dir) 979 if (idx && ep->dir_in != dir)
@@ -1151,24 +1191,28 @@ static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1151 ctrl->bRequest, ctrl->bRequestType, 1191 ctrl->bRequest, ctrl->bRequestType,
1152 ctrl->wValue, ctrl->wLength); 1192 ctrl->wValue, ctrl->wLength);
1153 1193
1154 /* record the direction of the request, for later use when enquing 1194 /*
1155 * packets onto EP0. */ 1195 * record the direction of the request, for later use when enquing
1196 * packets onto EP0.
1197 */
1156 1198
1157 ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0; 1199 ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
1158 dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in); 1200 dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
1159 1201
1160 /* if we've no data with this request, then the last part of the 1202 /*
1161 * transaction is going to implicitly be IN. */ 1203 * if we've no data with this request, then the last part of the
1204 * transaction is going to implicitly be IN.
1205 */
1162 if (ctrl->wLength == 0) 1206 if (ctrl->wLength == 0)
1163 ep0->dir_in = 1; 1207 ep0->dir_in = 1;
1164 1208
1165 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { 1209 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1166 switch (ctrl->bRequest) { 1210 switch (ctrl->bRequest) {
1167 case USB_REQ_SET_ADDRESS: 1211 case USB_REQ_SET_ADDRESS:
1168 dcfg = readl(hsotg->regs + S3C_DCFG); 1212 dcfg = readl(hsotg->regs + DCFG);
1169 dcfg &= ~S3C_DCFG_DevAddr_MASK; 1213 dcfg &= ~DCFG_DevAddr_MASK;
1170 dcfg |= ctrl->wValue << S3C_DCFG_DevAddr_SHIFT; 1214 dcfg |= ctrl->wValue << DCFG_DevAddr_SHIFT;
1171 writel(dcfg, hsotg->regs + S3C_DCFG); 1215 writel(dcfg, hsotg->regs + DCFG);
1172 1216
1173 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); 1217 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1174 1218
@@ -1194,7 +1238,8 @@ static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1194 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret); 1238 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1195 } 1239 }
1196 1240
1197 /* the request is either unhandlable, or is not formatted correctly 1241 /*
1242 * the request is either unhandlable, or is not formatted correctly
1198 * so respond with a STALL for the status stage to indicate failure. 1243 * so respond with a STALL for the status stage to indicate failure.
1199 */ 1244 */
1200 1245
@@ -1203,22 +1248,26 @@ static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1203 u32 ctrl; 1248 u32 ctrl;
1204 1249
1205 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in); 1250 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1206 reg = (ep0->dir_in) ? S3C_DIEPCTL0 : S3C_DOEPCTL0; 1251 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1207 1252
1208 /* S3C_DxEPCTL_Stall will be cleared by EP once it has 1253 /*
1209 * taken effect, so no need to clear later. */ 1254 * DxEPCTL_Stall will be cleared by EP once it has
1255 * taken effect, so no need to clear later.
1256 */
1210 1257
1211 ctrl = readl(hsotg->regs + reg); 1258 ctrl = readl(hsotg->regs + reg);
1212 ctrl |= S3C_DxEPCTL_Stall; 1259 ctrl |= DxEPCTL_Stall;
1213 ctrl |= S3C_DxEPCTL_CNAK; 1260 ctrl |= DxEPCTL_CNAK;
1214 writel(ctrl, hsotg->regs + reg); 1261 writel(ctrl, hsotg->regs + reg);
1215 1262
1216 dev_dbg(hsotg->dev, 1263 dev_dbg(hsotg->dev,
1217 "written DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n", 1264 "written DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1218 ctrl, reg, readl(hsotg->regs + reg)); 1265 ctrl, reg, readl(hsotg->regs + reg));
1219 1266
1220 /* don't believe we need to anything more to get the EP 1267 /*
1221 * to reply with a STALL packet */ 1268 * don't believe we need to anything more to get the EP
1269 * to reply with a STALL packet
1270 */
1222 } 1271 }
1223} 1272}
1224 1273
@@ -1279,8 +1328,10 @@ static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
1279 ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC); 1328 ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
1280 if (ret < 0) { 1329 if (ret < 0) {
1281 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret); 1330 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1282 /* Don't think there's much we can do other than watch the 1331 /*
1283 * driver fail. */ 1332 * Don't think there's much we can do other than watch the
1333 * driver fail.
1334 */
1284 } 1335 }
1285} 1336}
1286 1337
@@ -1296,7 +1347,7 @@ static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
1296 * on the endpoint. 1347 * on the endpoint.
1297 * 1348 *
1298 * Note, expects the ep to already be locked as appropriate. 1349 * Note, expects the ep to already be locked as appropriate.
1299*/ 1350 */
1300static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg, 1351static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1301 struct s3c_hsotg_ep *hs_ep, 1352 struct s3c_hsotg_ep *hs_ep,
1302 struct s3c_hsotg_req *hs_req, 1353 struct s3c_hsotg_req *hs_req,
@@ -1312,8 +1363,10 @@ static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1312 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n", 1363 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1313 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete); 1364 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1314 1365
1315 /* only replace the status if we've not already set an error 1366 /*
1316 * from a previous transaction */ 1367 * only replace the status if we've not already set an error
1368 * from a previous transaction
1369 */
1317 1370
1318 if (hs_req->req.status == -EINPROGRESS) 1371 if (hs_req->req.status == -EINPROGRESS)
1319 hs_req->req.status = result; 1372 hs_req->req.status = result;
@@ -1324,8 +1377,10 @@ static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1324 if (using_dma(hsotg)) 1377 if (using_dma(hsotg))
1325 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req); 1378 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1326 1379
1327 /* call the complete request with the locks off, just in case the 1380 /*
1328 * request tries to queue more work for this endpoint. */ 1381 * call the complete request with the locks off, just in case the
1382 * request tries to queue more work for this endpoint.
1383 */
1329 1384
1330 if (hs_req->req.complete) { 1385 if (hs_req->req.complete) {
1331 spin_unlock(&hs_ep->lock); 1386 spin_unlock(&hs_ep->lock);
@@ -1333,9 +1388,11 @@ static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1333 spin_lock(&hs_ep->lock); 1388 spin_lock(&hs_ep->lock);
1334 } 1389 }
1335 1390
1336 /* Look to see if there is anything else to do. Note, the completion 1391 /*
1392 * Look to see if there is anything else to do. Note, the completion
1337 * of the previous request may have caused a new request to be started 1393 * of the previous request may have caused a new request to be started
1338 * so be careful when doing this. */ 1394 * so be careful when doing this.
1395 */
1339 1396
1340 if (!hs_ep->req && result >= 0) { 1397 if (!hs_ep->req && result >= 0) {
1341 restart = !list_empty(&hs_ep->queue); 1398 restart = !list_empty(&hs_ep->queue);
@@ -1355,7 +1412,7 @@ static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1355 * 1412 *
1356 * See s3c_hsotg_complete_request(), but called with the endpoint's 1413 * See s3c_hsotg_complete_request(), but called with the endpoint's
1357 * lock held. 1414 * lock held.
1358*/ 1415 */
1359static void s3c_hsotg_complete_request_lock(struct s3c_hsotg *hsotg, 1416static void s3c_hsotg_complete_request_lock(struct s3c_hsotg *hsotg,
1360 struct s3c_hsotg_ep *hs_ep, 1417 struct s3c_hsotg_ep *hs_ep,
1361 struct s3c_hsotg_req *hs_req, 1418 struct s3c_hsotg_req *hs_req,
@@ -1382,13 +1439,13 @@ static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1382{ 1439{
1383 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx]; 1440 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1384 struct s3c_hsotg_req *hs_req = hs_ep->req; 1441 struct s3c_hsotg_req *hs_req = hs_ep->req;
1385 void __iomem *fifo = hsotg->regs + S3C_EPFIFO(ep_idx); 1442 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
1386 int to_read; 1443 int to_read;
1387 int max_req; 1444 int max_req;
1388 int read_ptr; 1445 int read_ptr;
1389 1446
1390 if (!hs_req) { 1447 if (!hs_req) {
1391 u32 epctl = readl(hsotg->regs + S3C_DOEPCTL(ep_idx)); 1448 u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx));
1392 int ptr; 1449 int ptr;
1393 1450
1394 dev_warn(hsotg->dev, 1451 dev_warn(hsotg->dev,
@@ -1412,7 +1469,8 @@ static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1412 __func__, to_read, max_req, read_ptr, hs_req->req.length); 1469 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1413 1470
1414 if (to_read > max_req) { 1471 if (to_read > max_req) {
1415 /* more data appeared than we where willing 1472 /*
1473 * more data appeared than we where willing
1416 * to deal with in this request. 1474 * to deal with in this request.
1417 */ 1475 */
1418 1476
@@ -1424,8 +1482,10 @@ static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1424 hs_req->req.actual += to_read; 1482 hs_req->req.actual += to_read;
1425 to_read = DIV_ROUND_UP(to_read, 4); 1483 to_read = DIV_ROUND_UP(to_read, 4);
1426 1484
1427 /* note, we might over-write the buffer end by 3 bytes depending on 1485 /*
1428 * alignment of the data. */ 1486 * note, we might over-write the buffer end by 3 bytes depending on
1487 * alignment of the data.
1488 */
1429 readsl(fifo, hs_req->req.buf + read_ptr, to_read); 1489 readsl(fifo, hs_req->req.buf + read_ptr, to_read);
1430 1490
1431 spin_unlock(&hs_ep->lock); 1491 spin_unlock(&hs_ep->lock);
@@ -1465,14 +1525,14 @@ static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1465 dev_dbg(hsotg->dev, "sending zero-length packet\n"); 1525 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1466 1526
1467 /* issue a zero-sized packet to terminate this */ 1527 /* issue a zero-sized packet to terminate this */
1468 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) | 1528 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
1469 S3C_DxEPTSIZ_XferSize(0), hsotg->regs + S3C_DIEPTSIZ(0)); 1529 DxEPTSIZ_XferSize(0), hsotg->regs + DIEPTSIZ(0));
1470 1530
1471 ctrl = readl(hsotg->regs + S3C_DIEPCTL0); 1531 ctrl = readl(hsotg->regs + DIEPCTL0);
1472 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */ 1532 ctrl |= DxEPCTL_CNAK; /* clear NAK set by core */
1473 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */ 1533 ctrl |= DxEPCTL_EPEna; /* ensure ep enabled */
1474 ctrl |= S3C_DxEPCTL_USBActEp; 1534 ctrl |= DxEPCTL_USBActEp;
1475 writel(ctrl, hsotg->regs + S3C_DIEPCTL0); 1535 writel(ctrl, hsotg->regs + DIEPCTL0);
1476} 1536}
1477 1537
1478/** 1538/**
@@ -1484,15 +1544,15 @@ static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1484 * The RXFIFO has delivered an OutDone event, which means that the data 1544 * The RXFIFO has delivered an OutDone event, which means that the data
1485 * transfer for an OUT endpoint has been completed, either by a short 1545 * transfer for an OUT endpoint has been completed, either by a short
1486 * packet or by the finish of a transfer. 1546 * packet or by the finish of a transfer.
1487*/ 1547 */
1488static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg, 1548static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1489 int epnum, bool was_setup) 1549 int epnum, bool was_setup)
1490{ 1550{
1491 u32 epsize = readl(hsotg->regs + S3C_DOEPTSIZ(epnum)); 1551 u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum));
1492 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum]; 1552 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1493 struct s3c_hsotg_req *hs_req = hs_ep->req; 1553 struct s3c_hsotg_req *hs_req = hs_ep->req;
1494 struct usb_request *req = &hs_req->req; 1554 struct usb_request *req = &hs_req->req;
1495 unsigned size_left = S3C_DxEPTSIZ_XferSize_GET(epsize); 1555 unsigned size_left = DxEPTSIZ_XferSize_GET(epsize);
1496 int result = 0; 1556 int result = 0;
1497 1557
1498 if (!hs_req) { 1558 if (!hs_req) {
@@ -1503,7 +1563,8 @@ static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1503 if (using_dma(hsotg)) { 1563 if (using_dma(hsotg)) {
1504 unsigned size_done; 1564 unsigned size_done;
1505 1565
1506 /* Calculate the size of the transfer by checking how much 1566 /*
1567 * Calculate the size of the transfer by checking how much
1507 * is left in the endpoint size register and then working it 1568 * is left in the endpoint size register and then working it
1508 * out from the amount we loaded for the transfer. 1569 * out from the amount we loaded for the transfer.
1509 * 1570 *
@@ -1521,17 +1582,29 @@ static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1521 if (req->actual < req->length && size_left == 0) { 1582 if (req->actual < req->length && size_left == 0) {
1522 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true); 1583 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1523 return; 1584 return;
1585 } else if (epnum == 0) {
1586 /*
1587 * After was_setup = 1 =>
1588 * set CNAK for non Setup requests
1589 */
1590 hsotg->setup = was_setup ? 0 : 1;
1524 } 1591 }
1525 1592
1526 if (req->actual < req->length && req->short_not_ok) { 1593 if (req->actual < req->length && req->short_not_ok) {
1527 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n", 1594 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1528 __func__, req->actual, req->length); 1595 __func__, req->actual, req->length);
1529 1596
1530 /* todo - what should we return here? there's no one else 1597 /*
1531 * even bothering to check the status. */ 1598 * todo - what should we return here? there's no one else
1599 * even bothering to check the status.
1600 */
1532 } 1601 }
1533 1602
1534 if (epnum == 0) { 1603 if (epnum == 0) {
1604 /*
1605 * Condition req->complete != s3c_hsotg_complete_setup says:
1606 * send ZLP when we have an asynchronous request from gadget
1607 */
1535 if (!was_setup && req->complete != s3c_hsotg_complete_setup) 1608 if (!was_setup && req->complete != s3c_hsotg_complete_setup)
1536 s3c_hsotg_send_zlp(hsotg, hs_req); 1609 s3c_hsotg_send_zlp(hsotg, hs_req);
1537 } 1610 }
@@ -1544,14 +1617,14 @@ static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1544 * @hsotg: The device instance 1617 * @hsotg: The device instance
1545 * 1618 *
1546 * Return the current frame number 1619 * Return the current frame number
1547*/ 1620 */
1548static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg) 1621static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1549{ 1622{
1550 u32 dsts; 1623 u32 dsts;
1551 1624
1552 dsts = readl(hsotg->regs + S3C_DSTS); 1625 dsts = readl(hsotg->regs + DSTS);
1553 dsts &= S3C_DSTS_SOFFN_MASK; 1626 dsts &= DSTS_SOFFN_MASK;
1554 dsts >>= S3C_DSTS_SOFFN_SHIFT; 1627 dsts >>= DSTS_SOFFN_SHIFT;
1555 1628
1556 return dsts; 1629 return dsts;
1557} 1630}
@@ -1574,29 +1647,29 @@ static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1574 */ 1647 */
1575static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg) 1648static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1576{ 1649{
1577 u32 grxstsr = readl(hsotg->regs + S3C_GRXSTSP); 1650 u32 grxstsr = readl(hsotg->regs + GRXSTSP);
1578 u32 epnum, status, size; 1651 u32 epnum, status, size;
1579 1652
1580 WARN_ON(using_dma(hsotg)); 1653 WARN_ON(using_dma(hsotg));
1581 1654
1582 epnum = grxstsr & S3C_GRXSTS_EPNum_MASK; 1655 epnum = grxstsr & GRXSTS_EPNum_MASK;
1583 status = grxstsr & S3C_GRXSTS_PktSts_MASK; 1656 status = grxstsr & GRXSTS_PktSts_MASK;
1584 1657
1585 size = grxstsr & S3C_GRXSTS_ByteCnt_MASK; 1658 size = grxstsr & GRXSTS_ByteCnt_MASK;
1586 size >>= S3C_GRXSTS_ByteCnt_SHIFT; 1659 size >>= GRXSTS_ByteCnt_SHIFT;
1587 1660
1588 if (1) 1661 if (1)
1589 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", 1662 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1590 __func__, grxstsr, size, epnum); 1663 __func__, grxstsr, size, epnum);
1591 1664
1592#define __status(x) ((x) >> S3C_GRXSTS_PktSts_SHIFT) 1665#define __status(x) ((x) >> GRXSTS_PktSts_SHIFT)
1593 1666
1594 switch (status >> S3C_GRXSTS_PktSts_SHIFT) { 1667 switch (status >> GRXSTS_PktSts_SHIFT) {
1595 case __status(S3C_GRXSTS_PktSts_GlobalOutNAK): 1668 case __status(GRXSTS_PktSts_GlobalOutNAK):
1596 dev_dbg(hsotg->dev, "GlobalOutNAK\n"); 1669 dev_dbg(hsotg->dev, "GlobalOutNAK\n");
1597 break; 1670 break;
1598 1671
1599 case __status(S3C_GRXSTS_PktSts_OutDone): 1672 case __status(GRXSTS_PktSts_OutDone):
1600 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", 1673 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1601 s3c_hsotg_read_frameno(hsotg)); 1674 s3c_hsotg_read_frameno(hsotg));
1602 1675
@@ -1604,24 +1677,24 @@ static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1604 s3c_hsotg_handle_outdone(hsotg, epnum, false); 1677 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1605 break; 1678 break;
1606 1679
1607 case __status(S3C_GRXSTS_PktSts_SetupDone): 1680 case __status(GRXSTS_PktSts_SetupDone):
1608 dev_dbg(hsotg->dev, 1681 dev_dbg(hsotg->dev,
1609 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", 1682 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1610 s3c_hsotg_read_frameno(hsotg), 1683 s3c_hsotg_read_frameno(hsotg),
1611 readl(hsotg->regs + S3C_DOEPCTL(0))); 1684 readl(hsotg->regs + DOEPCTL(0)));
1612 1685
1613 s3c_hsotg_handle_outdone(hsotg, epnum, true); 1686 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1614 break; 1687 break;
1615 1688
1616 case __status(S3C_GRXSTS_PktSts_OutRX): 1689 case __status(GRXSTS_PktSts_OutRX):
1617 s3c_hsotg_rx_data(hsotg, epnum, size); 1690 s3c_hsotg_rx_data(hsotg, epnum, size);
1618 break; 1691 break;
1619 1692
1620 case __status(S3C_GRXSTS_PktSts_SetupRX): 1693 case __status(GRXSTS_PktSts_SetupRX):
1621 dev_dbg(hsotg->dev, 1694 dev_dbg(hsotg->dev,
1622 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", 1695 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1623 s3c_hsotg_read_frameno(hsotg), 1696 s3c_hsotg_read_frameno(hsotg),
1624 readl(hsotg->regs + S3C_DOEPCTL(0))); 1697 readl(hsotg->regs + DOEPCTL(0)));
1625 1698
1626 s3c_hsotg_rx_data(hsotg, epnum, size); 1699 s3c_hsotg_rx_data(hsotg, epnum, size);
1627 break; 1700 break;
@@ -1638,18 +1711,18 @@ static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1638/** 1711/**
1639 * s3c_hsotg_ep0_mps - turn max packet size into register setting 1712 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1640 * @mps: The maximum packet size in bytes. 1713 * @mps: The maximum packet size in bytes.
1641*/ 1714 */
1642static u32 s3c_hsotg_ep0_mps(unsigned int mps) 1715static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1643{ 1716{
1644 switch (mps) { 1717 switch (mps) {
1645 case 64: 1718 case 64:
1646 return S3C_D0EPCTL_MPS_64; 1719 return D0EPCTL_MPS_64;
1647 case 32: 1720 case 32:
1648 return S3C_D0EPCTL_MPS_32; 1721 return D0EPCTL_MPS_32;
1649 case 16: 1722 case 16:
1650 return S3C_D0EPCTL_MPS_16; 1723 return D0EPCTL_MPS_16;
1651 case 8: 1724 case 8:
1652 return S3C_D0EPCTL_MPS_8; 1725 return D0EPCTL_MPS_8;
1653 } 1726 }
1654 1727
1655 /* bad max packet size, warn and return invalid result */ 1728 /* bad max packet size, warn and return invalid result */
@@ -1680,7 +1753,7 @@ static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1680 if (mpsval > 3) 1753 if (mpsval > 3)
1681 goto bad_mps; 1754 goto bad_mps;
1682 } else { 1755 } else {
1683 if (mps >= S3C_DxEPCTL_MPS_LIMIT+1) 1756 if (mps >= DxEPCTL_MPS_LIMIT+1)
1684 goto bad_mps; 1757 goto bad_mps;
1685 1758
1686 mpsval = mps; 1759 mpsval = mps;
@@ -1688,18 +1761,22 @@ static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1688 1761
1689 hs_ep->ep.maxpacket = mps; 1762 hs_ep->ep.maxpacket = mps;
1690 1763
1691 /* update both the in and out endpoint controldir_ registers, even 1764 /*
1692 * if one of the directions may not be in use. */ 1765 * update both the in and out endpoint controldir_ registers, even
1766 * if one of the directions may not be in use.
1767 */
1693 1768
1694 reg = readl(regs + S3C_DIEPCTL(ep)); 1769 reg = readl(regs + DIEPCTL(ep));
1695 reg &= ~S3C_DxEPCTL_MPS_MASK; 1770 reg &= ~DxEPCTL_MPS_MASK;
1696 reg |= mpsval; 1771 reg |= mpsval;
1697 writel(reg, regs + S3C_DIEPCTL(ep)); 1772 writel(reg, regs + DIEPCTL(ep));
1698 1773
1699 reg = readl(regs + S3C_DOEPCTL(ep)); 1774 if (ep) {
1700 reg &= ~S3C_DxEPCTL_MPS_MASK; 1775 reg = readl(regs + DOEPCTL(ep));
1701 reg |= mpsval; 1776 reg &= ~DxEPCTL_MPS_MASK;
1702 writel(reg, regs + S3C_DOEPCTL(ep)); 1777 reg |= mpsval;
1778 writel(reg, regs + DOEPCTL(ep));
1779 }
1703 1780
1704 return; 1781 return;
1705 1782
@@ -1717,16 +1794,16 @@ static void s3c_hsotg_txfifo_flush(struct s3c_hsotg *hsotg, unsigned int idx)
1717 int timeout; 1794 int timeout;
1718 int val; 1795 int val;
1719 1796
1720 writel(S3C_GRSTCTL_TxFNum(idx) | S3C_GRSTCTL_TxFFlsh, 1797 writel(GRSTCTL_TxFNum(idx) | GRSTCTL_TxFFlsh,
1721 hsotg->regs + S3C_GRSTCTL); 1798 hsotg->regs + GRSTCTL);
1722 1799
1723 /* wait until the fifo is flushed */ 1800 /* wait until the fifo is flushed */
1724 timeout = 100; 1801 timeout = 100;
1725 1802
1726 while (1) { 1803 while (1) {
1727 val = readl(hsotg->regs + S3C_GRSTCTL); 1804 val = readl(hsotg->regs + GRSTCTL);
1728 1805
1729 if ((val & (S3C_GRSTCTL_TxFFlsh)) == 0) 1806 if ((val & (GRSTCTL_TxFFlsh)) == 0)
1730 break; 1807 break;
1731 1808
1732 if (--timeout == 0) { 1809 if (--timeout == 0) {
@@ -1776,7 +1853,7 @@ static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1776 struct s3c_hsotg_ep *hs_ep) 1853 struct s3c_hsotg_ep *hs_ep)
1777{ 1854{
1778 struct s3c_hsotg_req *hs_req = hs_ep->req; 1855 struct s3c_hsotg_req *hs_req = hs_ep->req;
1779 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index)); 1856 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1780 int size_left, size_done; 1857 int size_left, size_done;
1781 1858
1782 if (!hs_req) { 1859 if (!hs_req) {
@@ -1784,7 +1861,15 @@ static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1784 return; 1861 return;
1785 } 1862 }
1786 1863
1787 /* Calculate the size of the transfer by checking how much is left 1864 /* Finish ZLP handling for IN EP0 transactions */
1865 if (hsotg->eps[0].sent_zlp) {
1866 dev_dbg(hsotg->dev, "zlp packet received\n");
1867 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, 0);
1868 return;
1869 }
1870
1871 /*
1872 * Calculate the size of the transfer by checking how much is left
1788 * in the endpoint size register and then working it out from 1873 * in the endpoint size register and then working it out from
1789 * the amount we loaded for the transfer. 1874 * the amount we loaded for the transfer.
1790 * 1875 *
@@ -1793,7 +1878,7 @@ static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1793 * aligned). 1878 * aligned).
1794 */ 1879 */
1795 1880
1796 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize); 1881 size_left = DxEPTSIZ_XferSize_GET(epsize);
1797 1882
1798 size_done = hs_ep->size_loaded - size_left; 1883 size_done = hs_ep->size_loaded - size_left;
1799 size_done += hs_ep->last_load; 1884 size_done += hs_ep->last_load;
@@ -1803,9 +1888,28 @@ static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1803 __func__, hs_req->req.actual, size_done); 1888 __func__, hs_req->req.actual, size_done);
1804 1889
1805 hs_req->req.actual = size_done; 1890 hs_req->req.actual = size_done;
1891 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
1892 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
1893
1894 /*
1895 * Check if dealing with Maximum Packet Size(MPS) IN transfer at EP0
1896 * When sent data is a multiple MPS size (e.g. 64B ,128B ,192B
1897 * ,256B ... ), after last MPS sized packet send IN ZLP packet to
1898 * inform the host that no more data is available.
1899 * The state of req.zero member is checked to be sure that the value to
1900 * send is smaller than wValue expected from host.
1901 * Check req.length to NOT send another ZLP when the current one is
1902 * under completion (the one for which this completion has been called).
1903 */
1904 if (hs_req->req.length && hs_ep->index == 0 && hs_req->req.zero &&
1905 hs_req->req.length == hs_req->req.actual &&
1906 !(hs_req->req.length % hs_ep->ep.maxpacket)) {
1907
1908 dev_dbg(hsotg->dev, "ep0 zlp IN packet sent\n");
1909 s3c_hsotg_send_zlp(hsotg, hs_req);
1806 1910
1807 /* if we did all of the transfer, and there is more data left 1911 return;
1808 * around, then try restarting the rest of the request */ 1912 }
1809 1913
1810 if (!size_left && hs_req->req.actual < hs_req->req.length) { 1914 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1811 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__); 1915 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
@@ -1821,14 +1925,14 @@ static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1821 * @dir_in: Set if this is an IN endpoint 1925 * @dir_in: Set if this is an IN endpoint
1822 * 1926 *
1823 * Process and clear any interrupt pending for an individual endpoint 1927 * Process and clear any interrupt pending for an individual endpoint
1824*/ 1928 */
1825static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx, 1929static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1826 int dir_in) 1930 int dir_in)
1827{ 1931{
1828 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx]; 1932 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
1829 u32 epint_reg = dir_in ? S3C_DIEPINT(idx) : S3C_DOEPINT(idx); 1933 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
1830 u32 epctl_reg = dir_in ? S3C_DIEPCTL(idx) : S3C_DOEPCTL(idx); 1934 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
1831 u32 epsiz_reg = dir_in ? S3C_DIEPTSIZ(idx) : S3C_DOEPTSIZ(idx); 1935 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
1832 u32 ints; 1936 u32 ints;
1833 1937
1834 ints = readl(hsotg->regs + epint_reg); 1938 ints = readl(hsotg->regs + epint_reg);
@@ -1839,28 +1943,32 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1839 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", 1943 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1840 __func__, idx, dir_in ? "in" : "out", ints); 1944 __func__, idx, dir_in ? "in" : "out", ints);
1841 1945
1842 if (ints & S3C_DxEPINT_XferCompl) { 1946 if (ints & DxEPINT_XferCompl) {
1843 dev_dbg(hsotg->dev, 1947 dev_dbg(hsotg->dev,
1844 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n", 1948 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1845 __func__, readl(hsotg->regs + epctl_reg), 1949 __func__, readl(hsotg->regs + epctl_reg),
1846 readl(hsotg->regs + epsiz_reg)); 1950 readl(hsotg->regs + epsiz_reg));
1847 1951
1848 /* we get OutDone from the FIFO, so we only need to look 1952 /*
1849 * at completing IN requests here */ 1953 * we get OutDone from the FIFO, so we only need to look
1954 * at completing IN requests here
1955 */
1850 if (dir_in) { 1956 if (dir_in) {
1851 s3c_hsotg_complete_in(hsotg, hs_ep); 1957 s3c_hsotg_complete_in(hsotg, hs_ep);
1852 1958
1853 if (idx == 0 && !hs_ep->req) 1959 if (idx == 0 && !hs_ep->req)
1854 s3c_hsotg_enqueue_setup(hsotg); 1960 s3c_hsotg_enqueue_setup(hsotg);
1855 } else if (using_dma(hsotg)) { 1961 } else if (using_dma(hsotg)) {
1856 /* We're using DMA, we need to fire an OutDone here 1962 /*
1857 * as we ignore the RXFIFO. */ 1963 * We're using DMA, we need to fire an OutDone here
1964 * as we ignore the RXFIFO.
1965 */
1858 1966
1859 s3c_hsotg_handle_outdone(hsotg, idx, false); 1967 s3c_hsotg_handle_outdone(hsotg, idx, false);
1860 } 1968 }
1861 } 1969 }
1862 1970
1863 if (ints & S3C_DxEPINT_EPDisbld) { 1971 if (ints & DxEPINT_EPDisbld) {
1864 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); 1972 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1865 1973
1866 if (dir_in) { 1974 if (dir_in) {
@@ -1868,27 +1976,29 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1868 1976
1869 s3c_hsotg_txfifo_flush(hsotg, idx); 1977 s3c_hsotg_txfifo_flush(hsotg, idx);
1870 1978
1871 if ((epctl & S3C_DxEPCTL_Stall) && 1979 if ((epctl & DxEPCTL_Stall) &&
1872 (epctl & S3C_DxEPCTL_EPType_Bulk)) { 1980 (epctl & DxEPCTL_EPType_Bulk)) {
1873 int dctl = readl(hsotg->regs + S3C_DCTL); 1981 int dctl = readl(hsotg->regs + DCTL);
1874 1982
1875 dctl |= S3C_DCTL_CGNPInNAK; 1983 dctl |= DCTL_CGNPInNAK;
1876 writel(dctl, hsotg->regs + S3C_DCTL); 1984 writel(dctl, hsotg->regs + DCTL);
1877 } 1985 }
1878 } 1986 }
1879 } 1987 }
1880 1988
1881 if (ints & S3C_DxEPINT_AHBErr) 1989 if (ints & DxEPINT_AHBErr)
1882 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); 1990 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
1883 1991
1884 if (ints & S3C_DxEPINT_Setup) { /* Setup or Timeout */ 1992 if (ints & DxEPINT_Setup) { /* Setup or Timeout */
1885 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); 1993 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
1886 1994
1887 if (using_dma(hsotg) && idx == 0) { 1995 if (using_dma(hsotg) && idx == 0) {
1888 /* this is the notification we've received a 1996 /*
1997 * this is the notification we've received a
1889 * setup packet. In non-DMA mode we'd get this 1998 * setup packet. In non-DMA mode we'd get this
1890 * from the RXFIFO, instead we need to process 1999 * from the RXFIFO, instead we need to process
1891 * the setup here. */ 2000 * the setup here.
2001 */
1892 2002
1893 if (dir_in) 2003 if (dir_in)
1894 WARN_ON_ONCE(1); 2004 WARN_ON_ONCE(1);
@@ -1897,29 +2007,29 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1897 } 2007 }
1898 } 2008 }
1899 2009
1900 if (ints & S3C_DxEPINT_Back2BackSetup) 2010 if (ints & DxEPINT_Back2BackSetup)
1901 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); 2011 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
1902 2012
1903 if (dir_in) { 2013 if (dir_in) {
1904 /* not sure if this is important, but we'll clear it anyway 2014 /* not sure if this is important, but we'll clear it anyway */
1905 */ 2015 if (ints & DIEPMSK_INTknTXFEmpMsk) {
1906 if (ints & S3C_DIEPMSK_INTknTXFEmpMsk) {
1907 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", 2016 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
1908 __func__, idx); 2017 __func__, idx);
1909 } 2018 }
1910 2019
1911 /* this probably means something bad is happening */ 2020 /* this probably means something bad is happening */
1912 if (ints & S3C_DIEPMSK_INTknEPMisMsk) { 2021 if (ints & DIEPMSK_INTknEPMisMsk) {
1913 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", 2022 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
1914 __func__, idx); 2023 __func__, idx);
1915 } 2024 }
1916 2025
1917 /* FIFO has space or is empty (see GAHBCFG) */ 2026 /* FIFO has space or is empty (see GAHBCFG) */
1918 if (hsotg->dedicated_fifos && 2027 if (hsotg->dedicated_fifos &&
1919 ints & S3C_DIEPMSK_TxFIFOEmpty) { 2028 ints & DIEPMSK_TxFIFOEmpty) {
1920 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", 2029 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
1921 __func__, idx); 2030 __func__, idx);
1922 s3c_hsotg_trytx(hsotg, hs_ep); 2031 if (!using_dma(hsotg))
2032 s3c_hsotg_trytx(hsotg, hs_ep);
1923 } 2033 }
1924 } 2034 }
1925} 2035}
@@ -1930,40 +2040,45 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1930 * 2040 *
1931 * Handle updating the device settings after the enumeration phase has 2041 * Handle updating the device settings after the enumeration phase has
1932 * been completed. 2042 * been completed.
1933*/ 2043 */
1934static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg) 2044static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
1935{ 2045{
1936 u32 dsts = readl(hsotg->regs + S3C_DSTS); 2046 u32 dsts = readl(hsotg->regs + DSTS);
1937 int ep0_mps = 0, ep_mps; 2047 int ep0_mps = 0, ep_mps;
1938 2048
1939 /* This should signal the finish of the enumeration phase 2049 /*
2050 * This should signal the finish of the enumeration phase
1940 * of the USB handshaking, so we should now know what rate 2051 * of the USB handshaking, so we should now know what rate
1941 * we connected at. */ 2052 * we connected at.
2053 */
1942 2054
1943 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts); 2055 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
1944 2056
1945 /* note, since we're limited by the size of transfer on EP0, and 2057 /*
2058 * note, since we're limited by the size of transfer on EP0, and
1946 * it seems IN transfers must be a even number of packets we do 2059 * it seems IN transfers must be a even number of packets we do
1947 * not advertise a 64byte MPS on EP0. */ 2060 * not advertise a 64byte MPS on EP0.
2061 */
1948 2062
1949 /* catch both EnumSpd_FS and EnumSpd_FS48 */ 2063 /* catch both EnumSpd_FS and EnumSpd_FS48 */
1950 switch (dsts & S3C_DSTS_EnumSpd_MASK) { 2064 switch (dsts & DSTS_EnumSpd_MASK) {
1951 case S3C_DSTS_EnumSpd_FS: 2065 case DSTS_EnumSpd_FS:
1952 case S3C_DSTS_EnumSpd_FS48: 2066 case DSTS_EnumSpd_FS48:
1953 hsotg->gadget.speed = USB_SPEED_FULL; 2067 hsotg->gadget.speed = USB_SPEED_FULL;
1954 ep0_mps = EP0_MPS_LIMIT; 2068 ep0_mps = EP0_MPS_LIMIT;
1955 ep_mps = 64; 2069 ep_mps = 64;
1956 break; 2070 break;
1957 2071
1958 case S3C_DSTS_EnumSpd_HS: 2072 case DSTS_EnumSpd_HS:
1959 hsotg->gadget.speed = USB_SPEED_HIGH; 2073 hsotg->gadget.speed = USB_SPEED_HIGH;
1960 ep0_mps = EP0_MPS_LIMIT; 2074 ep0_mps = EP0_MPS_LIMIT;
1961 ep_mps = 512; 2075 ep_mps = 512;
1962 break; 2076 break;
1963 2077
1964 case S3C_DSTS_EnumSpd_LS: 2078 case DSTS_EnumSpd_LS:
1965 hsotg->gadget.speed = USB_SPEED_LOW; 2079 hsotg->gadget.speed = USB_SPEED_LOW;
1966 /* note, we don't actually support LS in this driver at the 2080 /*
2081 * note, we don't actually support LS in this driver at the
1967 * moment, and the documentation seems to imply that it isn't 2082 * moment, and the documentation seems to imply that it isn't
1968 * supported by the PHYs on some of the devices. 2083 * supported by the PHYs on some of the devices.
1969 */ 2084 */
@@ -1972,13 +2087,15 @@ static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
1972 dev_info(hsotg->dev, "new device is %s\n", 2087 dev_info(hsotg->dev, "new device is %s\n",
1973 usb_speed_string(hsotg->gadget.speed)); 2088 usb_speed_string(hsotg->gadget.speed));
1974 2089
1975 /* we should now know the maximum packet size for an 2090 /*
1976 * endpoint, so set the endpoints to a default value. */ 2091 * we should now know the maximum packet size for an
2092 * endpoint, so set the endpoints to a default value.
2093 */
1977 2094
1978 if (ep0_mps) { 2095 if (ep0_mps) {
1979 int i; 2096 int i;
1980 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps); 2097 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
1981 for (i = 1; i < S3C_HSOTG_EPS; i++) 2098 for (i = 1; i < hsotg->num_of_eps; i++)
1982 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps); 2099 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
1983 } 2100 }
1984 2101
@@ -1987,8 +2104,8 @@ static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
1987 s3c_hsotg_enqueue_setup(hsotg); 2104 s3c_hsotg_enqueue_setup(hsotg);
1988 2105
1989 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", 2106 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1990 readl(hsotg->regs + S3C_DIEPCTL0), 2107 readl(hsotg->regs + DIEPCTL0),
1991 readl(hsotg->regs + S3C_DOEPCTL0)); 2108 readl(hsotg->regs + DOEPCTL0));
1992} 2109}
1993 2110
1994/** 2111/**
@@ -2011,8 +2128,10 @@ static void kill_all_requests(struct s3c_hsotg *hsotg,
2011 spin_lock_irqsave(&ep->lock, flags); 2128 spin_lock_irqsave(&ep->lock, flags);
2012 2129
2013 list_for_each_entry_safe(req, treq, &ep->queue, queue) { 2130 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2014 /* currently, we can't do much about an already 2131 /*
2015 * running request on an in endpoint */ 2132 * currently, we can't do much about an already
2133 * running request on an in endpoint
2134 */
2016 2135
2017 if (ep->req == req && ep->dir_in && !force) 2136 if (ep->req == req && ep->dir_in && !force)
2018 continue; 2137 continue;
@@ -2030,18 +2149,18 @@ static void kill_all_requests(struct s3c_hsotg *hsotg,
2030 (_hs)->driver->_entry(&(_hs)->gadget); 2149 (_hs)->driver->_entry(&(_hs)->gadget);
2031 2150
2032/** 2151/**
2033 * s3c_hsotg_disconnect_irq - disconnect irq service 2152 * s3c_hsotg_disconnect - disconnect service
2034 * @hsotg: The device state. 2153 * @hsotg: The device state.
2035 * 2154 *
2036 * A disconnect IRQ has been received, meaning that the host has 2155 * The device has been disconnected. Remove all current
2037 * lost contact with the bus. Remove all current transactions 2156 * transactions and signal the gadget driver that this
2038 * and signal the gadget driver that this has happened. 2157 * has happened.
2039*/ 2158 */
2040static void s3c_hsotg_disconnect_irq(struct s3c_hsotg *hsotg) 2159static void s3c_hsotg_disconnect(struct s3c_hsotg *hsotg)
2041{ 2160{
2042 unsigned ep; 2161 unsigned ep;
2043 2162
2044 for (ep = 0; ep < S3C_HSOTG_EPS; ep++) 2163 for (ep = 0; ep < hsotg->num_of_eps; ep++)
2045 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true); 2164 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
2046 2165
2047 call_gadget(hsotg, disconnect); 2166 call_gadget(hsotg, disconnect);
@@ -2059,7 +2178,7 @@ static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
2059 2178
2060 /* look through for any more data to transmit */ 2179 /* look through for any more data to transmit */
2061 2180
2062 for (epno = 0; epno < S3C_HSOTG_EPS; epno++) { 2181 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
2063 ep = &hsotg->eps[epno]; 2182 ep = &hsotg->eps[epno];
2064 2183
2065 if (!ep->dir_in) 2184 if (!ep->dir_in)
@@ -2075,12 +2194,187 @@ static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
2075 } 2194 }
2076} 2195}
2077 2196
2078static struct s3c_hsotg *our_hsotg;
2079
2080/* IRQ flags which will trigger a retry around the IRQ loop */ 2197/* IRQ flags which will trigger a retry around the IRQ loop */
2081#define IRQ_RETRY_MASK (S3C_GINTSTS_NPTxFEmp | \ 2198#define IRQ_RETRY_MASK (GINTSTS_NPTxFEmp | \
2082 S3C_GINTSTS_PTxFEmp | \ 2199 GINTSTS_PTxFEmp | \
2083 S3C_GINTSTS_RxFLvl) 2200 GINTSTS_RxFLvl)
2201
2202/**
2203 * s3c_hsotg_corereset - issue softreset to the core
2204 * @hsotg: The device state
2205 *
2206 * Issue a soft reset to the core, and await the core finishing it.
2207 */
2208static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2209{
2210 int timeout;
2211 u32 grstctl;
2212
2213 dev_dbg(hsotg->dev, "resetting core\n");
2214
2215 /* issue soft reset */
2216 writel(GRSTCTL_CSftRst, hsotg->regs + GRSTCTL);
2217
2218 timeout = 1000;
2219 do {
2220 grstctl = readl(hsotg->regs + GRSTCTL);
2221 } while ((grstctl & GRSTCTL_CSftRst) && timeout-- > 0);
2222
2223 if (grstctl & GRSTCTL_CSftRst) {
2224 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2225 return -EINVAL;
2226 }
2227
2228 timeout = 1000;
2229
2230 while (1) {
2231 u32 grstctl = readl(hsotg->regs + GRSTCTL);
2232
2233 if (timeout-- < 0) {
2234 dev_info(hsotg->dev,
2235 "%s: reset failed, GRSTCTL=%08x\n",
2236 __func__, grstctl);
2237 return -ETIMEDOUT;
2238 }
2239
2240 if (!(grstctl & GRSTCTL_AHBIdle))
2241 continue;
2242
2243 break; /* reset done */
2244 }
2245
2246 dev_dbg(hsotg->dev, "reset successful\n");
2247 return 0;
2248}
2249
2250/**
2251 * s3c_hsotg_core_init - issue softreset to the core
2252 * @hsotg: The device state
2253 *
2254 * Issue a soft reset to the core, and await the core finishing it.
2255 */
2256static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
2257{
2258 s3c_hsotg_corereset(hsotg);
2259
2260 /*
2261 * we must now enable ep0 ready for host detection and then
2262 * set configuration.
2263 */
2264
2265 /* set the PLL on, remove the HNP/SRP and set the PHY */
2266 writel(GUSBCFG_PHYIf16 | GUSBCFG_TOutCal(7) |
2267 (0x5 << 10), hsotg->regs + GUSBCFG);
2268
2269 s3c_hsotg_init_fifo(hsotg);
2270
2271 __orr32(hsotg->regs + DCTL, DCTL_SftDiscon);
2272
2273 writel(1 << 18 | DCFG_DevSpd_HS, hsotg->regs + DCFG);
2274
2275 /* Clear any pending OTG interrupts */
2276 writel(0xffffffff, hsotg->regs + GOTGINT);
2277
2278 /* Clear any pending interrupts */
2279 writel(0xffffffff, hsotg->regs + GINTSTS);
2280
2281 writel(GINTSTS_ErlySusp | GINTSTS_SessReqInt |
2282 GINTSTS_GOUTNakEff | GINTSTS_GINNakEff |
2283 GINTSTS_ConIDStsChng | GINTSTS_USBRst |
2284 GINTSTS_EnumDone | GINTSTS_OTGInt |
2285 GINTSTS_USBSusp | GINTSTS_WkUpInt,
2286 hsotg->regs + GINTMSK);
2287
2288 if (using_dma(hsotg))
2289 writel(GAHBCFG_GlblIntrEn | GAHBCFG_DMAEn |
2290 GAHBCFG_HBstLen_Incr4,
2291 hsotg->regs + GAHBCFG);
2292 else
2293 writel(GAHBCFG_GlblIntrEn, hsotg->regs + GAHBCFG);
2294
2295 /*
2296 * Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2297 * up being flooded with interrupts if the host is polling the
2298 * endpoint to try and read data.
2299 */
2300
2301 writel(((hsotg->dedicated_fifos) ? DIEPMSK_TxFIFOEmpty : 0) |
2302 DIEPMSK_EPDisbldMsk | DIEPMSK_XferComplMsk |
2303 DIEPMSK_TimeOUTMsk | DIEPMSK_AHBErrMsk |
2304 DIEPMSK_INTknEPMisMsk,
2305 hsotg->regs + DIEPMSK);
2306
2307 /*
2308 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2309 * DMA mode we may need this.
2310 */
2311 writel((using_dma(hsotg) ? (DIEPMSK_XferComplMsk |
2312 DIEPMSK_TimeOUTMsk) : 0) |
2313 DOEPMSK_EPDisbldMsk | DOEPMSK_AHBErrMsk |
2314 DOEPMSK_SetupMsk,
2315 hsotg->regs + DOEPMSK);
2316
2317 writel(0, hsotg->regs + DAINTMSK);
2318
2319 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2320 readl(hsotg->regs + DIEPCTL0),
2321 readl(hsotg->regs + DOEPCTL0));
2322
2323 /* enable in and out endpoint interrupts */
2324 s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPInt | GINTSTS_IEPInt);
2325
2326 /*
2327 * Enable the RXFIFO when in slave mode, as this is how we collect
2328 * the data. In DMA mode, we get events from the FIFO but also
2329 * things we cannot process, so do not use it.
2330 */
2331 if (!using_dma(hsotg))
2332 s3c_hsotg_en_gsint(hsotg, GINTSTS_RxFLvl);
2333
2334 /* Enable interrupts for EP0 in and out */
2335 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2336 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2337
2338 __orr32(hsotg->regs + DCTL, DCTL_PWROnPrgDone);
2339 udelay(10); /* see openiboot */
2340 __bic32(hsotg->regs + DCTL, DCTL_PWROnPrgDone);
2341
2342 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL));
2343
2344 /*
2345 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2346 * writing to the EPCTL register..
2347 */
2348
2349 /* set to read 1 8byte packet */
2350 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
2351 DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
2352
2353 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2354 DxEPCTL_CNAK | DxEPCTL_EPEna |
2355 DxEPCTL_USBActEp,
2356 hsotg->regs + DOEPCTL0);
2357
2358 /* enable, but don't activate EP0in */
2359 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2360 DxEPCTL_USBActEp, hsotg->regs + DIEPCTL0);
2361
2362 s3c_hsotg_enqueue_setup(hsotg);
2363
2364 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2365 readl(hsotg->regs + DIEPCTL0),
2366 readl(hsotg->regs + DOEPCTL0));
2367
2368 /* clear global NAKs */
2369 writel(DCTL_CGOUTNak | DCTL_CGNPInNAK,
2370 hsotg->regs + DCTL);
2371
2372 /* must be at-least 3ms to allow bus to see disconnect */
2373 mdelay(3);
2374
2375 /* remove the soft-disconnect and let's go */
2376 __bic32(hsotg->regs + DCTL, DCTL_SftDiscon);
2377}
2084 2378
2085/** 2379/**
2086 * s3c_hsotg_irq - handle device interrupt 2380 * s3c_hsotg_irq - handle device interrupt
@@ -2095,52 +2389,45 @@ static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
2095 u32 gintmsk; 2389 u32 gintmsk;
2096 2390
2097irq_retry: 2391irq_retry:
2098 gintsts = readl(hsotg->regs + S3C_GINTSTS); 2392 gintsts = readl(hsotg->regs + GINTSTS);
2099 gintmsk = readl(hsotg->regs + S3C_GINTMSK); 2393 gintmsk = readl(hsotg->regs + GINTMSK);
2100 2394
2101 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", 2395 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2102 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); 2396 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2103 2397
2104 gintsts &= gintmsk; 2398 gintsts &= gintmsk;
2105 2399
2106 if (gintsts & S3C_GINTSTS_OTGInt) { 2400 if (gintsts & GINTSTS_OTGInt) {
2107 u32 otgint = readl(hsotg->regs + S3C_GOTGINT); 2401 u32 otgint = readl(hsotg->regs + GOTGINT);
2108 2402
2109 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint); 2403 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
2110 2404
2111 writel(otgint, hsotg->regs + S3C_GOTGINT); 2405 writel(otgint, hsotg->regs + GOTGINT);
2112 } 2406 }
2113 2407
2114 if (gintsts & S3C_GINTSTS_DisconnInt) { 2408 if (gintsts & GINTSTS_SessReqInt) {
2115 dev_dbg(hsotg->dev, "%s: DisconnInt\n", __func__);
2116 writel(S3C_GINTSTS_DisconnInt, hsotg->regs + S3C_GINTSTS);
2117
2118 s3c_hsotg_disconnect_irq(hsotg);
2119 }
2120
2121 if (gintsts & S3C_GINTSTS_SessReqInt) {
2122 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__); 2409 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
2123 writel(S3C_GINTSTS_SessReqInt, hsotg->regs + S3C_GINTSTS); 2410 writel(GINTSTS_SessReqInt, hsotg->regs + GINTSTS);
2124 } 2411 }
2125 2412
2126 if (gintsts & S3C_GINTSTS_EnumDone) { 2413 if (gintsts & GINTSTS_EnumDone) {
2127 writel(S3C_GINTSTS_EnumDone, hsotg->regs + S3C_GINTSTS); 2414 writel(GINTSTS_EnumDone, hsotg->regs + GINTSTS);
2128 2415
2129 s3c_hsotg_irq_enumdone(hsotg); 2416 s3c_hsotg_irq_enumdone(hsotg);
2130 } 2417 }
2131 2418
2132 if (gintsts & S3C_GINTSTS_ConIDStsChng) { 2419 if (gintsts & GINTSTS_ConIDStsChng) {
2133 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n", 2420 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2134 readl(hsotg->regs + S3C_DSTS), 2421 readl(hsotg->regs + DSTS),
2135 readl(hsotg->regs + S3C_GOTGCTL)); 2422 readl(hsotg->regs + GOTGCTL));
2136 2423
2137 writel(S3C_GINTSTS_ConIDStsChng, hsotg->regs + S3C_GINTSTS); 2424 writel(GINTSTS_ConIDStsChng, hsotg->regs + GINTSTS);
2138 } 2425 }
2139 2426
2140 if (gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt)) { 2427 if (gintsts & (GINTSTS_OEPInt | GINTSTS_IEPInt)) {
2141 u32 daint = readl(hsotg->regs + S3C_DAINT); 2428 u32 daint = readl(hsotg->regs + DAINT);
2142 u32 daint_out = daint >> S3C_DAINT_OutEP_SHIFT; 2429 u32 daint_out = daint >> DAINT_OutEP_SHIFT;
2143 u32 daint_in = daint & ~(daint_out << S3C_DAINT_OutEP_SHIFT); 2430 u32 daint_in = daint & ~(daint_out << DAINT_OutEP_SHIFT);
2144 int ep; 2431 int ep;
2145 2432
2146 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); 2433 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
@@ -2156,102 +2443,116 @@ irq_retry:
2156 } 2443 }
2157 } 2444 }
2158 2445
2159 if (gintsts & S3C_GINTSTS_USBRst) { 2446 if (gintsts & GINTSTS_USBRst) {
2447
2448 u32 usb_status = readl(hsotg->regs + GOTGCTL);
2449
2160 dev_info(hsotg->dev, "%s: USBRst\n", __func__); 2450 dev_info(hsotg->dev, "%s: USBRst\n", __func__);
2161 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", 2451 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2162 readl(hsotg->regs + S3C_GNPTXSTS)); 2452 readl(hsotg->regs + GNPTXSTS));
2163
2164 writel(S3C_GINTSTS_USBRst, hsotg->regs + S3C_GINTSTS);
2165 2453
2166 kill_all_requests(hsotg, &hsotg->eps[0], -ECONNRESET, true); 2454 writel(GINTSTS_USBRst, hsotg->regs + GINTSTS);
2167 2455
2168 /* it seems after a reset we can end up with a situation 2456 if (usb_status & GOTGCTL_BSESVLD) {
2169 * where the TXFIFO still has data in it... the docs 2457 if (time_after(jiffies, hsotg->last_rst +
2170 * suggest resetting all the fifos, so use the init_fifo 2458 msecs_to_jiffies(200))) {
2171 * code to relayout and flush the fifos.
2172 */
2173 2459
2174 s3c_hsotg_init_fifo(hsotg); 2460 kill_all_requests(hsotg, &hsotg->eps[0],
2461 -ECONNRESET, true);
2175 2462
2176 s3c_hsotg_enqueue_setup(hsotg); 2463 s3c_hsotg_core_init(hsotg);
2464 hsotg->last_rst = jiffies;
2465 }
2466 }
2177 } 2467 }
2178 2468
2179 /* check both FIFOs */ 2469 /* check both FIFOs */
2180 2470
2181 if (gintsts & S3C_GINTSTS_NPTxFEmp) { 2471 if (gintsts & GINTSTS_NPTxFEmp) {
2182 dev_dbg(hsotg->dev, "NPTxFEmp\n"); 2472 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2183 2473
2184 /* Disable the interrupt to stop it happening again 2474 /*
2475 * Disable the interrupt to stop it happening again
2185 * unless one of these endpoint routines decides that 2476 * unless one of these endpoint routines decides that
2186 * it needs re-enabling */ 2477 * it needs re-enabling
2478 */
2187 2479
2188 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_NPTxFEmp); 2480 s3c_hsotg_disable_gsint(hsotg, GINTSTS_NPTxFEmp);
2189 s3c_hsotg_irq_fifoempty(hsotg, false); 2481 s3c_hsotg_irq_fifoempty(hsotg, false);
2190 } 2482 }
2191 2483
2192 if (gintsts & S3C_GINTSTS_PTxFEmp) { 2484 if (gintsts & GINTSTS_PTxFEmp) {
2193 dev_dbg(hsotg->dev, "PTxFEmp\n"); 2485 dev_dbg(hsotg->dev, "PTxFEmp\n");
2194 2486
2195 /* See note in S3C_GINTSTS_NPTxFEmp */ 2487 /* See note in GINTSTS_NPTxFEmp */
2196 2488
2197 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_PTxFEmp); 2489 s3c_hsotg_disable_gsint(hsotg, GINTSTS_PTxFEmp);
2198 s3c_hsotg_irq_fifoempty(hsotg, true); 2490 s3c_hsotg_irq_fifoempty(hsotg, true);
2199 } 2491 }
2200 2492
2201 if (gintsts & S3C_GINTSTS_RxFLvl) { 2493 if (gintsts & GINTSTS_RxFLvl) {
2202 /* note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, 2494 /*
2495 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2203 * we need to retry s3c_hsotg_handle_rx if this is still 2496 * we need to retry s3c_hsotg_handle_rx if this is still
2204 * set. */ 2497 * set.
2498 */
2205 2499
2206 s3c_hsotg_handle_rx(hsotg); 2500 s3c_hsotg_handle_rx(hsotg);
2207 } 2501 }
2208 2502
2209 if (gintsts & S3C_GINTSTS_ModeMis) { 2503 if (gintsts & GINTSTS_ModeMis) {
2210 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n"); 2504 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
2211 writel(S3C_GINTSTS_ModeMis, hsotg->regs + S3C_GINTSTS); 2505 writel(GINTSTS_ModeMis, hsotg->regs + GINTSTS);
2212 } 2506 }
2213 2507
2214 if (gintsts & S3C_GINTSTS_USBSusp) { 2508 if (gintsts & GINTSTS_USBSusp) {
2215 dev_info(hsotg->dev, "S3C_GINTSTS_USBSusp\n"); 2509 dev_info(hsotg->dev, "GINTSTS_USBSusp\n");
2216 writel(S3C_GINTSTS_USBSusp, hsotg->regs + S3C_GINTSTS); 2510 writel(GINTSTS_USBSusp, hsotg->regs + GINTSTS);
2217 2511
2218 call_gadget(hsotg, suspend); 2512 call_gadget(hsotg, suspend);
2513 s3c_hsotg_disconnect(hsotg);
2219 } 2514 }
2220 2515
2221 if (gintsts & S3C_GINTSTS_WkUpInt) { 2516 if (gintsts & GINTSTS_WkUpInt) {
2222 dev_info(hsotg->dev, "S3C_GINTSTS_WkUpIn\n"); 2517 dev_info(hsotg->dev, "GINTSTS_WkUpIn\n");
2223 writel(S3C_GINTSTS_WkUpInt, hsotg->regs + S3C_GINTSTS); 2518 writel(GINTSTS_WkUpInt, hsotg->regs + GINTSTS);
2224 2519
2225 call_gadget(hsotg, resume); 2520 call_gadget(hsotg, resume);
2226 } 2521 }
2227 2522
2228 if (gintsts & S3C_GINTSTS_ErlySusp) { 2523 if (gintsts & GINTSTS_ErlySusp) {
2229 dev_dbg(hsotg->dev, "S3C_GINTSTS_ErlySusp\n"); 2524 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
2230 writel(S3C_GINTSTS_ErlySusp, hsotg->regs + S3C_GINTSTS); 2525 writel(GINTSTS_ErlySusp, hsotg->regs + GINTSTS);
2526
2527 s3c_hsotg_disconnect(hsotg);
2231 } 2528 }
2232 2529
2233 /* these next two seem to crop-up occasionally causing the core 2530 /*
2531 * these next two seem to crop-up occasionally causing the core
2234 * to shutdown the USB transfer, so try clearing them and logging 2532 * to shutdown the USB transfer, so try clearing them and logging
2235 * the occurrence. */ 2533 * the occurrence.
2534 */
2236 2535
2237 if (gintsts & S3C_GINTSTS_GOUTNakEff) { 2536 if (gintsts & GINTSTS_GOUTNakEff) {
2238 dev_info(hsotg->dev, "GOUTNakEff triggered\n"); 2537 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2239 2538
2240 writel(S3C_DCTL_CGOUTNak, hsotg->regs + S3C_DCTL); 2539 writel(DCTL_CGOUTNak, hsotg->regs + DCTL);
2241 2540
2242 s3c_hsotg_dump(hsotg); 2541 s3c_hsotg_dump(hsotg);
2243 } 2542 }
2244 2543
2245 if (gintsts & S3C_GINTSTS_GINNakEff) { 2544 if (gintsts & GINTSTS_GINNakEff) {
2246 dev_info(hsotg->dev, "GINNakEff triggered\n"); 2545 dev_info(hsotg->dev, "GINNakEff triggered\n");
2247 2546
2248 writel(S3C_DCTL_CGNPInNAK, hsotg->regs + S3C_DCTL); 2547 writel(DCTL_CGNPInNAK, hsotg->regs + DCTL);
2249 2548
2250 s3c_hsotg_dump(hsotg); 2549 s3c_hsotg_dump(hsotg);
2251 } 2550 }
2252 2551
2253 /* if we've had fifo events, we should try and go around the 2552 /*
2254 * loop again to see if there's any point in returning yet. */ 2553 * if we've had fifo events, we should try and go around the
2554 * loop again to see if there's any point in returning yet.
2555 */
2255 2556
2256 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0) 2557 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2257 goto irq_retry; 2558 goto irq_retry;
@@ -2265,7 +2566,7 @@ irq_retry:
2265 * @desc: The USB endpoint descriptor to configure with. 2566 * @desc: The USB endpoint descriptor to configure with.
2266 * 2567 *
2267 * This is called from the USB gadget code's usb_ep_enable(). 2568 * This is called from the USB gadget code's usb_ep_enable().
2268*/ 2569 */
2269static int s3c_hsotg_ep_enable(struct usb_ep *ep, 2570static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2270 const struct usb_endpoint_descriptor *desc) 2571 const struct usb_endpoint_descriptor *desc)
2271{ 2572{
@@ -2297,7 +2598,7 @@ static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2297 2598
2298 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */ 2599 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2299 2600
2300 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index); 2601 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2301 epctrl = readl(hsotg->regs + epctrl_reg); 2602 epctrl = readl(hsotg->regs + epctrl_reg);
2302 2603
2303 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", 2604 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
@@ -2305,20 +2606,23 @@ static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2305 2606
2306 spin_lock_irqsave(&hs_ep->lock, flags); 2607 spin_lock_irqsave(&hs_ep->lock, flags);
2307 2608
2308 epctrl &= ~(S3C_DxEPCTL_EPType_MASK | S3C_DxEPCTL_MPS_MASK); 2609 epctrl &= ~(DxEPCTL_EPType_MASK | DxEPCTL_MPS_MASK);
2309 epctrl |= S3C_DxEPCTL_MPS(mps); 2610 epctrl |= DxEPCTL_MPS(mps);
2310 2611
2311 /* mark the endpoint as active, otherwise the core may ignore 2612 /*
2312 * transactions entirely for this endpoint */ 2613 * mark the endpoint as active, otherwise the core may ignore
2313 epctrl |= S3C_DxEPCTL_USBActEp; 2614 * transactions entirely for this endpoint
2615 */
2616 epctrl |= DxEPCTL_USBActEp;
2314 2617
2315 /* set the NAK status on the endpoint, otherwise we might try and 2618 /*
2619 * set the NAK status on the endpoint, otherwise we might try and
2316 * do something with data that we've yet got a request to process 2620 * do something with data that we've yet got a request to process
2317 * since the RXFIFO will take data for an endpoint even if the 2621 * since the RXFIFO will take data for an endpoint even if the
2318 * size register hasn't been set. 2622 * size register hasn't been set.
2319 */ 2623 */
2320 2624
2321 epctrl |= S3C_DxEPCTL_SNAK; 2625 epctrl |= DxEPCTL_SNAK;
2322 2626
2323 /* update the endpoint state */ 2627 /* update the endpoint state */
2324 hs_ep->ep.maxpacket = mps; 2628 hs_ep->ep.maxpacket = mps;
@@ -2333,37 +2637,40 @@ static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2333 goto out; 2637 goto out;
2334 2638
2335 case USB_ENDPOINT_XFER_BULK: 2639 case USB_ENDPOINT_XFER_BULK:
2336 epctrl |= S3C_DxEPCTL_EPType_Bulk; 2640 epctrl |= DxEPCTL_EPType_Bulk;
2337 break; 2641 break;
2338 2642
2339 case USB_ENDPOINT_XFER_INT: 2643 case USB_ENDPOINT_XFER_INT:
2340 if (dir_in) { 2644 if (dir_in) {
2341 /* Allocate our TxFNum by simply using the index 2645 /*
2646 * Allocate our TxFNum by simply using the index
2342 * of the endpoint for the moment. We could do 2647 * of the endpoint for the moment. We could do
2343 * something better if the host indicates how 2648 * something better if the host indicates how
2344 * many FIFOs we are expecting to use. */ 2649 * many FIFOs we are expecting to use.
2650 */
2345 2651
2346 hs_ep->periodic = 1; 2652 hs_ep->periodic = 1;
2347 epctrl |= S3C_DxEPCTL_TxFNum(index); 2653 epctrl |= DxEPCTL_TxFNum(index);
2348 } 2654 }
2349 2655
2350 epctrl |= S3C_DxEPCTL_EPType_Intterupt; 2656 epctrl |= DxEPCTL_EPType_Intterupt;
2351 break; 2657 break;
2352 2658
2353 case USB_ENDPOINT_XFER_CONTROL: 2659 case USB_ENDPOINT_XFER_CONTROL:
2354 epctrl |= S3C_DxEPCTL_EPType_Control; 2660 epctrl |= DxEPCTL_EPType_Control;
2355 break; 2661 break;
2356 } 2662 }
2357 2663
2358 /* if the hardware has dedicated fifos, we must give each IN EP 2664 /*
2665 * if the hardware has dedicated fifos, we must give each IN EP
2359 * a unique tx-fifo even if it is non-periodic. 2666 * a unique tx-fifo even if it is non-periodic.
2360 */ 2667 */
2361 if (dir_in && hsotg->dedicated_fifos) 2668 if (dir_in && hsotg->dedicated_fifos)
2362 epctrl |= S3C_DxEPCTL_TxFNum(index); 2669 epctrl |= DxEPCTL_TxFNum(index);
2363 2670
2364 /* for non control endpoints, set PID to D0 */ 2671 /* for non control endpoints, set PID to D0 */
2365 if (index) 2672 if (index)
2366 epctrl |= S3C_DxEPCTL_SetD0PID; 2673 epctrl |= DxEPCTL_SetD0PID;
2367 2674
2368 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", 2675 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2369 __func__, epctrl); 2676 __func__, epctrl);
@@ -2380,6 +2687,10 @@ out:
2380 return ret; 2687 return ret;
2381} 2688}
2382 2689
2690/**
2691 * s3c_hsotg_ep_disable - disable given endpoint
2692 * @ep: The endpoint to disable.
2693 */
2383static int s3c_hsotg_ep_disable(struct usb_ep *ep) 2694static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2384{ 2695{
2385 struct s3c_hsotg_ep *hs_ep = our_ep(ep); 2696 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
@@ -2397,7 +2708,7 @@ static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2397 return -EINVAL; 2708 return -EINVAL;
2398 } 2709 }
2399 2710
2400 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index); 2711 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2401 2712
2402 /* terminate all requests with shutdown */ 2713 /* terminate all requests with shutdown */
2403 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false); 2714 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
@@ -2405,9 +2716,9 @@ static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2405 spin_lock_irqsave(&hs_ep->lock, flags); 2716 spin_lock_irqsave(&hs_ep->lock, flags);
2406 2717
2407 ctrl = readl(hsotg->regs + epctrl_reg); 2718 ctrl = readl(hsotg->regs + epctrl_reg);
2408 ctrl &= ~S3C_DxEPCTL_EPEna; 2719 ctrl &= ~DxEPCTL_EPEna;
2409 ctrl &= ~S3C_DxEPCTL_USBActEp; 2720 ctrl &= ~DxEPCTL_USBActEp;
2410 ctrl |= S3C_DxEPCTL_SNAK; 2721 ctrl |= DxEPCTL_SNAK;
2411 2722
2412 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); 2723 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2413 writel(ctrl, hsotg->regs + epctrl_reg); 2724 writel(ctrl, hsotg->regs + epctrl_reg);
@@ -2423,7 +2734,7 @@ static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2423 * on_list - check request is on the given endpoint 2734 * on_list - check request is on the given endpoint
2424 * @ep: The endpoint to check. 2735 * @ep: The endpoint to check.
2425 * @test: The request to test if it is on the endpoint. 2736 * @test: The request to test if it is on the endpoint.
2426*/ 2737 */
2427static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test) 2738static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2428{ 2739{
2429 struct s3c_hsotg_req *req, *treq; 2740 struct s3c_hsotg_req *req, *treq;
@@ -2436,6 +2747,11 @@ static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2436 return false; 2747 return false;
2437} 2748}
2438 2749
2750/**
2751 * s3c_hsotg_ep_dequeue - dequeue given endpoint
2752 * @ep: The endpoint to dequeue.
2753 * @req: The request to be removed from a queue.
2754 */
2439static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req) 2755static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2440{ 2756{
2441 struct s3c_hsotg_req *hs_req = our_req(req); 2757 struct s3c_hsotg_req *hs_req = our_req(req);
@@ -2458,6 +2774,11 @@ static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2458 return 0; 2774 return 0;
2459} 2775}
2460 2776
2777/**
2778 * s3c_hsotg_ep_sethalt - set halt on a given endpoint
2779 * @ep: The endpoint to set halt.
2780 * @value: Set or unset the halt.
2781 */
2461static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value) 2782static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2462{ 2783{
2463 struct s3c_hsotg_ep *hs_ep = our_ep(ep); 2784 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
@@ -2474,34 +2795,34 @@ static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2474 2795
2475 /* write both IN and OUT control registers */ 2796 /* write both IN and OUT control registers */
2476 2797
2477 epreg = S3C_DIEPCTL(index); 2798 epreg = DIEPCTL(index);
2478 epctl = readl(hs->regs + epreg); 2799 epctl = readl(hs->regs + epreg);
2479 2800
2480 if (value) { 2801 if (value) {
2481 epctl |= S3C_DxEPCTL_Stall + S3C_DxEPCTL_SNAK; 2802 epctl |= DxEPCTL_Stall + DxEPCTL_SNAK;
2482 if (epctl & S3C_DxEPCTL_EPEna) 2803 if (epctl & DxEPCTL_EPEna)
2483 epctl |= S3C_DxEPCTL_EPDis; 2804 epctl |= DxEPCTL_EPDis;
2484 } else { 2805 } else {
2485 epctl &= ~S3C_DxEPCTL_Stall; 2806 epctl &= ~DxEPCTL_Stall;
2486 xfertype = epctl & S3C_DxEPCTL_EPType_MASK; 2807 xfertype = epctl & DxEPCTL_EPType_MASK;
2487 if (xfertype == S3C_DxEPCTL_EPType_Bulk || 2808 if (xfertype == DxEPCTL_EPType_Bulk ||
2488 xfertype == S3C_DxEPCTL_EPType_Intterupt) 2809 xfertype == DxEPCTL_EPType_Intterupt)
2489 epctl |= S3C_DxEPCTL_SetD0PID; 2810 epctl |= DxEPCTL_SetD0PID;
2490 } 2811 }
2491 2812
2492 writel(epctl, hs->regs + epreg); 2813 writel(epctl, hs->regs + epreg);
2493 2814
2494 epreg = S3C_DOEPCTL(index); 2815 epreg = DOEPCTL(index);
2495 epctl = readl(hs->regs + epreg); 2816 epctl = readl(hs->regs + epreg);
2496 2817
2497 if (value) 2818 if (value)
2498 epctl |= S3C_DxEPCTL_Stall; 2819 epctl |= DxEPCTL_Stall;
2499 else { 2820 else {
2500 epctl &= ~S3C_DxEPCTL_Stall; 2821 epctl &= ~DxEPCTL_Stall;
2501 xfertype = epctl & S3C_DxEPCTL_EPType_MASK; 2822 xfertype = epctl & DxEPCTL_EPType_MASK;
2502 if (xfertype == S3C_DxEPCTL_EPType_Bulk || 2823 if (xfertype == DxEPCTL_EPType_Bulk ||
2503 xfertype == S3C_DxEPCTL_EPType_Intterupt) 2824 xfertype == DxEPCTL_EPType_Intterupt)
2504 epctl |= S3C_DxEPCTL_SetD0PID; 2825 epctl |= DxEPCTL_SetD0PID;
2505 } 2826 }
2506 2827
2507 writel(epctl, hs->regs + epreg); 2828 writel(epctl, hs->regs + epreg);
@@ -2523,57 +2844,91 @@ static struct usb_ep_ops s3c_hsotg_ep_ops = {
2523}; 2844};
2524 2845
2525/** 2846/**
2526 * s3c_hsotg_corereset - issue softreset to the core 2847 * s3c_hsotg_phy_enable - enable platform phy dev
2527 * @hsotg: The device state 2848 * @hsotg: The driver state
2528 * 2849 *
2529 * Issue a soft reset to the core, and await the core finishing it. 2850 * A wrapper for platform code responsible for controlling
2530*/ 2851 * low-level USB code
2531static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg) 2852 */
2853static void s3c_hsotg_phy_enable(struct s3c_hsotg *hsotg)
2532{ 2854{
2533 int timeout; 2855 struct platform_device *pdev = to_platform_device(hsotg->dev);
2534 u32 grstctl;
2535 2856
2536 dev_dbg(hsotg->dev, "resetting core\n"); 2857 dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
2858 if (hsotg->plat->phy_init)
2859 hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
2860}
2537 2861
2538 /* issue soft reset */ 2862/**
2539 writel(S3C_GRSTCTL_CSftRst, hsotg->regs + S3C_GRSTCTL); 2863 * s3c_hsotg_phy_disable - disable platform phy dev
2864 * @hsotg: The driver state
2865 *
2866 * A wrapper for platform code responsible for controlling
2867 * low-level USB code
2868 */
2869static void s3c_hsotg_phy_disable(struct s3c_hsotg *hsotg)
2870{
2871 struct platform_device *pdev = to_platform_device(hsotg->dev);
2540 2872
2541 timeout = 1000; 2873 if (hsotg->plat->phy_exit)
2542 do { 2874 hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
2543 grstctl = readl(hsotg->regs + S3C_GRSTCTL); 2875}
2544 } while ((grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0);
2545 2876
2546 if (grstctl & S3C_GRSTCTL_CSftRst) { 2877/**
2547 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n"); 2878 * s3c_hsotg_init - initalize the usb core
2548 return -EINVAL; 2879 * @hsotg: The driver state
2549 } 2880 */
2881static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2882{
2883 /* unmask subset of endpoint interrupts */
2550 2884
2551 timeout = 1000; 2885 writel(DIEPMSK_TimeOUTMsk | DIEPMSK_AHBErrMsk |
2886 DIEPMSK_EPDisbldMsk | DIEPMSK_XferComplMsk,
2887 hsotg->regs + DIEPMSK);
2552 2888
2553 while (1) { 2889 writel(DOEPMSK_SetupMsk | DOEPMSK_AHBErrMsk |
2554 u32 grstctl = readl(hsotg->regs + S3C_GRSTCTL); 2890 DOEPMSK_EPDisbldMsk | DOEPMSK_XferComplMsk,
2891 hsotg->regs + DOEPMSK);
2555 2892
2556 if (timeout-- < 0) { 2893 writel(0, hsotg->regs + DAINTMSK);
2557 dev_info(hsotg->dev,
2558 "%s: reset failed, GRSTCTL=%08x\n",
2559 __func__, grstctl);
2560 return -ETIMEDOUT;
2561 }
2562 2894
2563 if (!(grstctl & S3C_GRSTCTL_AHBIdle)) 2895 /* Be in disconnected state until gadget is registered */
2564 continue; 2896 __orr32(hsotg->regs + DCTL, DCTL_SftDiscon);
2565 2897
2566 break; /* reset done */ 2898 if (0) {
2899 /* post global nak until we're ready */
2900 writel(DCTL_SGNPInNAK | DCTL_SGOUTNak,
2901 hsotg->regs + DCTL);
2567 } 2902 }
2568 2903
2569 dev_dbg(hsotg->dev, "reset successful\n"); 2904 /* setup fifos */
2570 return 0; 2905
2906 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2907 readl(hsotg->regs + GRXFSIZ),
2908 readl(hsotg->regs + GNPTXFSIZ));
2909
2910 s3c_hsotg_init_fifo(hsotg);
2911
2912 /* set the PLL on, remove the HNP/SRP and set the PHY */
2913 writel(GUSBCFG_PHYIf16 | GUSBCFG_TOutCal(7) | (0x5 << 10),
2914 hsotg->regs + GUSBCFG);
2915
2916 writel(using_dma(hsotg) ? GAHBCFG_DMAEn : 0x0,
2917 hsotg->regs + GAHBCFG);
2571} 2918}
2572 2919
2573static int s3c_hsotg_start(struct usb_gadget_driver *driver, 2920/**
2574 int (*bind)(struct usb_gadget *)) 2921 * s3c_hsotg_udc_start - prepare the udc for work
2922 * @gadget: The usb gadget state
2923 * @driver: The usb gadget driver
2924 *
2925 * Perform initialization to prepare udc device and driver
2926 * to work.
2927 */
2928static int s3c_hsotg_udc_start(struct usb_gadget *gadget,
2929 struct usb_gadget_driver *driver)
2575{ 2930{
2576 struct s3c_hsotg *hsotg = our_hsotg; 2931 struct s3c_hsotg *hsotg = to_hsotg(gadget);
2577 int ret; 2932 int ret;
2578 2933
2579 if (!hsotg) { 2934 if (!hsotg) {
@@ -2589,7 +2944,7 @@ static int s3c_hsotg_start(struct usb_gadget_driver *driver,
2589 if (driver->max_speed < USB_SPEED_FULL) 2944 if (driver->max_speed < USB_SPEED_FULL)
2590 dev_err(hsotg->dev, "%s: bad speed\n", __func__); 2945 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
2591 2946
2592 if (!bind || !driver->setup) { 2947 if (!driver->setup) {
2593 dev_err(hsotg->dev, "%s: missing entry points\n", __func__); 2948 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
2594 return -EINVAL; 2949 return -EINVAL;
2595 } 2950 }
@@ -2602,135 +2957,17 @@ static int s3c_hsotg_start(struct usb_gadget_driver *driver,
2602 hsotg->gadget.dev.dma_mask = hsotg->dev->dma_mask; 2957 hsotg->gadget.dev.dma_mask = hsotg->dev->dma_mask;
2603 hsotg->gadget.speed = USB_SPEED_UNKNOWN; 2958 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2604 2959
2605 ret = device_add(&hsotg->gadget.dev); 2960 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
2961 hsotg->supplies);
2606 if (ret) { 2962 if (ret) {
2607 dev_err(hsotg->dev, "failed to register gadget device\n"); 2963 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
2608 goto err; 2964 goto err;
2609 } 2965 }
2610 2966
2611 ret = bind(&hsotg->gadget); 2967 s3c_hsotg_phy_enable(hsotg);
2612 if (ret) {
2613 dev_err(hsotg->dev, "failed bind %s\n", driver->driver.name);
2614
2615 hsotg->gadget.dev.driver = NULL;
2616 hsotg->driver = NULL;
2617 goto err;
2618 }
2619
2620 /* we must now enable ep0 ready for host detection and then
2621 * set configuration. */
2622
2623 s3c_hsotg_corereset(hsotg);
2624
2625 /* set the PLL on, remove the HNP/SRP and set the PHY */
2626 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) |
2627 (0x5 << 10), hsotg->regs + S3C_GUSBCFG);
2628
2629 /* looks like soft-reset changes state of FIFOs */
2630 s3c_hsotg_init_fifo(hsotg);
2631
2632 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2633
2634 writel(1 << 18 | S3C_DCFG_DevSpd_HS, hsotg->regs + S3C_DCFG);
2635
2636 /* Clear any pending OTG interrupts */
2637 writel(0xffffffff, hsotg->regs + S3C_GOTGINT);
2638
2639 /* Clear any pending interrupts */
2640 writel(0xffffffff, hsotg->regs + S3C_GINTSTS);
2641
2642 writel(S3C_GINTSTS_DisconnInt | S3C_GINTSTS_SessReqInt |
2643 S3C_GINTSTS_ConIDStsChng | S3C_GINTSTS_USBRst |
2644 S3C_GINTSTS_EnumDone | S3C_GINTSTS_OTGInt |
2645 S3C_GINTSTS_USBSusp | S3C_GINTSTS_WkUpInt |
2646 S3C_GINTSTS_GOUTNakEff | S3C_GINTSTS_GINNakEff |
2647 S3C_GINTSTS_ErlySusp,
2648 hsotg->regs + S3C_GINTMSK);
2649
2650 if (using_dma(hsotg))
2651 writel(S3C_GAHBCFG_GlblIntrEn | S3C_GAHBCFG_DMAEn |
2652 S3C_GAHBCFG_HBstLen_Incr4,
2653 hsotg->regs + S3C_GAHBCFG);
2654 else
2655 writel(S3C_GAHBCFG_GlblIntrEn, hsotg->regs + S3C_GAHBCFG);
2656
2657 /* Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2658 * up being flooded with interrupts if the host is polling the
2659 * endpoint to try and read data. */
2660
2661 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2662 S3C_DIEPMSK_INTknEPMisMsk |
2663 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk |
2664 ((hsotg->dedicated_fifos) ? S3C_DIEPMSK_TxFIFOEmpty : 0),
2665 hsotg->regs + S3C_DIEPMSK);
2666
2667 /* don't need XferCompl, we get that from RXFIFO in slave mode. In
2668 * DMA mode we may need this. */
2669 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2670 S3C_DOEPMSK_EPDisbldMsk |
2671 (using_dma(hsotg) ? (S3C_DIEPMSK_XferComplMsk |
2672 S3C_DIEPMSK_TimeOUTMsk) : 0),
2673 hsotg->regs + S3C_DOEPMSK);
2674
2675 writel(0, hsotg->regs + S3C_DAINTMSK);
2676
2677 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2678 readl(hsotg->regs + S3C_DIEPCTL0),
2679 readl(hsotg->regs + S3C_DOEPCTL0));
2680
2681 /* enable in and out endpoint interrupts */
2682 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt);
2683
2684 /* Enable the RXFIFO when in slave mode, as this is how we collect
2685 * the data. In DMA mode, we get events from the FIFO but also
2686 * things we cannot process, so do not use it. */
2687 if (!using_dma(hsotg))
2688 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_RxFLvl);
2689
2690 /* Enable interrupts for EP0 in and out */
2691 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2692 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2693
2694 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2695 udelay(10); /* see openiboot */
2696 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2697
2698 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + S3C_DCTL));
2699
2700 /* S3C_DxEPCTL_USBActEp says RO in manual, but seems to be set by
2701 writing to the EPCTL register.. */
2702
2703 /* set to read 1 8byte packet */
2704 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
2705 S3C_DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
2706
2707 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2708 S3C_DxEPCTL_CNAK | S3C_DxEPCTL_EPEna |
2709 S3C_DxEPCTL_USBActEp,
2710 hsotg->regs + S3C_DOEPCTL0);
2711
2712 /* enable, but don't activate EP0in */
2713 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2714 S3C_DxEPCTL_USBActEp, hsotg->regs + S3C_DIEPCTL0);
2715
2716 s3c_hsotg_enqueue_setup(hsotg);
2717
2718 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2719 readl(hsotg->regs + S3C_DIEPCTL0),
2720 readl(hsotg->regs + S3C_DOEPCTL0));
2721
2722 /* clear global NAKs */
2723 writel(S3C_DCTL_CGOUTNak | S3C_DCTL_CGNPInNAK,
2724 hsotg->regs + S3C_DCTL);
2725
2726 /* must be at-least 3ms to allow bus to see disconnect */
2727 msleep(3);
2728
2729 /* remove the soft-disconnect and let's go */
2730 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2731
2732 /* report to the user, and return */
2733 2968
2969 s3c_hsotg_core_init(hsotg);
2970 hsotg->last_rst = jiffies;
2734 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name); 2971 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
2735 return 0; 2972 return 0;
2736 2973
@@ -2740,9 +2977,17 @@ err:
2740 return ret; 2977 return ret;
2741} 2978}
2742 2979
2743static int s3c_hsotg_stop(struct usb_gadget_driver *driver) 2980/**
2981 * s3c_hsotg_udc_stop - stop the udc
2982 * @gadget: The usb gadget state
2983 * @driver: The usb gadget driver
2984 *
2985 * Stop udc hw block and stay tunned for future transmissions
2986 */
2987static int s3c_hsotg_udc_stop(struct usb_gadget *gadget,
2988 struct usb_gadget_driver *driver)
2744{ 2989{
2745 struct s3c_hsotg *hsotg = our_hsotg; 2990 struct s3c_hsotg *hsotg = to_hsotg(gadget);
2746 int ep; 2991 int ep;
2747 2992
2748 if (!hsotg) 2993 if (!hsotg)
@@ -2752,16 +2997,15 @@ static int s3c_hsotg_stop(struct usb_gadget_driver *driver)
2752 return -EINVAL; 2997 return -EINVAL;
2753 2998
2754 /* all endpoints should be shutdown */ 2999 /* all endpoints should be shutdown */
2755 for (ep = 0; ep < S3C_HSOTG_EPS; ep++) 3000 for (ep = 0; ep < hsotg->num_of_eps; ep++)
2756 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep); 3001 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
2757 3002
2758 call_gadget(hsotg, disconnect); 3003 s3c_hsotg_phy_disable(hsotg);
3004 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
2759 3005
2760 driver->unbind(&hsotg->gadget);
2761 hsotg->driver = NULL; 3006 hsotg->driver = NULL;
2762 hsotg->gadget.speed = USB_SPEED_UNKNOWN; 3007 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2763 3008 hsotg->gadget.dev.driver = NULL;
2764 device_del(&hsotg->gadget.dev);
2765 3009
2766 dev_info(hsotg->dev, "unregistered gadget driver '%s'\n", 3010 dev_info(hsotg->dev, "unregistered gadget driver '%s'\n",
2767 driver->driver.name); 3011 driver->driver.name);
@@ -2769,6 +3013,12 @@ static int s3c_hsotg_stop(struct usb_gadget_driver *driver)
2769 return 0; 3013 return 0;
2770} 3014}
2771 3015
3016/**
3017 * s3c_hsotg_gadget_getframe - read the frame number
3018 * @gadget: The usb gadget state
3019 *
3020 * Read the {micro} frame number
3021 */
2772static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget) 3022static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
2773{ 3023{
2774 return s3c_hsotg_read_frameno(to_hsotg(gadget)); 3024 return s3c_hsotg_read_frameno(to_hsotg(gadget));
@@ -2776,8 +3026,8 @@ static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
2776 3026
2777static struct usb_gadget_ops s3c_hsotg_gadget_ops = { 3027static struct usb_gadget_ops s3c_hsotg_gadget_ops = {
2778 .get_frame = s3c_hsotg_gadget_getframe, 3028 .get_frame = s3c_hsotg_gadget_getframe,
2779 .start = s3c_hsotg_start, 3029 .udc_start = s3c_hsotg_udc_start,
2780 .stop = s3c_hsotg_stop, 3030 .udc_stop = s3c_hsotg_udc_stop,
2781}; 3031};
2782 3032
2783/** 3033/**
@@ -2824,111 +3074,42 @@ static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg,
2824 hs_ep->ep.maxpacket = epnum ? 512 : EP0_MPS_LIMIT; 3074 hs_ep->ep.maxpacket = epnum ? 512 : EP0_MPS_LIMIT;
2825 hs_ep->ep.ops = &s3c_hsotg_ep_ops; 3075 hs_ep->ep.ops = &s3c_hsotg_ep_ops;
2826 3076
2827 /* Read the FIFO size for the Periodic TX FIFO, even if we're 3077 /*
3078 * Read the FIFO size for the Periodic TX FIFO, even if we're
2828 * an OUT endpoint, we may as well do this if in future the 3079 * an OUT endpoint, we may as well do this if in future the
2829 * code is changed to make each endpoint's direction changeable. 3080 * code is changed to make each endpoint's direction changeable.
2830 */ 3081 */
2831 3082
2832 ptxfifo = readl(hsotg->regs + S3C_DPTXFSIZn(epnum)); 3083 ptxfifo = readl(hsotg->regs + DPTXFSIZn(epnum));
2833 hs_ep->fifo_size = S3C_DPTXFSIZn_DPTxFSize_GET(ptxfifo) * 4; 3084 hs_ep->fifo_size = DPTXFSIZn_DPTxFSize_GET(ptxfifo) * 4;
2834 3085
2835 /* if we're using dma, we need to set the next-endpoint pointer 3086 /*
3087 * if we're using dma, we need to set the next-endpoint pointer
2836 * to be something valid. 3088 * to be something valid.
2837 */ 3089 */
2838 3090
2839 if (using_dma(hsotg)) { 3091 if (using_dma(hsotg)) {
2840 u32 next = S3C_DxEPCTL_NextEp((epnum + 1) % 15); 3092 u32 next = DxEPCTL_NextEp((epnum + 1) % 15);
2841 writel(next, hsotg->regs + S3C_DIEPCTL(epnum)); 3093 writel(next, hsotg->regs + DIEPCTL(epnum));
2842 writel(next, hsotg->regs + S3C_DOEPCTL(epnum)); 3094 writel(next, hsotg->regs + DOEPCTL(epnum));
2843 } 3095 }
2844} 3096}
2845 3097
2846/** 3098/**
2847 * s3c_hsotg_otgreset - reset the OtG phy block 3099 * s3c_hsotg_hw_cfg - read HW configuration registers
2848 * @hsotg: The host state. 3100 * @param: The device state
2849 * 3101 *
2850 * Power up the phy, set the basic configuration and start the PHY. 3102 * Read the USB core HW configuration registers
2851 */ 3103 */
2852static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg) 3104static void s3c_hsotg_hw_cfg(struct s3c_hsotg *hsotg)
2853{ 3105{
2854 struct clk *xusbxti; 3106 u32 cfg2, cfg4;
2855 u32 pwr, osc; 3107 /* check hardware configuration */
2856
2857 pwr = readl(S3C_PHYPWR);
2858 pwr &= ~0x19;
2859 writel(pwr, S3C_PHYPWR);
2860 mdelay(1);
2861
2862 osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0;
2863
2864 xusbxti = clk_get(hsotg->dev, "xusbxti");
2865 if (xusbxti && !IS_ERR(xusbxti)) {
2866 switch (clk_get_rate(xusbxti)) {
2867 case 12*MHZ:
2868 osc |= S3C_PHYCLK_CLKSEL_12M;
2869 break;
2870 case 24*MHZ:
2871 osc |= S3C_PHYCLK_CLKSEL_24M;
2872 break;
2873 default:
2874 case 48*MHZ:
2875 /* default reference clock */
2876 break;
2877 }
2878 clk_put(xusbxti);
2879 }
2880
2881 writel(osc | 0x10, S3C_PHYCLK);
2882
2883 /* issue a full set of resets to the otg and core */
2884
2885 writel(S3C_RSTCON_PHY, S3C_RSTCON);
2886 udelay(20); /* at-least 10uS */
2887 writel(0, S3C_RSTCON);
2888}
2889
2890
2891static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2892{
2893 u32 cfg4;
2894
2895 /* unmask subset of endpoint interrupts */
2896
2897 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2898 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
2899 hsotg->regs + S3C_DIEPMSK);
2900
2901 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2902 S3C_DOEPMSK_EPDisbldMsk | S3C_DOEPMSK_XferComplMsk,
2903 hsotg->regs + S3C_DOEPMSK);
2904
2905 writel(0, hsotg->regs + S3C_DAINTMSK);
2906
2907 /* Be in disconnected state until gadget is registered */
2908 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2909
2910 if (0) {
2911 /* post global nak until we're ready */
2912 writel(S3C_DCTL_SGNPInNAK | S3C_DCTL_SGOUTNak,
2913 hsotg->regs + S3C_DCTL);
2914 }
2915
2916 /* setup fifos */
2917
2918 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2919 readl(hsotg->regs + S3C_GRXFSIZ),
2920 readl(hsotg->regs + S3C_GNPTXFSIZ));
2921
2922 s3c_hsotg_init_fifo(hsotg);
2923
2924 /* set the PLL on, remove the HNP/SRP and set the PHY */
2925 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) | (0x5 << 10),
2926 hsotg->regs + S3C_GUSBCFG);
2927 3108
2928 writel(using_dma(hsotg) ? S3C_GAHBCFG_DMAEn : 0x0, 3109 cfg2 = readl(hsotg->regs + 0x48);
2929 hsotg->regs + S3C_GAHBCFG); 3110 hsotg->num_of_eps = (cfg2 >> 10) & 0xF;
2930 3111
2931 /* check hardware configuration */ 3112 dev_info(hsotg->dev, "EPs:%d\n", hsotg->num_of_eps);
2932 3113
2933 cfg4 = readl(hsotg->regs + 0x50); 3114 cfg4 = readl(hsotg->regs + 0x50);
2934 hsotg->dedicated_fifos = (cfg4 >> 25) & 1; 3115 hsotg->dedicated_fifos = (cfg4 >> 25) & 1;
@@ -2937,6 +3118,10 @@ static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2937 hsotg->dedicated_fifos ? "dedicated" : "shared"); 3118 hsotg->dedicated_fifos ? "dedicated" : "shared");
2938} 3119}
2939 3120
3121/**
3122 * s3c_hsotg_dump - dump state of the udc
3123 * @param: The device state
3124 */
2940static void s3c_hsotg_dump(struct s3c_hsotg *hsotg) 3125static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
2941{ 3126{
2942#ifdef DEBUG 3127#ifdef DEBUG
@@ -2946,46 +3131,45 @@ static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
2946 int idx; 3131 int idx;
2947 3132
2948 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", 3133 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
2949 readl(regs + S3C_DCFG), readl(regs + S3C_DCTL), 3134 readl(regs + DCFG), readl(regs + DCTL),
2950 readl(regs + S3C_DIEPMSK)); 3135 readl(regs + DIEPMSK));
2951 3136
2952 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n", 3137 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
2953 readl(regs + S3C_GAHBCFG), readl(regs + 0x44)); 3138 readl(regs + GAHBCFG), readl(regs + 0x44));
2954 3139
2955 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", 3140 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2956 readl(regs + S3C_GRXFSIZ), readl(regs + S3C_GNPTXFSIZ)); 3141 readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ));
2957 3142
2958 /* show periodic fifo settings */ 3143 /* show periodic fifo settings */
2959 3144
2960 for (idx = 1; idx <= 15; idx++) { 3145 for (idx = 1; idx <= 15; idx++) {
2961 val = readl(regs + S3C_DPTXFSIZn(idx)); 3146 val = readl(regs + DPTXFSIZn(idx));
2962 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, 3147 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
2963 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT, 3148 val >> DPTXFSIZn_DPTxFSize_SHIFT,
2964 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK); 3149 val & DPTXFSIZn_DPTxFStAddr_MASK);
2965 } 3150 }
2966 3151
2967 for (idx = 0; idx < 15; idx++) { 3152 for (idx = 0; idx < 15; idx++) {
2968 dev_info(dev, 3153 dev_info(dev,
2969 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, 3154 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
2970 readl(regs + S3C_DIEPCTL(idx)), 3155 readl(regs + DIEPCTL(idx)),
2971 readl(regs + S3C_DIEPTSIZ(idx)), 3156 readl(regs + DIEPTSIZ(idx)),
2972 readl(regs + S3C_DIEPDMA(idx))); 3157 readl(regs + DIEPDMA(idx)));
2973 3158
2974 val = readl(regs + S3C_DOEPCTL(idx)); 3159 val = readl(regs + DOEPCTL(idx));
2975 dev_info(dev, 3160 dev_info(dev,
2976 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", 3161 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
2977 idx, readl(regs + S3C_DOEPCTL(idx)), 3162 idx, readl(regs + DOEPCTL(idx)),
2978 readl(regs + S3C_DOEPTSIZ(idx)), 3163 readl(regs + DOEPTSIZ(idx)),
2979 readl(regs + S3C_DOEPDMA(idx))); 3164 readl(regs + DOEPDMA(idx)));
2980 3165
2981 } 3166 }
2982 3167
2983 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", 3168 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
2984 readl(regs + S3C_DVBUSDIS), readl(regs + S3C_DVBUSPULSE)); 3169 readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE));
2985#endif 3170#endif
2986} 3171}
2987 3172
2988
2989/** 3173/**
2990 * state_show - debugfs: show overall driver and device state. 3174 * state_show - debugfs: show overall driver and device state.
2991 * @seq: The seq file to write to. 3175 * @seq: The seq file to write to.
@@ -3002,38 +3186,38 @@ static int state_show(struct seq_file *seq, void *v)
3002 int idx; 3186 int idx;
3003 3187
3004 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n", 3188 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
3005 readl(regs + S3C_DCFG), 3189 readl(regs + DCFG),
3006 readl(regs + S3C_DCTL), 3190 readl(regs + DCTL),
3007 readl(regs + S3C_DSTS)); 3191 readl(regs + DSTS));
3008 3192
3009 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n", 3193 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
3010 readl(regs + S3C_DIEPMSK), readl(regs + S3C_DOEPMSK)); 3194 readl(regs + DIEPMSK), readl(regs + DOEPMSK));
3011 3195
3012 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n", 3196 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
3013 readl(regs + S3C_GINTMSK), 3197 readl(regs + GINTMSK),
3014 readl(regs + S3C_GINTSTS)); 3198 readl(regs + GINTSTS));
3015 3199
3016 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n", 3200 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
3017 readl(regs + S3C_DAINTMSK), 3201 readl(regs + DAINTMSK),
3018 readl(regs + S3C_DAINT)); 3202 readl(regs + DAINT));
3019 3203
3020 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n", 3204 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3021 readl(regs + S3C_GNPTXSTS), 3205 readl(regs + GNPTXSTS),
3022 readl(regs + S3C_GRXSTSR)); 3206 readl(regs + GRXSTSR));
3023 3207
3024 seq_printf(seq, "\nEndpoint status:\n"); 3208 seq_printf(seq, "\nEndpoint status:\n");
3025 3209
3026 for (idx = 0; idx < 15; idx++) { 3210 for (idx = 0; idx < 15; idx++) {
3027 u32 in, out; 3211 u32 in, out;
3028 3212
3029 in = readl(regs + S3C_DIEPCTL(idx)); 3213 in = readl(regs + DIEPCTL(idx));
3030 out = readl(regs + S3C_DOEPCTL(idx)); 3214 out = readl(regs + DOEPCTL(idx));
3031 3215
3032 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x", 3216 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3033 idx, in, out); 3217 idx, in, out);
3034 3218
3035 in = readl(regs + S3C_DIEPTSIZ(idx)); 3219 in = readl(regs + DIEPTSIZ(idx));
3036 out = readl(regs + S3C_DOEPTSIZ(idx)); 3220 out = readl(regs + DOEPTSIZ(idx));
3037 3221
3038 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x", 3222 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3039 in, out); 3223 in, out);
@@ -3064,7 +3248,7 @@ static const struct file_operations state_fops = {
3064 * 3248 *
3065 * Show the FIFO information for the overall fifo and all the 3249 * Show the FIFO information for the overall fifo and all the
3066 * periodic transmission FIFOs. 3250 * periodic transmission FIFOs.
3067*/ 3251 */
3068static int fifo_show(struct seq_file *seq, void *v) 3252static int fifo_show(struct seq_file *seq, void *v)
3069{ 3253{
3070 struct s3c_hsotg *hsotg = seq->private; 3254 struct s3c_hsotg *hsotg = seq->private;
@@ -3073,21 +3257,21 @@ static int fifo_show(struct seq_file *seq, void *v)
3073 int idx; 3257 int idx;
3074 3258
3075 seq_printf(seq, "Non-periodic FIFOs:\n"); 3259 seq_printf(seq, "Non-periodic FIFOs:\n");
3076 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + S3C_GRXFSIZ)); 3260 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ));
3077 3261
3078 val = readl(regs + S3C_GNPTXFSIZ); 3262 val = readl(regs + GNPTXFSIZ);
3079 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n", 3263 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
3080 val >> S3C_GNPTXFSIZ_NPTxFDep_SHIFT, 3264 val >> GNPTXFSIZ_NPTxFDep_SHIFT,
3081 val & S3C_GNPTXFSIZ_NPTxFStAddr_MASK); 3265 val & GNPTXFSIZ_NPTxFStAddr_MASK);
3082 3266
3083 seq_printf(seq, "\nPeriodic TXFIFOs:\n"); 3267 seq_printf(seq, "\nPeriodic TXFIFOs:\n");
3084 3268
3085 for (idx = 1; idx <= 15; idx++) { 3269 for (idx = 1; idx <= 15; idx++) {
3086 val = readl(regs + S3C_DPTXFSIZn(idx)); 3270 val = readl(regs + DPTXFSIZn(idx));
3087 3271
3088 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx, 3272 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
3089 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT, 3273 val >> DPTXFSIZn_DPTxFSize_SHIFT,
3090 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK); 3274 val & DPTXFSIZn_DPTxFStAddr_MASK);
3091 } 3275 }
3092 3276
3093 return 0; 3277 return 0;
@@ -3119,7 +3303,7 @@ static const char *decode_direction(int is_in)
3119 * 3303 *
3120 * This debugfs entry shows the state of the given endpoint (one is 3304 * This debugfs entry shows the state of the given endpoint (one is
3121 * registered for each available). 3305 * registered for each available).
3122*/ 3306 */
3123static int ep_show(struct seq_file *seq, void *v) 3307static int ep_show(struct seq_file *seq, void *v)
3124{ 3308{
3125 struct s3c_hsotg_ep *ep = seq->private; 3309 struct s3c_hsotg_ep *ep = seq->private;
@@ -3136,20 +3320,20 @@ static int ep_show(struct seq_file *seq, void *v)
3136 /* first show the register state */ 3320 /* first show the register state */
3137 3321
3138 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n", 3322 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3139 readl(regs + S3C_DIEPCTL(index)), 3323 readl(regs + DIEPCTL(index)),
3140 readl(regs + S3C_DOEPCTL(index))); 3324 readl(regs + DOEPCTL(index)));
3141 3325
3142 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n", 3326 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3143 readl(regs + S3C_DIEPDMA(index)), 3327 readl(regs + DIEPDMA(index)),
3144 readl(regs + S3C_DOEPDMA(index))); 3328 readl(regs + DOEPDMA(index)));
3145 3329
3146 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n", 3330 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3147 readl(regs + S3C_DIEPINT(index)), 3331 readl(regs + DIEPINT(index)),
3148 readl(regs + S3C_DOEPINT(index))); 3332 readl(regs + DOEPINT(index)));
3149 3333
3150 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n", 3334 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3151 readl(regs + S3C_DIEPTSIZ(index)), 3335 readl(regs + DIEPTSIZ(index)),
3152 readl(regs + S3C_DOEPTSIZ(index))); 3336 readl(regs + DOEPTSIZ(index)));
3153 3337
3154 seq_printf(seq, "\n"); 3338 seq_printf(seq, "\n");
3155 seq_printf(seq, "mps %d\n", ep->ep.maxpacket); 3339 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
@@ -3199,7 +3383,7 @@ static const struct file_operations ep_fops = {
3199 * about the state of the system. The directory name is created 3383 * about the state of the system. The directory name is created
3200 * with the same name as the device itself, in case we end up 3384 * with the same name as the device itself, in case we end up
3201 * with multiple blocks in future systems. 3385 * with multiple blocks in future systems.
3202*/ 3386 */
3203static void __devinit s3c_hsotg_create_debug(struct s3c_hsotg *hsotg) 3387static void __devinit s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
3204{ 3388{
3205 struct dentry *root; 3389 struct dentry *root;
@@ -3228,7 +3412,7 @@ static void __devinit s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
3228 3412
3229 /* create one file for each endpoint */ 3413 /* create one file for each endpoint */
3230 3414
3231 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) { 3415 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3232 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx]; 3416 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3233 3417
3234 ep->debugfs = debugfs_create_file(ep->name, 0444, 3418 ep->debugfs = debugfs_create_file(ep->name, 0444,
@@ -3245,12 +3429,12 @@ static void __devinit s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
3245 * @hsotg: The driver state 3429 * @hsotg: The driver state
3246 * 3430 *
3247 * Cleanup (remove) the debugfs files for use on module exit. 3431 * Cleanup (remove) the debugfs files for use on module exit.
3248*/ 3432 */
3249static void __devexit s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg) 3433static void __devexit s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
3250{ 3434{
3251 unsigned epidx; 3435 unsigned epidx;
3252 3436
3253 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) { 3437 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3254 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx]; 3438 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3255 debugfs_remove(ep->debugfs); 3439 debugfs_remove(ep->debugfs);
3256 } 3440 }
@@ -3261,48 +3445,39 @@ static void __devexit s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
3261} 3445}
3262 3446
3263/** 3447/**
3264 * s3c_hsotg_gate - set the hardware gate for the block 3448 * s3c_hsotg_release - release callback for hsotg device
3265 * @pdev: The device we bound to 3449 * @dev: Device to for which release is called
3266 * @on: On or off.
3267 *
3268 * Set the hardware gate setting into the block. If we end up on
3269 * something other than an S3C64XX, then we might need to change this
3270 * to using a platform data callback, or some other mechanism.
3271 */ 3450 */
3272static void s3c_hsotg_gate(struct platform_device *pdev, bool on) 3451static void s3c_hsotg_release(struct device *dev)
3273{ 3452{
3274 unsigned long flags; 3453 struct s3c_hsotg *hsotg = dev_get_drvdata(dev);
3275 u32 others;
3276 3454
3277 local_irq_save(flags); 3455 kfree(hsotg);
3278
3279 others = __raw_readl(S3C64XX_OTHERS);
3280 if (on)
3281 others |= S3C64XX_OTHERS_USBMASK;
3282 else
3283 others &= ~S3C64XX_OTHERS_USBMASK;
3284 __raw_writel(others, S3C64XX_OTHERS);
3285
3286 local_irq_restore(flags);
3287} 3456}
3288 3457
3289static struct s3c_hsotg_plat s3c_hsotg_default_pdata; 3458/**
3459 * s3c_hsotg_probe - probe function for hsotg driver
3460 * @pdev: The platform information for the driver
3461 */
3290 3462
3291static int __devinit s3c_hsotg_probe(struct platform_device *pdev) 3463static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
3292{ 3464{
3293 struct s3c_hsotg_plat *plat = pdev->dev.platform_data; 3465 struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
3294 struct device *dev = &pdev->dev; 3466 struct device *dev = &pdev->dev;
3467 struct s3c_hsotg_ep *eps;
3295 struct s3c_hsotg *hsotg; 3468 struct s3c_hsotg *hsotg;
3296 struct resource *res; 3469 struct resource *res;
3297 int epnum; 3470 int epnum;
3298 int ret; 3471 int ret;
3472 int i;
3299 3473
3300 if (!plat) 3474 plat = pdev->dev.platform_data;
3301 plat = &s3c_hsotg_default_pdata; 3475 if (!plat) {
3476 dev_err(&pdev->dev, "no platform data defined\n");
3477 return -EINVAL;
3478 }
3302 3479
3303 hsotg = kzalloc(sizeof(struct s3c_hsotg) + 3480 hsotg = kzalloc(sizeof(struct s3c_hsotg), GFP_KERNEL);
3304 sizeof(struct s3c_hsotg_ep) * S3C_HSOTG_EPS,
3305 GFP_KERNEL);
3306 if (!hsotg) { 3481 if (!hsotg) {
3307 dev_err(dev, "cannot get memory\n"); 3482 dev_err(dev, "cannot get memory\n");
3308 return -ENOMEM; 3483 return -ENOMEM;
@@ -3368,6 +3543,54 @@ static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
3368 3543
3369 hsotg->gadget.dev.parent = dev; 3544 hsotg->gadget.dev.parent = dev;
3370 hsotg->gadget.dev.dma_mask = dev->dma_mask; 3545 hsotg->gadget.dev.dma_mask = dev->dma_mask;
3546 hsotg->gadget.dev.release = s3c_hsotg_release;
3547
3548 /* reset the system */
3549
3550 clk_prepare_enable(hsotg->clk);
3551
3552 /* regulators */
3553
3554 for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
3555 hsotg->supplies[i].supply = s3c_hsotg_supply_names[i];
3556
3557 ret = regulator_bulk_get(dev, ARRAY_SIZE(hsotg->supplies),
3558 hsotg->supplies);
3559 if (ret) {
3560 dev_err(dev, "failed to request supplies: %d\n", ret);
3561 goto err_irq;
3562 }
3563
3564 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3565 hsotg->supplies);
3566
3567 if (ret) {
3568 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
3569 goto err_supplies;
3570 }
3571
3572 /* usb phy enable */
3573 s3c_hsotg_phy_enable(hsotg);
3574
3575 s3c_hsotg_corereset(hsotg);
3576 s3c_hsotg_init(hsotg);
3577 s3c_hsotg_hw_cfg(hsotg);
3578
3579 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3580
3581 if (hsotg->num_of_eps == 0) {
3582 dev_err(dev, "wrong number of EPs (zero)\n");
3583 goto err_supplies;
3584 }
3585
3586 eps = kcalloc(hsotg->num_of_eps + 1, sizeof(struct s3c_hsotg_ep),
3587 GFP_KERNEL);
3588 if (!eps) {
3589 dev_err(dev, "cannot get memory\n");
3590 goto err_supplies;
3591 }
3592
3593 hsotg->eps = eps;
3371 3594
3372 /* setup endpoint information */ 3595 /* setup endpoint information */
3373 3596
@@ -3380,39 +3603,47 @@ static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
3380 GFP_KERNEL); 3603 GFP_KERNEL);
3381 if (!hsotg->ctrl_req) { 3604 if (!hsotg->ctrl_req) {
3382 dev_err(dev, "failed to allocate ctrl req\n"); 3605 dev_err(dev, "failed to allocate ctrl req\n");
3383 goto err_regs; 3606 goto err_ep_mem;
3384 } 3607 }
3385 3608
3386 /* reset the system */ 3609 /* initialise the endpoints now the core has been initialised */
3610 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++)
3611 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
3387 3612
3388 clk_enable(hsotg->clk); 3613 /* disable power and clock */
3389 3614
3390 s3c_hsotg_gate(pdev, true); 3615 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3616 hsotg->supplies);
3617 if (ret) {
3618 dev_err(hsotg->dev, "failed to disable supplies: %d\n", ret);
3619 goto err_ep_mem;
3620 }
3391 3621
3392 s3c_hsotg_otgreset(hsotg); 3622 s3c_hsotg_phy_disable(hsotg);
3393 s3c_hsotg_corereset(hsotg);
3394 s3c_hsotg_init(hsotg);
3395 3623
3396 /* initialise the endpoints now the core has been initialised */ 3624 ret = device_add(&hsotg->gadget.dev);
3397 for (epnum = 0; epnum < S3C_HSOTG_EPS; epnum++) 3625 if (ret) {
3398 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum); 3626 put_device(&hsotg->gadget.dev);
3627 goto err_ep_mem;
3628 }
3399 3629
3400 ret = usb_add_gadget_udc(&pdev->dev, &hsotg->gadget); 3630 ret = usb_add_gadget_udc(&pdev->dev, &hsotg->gadget);
3401 if (ret) 3631 if (ret)
3402 goto err_add_udc; 3632 goto err_ep_mem;
3403 3633
3404 s3c_hsotg_create_debug(hsotg); 3634 s3c_hsotg_create_debug(hsotg);
3405 3635
3406 s3c_hsotg_dump(hsotg); 3636 s3c_hsotg_dump(hsotg);
3407 3637
3408 our_hsotg = hsotg;
3409 return 0; 3638 return 0;
3410 3639
3411err_add_udc: 3640err_ep_mem:
3412 s3c_hsotg_gate(pdev, false); 3641 kfree(eps);
3413 clk_disable(hsotg->clk); 3642err_supplies:
3414 clk_put(hsotg->clk); 3643 s3c_hsotg_phy_disable(hsotg);
3415 3644 regulator_bulk_free(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
3645err_irq:
3646 free_irq(hsotg->irq, hsotg);
3416err_regs: 3647err_regs:
3417 iounmap(hsotg->regs); 3648 iounmap(hsotg->regs);
3418 3649
@@ -3420,12 +3651,17 @@ err_regs_res:
3420 release_resource(hsotg->regs_res); 3651 release_resource(hsotg->regs_res);
3421 kfree(hsotg->regs_res); 3652 kfree(hsotg->regs_res);
3422err_clk: 3653err_clk:
3654 clk_disable_unprepare(hsotg->clk);
3423 clk_put(hsotg->clk); 3655 clk_put(hsotg->clk);
3424err_mem: 3656err_mem:
3425 kfree(hsotg); 3657 kfree(hsotg);
3426 return ret; 3658 return ret;
3427} 3659}
3428 3660
3661/**
3662 * s3c_hsotg_remove - remove function for hsotg driver
3663 * @pdev: The platform information for the driver
3664 */
3429static int __devexit s3c_hsotg_remove(struct platform_device *pdev) 3665static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
3430{ 3666{
3431 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev); 3667 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
@@ -3434,7 +3670,10 @@ static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
3434 3670
3435 s3c_hsotg_delete_debug(hsotg); 3671 s3c_hsotg_delete_debug(hsotg);
3436 3672
3437 usb_gadget_unregister_driver(hsotg->driver); 3673 if (hsotg->driver) {
3674 /* should have been done already by driver model core */
3675 usb_gadget_unregister_driver(hsotg->driver);
3676 }
3438 3677
3439 free_irq(hsotg->irq, hsotg); 3678 free_irq(hsotg->irq, hsotg);
3440 iounmap(hsotg->regs); 3679 iounmap(hsotg->regs);
@@ -3442,12 +3681,13 @@ static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
3442 release_resource(hsotg->regs_res); 3681 release_resource(hsotg->regs_res);
3443 kfree(hsotg->regs_res); 3682 kfree(hsotg->regs_res);
3444 3683
3445 s3c_hsotg_gate(pdev, false); 3684 s3c_hsotg_phy_disable(hsotg);
3685 regulator_bulk_free(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
3446 3686
3447 clk_disable(hsotg->clk); 3687 clk_disable_unprepare(hsotg->clk);
3448 clk_put(hsotg->clk); 3688 clk_put(hsotg->clk);
3449 3689
3450 kfree(hsotg); 3690 device_unregister(&hsotg->gadget.dev);
3451 return 0; 3691 return 0;
3452} 3692}
3453 3693
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-27 00:35:22 -0500