diff options
Diffstat (limited to 'drivers/tty/serial/sh-sci.h')
-rw-r--r-- | drivers/tty/serial/sh-sci.h | 660 |
1 files changed, 660 insertions, 0 deletions
diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h new file mode 100644 index 00000000000..4bc614e4221 --- /dev/null +++ b/drivers/tty/serial/sh-sci.h | |||
@@ -0,0 +1,660 @@ | |||
1 | #include <linux/serial_core.h> | ||
2 | #include <linux/io.h> | ||
3 | #include <linux/gpio.h> | ||
4 | |||
5 | #if defined(CONFIG_H83007) || defined(CONFIG_H83068) | ||
6 | #include <asm/regs306x.h> | ||
7 | #endif | ||
8 | #if defined(CONFIG_H8S2678) | ||
9 | #include <asm/regs267x.h> | ||
10 | #endif | ||
11 | |||
12 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ | ||
13 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | ||
14 | defined(CONFIG_CPU_SUBTYPE_SH7708) || \ | ||
15 | defined(CONFIG_CPU_SUBTYPE_SH7709) | ||
16 | # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ | ||
17 | # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ | ||
18 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | ||
19 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) | ||
20 | # define SCIF0 0xA4400000 | ||
21 | # define SCIF2 0xA4410000 | ||
22 | # define SCSMR_Ir 0xA44A0000 | ||
23 | # define IRDA_SCIF SCIF0 | ||
24 | # define SCPCR 0xA4000116 | ||
25 | # define SCPDR 0xA4000136 | ||
26 | |||
27 | /* Set the clock source, | ||
28 | * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input | ||
29 | * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output | ||
30 | */ | ||
31 | # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 | ||
32 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | ||
33 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ | ||
34 | defined(CONFIG_ARCH_SH73A0) || \ | ||
35 | defined(CONFIG_ARCH_SH7367) || \ | ||
36 | defined(CONFIG_ARCH_SH7377) || \ | ||
37 | defined(CONFIG_ARCH_SH7372) | ||
38 | # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ | ||
39 | # define PORT_PTCR 0xA405011EUL | ||
40 | # define PORT_PVCR 0xA4050122UL | ||
41 | # define SCIF_ORER 0x0200 /* overrun error bit */ | ||
42 | #elif defined(CONFIG_SH_RTS7751R2D) | ||
43 | # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */ | ||
44 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ | ||
45 | # define SCIF_ORER 0x0001 /* overrun error bit */ | ||
46 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
47 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ | ||
48 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | ||
49 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | ||
50 | defined(CONFIG_CPU_SUBTYPE_SH7091) || \ | ||
51 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | ||
52 | defined(CONFIG_CPU_SUBTYPE_SH7751R) | ||
53 | # define SCSPTR1 0xffe0001c /* 8 bit SCI */ | ||
54 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ | ||
55 | # define SCIF_ORER 0x0001 /* overrun error bit */ | ||
56 | # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ | ||
57 | 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ | ||
58 | 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) | ||
59 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) | ||
60 | # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ | ||
61 | # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ | ||
62 | # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ | ||
63 | # define SCIF_ORER 0x0001 /* overrun error bit */ | ||
64 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
65 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) | ||
66 | # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ | ||
67 | # define SCIF_ORER 0x0001 /* overrun error bit */ | ||
68 | # define PACR 0xa4050100 | ||
69 | # define PBCR 0xa4050102 | ||
70 | # define SCSCR_INIT(port) 0x3B | ||
71 | #elif defined(CONFIG_CPU_SUBTYPE_SH7343) | ||
72 | # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ | ||
73 | # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ | ||
74 | # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ | ||
75 | # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ | ||
76 | # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ | ||
77 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) | ||
78 | # define PADR 0xA4050120 | ||
79 | # define PSDR 0xA405013e | ||
80 | # define PWDR 0xA4050166 | ||
81 | # define PSCR 0xA405011E | ||
82 | # define SCIF_ORER 0x0001 /* overrun error bit */ | ||
83 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
84 | #elif defined(CONFIG_CPU_SUBTYPE_SH7366) | ||
85 | # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ | ||
86 | # define SCSPTR0 SCPDR0 | ||
87 | # define SCIF_ORER 0x0001 /* overrun error bit */ | ||
88 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
89 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) | ||
90 | # define SCSPTR0 0xa4050160 | ||
91 | # define SCSPTR1 0xa405013e | ||
92 | # define SCSPTR2 0xa4050160 | ||
93 | # define SCSPTR3 0xa405013e | ||
94 | # define SCSPTR4 0xa4050128 | ||
95 | # define SCSPTR5 0xa4050128 | ||
96 | # define SCIF_ORER 0x0001 /* overrun error bit */ | ||
97 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
98 | #elif defined(CONFIG_CPU_SUBTYPE_SH7724) | ||
99 | # define SCIF_ORER 0x0001 /* overrun error bit */ | ||
100 | # define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \ | ||
101 | 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ | ||
102 | 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) | ||
103 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) | ||
104 | # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ | ||
105 | # define SCIF_ORER 0x0001 /* overrun error bit */ | ||
106 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
107 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) | ||
108 | # define SCIF_BASE_ADDR 0x01030000 | ||
109 | # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR | ||
110 | # define SCIF_PTR2_OFFS 0x0000020 | ||
111 | # define SCIF_LSR2_OFFS 0x0000024 | ||
112 | # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ | ||
113 | # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ | ||
114 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ | ||
115 | #elif defined(CONFIG_H83007) || defined(CONFIG_H83068) | ||
116 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | ||
117 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) | ||
118 | #elif defined(CONFIG_H8S2678) | ||
119 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ | ||
120 | # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) | ||
121 | #elif defined(CONFIG_CPU_SUBTYPE_SH7757) | ||
122 | # define SCSPTR0 0xfe4b0020 | ||
123 | # define SCSPTR1 0xfe4b0020 | ||
124 | # define SCSPTR2 0xfe4b0020 | ||
125 | # define SCIF_ORER 0x0001 | ||
126 | # define SCSCR_INIT(port) 0x38 | ||
127 | # define SCIF_ONLY | ||
128 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) | ||
129 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ | ||
130 | # define SCSPTR1 0xffe08024 /* 16 bit SCIF */ | ||
131 | # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ | ||
132 | # define SCIF_ORER 0x0001 /* overrun error bit */ | ||
133 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
134 | #elif defined(CONFIG_CPU_SUBTYPE_SH7770) | ||
135 | # define SCSPTR0 0xff923020 /* 16 bit SCIF */ | ||
136 | # define SCSPTR1 0xff924020 /* 16 bit SCIF */ | ||
137 | # define SCSPTR2 0xff925020 /* 16 bit SCIF */ | ||
138 | # define SCIF_ORER 0x0001 /* overrun error bit */ | ||
139 | # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ | ||
140 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) | ||
141 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ | ||
142 | # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ | ||
143 | # define SCIF_ORER 0x0001 /* Overrun error bit */ | ||
144 | |||
145 | #if defined(CONFIG_SH_SH2007) | ||
146 | /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */ | ||
147 | # define SCSCR_INIT(port) 0x38 | ||
148 | #else | ||
149 | /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */ | ||
150 | # define SCSCR_INIT(port) 0x3a | ||
151 | #endif | ||
152 | |||
153 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \ | ||
154 | defined(CONFIG_CPU_SUBTYPE_SH7786) | ||
155 | # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ | ||
156 | # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ | ||
157 | # define SCSPTR2 0xffec0024 /* 16 bit SCIF */ | ||
158 | # define SCSPTR3 0xffed0024 /* 16 bit SCIF */ | ||
159 | # define SCSPTR4 0xffee0024 /* 16 bit SCIF */ | ||
160 | # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ | ||
161 | # define SCIF_ORER 0x0001 /* Overrun error bit */ | ||
162 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
163 | #elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \ | ||
164 | defined(CONFIG_CPU_SUBTYPE_SH7203) || \ | ||
165 | defined(CONFIG_CPU_SUBTYPE_SH7206) || \ | ||
166 | defined(CONFIG_CPU_SUBTYPE_SH7263) | ||
167 | # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ | ||
168 | # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ | ||
169 | # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ | ||
170 | # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ | ||
171 | # if defined(CONFIG_CPU_SUBTYPE_SH7201) | ||
172 | # define SCSPTR4 0xfffeA020 /* 16 bit SCIF */ | ||
173 | # define SCSPTR5 0xfffeA820 /* 16 bit SCIF */ | ||
174 | # define SCSPTR6 0xfffeB020 /* 16 bit SCIF */ | ||
175 | # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ | ||
176 | # endif | ||
177 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
178 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) | ||
179 | # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ | ||
180 | # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ | ||
181 | # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ | ||
182 | # define SCIF_ORER 0x0001 /* overrun error bit */ | ||
183 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
184 | #elif defined(CONFIG_CPU_SUBTYPE_SHX3) | ||
185 | # define SCSPTR0 0xffc30020 /* 16 bit SCIF */ | ||
186 | # define SCSPTR1 0xffc40020 /* 16 bit SCIF */ | ||
187 | # define SCSPTR2 0xffc50020 /* 16 bit SCIF */ | ||
188 | # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ | ||
189 | # define SCIF_ORER 0x0001 /* Overrun error bit */ | ||
190 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ | ||
191 | #else | ||
192 | # error CPU subtype not defined | ||
193 | #endif | ||
194 | |||
195 | /* SCSCR */ | ||
196 | #define SCI_CTRL_FLAGS_TIE 0x80 /* all */ | ||
197 | #define SCI_CTRL_FLAGS_RIE 0x40 /* all */ | ||
198 | #define SCI_CTRL_FLAGS_TE 0x20 /* all */ | ||
199 | #define SCI_CTRL_FLAGS_RE 0x10 /* all */ | ||
200 | #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ | ||
201 | defined(CONFIG_CPU_SUBTYPE_SH7091) || \ | ||
202 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | ||
203 | defined(CONFIG_CPU_SUBTYPE_SH7722) || \ | ||
204 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | ||
205 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | ||
206 | defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ | ||
207 | defined(CONFIG_CPU_SUBTYPE_SH7763) || \ | ||
208 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | ||
209 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ | ||
210 | defined(CONFIG_CPU_SUBTYPE_SH7786) || \ | ||
211 | defined(CONFIG_CPU_SUBTYPE_SHX3) | ||
212 | #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ | ||
213 | #elif defined(CONFIG_CPU_SUBTYPE_SH7724) | ||
214 | #define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8) | ||
215 | #else | ||
216 | #define SCI_CTRL_FLAGS_REIE 0 | ||
217 | #endif | ||
218 | /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | ||
219 | /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | ||
220 | /* SCI_CTRL_FLAGS_CKE1 0x02 * all */ | ||
221 | /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */ | ||
222 | |||
223 | /* SCxSR SCI */ | ||
224 | #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | ||
225 | #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | ||
226 | #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | ||
227 | #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | ||
228 | #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | ||
229 | #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | ||
230 | /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | ||
231 | /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ | ||
232 | |||
233 | #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER) | ||
234 | |||
235 | /* SCxSR SCIF */ | ||
236 | #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | ||
237 | #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | ||
238 | #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | ||
239 | #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | ||
240 | #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | ||
241 | #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | ||
242 | #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | ||
243 | #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ | ||
244 | |||
245 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | ||
246 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | ||
247 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ | ||
248 | defined(CONFIG_ARCH_SH73A0) || \ | ||
249 | defined(CONFIG_ARCH_SH7367) || \ | ||
250 | defined(CONFIG_ARCH_SH7377) || \ | ||
251 | defined(CONFIG_ARCH_SH7372) | ||
252 | # define SCIF_ORER 0x0200 | ||
253 | # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) | ||
254 | # define SCIF_RFDC_MASK 0x007f | ||
255 | # define SCIF_TXROOM_MAX 64 | ||
256 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) | ||
257 | # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK ) | ||
258 | # define SCIF_RFDC_MASK 0x007f | ||
259 | # define SCIF_TXROOM_MAX 64 | ||
260 | /* SH7763 SCIF2 support */ | ||
261 | # define SCIF2_RFDC_MASK 0x001f | ||
262 | # define SCIF2_TXROOM_MAX 16 | ||
263 | #else | ||
264 | # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) | ||
265 | # define SCIF_RFDC_MASK 0x001f | ||
266 | # define SCIF_TXROOM_MAX 16 | ||
267 | #endif | ||
268 | |||
269 | #ifndef SCIF_ORER | ||
270 | #define SCIF_ORER 0x0000 | ||
271 | #endif | ||
272 | |||
273 | #define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) | ||
274 | #define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) | ||
275 | #define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) | ||
276 | #define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) | ||
277 | #define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) | ||
278 | #define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) | ||
279 | #define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) | ||
280 | #define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) | ||
281 | |||
282 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | ||
283 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | ||
284 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ | ||
285 | defined(CONFIG_ARCH_SH73A0) || \ | ||
286 | defined(CONFIG_ARCH_SH7367) || \ | ||
287 | defined(CONFIG_ARCH_SH7377) || \ | ||
288 | defined(CONFIG_ARCH_SH7372) | ||
289 | # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) | ||
290 | # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) | ||
291 | # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) | ||
292 | # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3) | ||
293 | #else | ||
294 | # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) | ||
295 | # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) | ||
296 | # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) | ||
297 | # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3) | ||
298 | #endif | ||
299 | |||
300 | /* SCFCR */ | ||
301 | #define SCFCR_RFRST 0x0002 | ||
302 | #define SCFCR_TFRST 0x0004 | ||
303 | #define SCFCR_TCRST 0x4000 | ||
304 | #define SCFCR_MCE 0x0008 | ||
305 | |||
306 | #define SCI_MAJOR 204 | ||
307 | #define SCI_MINOR_START 8 | ||
308 | |||
309 | /* Generic serial flags */ | ||
310 | #define SCI_RX_THROTTLE 0x0000001 | ||
311 | |||
312 | #define SCI_MAGIC 0xbabeface | ||
313 | |||
314 | /* | ||
315 | * Events are used to schedule things to happen at timer-interrupt | ||
316 | * time, instead of at rs interrupt time. | ||
317 | */ | ||
318 | #define SCI_EVENT_WRITE_WAKEUP 0 | ||
319 | |||
320 | #define SCI_IN(size, offset) \ | ||
321 | if ((size) == 8) { \ | ||
322 | return ioread8(port->membase + (offset)); \ | ||
323 | } else { \ | ||
324 | return ioread16(port->membase + (offset)); \ | ||
325 | } | ||
326 | #define SCI_OUT(size, offset, value) \ | ||
327 | if ((size) == 8) { \ | ||
328 | iowrite8(value, port->membase + (offset)); \ | ||
329 | } else if ((size) == 16) { \ | ||
330 | iowrite16(value, port->membase + (offset)); \ | ||
331 | } | ||
332 | |||
333 | #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ | ||
334 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ | ||
335 | { \ | ||
336 | if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \ | ||
337 | SCI_IN(scif_size, scif_offset) \ | ||
338 | } else { /* PORT_SCI or PORT_SCIFA */ \ | ||
339 | SCI_IN(sci_size, sci_offset); \ | ||
340 | } \ | ||
341 | } \ | ||
342 | static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ | ||
343 | { \ | ||
344 | if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \ | ||
345 | SCI_OUT(scif_size, scif_offset, value) \ | ||
346 | } else { /* PORT_SCI or PORT_SCIFA */ \ | ||
347 | SCI_OUT(sci_size, sci_offset, value); \ | ||
348 | } \ | ||
349 | } | ||
350 | |||
351 | #ifdef CONFIG_H8300 | ||
352 | /* h8300 don't have SCIF */ | ||
353 | #define CPU_SCIF_FNS(name) \ | ||
354 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ | ||
355 | { \ | ||
356 | return 0; \ | ||
357 | } \ | ||
358 | static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ | ||
359 | { \ | ||
360 | } | ||
361 | #else | ||
362 | #define CPU_SCIF_FNS(name, scif_offset, scif_size) \ | ||
363 | static inline unsigned int sci_##name##_in(struct uart_port *port) \ | ||
364 | { \ | ||
365 | SCI_IN(scif_size, scif_offset); \ | ||
366 | } \ | ||
367 | static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \ | ||
368 | { \ | ||
369 | SCI_OUT(scif_size, scif_offset, value); \ | ||
370 | } | ||
371 | #endif | ||
372 | |||
373 | #define CPU_SCI_FNS(name, sci_offset, sci_size) \ | ||
374 | static inline unsigned int sci_##name##_in(struct uart_port* port) \ | ||
375 | { \ | ||
376 | SCI_IN(sci_size, sci_offset); \ | ||
377 | } \ | ||
378 | static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \ | ||
379 | { \ | ||
380 | SCI_OUT(sci_size, sci_offset, value); \ | ||
381 | } | ||
382 | |||
383 | #if defined(CONFIG_CPU_SH3) || \ | ||
384 | defined(CONFIG_ARCH_SH73A0) || \ | ||
385 | defined(CONFIG_ARCH_SH7367) || \ | ||
386 | defined(CONFIG_ARCH_SH7377) || \ | ||
387 | defined(CONFIG_ARCH_SH7372) | ||
388 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) | ||
389 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | ||
390 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | ||
391 | h8_sci_offset, h8_sci_size) \ | ||
392 | CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) | ||
393 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ | ||
394 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | ||
395 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | ||
396 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | ||
397 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ | ||
398 | defined(CONFIG_ARCH_SH73A0) || \ | ||
399 | defined(CONFIG_ARCH_SH7367) || \ | ||
400 | defined(CONFIG_ARCH_SH7377) | ||
401 | #define SCIF_FNS(name, scif_offset, scif_size) \ | ||
402 | CPU_SCIF_FNS(name, scif_offset, scif_size) | ||
403 | #elif defined(CONFIG_ARCH_SH7372) | ||
404 | #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size) \ | ||
405 | CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size) | ||
406 | #define SCIF_FNS(name, scif_offset, scif_size) \ | ||
407 | CPU_SCIF_FNS(name, scif_offset, scif_size) | ||
408 | #else | ||
409 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | ||
410 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | ||
411 | h8_sci_offset, h8_sci_size) \ | ||
412 | CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size) | ||
413 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ | ||
414 | CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) | ||
415 | #endif | ||
416 | #elif defined(__H8300H__) || defined(__H8300S__) | ||
417 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | ||
418 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | ||
419 | h8_sci_offset, h8_sci_size) \ | ||
420 | CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) | ||
421 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ | ||
422 | CPU_SCIF_FNS(name) | ||
423 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ | ||
424 | defined(CONFIG_CPU_SUBTYPE_SH7724) | ||
425 | #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \ | ||
426 | CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) | ||
427 | #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ | ||
428 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | ||
429 | #else | ||
430 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \ | ||
431 | sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ | ||
432 | h8_sci_offset, h8_sci_size) \ | ||
433 | CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size) | ||
434 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ | ||
435 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) | ||
436 | #endif | ||
437 | |||
438 | #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | ||
439 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | ||
440 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ | ||
441 | defined(CONFIG_ARCH_SH73A0) || \ | ||
442 | defined(CONFIG_ARCH_SH7367) || \ | ||
443 | defined(CONFIG_ARCH_SH7377) | ||
444 | |||
445 | SCIF_FNS(SCSMR, 0x00, 16) | ||
446 | SCIF_FNS(SCBRR, 0x04, 8) | ||
447 | SCIF_FNS(SCSCR, 0x08, 16) | ||
448 | SCIF_FNS(SCTDSR, 0x0c, 8) | ||
449 | SCIF_FNS(SCFER, 0x10, 16) | ||
450 | SCIF_FNS(SCxSR, 0x14, 16) | ||
451 | SCIF_FNS(SCFCR, 0x18, 16) | ||
452 | SCIF_FNS(SCFDR, 0x1c, 16) | ||
453 | SCIF_FNS(SCxTDR, 0x20, 8) | ||
454 | SCIF_FNS(SCxRDR, 0x24, 8) | ||
455 | SCIF_FNS(SCLSR, 0x00, 0) | ||
456 | #elif defined(CONFIG_ARCH_SH7372) | ||
457 | SCIF_FNS(SCSMR, 0x00, 16) | ||
458 | SCIF_FNS(SCBRR, 0x04, 8) | ||
459 | SCIF_FNS(SCSCR, 0x08, 16) | ||
460 | SCIF_FNS(SCTDSR, 0x0c, 16) | ||
461 | SCIF_FNS(SCFER, 0x10, 16) | ||
462 | SCIF_FNS(SCxSR, 0x14, 16) | ||
463 | SCIF_FNS(SCFCR, 0x18, 16) | ||
464 | SCIF_FNS(SCFDR, 0x1c, 16) | ||
465 | SCIF_FNS(SCTFDR, 0x38, 16) | ||
466 | SCIF_FNS(SCRFDR, 0x3c, 16) | ||
467 | SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8) | ||
468 | SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8) | ||
469 | SCIF_FNS(SCLSR, 0x00, 0) | ||
470 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ | ||
471 | defined(CONFIG_CPU_SUBTYPE_SH7724) | ||
472 | SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) | ||
473 | SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8) | ||
474 | SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16) | ||
475 | SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8) | ||
476 | SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16) | ||
477 | SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8) | ||
478 | SCIx_FNS(SCSPTR, 0, 0, 0, 0) | ||
479 | SCIF_FNS(SCTDSR, 0x0c, 8) | ||
480 | SCIF_FNS(SCFER, 0x10, 16) | ||
481 | SCIF_FNS(SCFCR, 0x18, 16) | ||
482 | SCIF_FNS(SCFDR, 0x1c, 16) | ||
483 | SCIF_FNS(SCLSR, 0x24, 16) | ||
484 | #else | ||
485 | /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ | ||
486 | /* name off sz off sz off sz off sz off sz*/ | ||
487 | SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8) | ||
488 | SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8) | ||
489 | SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8) | ||
490 | SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) | ||
491 | SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) | ||
492 | SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) | ||
493 | SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) | ||
494 | #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ | ||
495 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | ||
496 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ | ||
497 | defined(CONFIG_CPU_SUBTYPE_SH7786) | ||
498 | SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) | ||
499 | SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) | ||
500 | SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) | ||
501 | SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) | ||
502 | SCIF_FNS(SCLSR, 0, 0, 0x28, 16) | ||
503 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) | ||
504 | SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) | ||
505 | SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16) | ||
506 | SCIF_FNS(SCLSR2, 0, 0, 0x24, 16) | ||
507 | SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) | ||
508 | SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) | ||
509 | SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) | ||
510 | SCIF_FNS(SCLSR, 0, 0, 0x28, 16) | ||
511 | #else | ||
512 | SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) | ||
513 | #if defined(CONFIG_CPU_SUBTYPE_SH7722) | ||
514 | SCIF_FNS(SCSPTR, 0, 0, 0, 0) | ||
515 | #else | ||
516 | SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) | ||
517 | #endif | ||
518 | SCIF_FNS(SCLSR, 0, 0, 0x24, 16) | ||
519 | #endif | ||
520 | #endif | ||
521 | #define sci_in(port, reg) sci_##reg##_in(port) | ||
522 | #define sci_out(port, reg, value) sci_##reg##_out(port, value) | ||
523 | |||
524 | /* H8/300 series SCI pins assignment */ | ||
525 | #if defined(__H8300H__) || defined(__H8300S__) | ||
526 | static const struct __attribute__((packed)) { | ||
527 | int port; /* GPIO port no */ | ||
528 | unsigned short rx,tx; /* GPIO bit no */ | ||
529 | } h8300_sci_pins[] = { | ||
530 | #if defined(CONFIG_H83007) || defined(CONFIG_H83068) | ||
531 | { /* SCI0 */ | ||
532 | .port = H8300_GPIO_P9, | ||
533 | .rx = H8300_GPIO_B2, | ||
534 | .tx = H8300_GPIO_B0, | ||
535 | }, | ||
536 | { /* SCI1 */ | ||
537 | .port = H8300_GPIO_P9, | ||
538 | .rx = H8300_GPIO_B3, | ||
539 | .tx = H8300_GPIO_B1, | ||
540 | }, | ||
541 | { /* SCI2 */ | ||
542 | .port = H8300_GPIO_PB, | ||
543 | .rx = H8300_GPIO_B7, | ||
544 | .tx = H8300_GPIO_B6, | ||
545 | } | ||
546 | #elif defined(CONFIG_H8S2678) | ||
547 | { /* SCI0 */ | ||
548 | .port = H8300_GPIO_P3, | ||
549 | .rx = H8300_GPIO_B2, | ||
550 | .tx = H8300_GPIO_B0, | ||
551 | }, | ||
552 | { /* SCI1 */ | ||
553 | .port = H8300_GPIO_P3, | ||
554 | .rx = H8300_GPIO_B3, | ||
555 | .tx = H8300_GPIO_B1, | ||
556 | }, | ||
557 | { /* SCI2 */ | ||
558 | .port = H8300_GPIO_P5, | ||
559 | .rx = H8300_GPIO_B1, | ||
560 | .tx = H8300_GPIO_B0, | ||
561 | } | ||
562 | #endif | ||
563 | }; | ||
564 | #endif | ||
565 | |||
566 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ | ||
567 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | ||
568 | defined(CONFIG_CPU_SUBTYPE_SH7708) || \ | ||
569 | defined(CONFIG_CPU_SUBTYPE_SH7709) | ||
570 | static inline int sci_rxd_in(struct uart_port *port) | ||
571 | { | ||
572 | if (port->mapbase == 0xfffffe80) | ||
573 | return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */ | ||
574 | return 1; | ||
575 | } | ||
576 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ | ||
577 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | ||
578 | defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ | ||
579 | defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | ||
580 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | ||
581 | defined(CONFIG_CPU_SUBTYPE_SH7091) | ||
582 | static inline int sci_rxd_in(struct uart_port *port) | ||
583 | { | ||
584 | if (port->mapbase == 0xffe00000) | ||
585 | return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ | ||
586 | return 1; | ||
587 | } | ||
588 | #elif defined(__H8300H__) || defined(__H8300S__) | ||
589 | static inline int sci_rxd_in(struct uart_port *port) | ||
590 | { | ||
591 | int ch = (port->mapbase - SMR0) >> 3; | ||
592 | return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; | ||
593 | } | ||
594 | #else /* default case for non-SCI processors */ | ||
595 | static inline int sci_rxd_in(struct uart_port *port) | ||
596 | { | ||
597 | return 1; | ||
598 | } | ||
599 | #endif | ||
600 | |||
601 | /* | ||
602 | * Values for the BitRate Register (SCBRR) | ||
603 | * | ||
604 | * The values are actually divisors for a frequency which can | ||
605 | * be internal to the SH3 (14.7456MHz) or derived from an external | ||
606 | * clock source. This driver assumes the internal clock is used; | ||
607 | * to support using an external clock source, config options or | ||
608 | * possibly command-line options would need to be added. | ||
609 | * | ||
610 | * Also, to support speeds below 2400 (why?) the lower 2 bits of | ||
611 | * the SCSMR register would also need to be set to non-zero values. | ||
612 | * | ||
613 | * -- Greg Banks 27Feb2000 | ||
614 | * | ||
615 | * Answer: The SCBRR register is only eight bits, and the value in | ||
616 | * it gets larger with lower baud rates. At around 2400 (depending on | ||
617 | * the peripherial module clock) you run out of bits. However the | ||
618 | * lower two bits of SCSMR allow the module clock to be divided down, | ||
619 | * scaling the value which is needed in SCBRR. | ||
620 | * | ||
621 | * -- Stuart Menefy - 23 May 2000 | ||
622 | * | ||
623 | * I meant, why would anyone bother with bitrates below 2400. | ||
624 | * | ||
625 | * -- Greg Banks - 7Jul2000 | ||
626 | * | ||
627 | * You "speedist"! How will I use my 110bps ASR-33 teletype with paper | ||
628 | * tape reader as a console! | ||
629 | * | ||
630 | * -- Mitch Davis - 15 Jul 2000 | ||
631 | */ | ||
632 | |||
633 | #if (defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | ||
634 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ | ||
635 | defined(CONFIG_CPU_SUBTYPE_SH7786)) && \ | ||
636 | !defined(CONFIG_SH_SH2007) | ||
637 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) | ||
638 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | ||
639 | defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | ||
640 | defined(CONFIG_CPU_SUBTYPE_SH7721) || \ | ||
641 | defined(CONFIG_ARCH_SH73A0) || \ | ||
642 | defined(CONFIG_ARCH_SH7367) || \ | ||
643 | defined(CONFIG_ARCH_SH7377) || \ | ||
644 | defined(CONFIG_ARCH_SH7372) | ||
645 | #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) | ||
646 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ | ||
647 | defined(CONFIG_CPU_SUBTYPE_SH7724) | ||
648 | static inline int scbrr_calc(struct uart_port *port, int bps, int clk) | ||
649 | { | ||
650 | if (port->type == PORT_SCIF) | ||
651 | return (clk+16*bps)/(32*bps)-1; | ||
652 | else | ||
653 | return ((clk*2)+16*bps)/(16*bps)-1; | ||
654 | } | ||
655 | #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk) | ||
656 | #elif defined(__H8300H__) || defined(__H8300S__) | ||
657 | #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) | ||
658 | #else /* Generic SH */ | ||
659 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) | ||
660 | #endif | ||