diff options
Diffstat (limited to 'drivers/staging/octeon/cvmx-pcsxx-defs.h')
-rw-r--r-- | drivers/staging/octeon/cvmx-pcsxx-defs.h | 316 |
1 files changed, 0 insertions, 316 deletions
diff --git a/drivers/staging/octeon/cvmx-pcsxx-defs.h b/drivers/staging/octeon/cvmx-pcsxx-defs.h deleted file mode 100644 index 55d120fe8ae..00000000000 --- a/drivers/staging/octeon/cvmx-pcsxx-defs.h +++ /dev/null | |||
@@ -1,316 +0,0 @@ | |||
1 | /***********************license start*************** | ||
2 | * Author: Cavium Networks | ||
3 | * | ||
4 | * Contact: support@caviumnetworks.com | ||
5 | * This file is part of the OCTEON SDK | ||
6 | * | ||
7 | * Copyright (c) 2003-2008 Cavium Networks | ||
8 | * | ||
9 | * This file is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License, Version 2, as | ||
11 | * published by the Free Software Foundation. | ||
12 | * | ||
13 | * This file is distributed in the hope that it will be useful, but | ||
14 | * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or | ||
16 | * NONINFRINGEMENT. See the GNU General Public License for more | ||
17 | * details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this file; if not, write to the Free Software | ||
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
22 | * or visit http://www.gnu.org/licenses/. | ||
23 | * | ||
24 | * This file may also be available under a different license from Cavium. | ||
25 | * Contact Cavium Networks for more information | ||
26 | ***********************license end**************************************/ | ||
27 | |||
28 | #ifndef __CVMX_PCSXX_DEFS_H__ | ||
29 | #define __CVMX_PCSXX_DEFS_H__ | ||
30 | |||
31 | #define CVMX_PCSXX_10GBX_STATUS_REG(block_id) \ | ||
32 | CVMX_ADD_IO_SEG(0x00011800B0000828ull + (((block_id) & 1) * 0x8000000ull)) | ||
33 | #define CVMX_PCSXX_BIST_STATUS_REG(block_id) \ | ||
34 | CVMX_ADD_IO_SEG(0x00011800B0000870ull + (((block_id) & 1) * 0x8000000ull)) | ||
35 | #define CVMX_PCSXX_BIT_LOCK_STATUS_REG(block_id) \ | ||
36 | CVMX_ADD_IO_SEG(0x00011800B0000850ull + (((block_id) & 1) * 0x8000000ull)) | ||
37 | #define CVMX_PCSXX_CONTROL1_REG(block_id) \ | ||
38 | CVMX_ADD_IO_SEG(0x00011800B0000800ull + (((block_id) & 1) * 0x8000000ull)) | ||
39 | #define CVMX_PCSXX_CONTROL2_REG(block_id) \ | ||
40 | CVMX_ADD_IO_SEG(0x00011800B0000818ull + (((block_id) & 1) * 0x8000000ull)) | ||
41 | #define CVMX_PCSXX_INT_EN_REG(block_id) \ | ||
42 | CVMX_ADD_IO_SEG(0x00011800B0000860ull + (((block_id) & 1) * 0x8000000ull)) | ||
43 | #define CVMX_PCSXX_INT_REG(block_id) \ | ||
44 | CVMX_ADD_IO_SEG(0x00011800B0000858ull + (((block_id) & 1) * 0x8000000ull)) | ||
45 | #define CVMX_PCSXX_LOG_ANL_REG(block_id) \ | ||
46 | CVMX_ADD_IO_SEG(0x00011800B0000868ull + (((block_id) & 1) * 0x8000000ull)) | ||
47 | #define CVMX_PCSXX_MISC_CTL_REG(block_id) \ | ||
48 | CVMX_ADD_IO_SEG(0x00011800B0000848ull + (((block_id) & 1) * 0x8000000ull)) | ||
49 | #define CVMX_PCSXX_RX_SYNC_STATES_REG(block_id) \ | ||
50 | CVMX_ADD_IO_SEG(0x00011800B0000838ull + (((block_id) & 1) * 0x8000000ull)) | ||
51 | #define CVMX_PCSXX_SPD_ABIL_REG(block_id) \ | ||
52 | CVMX_ADD_IO_SEG(0x00011800B0000810ull + (((block_id) & 1) * 0x8000000ull)) | ||
53 | #define CVMX_PCSXX_STATUS1_REG(block_id) \ | ||
54 | CVMX_ADD_IO_SEG(0x00011800B0000808ull + (((block_id) & 1) * 0x8000000ull)) | ||
55 | #define CVMX_PCSXX_STATUS2_REG(block_id) \ | ||
56 | CVMX_ADD_IO_SEG(0x00011800B0000820ull + (((block_id) & 1) * 0x8000000ull)) | ||
57 | #define CVMX_PCSXX_TX_RX_POLARITY_REG(block_id) \ | ||
58 | CVMX_ADD_IO_SEG(0x00011800B0000840ull + (((block_id) & 1) * 0x8000000ull)) | ||
59 | #define CVMX_PCSXX_TX_RX_STATES_REG(block_id) \ | ||
60 | CVMX_ADD_IO_SEG(0x00011800B0000830ull + (((block_id) & 1) * 0x8000000ull)) | ||
61 | |||
62 | union cvmx_pcsxx_10gbx_status_reg { | ||
63 | uint64_t u64; | ||
64 | struct cvmx_pcsxx_10gbx_status_reg_s { | ||
65 | uint64_t reserved_13_63:51; | ||
66 | uint64_t alignd:1; | ||
67 | uint64_t pattst:1; | ||
68 | uint64_t reserved_4_10:7; | ||
69 | uint64_t l3sync:1; | ||
70 | uint64_t l2sync:1; | ||
71 | uint64_t l1sync:1; | ||
72 | uint64_t l0sync:1; | ||
73 | } s; | ||
74 | struct cvmx_pcsxx_10gbx_status_reg_s cn52xx; | ||
75 | struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1; | ||
76 | struct cvmx_pcsxx_10gbx_status_reg_s cn56xx; | ||
77 | struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1; | ||
78 | }; | ||
79 | |||
80 | union cvmx_pcsxx_bist_status_reg { | ||
81 | uint64_t u64; | ||
82 | struct cvmx_pcsxx_bist_status_reg_s { | ||
83 | uint64_t reserved_1_63:63; | ||
84 | uint64_t bist_status:1; | ||
85 | } s; | ||
86 | struct cvmx_pcsxx_bist_status_reg_s cn52xx; | ||
87 | struct cvmx_pcsxx_bist_status_reg_s cn52xxp1; | ||
88 | struct cvmx_pcsxx_bist_status_reg_s cn56xx; | ||
89 | struct cvmx_pcsxx_bist_status_reg_s cn56xxp1; | ||
90 | }; | ||
91 | |||
92 | union cvmx_pcsxx_bit_lock_status_reg { | ||
93 | uint64_t u64; | ||
94 | struct cvmx_pcsxx_bit_lock_status_reg_s { | ||
95 | uint64_t reserved_4_63:60; | ||
96 | uint64_t bitlck3:1; | ||
97 | uint64_t bitlck2:1; | ||
98 | uint64_t bitlck1:1; | ||
99 | uint64_t bitlck0:1; | ||
100 | } s; | ||
101 | struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx; | ||
102 | struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1; | ||
103 | struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx; | ||
104 | struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1; | ||
105 | }; | ||
106 | |||
107 | union cvmx_pcsxx_control1_reg { | ||
108 | uint64_t u64; | ||
109 | struct cvmx_pcsxx_control1_reg_s { | ||
110 | uint64_t reserved_16_63:48; | ||
111 | uint64_t reset:1; | ||
112 | uint64_t loopbck1:1; | ||
113 | uint64_t spdsel1:1; | ||
114 | uint64_t reserved_12_12:1; | ||
115 | uint64_t lo_pwr:1; | ||
116 | uint64_t reserved_7_10:4; | ||
117 | uint64_t spdsel0:1; | ||
118 | uint64_t spd:4; | ||
119 | uint64_t reserved_0_1:2; | ||
120 | } s; | ||
121 | struct cvmx_pcsxx_control1_reg_s cn52xx; | ||
122 | struct cvmx_pcsxx_control1_reg_s cn52xxp1; | ||
123 | struct cvmx_pcsxx_control1_reg_s cn56xx; | ||
124 | struct cvmx_pcsxx_control1_reg_s cn56xxp1; | ||
125 | }; | ||
126 | |||
127 | union cvmx_pcsxx_control2_reg { | ||
128 | uint64_t u64; | ||
129 | struct cvmx_pcsxx_control2_reg_s { | ||
130 | uint64_t reserved_2_63:62; | ||
131 | uint64_t type:2; | ||
132 | } s; | ||
133 | struct cvmx_pcsxx_control2_reg_s cn52xx; | ||
134 | struct cvmx_pcsxx_control2_reg_s cn52xxp1; | ||
135 | struct cvmx_pcsxx_control2_reg_s cn56xx; | ||
136 | struct cvmx_pcsxx_control2_reg_s cn56xxp1; | ||
137 | }; | ||
138 | |||
139 | union cvmx_pcsxx_int_en_reg { | ||
140 | uint64_t u64; | ||
141 | struct cvmx_pcsxx_int_en_reg_s { | ||
142 | uint64_t reserved_6_63:58; | ||
143 | uint64_t algnlos_en:1; | ||
144 | uint64_t synlos_en:1; | ||
145 | uint64_t bitlckls_en:1; | ||
146 | uint64_t rxsynbad_en:1; | ||
147 | uint64_t rxbad_en:1; | ||
148 | uint64_t txflt_en:1; | ||
149 | } s; | ||
150 | struct cvmx_pcsxx_int_en_reg_s cn52xx; | ||
151 | struct cvmx_pcsxx_int_en_reg_s cn52xxp1; | ||
152 | struct cvmx_pcsxx_int_en_reg_s cn56xx; | ||
153 | struct cvmx_pcsxx_int_en_reg_s cn56xxp1; | ||
154 | }; | ||
155 | |||
156 | union cvmx_pcsxx_int_reg { | ||
157 | uint64_t u64; | ||
158 | struct cvmx_pcsxx_int_reg_s { | ||
159 | uint64_t reserved_6_63:58; | ||
160 | uint64_t algnlos:1; | ||
161 | uint64_t synlos:1; | ||
162 | uint64_t bitlckls:1; | ||
163 | uint64_t rxsynbad:1; | ||
164 | uint64_t rxbad:1; | ||
165 | uint64_t txflt:1; | ||
166 | } s; | ||
167 | struct cvmx_pcsxx_int_reg_s cn52xx; | ||
168 | struct cvmx_pcsxx_int_reg_s cn52xxp1; | ||
169 | struct cvmx_pcsxx_int_reg_s cn56xx; | ||
170 | struct cvmx_pcsxx_int_reg_s cn56xxp1; | ||
171 | }; | ||
172 | |||
173 | union cvmx_pcsxx_log_anl_reg { | ||
174 | uint64_t u64; | ||
175 | struct cvmx_pcsxx_log_anl_reg_s { | ||
176 | uint64_t reserved_7_63:57; | ||
177 | uint64_t enc_mode:1; | ||
178 | uint64_t drop_ln:2; | ||
179 | uint64_t lafifovfl:1; | ||
180 | uint64_t la_en:1; | ||
181 | uint64_t pkt_sz:2; | ||
182 | } s; | ||
183 | struct cvmx_pcsxx_log_anl_reg_s cn52xx; | ||
184 | struct cvmx_pcsxx_log_anl_reg_s cn52xxp1; | ||
185 | struct cvmx_pcsxx_log_anl_reg_s cn56xx; | ||
186 | struct cvmx_pcsxx_log_anl_reg_s cn56xxp1; | ||
187 | }; | ||
188 | |||
189 | union cvmx_pcsxx_misc_ctl_reg { | ||
190 | uint64_t u64; | ||
191 | struct cvmx_pcsxx_misc_ctl_reg_s { | ||
192 | uint64_t reserved_4_63:60; | ||
193 | uint64_t tx_swap:1; | ||
194 | uint64_t rx_swap:1; | ||
195 | uint64_t xaui:1; | ||
196 | uint64_t gmxeno:1; | ||
197 | } s; | ||
198 | struct cvmx_pcsxx_misc_ctl_reg_s cn52xx; | ||
199 | struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1; | ||
200 | struct cvmx_pcsxx_misc_ctl_reg_s cn56xx; | ||
201 | struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1; | ||
202 | }; | ||
203 | |||
204 | union cvmx_pcsxx_rx_sync_states_reg { | ||
205 | uint64_t u64; | ||
206 | struct cvmx_pcsxx_rx_sync_states_reg_s { | ||
207 | uint64_t reserved_16_63:48; | ||
208 | uint64_t sync3st:4; | ||
209 | uint64_t sync2st:4; | ||
210 | uint64_t sync1st:4; | ||
211 | uint64_t sync0st:4; | ||
212 | } s; | ||
213 | struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx; | ||
214 | struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1; | ||
215 | struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx; | ||
216 | struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1; | ||
217 | }; | ||
218 | |||
219 | union cvmx_pcsxx_spd_abil_reg { | ||
220 | uint64_t u64; | ||
221 | struct cvmx_pcsxx_spd_abil_reg_s { | ||
222 | uint64_t reserved_2_63:62; | ||
223 | uint64_t tenpasst:1; | ||
224 | uint64_t tengb:1; | ||
225 | } s; | ||
226 | struct cvmx_pcsxx_spd_abil_reg_s cn52xx; | ||
227 | struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1; | ||
228 | struct cvmx_pcsxx_spd_abil_reg_s cn56xx; | ||
229 | struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1; | ||
230 | }; | ||
231 | |||
232 | union cvmx_pcsxx_status1_reg { | ||
233 | uint64_t u64; | ||
234 | struct cvmx_pcsxx_status1_reg_s { | ||
235 | uint64_t reserved_8_63:56; | ||
236 | uint64_t flt:1; | ||
237 | uint64_t reserved_3_6:4; | ||
238 | uint64_t rcv_lnk:1; | ||
239 | uint64_t lpable:1; | ||
240 | uint64_t reserved_0_0:1; | ||
241 | } s; | ||
242 | struct cvmx_pcsxx_status1_reg_s cn52xx; | ||
243 | struct cvmx_pcsxx_status1_reg_s cn52xxp1; | ||
244 | struct cvmx_pcsxx_status1_reg_s cn56xx; | ||
245 | struct cvmx_pcsxx_status1_reg_s cn56xxp1; | ||
246 | }; | ||
247 | |||
248 | union cvmx_pcsxx_status2_reg { | ||
249 | uint64_t u64; | ||
250 | struct cvmx_pcsxx_status2_reg_s { | ||
251 | uint64_t reserved_16_63:48; | ||
252 | uint64_t dev:2; | ||
253 | uint64_t reserved_12_13:2; | ||
254 | uint64_t xmtflt:1; | ||
255 | uint64_t rcvflt:1; | ||
256 | uint64_t reserved_3_9:7; | ||
257 | uint64_t tengb_w:1; | ||
258 | uint64_t tengb_x:1; | ||
259 | uint64_t tengb_r:1; | ||
260 | } s; | ||
261 | struct cvmx_pcsxx_status2_reg_s cn52xx; | ||
262 | struct cvmx_pcsxx_status2_reg_s cn52xxp1; | ||
263 | struct cvmx_pcsxx_status2_reg_s cn56xx; | ||
264 | struct cvmx_pcsxx_status2_reg_s cn56xxp1; | ||
265 | }; | ||
266 | |||
267 | union cvmx_pcsxx_tx_rx_polarity_reg { | ||
268 | uint64_t u64; | ||
269 | struct cvmx_pcsxx_tx_rx_polarity_reg_s { | ||
270 | uint64_t reserved_10_63:54; | ||
271 | uint64_t xor_rxplrt:4; | ||
272 | uint64_t xor_txplrt:4; | ||
273 | uint64_t rxplrt:1; | ||
274 | uint64_t txplrt:1; | ||
275 | } s; | ||
276 | struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx; | ||
277 | struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 { | ||
278 | uint64_t reserved_2_63:62; | ||
279 | uint64_t rxplrt:1; | ||
280 | uint64_t txplrt:1; | ||
281 | } cn52xxp1; | ||
282 | struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx; | ||
283 | struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1; | ||
284 | }; | ||
285 | |||
286 | union cvmx_pcsxx_tx_rx_states_reg { | ||
287 | uint64_t u64; | ||
288 | struct cvmx_pcsxx_tx_rx_states_reg_s { | ||
289 | uint64_t reserved_14_63:50; | ||
290 | uint64_t term_err:1; | ||
291 | uint64_t syn3bad:1; | ||
292 | uint64_t syn2bad:1; | ||
293 | uint64_t syn1bad:1; | ||
294 | uint64_t syn0bad:1; | ||
295 | uint64_t rxbad:1; | ||
296 | uint64_t algn_st:3; | ||
297 | uint64_t rx_st:2; | ||
298 | uint64_t tx_st:3; | ||
299 | } s; | ||
300 | struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx; | ||
301 | struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 { | ||
302 | uint64_t reserved_13_63:51; | ||
303 | uint64_t syn3bad:1; | ||
304 | uint64_t syn2bad:1; | ||
305 | uint64_t syn1bad:1; | ||
306 | uint64_t syn0bad:1; | ||
307 | uint64_t rxbad:1; | ||
308 | uint64_t algn_st:3; | ||
309 | uint64_t rx_st:2; | ||
310 | uint64_t tx_st:3; | ||
311 | } cn52xxp1; | ||
312 | struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx; | ||
313 | struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1; | ||
314 | }; | ||
315 | |||
316 | #endif | ||