diff options
Diffstat (limited to 'drivers/staging/et131x/et1310_address_map.h')
-rw-r--r-- | drivers/staging/et131x/et1310_address_map.h | 45 |
1 files changed, 14 insertions, 31 deletions
diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h index b395f9c660e..8aaa62bc113 100644 --- a/drivers/staging/et131x/et1310_address_map.h +++ b/drivers/staging/et131x/et1310_address_map.h | |||
@@ -73,37 +73,20 @@ | |||
73 | /* | 73 | /* |
74 | * structure for power management control status reg in global address map | 74 | * structure for power management control status reg in global address map |
75 | * located at address 0x0010 | 75 | * located at address 0x0010 |
76 | * jagcore_rx_rdy bit 9 | ||
77 | * jagcore_tx_rdy bit 8 | ||
78 | * phy_lped_en bit 7 | ||
79 | * phy_sw_coma bit 6 | ||
80 | * rxclk_gate bit 5 | ||
81 | * txclk_gate bit 4 | ||
82 | * sysclk_gate bit 3 | ||
83 | * jagcore_rx_en bit 2 | ||
84 | * jagcore_tx_en bit 1 | ||
85 | * gigephy_en bit 0 | ||
76 | */ | 86 | */ |
77 | typedef union _PM_CSR_t { | 87 | |
78 | u32 value; | 88 | #define ET_PM_PHY_SW_COMA 0x40 |
79 | struct { | 89 | #define ET_PMCSR_INIT 0x38 |
80 | #ifdef _BIT_FIELDS_HTOL | ||
81 | u32 unused:22; /* bits 10-31 */ | ||
82 | u32 pm_jagcore_rx_rdy:1; /* bit 9 */ | ||
83 | u32 pm_jagcore_tx_rdy:1; /* bit 8 */ | ||
84 | u32 pm_phy_lped_en:1; /* bit 7 */ | ||
85 | u32 pm_phy_sw_coma:1; /* bit 6 */ | ||
86 | u32 pm_rxclk_gate:1; /* bit 5 */ | ||
87 | u32 pm_txclk_gate:1; /* bit 4 */ | ||
88 | u32 pm_sysclk_gate:1; /* bit 3 */ | ||
89 | u32 pm_jagcore_rx_en:1; /* bit 2 */ | ||
90 | u32 pm_jagcore_tx_en:1; /* bit 1 */ | ||
91 | u32 pm_gigephy_en:1; /* bit 0 */ | ||
92 | #else | ||
93 | u32 pm_gigephy_en:1; /* bit 0 */ | ||
94 | u32 pm_jagcore_tx_en:1; /* bit 1 */ | ||
95 | u32 pm_jagcore_rx_en:1; /* bit 2 */ | ||
96 | u32 pm_sysclk_gate:1; /* bit 3 */ | ||
97 | u32 pm_txclk_gate:1; /* bit 4 */ | ||
98 | u32 pm_rxclk_gate:1; /* bit 5 */ | ||
99 | u32 pm_phy_sw_coma:1; /* bit 6 */ | ||
100 | u32 pm_phy_lped_en:1; /* bit 7 */ | ||
101 | u32 pm_jagcore_tx_rdy:1; /* bit 8 */ | ||
102 | u32 pm_jagcore_rx_rdy:1; /* bit 9 */ | ||
103 | u32 unused:22; /* bits 10-31 */ | ||
104 | #endif | ||
105 | } bits; | ||
106 | } PM_CSR_t, *PPM_CSR_t; | ||
107 | 90 | ||
108 | /* | 91 | /* |
109 | * structure for interrupt status reg in global address map | 92 | * structure for interrupt status reg in global address map |
@@ -271,7 +254,7 @@ typedef struct _GLOBAL_t { /* Location: */ | |||
271 | u32 txq_end_addr; /* 0x0004 */ | 254 | u32 txq_end_addr; /* 0x0004 */ |
272 | u32 rxq_start_addr; /* 0x0008 */ | 255 | u32 rxq_start_addr; /* 0x0008 */ |
273 | u32 rxq_end_addr; /* 0x000C */ | 256 | u32 rxq_end_addr; /* 0x000C */ |
274 | PM_CSR_t pm_csr; /* 0x0010 */ | 257 | u32 pm_csr; /* 0x0010 */ |
275 | u32 unused; /* 0x0014 */ | 258 | u32 unused; /* 0x0014 */ |
276 | INTERRUPT_t int_status; /* 0x0018 */ | 259 | INTERRUPT_t int_status; /* 0x0018 */ |
277 | INTERRUPT_t int_mask; /* 0x001C */ | 260 | INTERRUPT_t int_mask; /* 0x001C */ |