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-rw-r--r--drivers/scsi/mvsas/mv_defs.h441
1 files changed, 441 insertions, 0 deletions
diff --git a/drivers/scsi/mvsas/mv_defs.h b/drivers/scsi/mvsas/mv_defs.h
new file mode 100644
index 00000000000..d8e96a3e5a2
--- /dev/null
+++ b/drivers/scsi/mvsas/mv_defs.h
@@ -0,0 +1,441 @@
1/*
2 mv_defs.h - Marvell 88SE6440 SAS/SATA support
3
4 Copyright 2007 Red Hat, Inc.
5 Copyright 2008 Marvell. <kewei@marvell.com>
6
7 This program is free software; you can redistribute it and/or
8 modify it under the terms of the GNU General Public License as
9 published by the Free Software Foundation; either version 2,
10 or (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty
14 of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
15 See the GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public
18 License along with this program; see the file COPYING. If not,
19 write to the Free Software Foundation, 675 Mass Ave, Cambridge,
20 MA 02139, USA.
21
22 */
23
24#ifndef _MV_DEFS_H_
25#define _MV_DEFS_H_
26
27/* driver compile-time configuration */
28enum driver_configuration {
29 MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
30 MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
31 /* software requires power-of-2
32 ring size */
33
34 MVS_SLOTS = 512, /* command slots */
35 MVS_SLOT_BUF_SZ = 8192, /* cmd tbl + IU + status + PRD */
36 MVS_SSP_CMD_SZ = 64, /* SSP command table buffer size */
37 MVS_ATA_CMD_SZ = 96, /* SATA command table buffer size */
38 MVS_OAF_SZ = 64, /* Open address frame buffer size */
39
40 MVS_RX_FIS_COUNT = 17, /* Optional rx'd FISs (max 17) */
41
42 MVS_QUEUE_SIZE = 30, /* Support Queue depth */
43 MVS_CAN_QUEUE = MVS_SLOTS - 1, /* SCSI Queue depth */
44};
45
46/* unchangeable hardware details */
47enum hardware_details {
48 MVS_MAX_PHYS = 8, /* max. possible phys */
49 MVS_MAX_PORTS = 8, /* max. possible ports */
50 MVS_RX_FISL_SZ = 0x400 + (MVS_RX_FIS_COUNT * 0x100),
51};
52
53/* peripheral registers (BAR2) */
54enum peripheral_registers {
55 SPI_CTL = 0x10, /* EEPROM control */
56 SPI_CMD = 0x14, /* EEPROM command */
57 SPI_DATA = 0x18, /* EEPROM data */
58};
59
60enum peripheral_register_bits {
61 TWSI_RDY = (1U << 7), /* EEPROM interface ready */
62 TWSI_RD = (1U << 4), /* EEPROM read access */
63
64 SPI_ADDR_MASK = 0x3ffff, /* bits 17:0 */
65};
66
67enum hw_register_bits {
68 /* MVS_GBL_CTL */
69 INT_EN = (1U << 1), /* Global int enable */
70 HBA_RST = (1U << 0), /* HBA reset */
71
72 /* MVS_GBL_INT_STAT */
73 INT_XOR = (1U << 4), /* XOR engine event */
74 INT_SAS_SATA = (1U << 0), /* SAS/SATA event */
75
76 /* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
77 SATA_TARGET = (1U << 16), /* port0 SATA target enable */
78 MODE_AUTO_DET_PORT7 = (1U << 15), /* port0 SAS/SATA autodetect */
79 MODE_AUTO_DET_PORT6 = (1U << 14),
80 MODE_AUTO_DET_PORT5 = (1U << 13),
81 MODE_AUTO_DET_PORT4 = (1U << 12),
82 MODE_AUTO_DET_PORT3 = (1U << 11),
83 MODE_AUTO_DET_PORT2 = (1U << 10),
84 MODE_AUTO_DET_PORT1 = (1U << 9),
85 MODE_AUTO_DET_PORT0 = (1U << 8),
86 MODE_AUTO_DET_EN = MODE_AUTO_DET_PORT0 | MODE_AUTO_DET_PORT1 |
87 MODE_AUTO_DET_PORT2 | MODE_AUTO_DET_PORT3 |
88 MODE_AUTO_DET_PORT4 | MODE_AUTO_DET_PORT5 |
89 MODE_AUTO_DET_PORT6 | MODE_AUTO_DET_PORT7,
90 MODE_SAS_PORT7_MASK = (1U << 7), /* port0 SAS(1), SATA(0) mode */
91 MODE_SAS_PORT6_MASK = (1U << 6),
92 MODE_SAS_PORT5_MASK = (1U << 5),
93 MODE_SAS_PORT4_MASK = (1U << 4),
94 MODE_SAS_PORT3_MASK = (1U << 3),
95 MODE_SAS_PORT2_MASK = (1U << 2),
96 MODE_SAS_PORT1_MASK = (1U << 1),
97 MODE_SAS_PORT0_MASK = (1U << 0),
98 MODE_SAS_SATA = MODE_SAS_PORT0_MASK | MODE_SAS_PORT1_MASK |
99 MODE_SAS_PORT2_MASK | MODE_SAS_PORT3_MASK |
100 MODE_SAS_PORT4_MASK | MODE_SAS_PORT5_MASK |
101 MODE_SAS_PORT6_MASK | MODE_SAS_PORT7_MASK,
102
103 /* SAS_MODE value may be
104 * dictated (in hw) by values
105 * of SATA_TARGET & AUTO_DET
106 */
107
108 /* MVS_TX_CFG */
109 TX_EN = (1U << 16), /* Enable TX */
110 TX_RING_SZ_MASK = 0xfff, /* TX ring size, bits 11:0 */
111
112 /* MVS_RX_CFG */
113 RX_EN = (1U << 16), /* Enable RX */
114 RX_RING_SZ_MASK = 0xfff, /* RX ring size, bits 11:0 */
115
116 /* MVS_INT_COAL */
117 COAL_EN = (1U << 16), /* Enable int coalescing */
118
119 /* MVS_INT_STAT, MVS_INT_MASK */
120 CINT_I2C = (1U << 31), /* I2C event */
121 CINT_SW0 = (1U << 30), /* software event 0 */
122 CINT_SW1 = (1U << 29), /* software event 1 */
123 CINT_PRD_BC = (1U << 28), /* PRD BC err for read cmd */
124 CINT_DMA_PCIE = (1U << 27), /* DMA to PCIE timeout */
125 CINT_MEM = (1U << 26), /* int mem parity err */
126 CINT_I2C_SLAVE = (1U << 25), /* slave I2C event */
127 CINT_SRS = (1U << 3), /* SRS event */
128 CINT_CI_STOP = (1U << 1), /* cmd issue stopped */
129 CINT_DONE = (1U << 0), /* cmd completion */
130
131 /* shl for ports 1-3 */
132 CINT_PORT_STOPPED = (1U << 16), /* port0 stopped */
133 CINT_PORT = (1U << 8), /* port0 event */
134 CINT_PORT_MASK_OFFSET = 8,
135 CINT_PORT_MASK = (0xFF << CINT_PORT_MASK_OFFSET),
136
137 /* TX (delivery) ring bits */
138 TXQ_CMD_SHIFT = 29,
139 TXQ_CMD_SSP = 1, /* SSP protocol */
140 TXQ_CMD_SMP = 2, /* SMP protocol */
141 TXQ_CMD_STP = 3, /* STP/SATA protocol */
142 TXQ_CMD_SSP_FREE_LIST = 4, /* add to SSP targ free list */
143 TXQ_CMD_SLOT_RESET = 7, /* reset command slot */
144 TXQ_MODE_I = (1U << 28), /* mode: 0=target,1=initiator */
145 TXQ_PRIO_HI = (1U << 27), /* priority: 0=normal, 1=high */
146 TXQ_SRS_SHIFT = 20, /* SATA register set */
147 TXQ_SRS_MASK = 0x7f,
148 TXQ_PHY_SHIFT = 12, /* PHY bitmap */
149 TXQ_PHY_MASK = 0xff,
150 TXQ_SLOT_MASK = 0xfff, /* slot number */
151
152 /* RX (completion) ring bits */
153 RXQ_GOOD = (1U << 23), /* Response good */
154 RXQ_SLOT_RESET = (1U << 21), /* Slot reset complete */
155 RXQ_CMD_RX = (1U << 20), /* target cmd received */
156 RXQ_ATTN = (1U << 19), /* attention */
157 RXQ_RSP = (1U << 18), /* response frame xfer'd */
158 RXQ_ERR = (1U << 17), /* err info rec xfer'd */
159 RXQ_DONE = (1U << 16), /* cmd complete */
160 RXQ_SLOT_MASK = 0xfff, /* slot number */
161
162 /* mvs_cmd_hdr bits */
163 MCH_PRD_LEN_SHIFT = 16, /* 16-bit PRD table len */
164 MCH_SSP_FR_TYPE_SHIFT = 13, /* SSP frame type */
165
166 /* SSP initiator only */
167 MCH_SSP_FR_CMD = 0x0, /* COMMAND frame */
168
169 /* SSP initiator or target */
170 MCH_SSP_FR_TASK = 0x1, /* TASK frame */
171
172 /* SSP target only */
173 MCH_SSP_FR_XFER_RDY = 0x4, /* XFER_RDY frame */
174 MCH_SSP_FR_RESP = 0x5, /* RESPONSE frame */
175 MCH_SSP_FR_READ = 0x6, /* Read DATA frame(s) */
176 MCH_SSP_FR_READ_RESP = 0x7, /* ditto, plus RESPONSE */
177
178 MCH_PASSTHRU = (1U << 12), /* pass-through (SSP) */
179 MCH_FBURST = (1U << 11), /* first burst (SSP) */
180 MCH_CHK_LEN = (1U << 10), /* chk xfer len (SSP) */
181 MCH_RETRY = (1U << 9), /* tport layer retry (SSP) */
182 MCH_PROTECTION = (1U << 8), /* protection info rec (SSP) */
183 MCH_RESET = (1U << 7), /* Reset (STP/SATA) */
184 MCH_FPDMA = (1U << 6), /* First party DMA (STP/SATA) */
185 MCH_ATAPI = (1U << 5), /* ATAPI (STP/SATA) */
186 MCH_BIST = (1U << 4), /* BIST activate (STP/SATA) */
187 MCH_PMP_MASK = 0xf, /* PMP from cmd FIS (STP/SATA)*/
188
189 CCTL_RST = (1U << 5), /* port logic reset */
190
191 /* 0(LSB first), 1(MSB first) */
192 CCTL_ENDIAN_DATA = (1U << 3), /* PRD data */
193 CCTL_ENDIAN_RSP = (1U << 2), /* response frame */
194 CCTL_ENDIAN_OPEN = (1U << 1), /* open address frame */
195 CCTL_ENDIAN_CMD = (1U << 0), /* command table */
196
197 /* MVS_Px_SER_CTLSTAT (per-phy control) */
198 PHY_SSP_RST = (1U << 3), /* reset SSP link layer */
199 PHY_BCAST_CHG = (1U << 2), /* broadcast(change) notif */
200 PHY_RST_HARD = (1U << 1), /* hard reset + phy reset */
201 PHY_RST = (1U << 0), /* phy reset */
202 PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0xF << 8),
203 PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0xF << 12),
204 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16),
205 PHY_NEG_SPP_PHYS_LINK_RATE_MASK =
206 (0xF << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
207 PHY_READY_MASK = (1U << 20),
208
209 /* MVS_Px_INT_STAT, MVS_Px_INT_MASK (per-phy events) */
210 PHYEV_DEC_ERR = (1U << 24), /* Phy Decoding Error */
211 PHYEV_UNASSOC_FIS = (1U << 19), /* unassociated FIS rx'd */
212 PHYEV_AN = (1U << 18), /* SATA async notification */
213 PHYEV_BIST_ACT = (1U << 17), /* BIST activate FIS */
214 PHYEV_SIG_FIS = (1U << 16), /* signature FIS */
215 PHYEV_POOF = (1U << 12), /* phy ready from 1 -> 0 */
216 PHYEV_IU_BIG = (1U << 11), /* IU too long err */
217 PHYEV_IU_SMALL = (1U << 10), /* IU too short err */
218 PHYEV_UNK_TAG = (1U << 9), /* unknown tag */
219 PHYEV_BROAD_CH = (1U << 8), /* broadcast(CHANGE) */
220 PHYEV_COMWAKE = (1U << 7), /* COMWAKE rx'd */
221 PHYEV_PORT_SEL = (1U << 6), /* port selector present */
222 PHYEV_HARD_RST = (1U << 5), /* hard reset rx'd */
223 PHYEV_ID_TMOUT = (1U << 4), /* identify timeout */
224 PHYEV_ID_FAIL = (1U << 3), /* identify failed */
225 PHYEV_ID_DONE = (1U << 2), /* identify done */
226 PHYEV_HARD_RST_DONE = (1U << 1), /* hard reset done */
227 PHYEV_RDY_CH = (1U << 0), /* phy ready changed state */
228
229 /* MVS_PCS */
230 PCS_EN_SATA_REG_SHIFT = (16), /* Enable SATA Register Set */
231 PCS_EN_PORT_XMT_SHIFT = (12), /* Enable Port Transmit */
232 PCS_EN_PORT_XMT_SHIFT2 = (8), /* For 6480 */
233 PCS_SATA_RETRY = (1U << 8), /* retry ctl FIS on R_ERR */
234 PCS_RSP_RX_EN = (1U << 7), /* raw response rx */
235 PCS_SELF_CLEAR = (1U << 5), /* self-clearing int mode */
236 PCS_FIS_RX_EN = (1U << 4), /* FIS rx enable */
237 PCS_CMD_STOP_ERR = (1U << 3), /* cmd stop-on-err enable */
238 PCS_CMD_RST = (1U << 1), /* reset cmd issue */
239 PCS_CMD_EN = (1U << 0), /* enable cmd issue */
240
241 /* Port n Attached Device Info */
242 PORT_DEV_SSP_TRGT = (1U << 19),
243 PORT_DEV_SMP_TRGT = (1U << 18),
244 PORT_DEV_STP_TRGT = (1U << 17),
245 PORT_DEV_SSP_INIT = (1U << 11),
246 PORT_DEV_SMP_INIT = (1U << 10),
247 PORT_DEV_STP_INIT = (1U << 9),
248 PORT_PHY_ID_MASK = (0xFFU << 24),
249 PORT_DEV_TRGT_MASK = (0x7U << 17),
250 PORT_DEV_INIT_MASK = (0x7U << 9),
251 PORT_DEV_TYPE_MASK = (0x7U << 0),
252
253 /* Port n PHY Status */
254 PHY_RDY = (1U << 2),
255 PHY_DW_SYNC = (1U << 1),
256 PHY_OOB_DTCTD = (1U << 0),
257
258 /* VSR */
259 /* PHYMODE 6 (CDB) */
260 PHY_MODE6_LATECLK = (1U << 29), /* Lock Clock */
261 PHY_MODE6_DTL_SPEED = (1U << 27), /* Digital Loop Speed */
262 PHY_MODE6_FC_ORDER = (1U << 26), /* Fibre Channel Mode Order*/
263 PHY_MODE6_MUCNT_EN = (1U << 24), /* u Count Enable */
264 PHY_MODE6_SEL_MUCNT_LEN = (1U << 22), /* Training Length Select */
265 PHY_MODE6_SELMUPI = (1U << 20), /* Phase Multi Select (init) */
266 PHY_MODE6_SELMUPF = (1U << 18), /* Phase Multi Select (final) */
267 PHY_MODE6_SELMUFF = (1U << 16), /* Freq Loop Multi Sel(final) */
268 PHY_MODE6_SELMUFI = (1U << 14), /* Freq Loop Multi Sel(init) */
269 PHY_MODE6_FREEZE_LOOP = (1U << 12), /* Freeze Rx CDR Loop */
270 PHY_MODE6_INT_RXFOFFS = (1U << 3), /* Rx CDR Freq Loop Enable */
271 PHY_MODE6_FRC_RXFOFFS = (1U << 2), /* Initial Rx CDR Offset */
272 PHY_MODE6_STAU_0D8 = (1U << 1), /* Rx CDR Freq Loop Saturate */
273 PHY_MODE6_RXSAT_DIS = (1U << 0), /* Saturate Ctl */
274};
275
276/* SAS/SATA configuration port registers, aka phy registers */
277enum sas_sata_config_port_regs {
278 PHYR_IDENTIFY = 0x00, /* info for IDENTIFY frame */
279 PHYR_ADDR_LO = 0x04, /* my SAS address (low) */
280 PHYR_ADDR_HI = 0x08, /* my SAS address (high) */
281 PHYR_ATT_DEV_INFO = 0x0C, /* attached device info */
282 PHYR_ATT_ADDR_LO = 0x10, /* attached dev SAS addr (low) */
283 PHYR_ATT_ADDR_HI = 0x14, /* attached dev SAS addr (high) */
284 PHYR_SATA_CTL = 0x18, /* SATA control */
285 PHYR_PHY_STAT = 0x1C, /* PHY status */
286 PHYR_SATA_SIG0 = 0x20, /*port SATA signature FIS(Byte 0-3) */
287 PHYR_SATA_SIG1 = 0x24, /*port SATA signature FIS(Byte 4-7) */
288 PHYR_SATA_SIG2 = 0x28, /*port SATA signature FIS(Byte 8-11) */
289 PHYR_SATA_SIG3 = 0x2c, /*port SATA signature FIS(Byte 12-15) */
290 PHYR_R_ERR_COUNT = 0x30, /* port R_ERR count register */
291 PHYR_CRC_ERR_COUNT = 0x34, /* port CRC error count register */
292 PHYR_WIDE_PORT = 0x38, /* wide port participating */
293 PHYR_CURRENT0 = 0x80, /* current connection info 0 */
294 PHYR_CURRENT1 = 0x84, /* current connection info 1 */
295 PHYR_CURRENT2 = 0x88, /* current connection info 2 */
296};
297
298enum mvs_info_flags {
299 MVF_MSI = (1U << 0), /* MSI is enabled */
300 MVF_PHY_PWR_FIX = (1U << 1), /* bug workaround */
301};
302
303enum sas_cmd_port_registers {
304 CMD_CMRST_OOB_DET = 0x100, /* COMRESET OOB detect register */
305 CMD_CMWK_OOB_DET = 0x104, /* COMWAKE OOB detect register */
306 CMD_CMSAS_OOB_DET = 0x108, /* COMSAS OOB detect register */
307 CMD_BRST_OOB_DET = 0x10c, /* burst OOB detect register */
308 CMD_OOB_SPACE = 0x110, /* OOB space control register */
309 CMD_OOB_BURST = 0x114, /* OOB burst control register */
310 CMD_PHY_TIMER = 0x118, /* PHY timer control register */
311 CMD_PHY_CONFIG0 = 0x11c, /* PHY config register 0 */
312 CMD_PHY_CONFIG1 = 0x120, /* PHY config register 1 */
313 CMD_SAS_CTL0 = 0x124, /* SAS control register 0 */
314 CMD_SAS_CTL1 = 0x128, /* SAS control register 1 */
315 CMD_SAS_CTL2 = 0x12c, /* SAS control register 2 */
316 CMD_SAS_CTL3 = 0x130, /* SAS control register 3 */
317 CMD_ID_TEST = 0x134, /* ID test register */
318 CMD_PL_TIMER = 0x138, /* PL timer register */
319 CMD_WD_TIMER = 0x13c, /* WD timer register */
320 CMD_PORT_SEL_COUNT = 0x140, /* port selector count register */
321 CMD_APP_MEM_CTL = 0x144, /* Application Memory Control */
322 CMD_XOR_MEM_CTL = 0x148, /* XOR Block Memory Control */
323 CMD_DMA_MEM_CTL = 0x14c, /* DMA Block Memory Control */
324 CMD_PORT_MEM_CTL0 = 0x150, /* Port Memory Control 0 */
325 CMD_PORT_MEM_CTL1 = 0x154, /* Port Memory Control 1 */
326 CMD_SATA_PORT_MEM_CTL0 = 0x158, /* SATA Port Memory Control 0 */
327 CMD_SATA_PORT_MEM_CTL1 = 0x15c, /* SATA Port Memory Control 1 */
328 CMD_XOR_MEM_BIST_CTL = 0x160, /* XOR Memory BIST Control */
329 CMD_XOR_MEM_BIST_STAT = 0x164, /* XOR Memroy BIST Status */
330 CMD_DMA_MEM_BIST_CTL = 0x168, /* DMA Memory BIST Control */
331 CMD_DMA_MEM_BIST_STAT = 0x16c, /* DMA Memory BIST Status */
332 CMD_PORT_MEM_BIST_CTL = 0x170, /* Port Memory BIST Control */
333 CMD_PORT_MEM_BIST_STAT0 = 0x174, /* Port Memory BIST Status 0 */
334 CMD_PORT_MEM_BIST_STAT1 = 0x178, /* Port Memory BIST Status 1 */
335 CMD_STP_MEM_BIST_CTL = 0x17c, /* STP Memory BIST Control */
336 CMD_STP_MEM_BIST_STAT0 = 0x180, /* STP Memory BIST Status 0 */
337 CMD_STP_MEM_BIST_STAT1 = 0x184, /* STP Memory BIST Status 1 */
338 CMD_RESET_COUNT = 0x188, /* Reset Count */
339 CMD_MONTR_DATA_SEL = 0x18C, /* Monitor Data/Select */
340 CMD_PLL_PHY_CONFIG = 0x190, /* PLL/PHY Configuration */
341 CMD_PHY_CTL = 0x194, /* PHY Control and Status */
342 CMD_PHY_TEST_COUNT0 = 0x198, /* Phy Test Count 0 */
343 CMD_PHY_TEST_COUNT1 = 0x19C, /* Phy Test Count 1 */
344 CMD_PHY_TEST_COUNT2 = 0x1A0, /* Phy Test Count 2 */
345 CMD_APP_ERR_CONFIG = 0x1A4, /* Application Error Configuration */
346 CMD_PND_FIFO_CTL0 = 0x1A8, /* Pending FIFO Control 0 */
347 CMD_HOST_CTL = 0x1AC, /* Host Control Status */
348 CMD_HOST_WR_DATA = 0x1B0, /* Host Write Data */
349 CMD_HOST_RD_DATA = 0x1B4, /* Host Read Data */
350 CMD_PHY_MODE_21 = 0x1B8, /* Phy Mode 21 */
351 CMD_SL_MODE0 = 0x1BC, /* SL Mode 0 */
352 CMD_SL_MODE1 = 0x1C0, /* SL Mode 1 */
353 CMD_PND_FIFO_CTL1 = 0x1C4, /* Pending FIFO Control 1 */
354};
355
356enum pci_cfg_register_bits {
357 PCTL_PWR_ON = (0xFU << 24),
358 PCTL_OFF = (0xFU << 12),
359 PRD_REQ_SIZE = (0x4000),
360 PRD_REQ_MASK = (0x00007000),
361};
362
363enum nvram_layout_offsets {
364 NVR_SIG = 0x00, /* 0xAA, 0x55 */
365 NVR_SAS_ADDR = 0x02, /* 8-byte SAS address */
366};
367
368enum chip_flavors {
369 chip_6320,
370 chip_6440,
371 chip_6480,
372};
373
374enum port_type {
375 PORT_TYPE_SAS = (1L << 1),
376 PORT_TYPE_SATA = (1L << 0),
377};
378
379/* Command Table Format */
380enum ct_format {
381 /* SSP */
382 SSP_F_H = 0x00,
383 SSP_F_IU = 0x18,
384 SSP_F_MAX = 0x4D,
385 /* STP */
386 STP_CMD_FIS = 0x00,
387 STP_ATAPI_CMD = 0x40,
388 STP_F_MAX = 0x10,
389 /* SMP */
390 SMP_F_T = 0x00,
391 SMP_F_DEP = 0x01,
392 SMP_F_MAX = 0x101,
393};
394
395enum status_buffer {
396 SB_EIR_OFF = 0x00, /* Error Information Record */
397 SB_RFB_OFF = 0x08, /* Response Frame Buffer */
398 SB_RFB_MAX = 0x400, /* RFB size*/
399};
400
401enum error_info_rec {
402 CMD_ISS_STPD = (1U << 31), /* Cmd Issue Stopped */
403 CMD_PI_ERR = (1U << 30), /* Protection info error. see flags2 */
404 RSP_OVER = (1U << 29), /* rsp buffer overflow */
405 RETRY_LIM = (1U << 28), /* FIS/frame retry limit exceeded */
406 UNK_FIS = (1U << 27), /* unknown FIS */
407 DMA_TERM = (1U << 26), /* DMA terminate primitive rx'd */
408 SYNC_ERR = (1U << 25), /* SYNC rx'd during frame xmit */
409 TFILE_ERR = (1U << 24), /* SATA taskfile Error bit set */
410 R_ERR = (1U << 23), /* SATA returned R_ERR prim */
411 RD_OFS = (1U << 20), /* Read DATA frame invalid offset */
412 XFER_RDY_OFS = (1U << 19), /* XFER_RDY offset error */
413 UNEXP_XFER_RDY = (1U << 18), /* unexpected XFER_RDY error */
414 DATA_OVER_UNDER = (1U << 16), /* data overflow/underflow */
415 INTERLOCK = (1U << 15), /* interlock error */
416 NAK = (1U << 14), /* NAK rx'd */
417 ACK_NAK_TO = (1U << 13), /* ACK/NAK timeout */
418 CXN_CLOSED = (1U << 12), /* cxn closed w/out ack/nak */
419 OPEN_TO = (1U << 11), /* I_T nexus lost, open cxn timeout */
420 PATH_BLOCKED = (1U << 10), /* I_T nexus lost, pathway blocked */
421 NO_DEST = (1U << 9), /* I_T nexus lost, no destination */
422 STP_RES_BSY = (1U << 8), /* STP resources busy */
423 BREAK = (1U << 7), /* break received */
424 BAD_DEST = (1U << 6), /* bad destination */
425 BAD_PROTO = (1U << 5), /* protocol not supported */
426 BAD_RATE = (1U << 4), /* cxn rate not supported */
427 WRONG_DEST = (1U << 3), /* wrong destination error */
428 CREDIT_TO = (1U << 2), /* credit timeout */
429 WDOG_TO = (1U << 1), /* watchdog timeout */
430 BUF_PAR = (1U << 0), /* buffer parity error */
431};
432
433enum error_info_rec_2 {
434 SLOT_BSY_ERR = (1U << 31), /* Slot Busy Error */
435 GRD_CHK_ERR = (1U << 14), /* Guard Check Error */
436 APP_CHK_ERR = (1U << 13), /* Application Check error */
437 REF_CHK_ERR = (1U << 12), /* Reference Check Error */
438 USR_BLK_NM = (1U << 0), /* User Block Number */
439};
440
441#endif
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