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path: root/drivers/rapidio/switches/tsi57x.c
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Diffstat (limited to 'drivers/rapidio/switches/tsi57x.c')
-rw-r--r--drivers/rapidio/switches/tsi57x.c56
1 files changed, 24 insertions, 32 deletions
diff --git a/drivers/rapidio/switches/tsi57x.c b/drivers/rapidio/switches/tsi57x.c
index 2003fb63c40..1a62934bfeb 100644
--- a/drivers/rapidio/switches/tsi57x.c
+++ b/drivers/rapidio/switches/tsi57x.c
@@ -158,48 +158,45 @@ tsi57x_get_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
158static int 158static int
159tsi57x_em_init(struct rio_dev *rdev) 159tsi57x_em_init(struct rio_dev *rdev)
160{ 160{
161 struct rio_mport *mport = rdev->net->hport;
162 u16 destid = rdev->rswitch->destid;
163 u8 hopcount = rdev->rswitch->hopcount;
164 u32 regval; 161 u32 regval;
165 int portnum; 162 int portnum;
166 163
167 pr_debug("TSI578 %s [%d:%d]\n", __func__, destid, hopcount); 164 pr_debug("TSI578 %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount);
168 165
169 for (portnum = 0; 166 for (portnum = 0;
170 portnum < RIO_GET_TOTAL_PORTS(rdev->swpinfo); portnum++) { 167 portnum < RIO_GET_TOTAL_PORTS(rdev->swpinfo); portnum++) {
171 /* Make sure that Port-Writes are enabled (for all ports) */ 168 /* Make sure that Port-Writes are enabled (for all ports) */
172 rio_mport_read_config_32(mport, destid, hopcount, 169 rio_read_config_32(rdev,
173 TSI578_SP_MODE(portnum), &regval); 170 TSI578_SP_MODE(portnum), &regval);
174 rio_mport_write_config_32(mport, destid, hopcount, 171 rio_write_config_32(rdev,
175 TSI578_SP_MODE(portnum), 172 TSI578_SP_MODE(portnum),
176 regval & ~TSI578_SP_MODE_PW_DIS); 173 regval & ~TSI578_SP_MODE_PW_DIS);
177 174
178 /* Clear all pending interrupts */ 175 /* Clear all pending interrupts */
179 rio_mport_read_config_32(mport, destid, hopcount, 176 rio_read_config_32(rdev,
180 rdev->phys_efptr + 177 rdev->phys_efptr +
181 RIO_PORT_N_ERR_STS_CSR(portnum), 178 RIO_PORT_N_ERR_STS_CSR(portnum),
182 &regval); 179 &regval);
183 rio_mport_write_config_32(mport, destid, hopcount, 180 rio_write_config_32(rdev,
184 rdev->phys_efptr + 181 rdev->phys_efptr +
185 RIO_PORT_N_ERR_STS_CSR(portnum), 182 RIO_PORT_N_ERR_STS_CSR(portnum),
186 regval & 0x07120214); 183 regval & 0x07120214);
187 184
188 rio_mport_read_config_32(mport, destid, hopcount, 185 rio_read_config_32(rdev,
189 TSI578_SP_INT_STATUS(portnum), &regval); 186 TSI578_SP_INT_STATUS(portnum), &regval);
190 rio_mport_write_config_32(mport, destid, hopcount, 187 rio_write_config_32(rdev,
191 TSI578_SP_INT_STATUS(portnum), 188 TSI578_SP_INT_STATUS(portnum),
192 regval & 0x000700bd); 189 regval & 0x000700bd);
193 190
194 /* Enable all interrupts to allow ports to send a port-write */ 191 /* Enable all interrupts to allow ports to send a port-write */
195 rio_mport_read_config_32(mport, destid, hopcount, 192 rio_read_config_32(rdev,
196 TSI578_SP_CTL_INDEP(portnum), &regval); 193 TSI578_SP_CTL_INDEP(portnum), &regval);
197 rio_mport_write_config_32(mport, destid, hopcount, 194 rio_write_config_32(rdev,
198 TSI578_SP_CTL_INDEP(portnum), 195 TSI578_SP_CTL_INDEP(portnum),
199 regval | 0x000b0000); 196 regval | 0x000b0000);
200 197
201 /* Skip next (odd) port if the current port is in x4 mode */ 198 /* Skip next (odd) port if the current port is in x4 mode */
202 rio_mport_read_config_32(mport, destid, hopcount, 199 rio_read_config_32(rdev,
203 rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum), 200 rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
204 &regval); 201 &regval);
205 if ((regval & RIO_PORT_N_CTL_PWIDTH) == RIO_PORT_N_CTL_PWIDTH_4) 202 if ((regval & RIO_PORT_N_CTL_PWIDTH) == RIO_PORT_N_CTL_PWIDTH_4)
@@ -207,7 +204,7 @@ tsi57x_em_init(struct rio_dev *rdev)
207 } 204 }
208 205
209 /* set TVAL = ~50us */ 206 /* set TVAL = ~50us */
210 rio_mport_write_config_32(mport, destid, hopcount, 207 rio_write_config_32(rdev,
211 rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x9a << 8); 208 rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x9a << 8);
212 209
213 return 0; 210 return 0;
@@ -217,14 +214,12 @@ static int
217tsi57x_em_handler(struct rio_dev *rdev, u8 portnum) 214tsi57x_em_handler(struct rio_dev *rdev, u8 portnum)
218{ 215{
219 struct rio_mport *mport = rdev->net->hport; 216 struct rio_mport *mport = rdev->net->hport;
220 u16 destid = rdev->rswitch->destid;
221 u8 hopcount = rdev->rswitch->hopcount;
222 u32 intstat, err_status; 217 u32 intstat, err_status;
223 int sendcount, checkcount; 218 int sendcount, checkcount;
224 u8 route_port; 219 u8 route_port;
225 u32 regval; 220 u32 regval;
226 221
227 rio_mport_read_config_32(mport, destid, hopcount, 222 rio_read_config_32(rdev,
228 rdev->phys_efptr + RIO_PORT_N_ERR_STS_CSR(portnum), 223 rdev->phys_efptr + RIO_PORT_N_ERR_STS_CSR(portnum),
229 &err_status); 224 &err_status);
230 225
@@ -232,15 +227,15 @@ tsi57x_em_handler(struct rio_dev *rdev, u8 portnum)
232 (err_status & (RIO_PORT_N_ERR_STS_PW_OUT_ES | 227 (err_status & (RIO_PORT_N_ERR_STS_PW_OUT_ES |
233 RIO_PORT_N_ERR_STS_PW_INP_ES))) { 228 RIO_PORT_N_ERR_STS_PW_INP_ES))) {
234 /* Remove any queued packets by locking/unlocking port */ 229 /* Remove any queued packets by locking/unlocking port */
235 rio_mport_read_config_32(mport, destid, hopcount, 230 rio_read_config_32(rdev,
236 rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum), 231 rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
237 &regval); 232 &regval);
238 if (!(regval & RIO_PORT_N_CTL_LOCKOUT)) { 233 if (!(regval & RIO_PORT_N_CTL_LOCKOUT)) {
239 rio_mport_write_config_32(mport, destid, hopcount, 234 rio_write_config_32(rdev,
240 rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum), 235 rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
241 regval | RIO_PORT_N_CTL_LOCKOUT); 236 regval | RIO_PORT_N_CTL_LOCKOUT);
242 udelay(50); 237 udelay(50);
243 rio_mport_write_config_32(mport, destid, hopcount, 238 rio_write_config_32(rdev,
244 rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum), 239 rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
245 regval); 240 regval);
246 } 241 }
@@ -248,7 +243,7 @@ tsi57x_em_handler(struct rio_dev *rdev, u8 portnum)
248 /* Read from link maintenance response register to clear 243 /* Read from link maintenance response register to clear
249 * valid bit 244 * valid bit
250 */ 245 */
251 rio_mport_read_config_32(mport, destid, hopcount, 246 rio_read_config_32(rdev,
252 rdev->phys_efptr + RIO_PORT_N_MNT_RSP_CSR(portnum), 247 rdev->phys_efptr + RIO_PORT_N_MNT_RSP_CSR(portnum),
253 &regval); 248 &regval);
254 249
@@ -257,13 +252,12 @@ tsi57x_em_handler(struct rio_dev *rdev, u8 portnum)
257 */ 252 */
258 sendcount = 3; 253 sendcount = 3;
259 while (sendcount) { 254 while (sendcount) {
260 rio_mport_write_config_32(mport, destid, hopcount, 255 rio_write_config_32(rdev,
261 TSI578_SP_CS_TX(portnum), 0x40fc8000); 256 TSI578_SP_CS_TX(portnum), 0x40fc8000);
262 checkcount = 3; 257 checkcount = 3;
263 while (checkcount--) { 258 while (checkcount--) {
264 udelay(50); 259 udelay(50);
265 rio_mport_read_config_32( 260 rio_read_config_32(rdev,
266 mport, destid, hopcount,
267 rdev->phys_efptr + 261 rdev->phys_efptr +
268 RIO_PORT_N_MNT_RSP_CSR(portnum), 262 RIO_PORT_N_MNT_RSP_CSR(portnum),
269 &regval); 263 &regval);
@@ -277,25 +271,23 @@ tsi57x_em_handler(struct rio_dev *rdev, u8 portnum)
277 271
278exit_es: 272exit_es:
279 /* Clear implementation specific error status bits */ 273 /* Clear implementation specific error status bits */
280 rio_mport_read_config_32(mport, destid, hopcount, 274 rio_read_config_32(rdev, TSI578_SP_INT_STATUS(portnum), &intstat);
281 TSI578_SP_INT_STATUS(portnum), &intstat);
282 pr_debug("TSI578[%x:%x] SP%d_INT_STATUS=0x%08x\n", 275 pr_debug("TSI578[%x:%x] SP%d_INT_STATUS=0x%08x\n",
283 destid, hopcount, portnum, intstat); 276 rdev->destid, rdev->hopcount, portnum, intstat);
284 277
285 if (intstat & 0x10000) { 278 if (intstat & 0x10000) {
286 rio_mport_read_config_32(mport, destid, hopcount, 279 rio_read_config_32(rdev,
287 TSI578_SP_LUT_PEINF(portnum), &regval); 280 TSI578_SP_LUT_PEINF(portnum), &regval);
288 regval = (mport->sys_size) ? (regval >> 16) : (regval >> 24); 281 regval = (mport->sys_size) ? (regval >> 16) : (regval >> 24);
289 route_port = rdev->rswitch->route_table[regval]; 282 route_port = rdev->rswitch->route_table[regval];
290 pr_debug("RIO: TSI578[%s] P%d LUT Parity Error (destID=%d)\n", 283 pr_debug("RIO: TSI578[%s] P%d LUT Parity Error (destID=%d)\n",
291 rio_name(rdev), portnum, regval); 284 rio_name(rdev), portnum, regval);
292 tsi57x_route_add_entry(mport, destid, hopcount, 285 tsi57x_route_add_entry(mport, rdev->destid, rdev->hopcount,
293 RIO_GLOBAL_TABLE, regval, route_port); 286 RIO_GLOBAL_TABLE, regval, route_port);
294 } 287 }
295 288
296 rio_mport_write_config_32(mport, destid, hopcount, 289 rio_write_config_32(rdev, TSI578_SP_INT_STATUS(portnum),
297 TSI578_SP_INT_STATUS(portnum), 290 intstat & 0x000700bd);
298 intstat & 0x000700bd);
299 291
300 return 0; 292 return 0;
301} 293}