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-rw-r--r--drivers/pinctrl/Kconfig41
-rw-r--r--drivers/pinctrl/Makefile12
-rw-r--r--drivers/pinctrl/core.c244
-rw-r--r--drivers/pinctrl/core.h12
-rw-r--r--drivers/pinctrl/devicetree.c249
-rw-r--r--drivers/pinctrl/devicetree.h35
-rw-r--r--drivers/pinctrl/pinconf.c52
-rw-r--r--drivers/pinctrl/pinconf.h17
-rw-r--r--drivers/pinctrl/pinctrl-coh901.c4
-rw-r--r--drivers/pinctrl/pinctrl-imx.c627
-rw-r--r--drivers/pinctrl/pinctrl-imx.h106
-rw-r--r--drivers/pinctrl/pinctrl-imx23.c305
-rw-r--r--drivers/pinctrl/pinctrl-imx28.c421
-rw-r--r--drivers/pinctrl/pinctrl-imx6q.c2331
-rw-r--r--drivers/pinctrl/pinctrl-mxs.c508
-rw-r--r--drivers/pinctrl/pinctrl-mxs.h91
-rw-r--r--drivers/pinctrl/pinctrl-nomadik-db8500.c857
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.c1780
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.h77
-rw-r--r--drivers/pinctrl/pinctrl-pxa3xx.c24
-rw-r--r--drivers/pinctrl/pinctrl-sirf.c20
-rw-r--r--drivers/pinctrl/pinctrl-tegra.c439
-rw-r--r--drivers/pinctrl/pinctrl-tegra.h23
-rw-r--r--drivers/pinctrl/pinctrl-tegra20.c40
-rw-r--r--drivers/pinctrl/pinctrl-tegra30.c40
-rw-r--r--drivers/pinctrl/pinctrl-u300.c20
-rw-r--r--drivers/pinctrl/pinmux.c93
-rw-r--r--drivers/pinctrl/pinmux.h18
-rw-r--r--drivers/pinctrl/spear/Kconfig34
-rw-r--r--drivers/pinctrl/spear/Makefile7
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear.c354
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear.h142
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear300.c708
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear310.c431
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear320.c3468
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear3xx.c588
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear3xx.h92
37 files changed, 14029 insertions, 281 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index abfb9640877..ce2e756b19a 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -4,7 +4,6 @@
4 4
5config PINCTRL 5config PINCTRL
6 bool 6 bool
7 depends on EXPERIMENTAL
8 7
9if PINCTRL 8if PINCTRL
10 9
@@ -27,6 +26,19 @@ config DEBUG_PINCTRL
27 help 26 help
28 Say Y here to add some extra checks and diagnostics to PINCTRL calls. 27 Say Y here to add some extra checks and diagnostics to PINCTRL calls.
29 28
29config PINCTRL_IMX
30 bool
31 select PINMUX
32 select PINCONF
33
34config PINCTRL_IMX6Q
35 bool "IMX6Q pinctrl driver"
36 depends on OF
37 depends on SOC_IMX6Q
38 select PINCTRL_IMX
39 help
40 Say Y here to enable the imx6q pinctrl driver
41
30config PINCTRL_PXA3xx 42config PINCTRL_PXA3xx
31 bool 43 bool
32 select PINMUX 44 select PINMUX
@@ -37,6 +49,31 @@ config PINCTRL_MMP2
37 select PINCTRL_PXA3xx 49 select PINCTRL_PXA3xx
38 select PINCONF 50 select PINCONF
39 51
52config PINCTRL_MXS
53 bool
54
55config PINCTRL_IMX23
56 bool
57 select PINMUX
58 select PINCONF
59 select PINCTRL_MXS
60
61config PINCTRL_IMX28
62 bool
63 select PINMUX
64 select PINCONF
65 select PINCTRL_MXS
66
67config PINCTRL_NOMADIK
68 bool "Nomadik pin controller driver"
69 depends on ARCH_U8500 || ARCH_NOMADIK
70 select PINMUX
71 select PINCONF
72
73config PINCTRL_DB8500
74 bool "DB8500 pin controller driver"
75 depends on PINCTRL_NOMADIK && ARCH_U8500
76
40config PINCTRL_PXA168 77config PINCTRL_PXA168
41 bool "PXA168 pin controller driver" 78 bool "PXA168 pin controller driver"
42 depends on ARCH_MMP 79 depends on ARCH_MMP
@@ -84,6 +121,8 @@ config PINCTRL_COH901
84 COH 901 335 and COH 901 571/3. They contain 3, 5 or 7 121 COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
85 ports of 8 GPIO pins each. 122 ports of 8 GPIO pins each.
86 123
124source "drivers/pinctrl/spear/Kconfig"
125
87endmenu 126endmenu
88 127
89endif 128endif
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 6d4150b4ece..8e764ade929 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -5,9 +5,19 @@ ccflags-$(CONFIG_DEBUG_PINCTRL) += -DDEBUG
5obj-$(CONFIG_PINCTRL) += core.o 5obj-$(CONFIG_PINCTRL) += core.o
6obj-$(CONFIG_PINMUX) += pinmux.o 6obj-$(CONFIG_PINMUX) += pinmux.o
7obj-$(CONFIG_PINCONF) += pinconf.o 7obj-$(CONFIG_PINCONF) += pinconf.o
8ifeq ($(CONFIG_OF),y)
9obj-$(CONFIG_PINCTRL) += devicetree.o
10endif
8obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o 11obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
12obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
13obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
9obj-$(CONFIG_PINCTRL_PXA3xx) += pinctrl-pxa3xx.o 14obj-$(CONFIG_PINCTRL_PXA3xx) += pinctrl-pxa3xx.o
10obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o 15obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o
16obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
17obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
18obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
19obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
20obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
11obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o 21obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o
12obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o 22obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o
13obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o 23obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o
@@ -16,3 +26,5 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
16obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o 26obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
17obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o 27obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
18obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o 28obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
29
30obj-$(CONFIG_PLAT_SPEAR) += spear/
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index df6296c5f47..c3b331b74fa 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -23,9 +23,11 @@
23#include <linux/sysfs.h> 23#include <linux/sysfs.h>
24#include <linux/debugfs.h> 24#include <linux/debugfs.h>
25#include <linux/seq_file.h> 25#include <linux/seq_file.h>
26#include <linux/pinctrl/consumer.h>
26#include <linux/pinctrl/pinctrl.h> 27#include <linux/pinctrl/pinctrl.h>
27#include <linux/pinctrl/machine.h> 28#include <linux/pinctrl/machine.h>
28#include "core.h" 29#include "core.h"
30#include "devicetree.h"
29#include "pinmux.h" 31#include "pinmux.h"
30#include "pinconf.h" 32#include "pinconf.h"
31 33
@@ -41,11 +43,13 @@ struct pinctrl_maps {
41 unsigned num_maps; 43 unsigned num_maps;
42}; 44};
43 45
46static bool pinctrl_dummy_state;
47
44/* Mutex taken by all entry points */ 48/* Mutex taken by all entry points */
45DEFINE_MUTEX(pinctrl_mutex); 49DEFINE_MUTEX(pinctrl_mutex);
46 50
47/* Global list of pin control devices (struct pinctrl_dev) */ 51/* Global list of pin control devices (struct pinctrl_dev) */
48static LIST_HEAD(pinctrldev_list); 52LIST_HEAD(pinctrldev_list);
49 53
50/* List of pin controller handles (struct pinctrl) */ 54/* List of pin controller handles (struct pinctrl) */
51static LIST_HEAD(pinctrl_list); 55static LIST_HEAD(pinctrl_list);
@@ -59,6 +63,19 @@ static LIST_HEAD(pinctrl_maps);
59 _i_ < _maps_node_->num_maps; \ 63 _i_ < _maps_node_->num_maps; \
60 i++, _map_ = &_maps_node_->maps[_i_]) 64 i++, _map_ = &_maps_node_->maps[_i_])
61 65
66/**
67 * pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support
68 *
69 * Usually this function is called by platforms without pinctrl driver support
70 * but run with some shared drivers using pinctrl APIs.
71 * After calling this function, the pinctrl core will return successfully
72 * with creating a dummy state for the driver to keep going smoothly.
73 */
74void pinctrl_provide_dummies(void)
75{
76 pinctrl_dummy_state = true;
77}
78
62const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev) 79const char *pinctrl_dev_get_name(struct pinctrl_dev *pctldev)
63{ 80{
64 /* We're not allowed to register devices without name */ 81 /* We're not allowed to register devices without name */
@@ -124,6 +141,25 @@ int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name)
124} 141}
125 142
126/** 143/**
144 * pin_get_name_from_id() - look up a pin name from a pin id
145 * @pctldev: the pin control device to lookup the pin on
146 * @name: the name of the pin to look up
147 */
148const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin)
149{
150 const struct pin_desc *desc;
151
152 desc = pin_desc_get(pctldev, pin);
153 if (desc == NULL) {
154 dev_err(pctldev->dev, "failed to get pin(%d) name\n",
155 pin);
156 return NULL;
157 }
158
159 return desc->name;
160}
161
162/**
127 * pin_is_valid() - check if pin exists on controller 163 * pin_is_valid() - check if pin exists on controller
128 * @pctldev: the pin control device to check the pin on 164 * @pctldev: the pin control device to check the pin on
129 * @pin: pin to check, use the local pin controller index number 165 * @pin: pin to check, use the local pin controller index number
@@ -255,7 +291,8 @@ pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio)
255 * 291 *
256 * Find the pin controller handling a certain GPIO pin from the pinspace of 292 * Find the pin controller handling a certain GPIO pin from the pinspace of
257 * the GPIO subsystem, return the device and the matching GPIO range. Returns 293 * the GPIO subsystem, return the device and the matching GPIO range. Returns
258 * negative if the GPIO range could not be found in any device. 294 * -EPROBE_DEFER if the GPIO range could not be found in any device since it
295 * may still have not been registered.
259 */ 296 */
260static int pinctrl_get_device_gpio_range(unsigned gpio, 297static int pinctrl_get_device_gpio_range(unsigned gpio,
261 struct pinctrl_dev **outdev, 298 struct pinctrl_dev **outdev,
@@ -275,7 +312,7 @@ static int pinctrl_get_device_gpio_range(unsigned gpio,
275 } 312 }
276 } 313 }
277 314
278 return -EINVAL; 315 return -EPROBE_DEFER;
279} 316}
280 317
281/** 318/**
@@ -318,9 +355,10 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
318 const char *pin_group) 355 const char *pin_group)
319{ 356{
320 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; 357 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
358 unsigned ngroups = pctlops->get_groups_count(pctldev);
321 unsigned group_selector = 0; 359 unsigned group_selector = 0;
322 360
323 while (pctlops->list_groups(pctldev, group_selector) >= 0) { 361 while (group_selector < ngroups) {
324 const char *gname = pctlops->get_group_name(pctldev, 362 const char *gname = pctlops->get_group_name(pctldev,
325 group_selector); 363 group_selector);
326 if (!strcmp(gname, pin_group)) { 364 if (!strcmp(gname, pin_group)) {
@@ -360,7 +398,7 @@ int pinctrl_request_gpio(unsigned gpio)
360 ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range); 398 ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
361 if (ret) { 399 if (ret) {
362 mutex_unlock(&pinctrl_mutex); 400 mutex_unlock(&pinctrl_mutex);
363 return -EINVAL; 401 return ret;
364 } 402 }
365 403
366 /* Convert to the pin controllers number space */ 404 /* Convert to the pin controllers number space */
@@ -516,11 +554,14 @@ static int add_setting(struct pinctrl *p, struct pinctrl_map const *map)
516 554
517 setting->pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name); 555 setting->pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name);
518 if (setting->pctldev == NULL) { 556 if (setting->pctldev == NULL) {
519 dev_err(p->dev, "unknown pinctrl device %s in map entry", 557 dev_info(p->dev, "unknown pinctrl device %s in map entry, deferring probe",
520 map->ctrl_dev_name); 558 map->ctrl_dev_name);
521 kfree(setting); 559 kfree(setting);
522 /* Eventually, this should trigger deferred probe */ 560 /*
523 return -ENODEV; 561 * OK let us guess that the driver is not there yet, and
562 * let's defer obtaining this pinctrl handle to later...
563 */
564 return -EPROBE_DEFER;
524 } 565 }
525 566
526 switch (map->type) { 567 switch (map->type) {
@@ -579,6 +620,13 @@ static struct pinctrl *create_pinctrl(struct device *dev)
579 } 620 }
580 p->dev = dev; 621 p->dev = dev;
581 INIT_LIST_HEAD(&p->states); 622 INIT_LIST_HEAD(&p->states);
623 INIT_LIST_HEAD(&p->dt_maps);
624
625 ret = pinctrl_dt_to_map(p);
626 if (ret < 0) {
627 kfree(p);
628 return ERR_PTR(ret);
629 }
582 630
583 devname = dev_name(dev); 631 devname = dev_name(dev);
584 632
@@ -662,6 +710,8 @@ static void pinctrl_put_locked(struct pinctrl *p, bool inlist)
662 kfree(state); 710 kfree(state);
663 } 711 }
664 712
713 pinctrl_dt_free_maps(p);
714
665 if (inlist) 715 if (inlist)
666 list_del(&p->node); 716 list_del(&p->node);
667 kfree(p); 717 kfree(p);
@@ -685,8 +735,18 @@ static struct pinctrl_state *pinctrl_lookup_state_locked(struct pinctrl *p,
685 struct pinctrl_state *state; 735 struct pinctrl_state *state;
686 736
687 state = find_state(p, name); 737 state = find_state(p, name);
688 if (!state) 738 if (!state) {
689 return ERR_PTR(-ENODEV); 739 if (pinctrl_dummy_state) {
740 /* create dummy state */
741 dev_dbg(p->dev, "using pinctrl dummy state (%s)\n",
742 name);
743 state = create_state(p, name);
744 if (IS_ERR(state))
745 return state;
746 } else {
747 return ERR_PTR(-ENODEV);
748 }
749 }
690 750
691 return state; 751 return state;
692} 752}
@@ -787,15 +847,63 @@ int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *state)
787} 847}
788EXPORT_SYMBOL_GPL(pinctrl_select_state); 848EXPORT_SYMBOL_GPL(pinctrl_select_state);
789 849
850static void devm_pinctrl_release(struct device *dev, void *res)
851{
852 pinctrl_put(*(struct pinctrl **)res);
853}
854
790/** 855/**
791 * pinctrl_register_mappings() - register a set of pin controller mappings 856 * struct devm_pinctrl_get() - Resource managed pinctrl_get()
792 * @maps: the pincontrol mappings table to register. This should probably be 857 * @dev: the device to obtain the handle for
793 * marked with __initdata so it can be discarded after boot. This 858 *
794 * function will perform a shallow copy for the mapping entries. 859 * If there is a need to explicitly destroy the returned struct pinctrl,
795 * @num_maps: the number of maps in the mapping table 860 * devm_pinctrl_put() should be used, rather than plain pinctrl_put().
796 */ 861 */
797int pinctrl_register_mappings(struct pinctrl_map const *maps, 862struct pinctrl *devm_pinctrl_get(struct device *dev)
798 unsigned num_maps) 863{
864 struct pinctrl **ptr, *p;
865
866 ptr = devres_alloc(devm_pinctrl_release, sizeof(*ptr), GFP_KERNEL);
867 if (!ptr)
868 return ERR_PTR(-ENOMEM);
869
870 p = pinctrl_get(dev);
871 if (!IS_ERR(p)) {
872 *ptr = p;
873 devres_add(dev, ptr);
874 } else {
875 devres_free(ptr);
876 }
877
878 return p;
879}
880EXPORT_SYMBOL_GPL(devm_pinctrl_get);
881
882static int devm_pinctrl_match(struct device *dev, void *res, void *data)
883{
884 struct pinctrl **p = res;
885
886 return *p == data;
887}
888
889/**
890 * devm_pinctrl_put() - Resource managed pinctrl_put()
891 * @p: the pinctrl handle to release
892 *
893 * Deallocate a struct pinctrl obtained via devm_pinctrl_get(). Normally
894 * this function will not need to be called and the resource management
895 * code will ensure that the resource is freed.
896 */
897void devm_pinctrl_put(struct pinctrl *p)
898{
899 WARN_ON(devres_destroy(p->dev, devm_pinctrl_release,
900 devm_pinctrl_match, p));
901 pinctrl_put(p);
902}
903EXPORT_SYMBOL_GPL(devm_pinctrl_put);
904
905int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
906 bool dup, bool locked)
799{ 907{
800 int i, ret; 908 int i, ret;
801 struct pinctrl_maps *maps_node; 909 struct pinctrl_maps *maps_node;
@@ -829,13 +937,13 @@ int pinctrl_register_mappings(struct pinctrl_map const *maps,
829 case PIN_MAP_TYPE_MUX_GROUP: 937 case PIN_MAP_TYPE_MUX_GROUP:
830 ret = pinmux_validate_map(&maps[i], i); 938 ret = pinmux_validate_map(&maps[i], i);
831 if (ret < 0) 939 if (ret < 0)
832 return 0; 940 return ret;
833 break; 941 break;
834 case PIN_MAP_TYPE_CONFIGS_PIN: 942 case PIN_MAP_TYPE_CONFIGS_PIN:
835 case PIN_MAP_TYPE_CONFIGS_GROUP: 943 case PIN_MAP_TYPE_CONFIGS_GROUP:
836 ret = pinconf_validate_map(&maps[i], i); 944 ret = pinconf_validate_map(&maps[i], i);
837 if (ret < 0) 945 if (ret < 0)
838 return 0; 946 return ret;
839 break; 947 break;
840 default: 948 default:
841 pr_err("failed to register map %s (%d): invalid type given\n", 949 pr_err("failed to register map %s (%d): invalid type given\n",
@@ -851,20 +959,52 @@ int pinctrl_register_mappings(struct pinctrl_map const *maps,
851 } 959 }
852 960
853 maps_node->num_maps = num_maps; 961 maps_node->num_maps = num_maps;
854 maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps, GFP_KERNEL); 962 if (dup) {
855 if (!maps_node->maps) { 963 maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps,
856 pr_err("failed to duplicate mapping table\n"); 964 GFP_KERNEL);
857 kfree(maps_node); 965 if (!maps_node->maps) {
858 return -ENOMEM; 966 pr_err("failed to duplicate mapping table\n");
967 kfree(maps_node);
968 return -ENOMEM;
969 }
970 } else {
971 maps_node->maps = maps;
859 } 972 }
860 973
861 mutex_lock(&pinctrl_mutex); 974 if (!locked)
975 mutex_lock(&pinctrl_mutex);
862 list_add_tail(&maps_node->node, &pinctrl_maps); 976 list_add_tail(&maps_node->node, &pinctrl_maps);
863 mutex_unlock(&pinctrl_mutex); 977 if (!locked)
978 mutex_unlock(&pinctrl_mutex);
864 979
865 return 0; 980 return 0;
866} 981}
867 982
983/**
984 * pinctrl_register_mappings() - register a set of pin controller mappings
985 * @maps: the pincontrol mappings table to register. This should probably be
986 * marked with __initdata so it can be discarded after boot. This
987 * function will perform a shallow copy for the mapping entries.
988 * @num_maps: the number of maps in the mapping table
989 */
990int pinctrl_register_mappings(struct pinctrl_map const *maps,
991 unsigned num_maps)
992{
993 return pinctrl_register_map(maps, num_maps, true, false);
994}
995
996void pinctrl_unregister_map(struct pinctrl_map const *map)
997{
998 struct pinctrl_maps *maps_node;
999
1000 list_for_each_entry(maps_node, &pinctrl_maps, node) {
1001 if (maps_node->maps == map) {
1002 list_del(&maps_node->node);
1003 return;
1004 }
1005 }
1006}
1007
868#ifdef CONFIG_DEBUG_FS 1008#ifdef CONFIG_DEBUG_FS
869 1009
870static int pinctrl_pins_show(struct seq_file *s, void *what) 1010static int pinctrl_pins_show(struct seq_file *s, void *what)
@@ -906,15 +1046,17 @@ static int pinctrl_groups_show(struct seq_file *s, void *what)
906{ 1046{
907 struct pinctrl_dev *pctldev = s->private; 1047 struct pinctrl_dev *pctldev = s->private;
908 const struct pinctrl_ops *ops = pctldev->desc->pctlops; 1048 const struct pinctrl_ops *ops = pctldev->desc->pctlops;
909 unsigned selector = 0; 1049 unsigned ngroups, selector = 0;
910 1050
1051 ngroups = ops->get_groups_count(pctldev);
911 mutex_lock(&pinctrl_mutex); 1052 mutex_lock(&pinctrl_mutex);
912 1053
913 seq_puts(s, "registered pin groups:\n"); 1054 seq_puts(s, "registered pin groups:\n");
914 while (ops->list_groups(pctldev, selector) >= 0) { 1055 while (selector < ngroups) {
915 const unsigned *pins; 1056 const unsigned *pins;
916 unsigned num_pins; 1057 unsigned num_pins;
917 const char *gname = ops->get_group_name(pctldev, selector); 1058 const char *gname = ops->get_group_name(pctldev, selector);
1059 const char *pname;
918 int ret; 1060 int ret;
919 int i; 1061 int i;
920 1062
@@ -924,10 +1066,14 @@ static int pinctrl_groups_show(struct seq_file *s, void *what)
924 seq_printf(s, "%s [ERROR GETTING PINS]\n", 1066 seq_printf(s, "%s [ERROR GETTING PINS]\n",
925 gname); 1067 gname);
926 else { 1068 else {
927 seq_printf(s, "group: %s, pins = [ ", gname); 1069 seq_printf(s, "group: %s\n", gname);
928 for (i = 0; i < num_pins; i++) 1070 for (i = 0; i < num_pins; i++) {
929 seq_printf(s, "%d ", pins[i]); 1071 pname = pin_get_name(pctldev, pins[i]);
930 seq_puts(s, "]\n"); 1072 if (WARN_ON(!pname))
1073 return -EINVAL;
1074 seq_printf(s, "pin %d (%s)\n", pins[i], pname);
1075 }
1076 seq_puts(s, "\n");
931 } 1077 }
932 selector++; 1078 selector++;
933 } 1079 }
@@ -1226,11 +1372,14 @@ static int pinctrl_check_ops(struct pinctrl_dev *pctldev)
1226 const struct pinctrl_ops *ops = pctldev->desc->pctlops; 1372 const struct pinctrl_ops *ops = pctldev->desc->pctlops;
1227 1373
1228 if (!ops || 1374 if (!ops ||
1229 !ops->list_groups || 1375 !ops->get_groups_count ||
1230 !ops->get_group_name || 1376 !ops->get_group_name ||
1231 !ops->get_group_pins) 1377 !ops->get_group_pins)
1232 return -EINVAL; 1378 return -EINVAL;
1233 1379
1380 if (ops->dt_node_to_map && !ops->dt_free_map)
1381 return -EINVAL;
1382
1234 return 0; 1383 return 0;
1235} 1384}
1236 1385
@@ -1268,37 +1417,29 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
1268 /* check core ops for sanity */ 1417 /* check core ops for sanity */
1269 ret = pinctrl_check_ops(pctldev); 1418 ret = pinctrl_check_ops(pctldev);
1270 if (ret) { 1419 if (ret) {
1271 pr_err("%s pinctrl ops lacks necessary functions\n", 1420 dev_err(dev, "pinctrl ops lacks necessary functions\n");
1272 pctldesc->name);
1273 goto out_err; 1421 goto out_err;
1274 } 1422 }
1275 1423
1276 /* If we're implementing pinmuxing, check the ops for sanity */ 1424 /* If we're implementing pinmuxing, check the ops for sanity */
1277 if (pctldesc->pmxops) { 1425 if (pctldesc->pmxops) {
1278 ret = pinmux_check_ops(pctldev); 1426 ret = pinmux_check_ops(pctldev);
1279 if (ret) { 1427 if (ret)
1280 pr_err("%s pinmux ops lacks necessary functions\n",
1281 pctldesc->name);
1282 goto out_err; 1428 goto out_err;
1283 }
1284 } 1429 }
1285 1430
1286 /* If we're implementing pinconfig, check the ops for sanity */ 1431 /* If we're implementing pinconfig, check the ops for sanity */
1287 if (pctldesc->confops) { 1432 if (pctldesc->confops) {
1288 ret = pinconf_check_ops(pctldev); 1433 ret = pinconf_check_ops(pctldev);
1289 if (ret) { 1434 if (ret)
1290 pr_err("%s pin config ops lacks necessary functions\n",
1291 pctldesc->name);
1292 goto out_err; 1435 goto out_err;
1293 }
1294 } 1436 }
1295 1437
1296 /* Register all the pins */ 1438 /* Register all the pins */
1297 pr_debug("try to register %d pins on %s...\n", 1439 dev_dbg(dev, "try to register %d pins ...\n", pctldesc->npins);
1298 pctldesc->npins, pctldesc->name);
1299 ret = pinctrl_register_pins(pctldev, pctldesc->pins, pctldesc->npins); 1440 ret = pinctrl_register_pins(pctldev, pctldesc->pins, pctldesc->npins);
1300 if (ret) { 1441 if (ret) {
1301 pr_err("error during pin registration\n"); 1442 dev_err(dev, "error during pin registration\n");
1302 pinctrl_free_pindescs(pctldev, pctldesc->pins, 1443 pinctrl_free_pindescs(pctldev, pctldesc->pins,
1303 pctldesc->npins); 1444 pctldesc->npins);
1304 goto out_err; 1445 goto out_err;
@@ -1313,8 +1454,15 @@ struct pinctrl_dev *pinctrl_register(struct pinctrl_desc *pctldesc,
1313 struct pinctrl_state *s = 1454 struct pinctrl_state *s =
1314 pinctrl_lookup_state_locked(pctldev->p, 1455 pinctrl_lookup_state_locked(pctldev->p,
1315 PINCTRL_STATE_DEFAULT); 1456 PINCTRL_STATE_DEFAULT);
1316 if (!IS_ERR(s)) 1457 if (IS_ERR(s)) {
1317 pinctrl_select_state_locked(pctldev->p, s); 1458 dev_dbg(dev, "failed to lookup the default state\n");
1459 } else {
1460 ret = pinctrl_select_state_locked(pctldev->p, s);
1461 if (ret) {
1462 dev_err(dev,
1463 "failed to select default state\n");
1464 }
1465 }
1318 } 1466 }
1319 1467
1320 mutex_unlock(&pinctrl_mutex); 1468 mutex_unlock(&pinctrl_mutex);
diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h
index 17ecf651b12..1f40ff68a8c 100644
--- a/drivers/pinctrl/core.h
+++ b/drivers/pinctrl/core.h
@@ -52,12 +52,15 @@ struct pinctrl_dev {
52 * @dev: the device using this pin control handle 52 * @dev: the device using this pin control handle
53 * @states: a list of states for this device 53 * @states: a list of states for this device
54 * @state: the current state 54 * @state: the current state
55 * @dt_maps: the mapping table chunks dynamically parsed from device tree for
56 * this device, if any
55 */ 57 */
56struct pinctrl { 58struct pinctrl {
57 struct list_head node; 59 struct list_head node;
58 struct device *dev; 60 struct device *dev;
59 struct list_head states; 61 struct list_head states;
60 struct pinctrl_state *state; 62 struct pinctrl_state *state;
63 struct list_head dt_maps;
61}; 64};
62 65
63/** 66/**
@@ -100,7 +103,8 @@ struct pinctrl_setting_configs {
100 * struct pinctrl_setting - an individual mux or config setting 103 * struct pinctrl_setting - an individual mux or config setting
101 * @node: list node for struct pinctrl_settings's @settings field 104 * @node: list node for struct pinctrl_settings's @settings field
102 * @type: the type of setting 105 * @type: the type of setting
103 * @pctldev: pin control device handling to be programmed 106 * @pctldev: pin control device handling to be programmed. Not used for
107 * PIN_MAP_TYPE_DUMMY_STATE.
104 * @data: Data specific to the setting type 108 * @data: Data specific to the setting type
105 */ 109 */
106struct pinctrl_setting { 110struct pinctrl_setting {
@@ -144,6 +148,7 @@ struct pin_desc {
144 148
145struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name); 149struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name);
146int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name); 150int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name);
151const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin);
147int pinctrl_get_group_selector(struct pinctrl_dev *pctldev, 152int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
148 const char *pin_group); 153 const char *pin_group);
149 154
@@ -153,4 +158,9 @@ static inline struct pin_desc *pin_desc_get(struct pinctrl_dev *pctldev,
153 return radix_tree_lookup(&pctldev->pin_desc_tree, pin); 158 return radix_tree_lookup(&pctldev->pin_desc_tree, pin);
154} 159}
155 160
161int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
162 bool dup, bool locked);
163void pinctrl_unregister_map(struct pinctrl_map const *map);
164
156extern struct mutex pinctrl_mutex; 165extern struct mutex pinctrl_mutex;
166extern struct list_head pinctrldev_list;
diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c
new file mode 100644
index 00000000000..fcb1de45473
--- /dev/null
+++ b/drivers/pinctrl/devicetree.c
@@ -0,0 +1,249 @@
1/*
2 * Device tree integration for the pin control subsystem
3 *
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/device.h>
20#include <linux/of.h>
21#include <linux/pinctrl/pinctrl.h>
22#include <linux/slab.h>
23
24#include "core.h"
25#include "devicetree.h"
26
27/**
28 * struct pinctrl_dt_map - mapping table chunk parsed from device tree
29 * @node: list node for struct pinctrl's @dt_maps field
30 * @pctldev: the pin controller that allocated this struct, and will free it
31 * @maps: the mapping table entries
32 */
33struct pinctrl_dt_map {
34 struct list_head node;
35 struct pinctrl_dev *pctldev;
36 struct pinctrl_map *map;
37 unsigned num_maps;
38};
39
40static void dt_free_map(struct pinctrl_dev *pctldev,
41 struct pinctrl_map *map, unsigned num_maps)
42{
43 if (pctldev) {
44 struct pinctrl_ops *ops = pctldev->desc->pctlops;
45 ops->dt_free_map(pctldev, map, num_maps);
46 } else {
47 /* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
48 kfree(map);
49 }
50}
51
52void pinctrl_dt_free_maps(struct pinctrl *p)
53{
54 struct pinctrl_dt_map *dt_map, *n1;
55
56 list_for_each_entry_safe(dt_map, n1, &p->dt_maps, node) {
57 pinctrl_unregister_map(dt_map->map);
58 list_del(&dt_map->node);
59 dt_free_map(dt_map->pctldev, dt_map->map,
60 dt_map->num_maps);
61 kfree(dt_map);
62 }
63
64 of_node_put(p->dev->of_node);
65}
66
67static int dt_remember_or_free_map(struct pinctrl *p, const char *statename,
68 struct pinctrl_dev *pctldev,
69 struct pinctrl_map *map, unsigned num_maps)
70{
71 int i;
72 struct pinctrl_dt_map *dt_map;
73
74 /* Initialize common mapping table entry fields */
75 for (i = 0; i < num_maps; i++) {
76 map[i].dev_name = dev_name(p->dev);
77 map[i].name = statename;
78 if (pctldev)
79 map[i].ctrl_dev_name = dev_name(pctldev->dev);
80 }
81
82 /* Remember the converted mapping table entries */
83 dt_map = kzalloc(sizeof(*dt_map), GFP_KERNEL);
84 if (!dt_map) {
85 dev_err(p->dev, "failed to alloc struct pinctrl_dt_map\n");
86 dt_free_map(pctldev, map, num_maps);
87 return -ENOMEM;
88 }
89
90 dt_map->pctldev = pctldev;
91 dt_map->map = map;
92 dt_map->num_maps = num_maps;
93 list_add_tail(&dt_map->node, &p->dt_maps);
94
95 return pinctrl_register_map(map, num_maps, false, true);
96}
97
98static struct pinctrl_dev *find_pinctrl_by_of_node(struct device_node *np)
99{
100 struct pinctrl_dev *pctldev;
101
102 list_for_each_entry(pctldev, &pinctrldev_list, node)
103 if (pctldev->dev->of_node == np)
104 return pctldev;
105
106 return NULL;
107}
108
109static int dt_to_map_one_config(struct pinctrl *p, const char *statename,
110 struct device_node *np_config)
111{
112 struct device_node *np_pctldev;
113 struct pinctrl_dev *pctldev;
114 struct pinctrl_ops *ops;
115 int ret;
116 struct pinctrl_map *map;
117 unsigned num_maps;
118
119 /* Find the pin controller containing np_config */
120 np_pctldev = of_node_get(np_config);
121 for (;;) {
122 np_pctldev = of_get_next_parent(np_pctldev);
123 if (!np_pctldev || of_node_is_root(np_pctldev)) {
124 dev_info(p->dev, "could not find pctldev for node %s, deferring probe\n",
125 np_config->full_name);
126 of_node_put(np_pctldev);
127 /* OK let's just assume this will appear later then */
128 return -EPROBE_DEFER;
129 }
130 pctldev = find_pinctrl_by_of_node(np_pctldev);
131 if (pctldev)
132 break;
133 }
134 of_node_put(np_pctldev);
135
136 /*
137 * Call pinctrl driver to parse device tree node, and
138 * generate mapping table entries
139 */
140 ops = pctldev->desc->pctlops;
141 if (!ops->dt_node_to_map) {
142 dev_err(p->dev, "pctldev %s doesn't support DT\n",
143 dev_name(pctldev->dev));
144 return -ENODEV;
145 }
146 ret = ops->dt_node_to_map(pctldev, np_config, &map, &num_maps);
147 if (ret < 0)
148 return ret;
149
150 /* Stash the mapping table chunk away for later use */
151 return dt_remember_or_free_map(p, statename, pctldev, map, num_maps);
152}
153
154static int dt_remember_dummy_state(struct pinctrl *p, const char *statename)
155{
156 struct pinctrl_map *map;
157
158 map = kzalloc(sizeof(*map), GFP_KERNEL);
159 if (!map) {
160 dev_err(p->dev, "failed to alloc struct pinctrl_map\n");
161 return -ENOMEM;
162 }
163
164 /* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
165 map->type = PIN_MAP_TYPE_DUMMY_STATE;
166
167 return dt_remember_or_free_map(p, statename, NULL, map, 1);
168}
169
170int pinctrl_dt_to_map(struct pinctrl *p)
171{
172 struct device_node *np = p->dev->of_node;
173 int state, ret;
174 char *propname;
175 struct property *prop;
176 const char *statename;
177 const __be32 *list;
178 int size, config;
179 phandle phandle;
180 struct device_node *np_config;
181
182 /* CONFIG_OF enabled, p->dev not instantiated from DT */
183 if (!np) {
184 dev_dbg(p->dev, "no of_node; not parsing pinctrl DT\n");
185 return 0;
186 }
187
188 /* We may store pointers to property names within the node */
189 of_node_get(np);
190
191 /* For each defined state ID */
192 for (state = 0; ; state++) {
193 /* Retrieve the pinctrl-* property */
194 propname = kasprintf(GFP_KERNEL, "pinctrl-%d", state);
195 prop = of_find_property(np, propname, &size);
196 kfree(propname);
197 if (!prop)
198 break;
199 list = prop->value;
200 size /= sizeof(*list);
201
202 /* Determine whether pinctrl-names property names the state */
203 ret = of_property_read_string_index(np, "pinctrl-names",
204 state, &statename);
205 /*
206 * If not, statename is just the integer state ID. But rather
207 * than dynamically allocate it and have to free it later,
208 * just point part way into the property name for the string.
209 */
210 if (ret < 0) {
211 /* strlen("pinctrl-") == 8 */
212 statename = prop->name + 8;
213 }
214
215 /* For every referenced pin configuration node in it */
216 for (config = 0; config < size; config++) {
217 phandle = be32_to_cpup(list++);
218
219 /* Look up the pin configuration node */
220 np_config = of_find_node_by_phandle(phandle);
221 if (!np_config) {
222 dev_err(p->dev,
223 "prop %s index %i invalid phandle\n",
224 prop->name, config);
225 ret = -EINVAL;
226 goto err;
227 }
228
229 /* Parse the node */
230 ret = dt_to_map_one_config(p, statename, np_config);
231 of_node_put(np_config);
232 if (ret < 0)
233 goto err;
234 }
235
236 /* No entries in DT? Generate a dummy state table entry */
237 if (!size) {
238 ret = dt_remember_dummy_state(p, statename);
239 if (ret < 0)
240 goto err;
241 }
242 }
243
244 return 0;
245
246err:
247 pinctrl_dt_free_maps(p);
248 return ret;
249}
diff --git a/drivers/pinctrl/devicetree.h b/drivers/pinctrl/devicetree.h
new file mode 100644
index 00000000000..760bc4960f5
--- /dev/null
+++ b/drivers/pinctrl/devicetree.h
@@ -0,0 +1,35 @@
1/*
2 * Internal interface to pinctrl device tree integration
3 *
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#ifdef CONFIG_OF
20
21void pinctrl_dt_free_maps(struct pinctrl *p);
22int pinctrl_dt_to_map(struct pinctrl *p);
23
24#else
25
26static inline int pinctrl_dt_to_map(struct pinctrl *p)
27{
28 return 0;
29}
30
31static inline void pinctrl_dt_free_maps(struct pinctrl *p)
32{
33}
34
35#endif
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index 7321e860129..7ce139ef7e6 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -28,11 +28,17 @@ int pinconf_check_ops(struct pinctrl_dev *pctldev)
28 const struct pinconf_ops *ops = pctldev->desc->confops; 28 const struct pinconf_ops *ops = pctldev->desc->confops;
29 29
30 /* We must be able to read out pin status */ 30 /* We must be able to read out pin status */
31 if (!ops->pin_config_get && !ops->pin_config_group_get) 31 if (!ops->pin_config_get && !ops->pin_config_group_get) {
32 dev_err(pctldev->dev,
33 "pinconf must be able to read out pin status\n");
32 return -EINVAL; 34 return -EINVAL;
35 }
33 /* We have to be able to config the pins in SOME way */ 36 /* We have to be able to config the pins in SOME way */
34 if (!ops->pin_config_set && !ops->pin_config_group_set) 37 if (!ops->pin_config_set && !ops->pin_config_group_set) {
38 dev_err(pctldev->dev,
39 "pinconf has to be able to set a pins config\n");
35 return -EINVAL; 40 return -EINVAL;
41 }
36 return 0; 42 return 0;
37} 43}
38 44
@@ -379,8 +385,16 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting)
379 385
380void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map) 386void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map)
381{ 387{
388 struct pinctrl_dev *pctldev;
389 const struct pinconf_ops *confops;
382 int i; 390 int i;
383 391
392 pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name);
393 if (pctldev)
394 confops = pctldev->desc->confops;
395 else
396 confops = NULL;
397
384 switch (map->type) { 398 switch (map->type) {
385 case PIN_MAP_TYPE_CONFIGS_PIN: 399 case PIN_MAP_TYPE_CONFIGS_PIN:
386 seq_printf(s, "pin "); 400 seq_printf(s, "pin ");
@@ -394,8 +408,15 @@ void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map)
394 408
395 seq_printf(s, "%s\n", map->data.configs.group_or_pin); 409 seq_printf(s, "%s\n", map->data.configs.group_or_pin);
396 410
397 for (i = 0; i < map->data.configs.num_configs; i++) 411 for (i = 0; i < map->data.configs.num_configs; i++) {
398 seq_printf(s, "config %08lx\n", map->data.configs.configs[i]); 412 seq_printf(s, "config ");
413 if (confops && confops->pin_config_config_dbg_show)
414 confops->pin_config_config_dbg_show(pctldev, s,
415 map->data.configs.configs[i]);
416 else
417 seq_printf(s, "%08lx", map->data.configs.configs[i]);
418 seq_printf(s, "\n");
419 }
399} 420}
400 421
401void pinconf_show_setting(struct seq_file *s, 422void pinconf_show_setting(struct seq_file *s,
@@ -403,6 +424,7 @@ void pinconf_show_setting(struct seq_file *s,
403{ 424{
404 struct pinctrl_dev *pctldev = setting->pctldev; 425 struct pinctrl_dev *pctldev = setting->pctldev;
405 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; 426 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
427 const struct pinconf_ops *confops = pctldev->desc->confops;
406 struct pin_desc *desc; 428 struct pin_desc *desc;
407 int i; 429 int i;
408 430
@@ -428,8 +450,15 @@ void pinconf_show_setting(struct seq_file *s,
428 * FIXME: We should really get the pin controler to dump the config 450 * FIXME: We should really get the pin controler to dump the config
429 * values, so they can be decoded to something meaningful. 451 * values, so they can be decoded to something meaningful.
430 */ 452 */
431 for (i = 0; i < setting->data.configs.num_configs; i++) 453 for (i = 0; i < setting->data.configs.num_configs; i++) {
432 seq_printf(s, " %08lx", setting->data.configs.configs[i]); 454 seq_printf(s, " ");
455 if (confops && confops->pin_config_config_dbg_show)
456 confops->pin_config_config_dbg_show(pctldev, s,
457 setting->data.configs.configs[i]);
458 else
459 seq_printf(s, "%08lx",
460 setting->data.configs.configs[i]);
461 }
433 462
434 seq_printf(s, "\n"); 463 seq_printf(s, "\n");
435} 464}
@@ -448,10 +477,14 @@ static void pinconf_dump_pin(struct pinctrl_dev *pctldev,
448static int pinconf_pins_show(struct seq_file *s, void *what) 477static int pinconf_pins_show(struct seq_file *s, void *what)
449{ 478{
450 struct pinctrl_dev *pctldev = s->private; 479 struct pinctrl_dev *pctldev = s->private;
480 const struct pinconf_ops *ops = pctldev->desc->confops;
451 unsigned i, pin; 481 unsigned i, pin;
452 482
483 if (!ops || !ops->pin_config_get)
484 return 0;
485
453 seq_puts(s, "Pin config settings per pin\n"); 486 seq_puts(s, "Pin config settings per pin\n");
454 seq_puts(s, "Format: pin (name): pinmux setting array\n"); 487 seq_puts(s, "Format: pin (name): configs\n");
455 488
456 mutex_lock(&pinctrl_mutex); 489 mutex_lock(&pinctrl_mutex);
457 490
@@ -495,17 +528,18 @@ static int pinconf_groups_show(struct seq_file *s, void *what)
495 struct pinctrl_dev *pctldev = s->private; 528 struct pinctrl_dev *pctldev = s->private;
496 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; 529 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
497 const struct pinconf_ops *ops = pctldev->desc->confops; 530 const struct pinconf_ops *ops = pctldev->desc->confops;
531 unsigned ngroups = pctlops->get_groups_count(pctldev);
498 unsigned selector = 0; 532 unsigned selector = 0;
499 533
500 if (!ops || !ops->pin_config_group_get) 534 if (!ops || !ops->pin_config_group_get)
501 return 0; 535 return 0;
502 536
503 seq_puts(s, "Pin config settings per pin group\n"); 537 seq_puts(s, "Pin config settings per pin group\n");
504 seq_puts(s, "Format: group (name): pinmux setting array\n"); 538 seq_puts(s, "Format: group (name): configs\n");
505 539
506 mutex_lock(&pinctrl_mutex); 540 mutex_lock(&pinctrl_mutex);
507 541
508 while (pctlops->list_groups(pctldev, selector) >= 0) { 542 while (selector < ngroups) {
509 const char *gname = pctlops->get_group_name(pctldev, selector); 543 const char *gname = pctlops->get_group_name(pctldev, selector);
510 544
511 seq_printf(s, "%u (%s):", selector, gname); 545 seq_printf(s, "%u (%s):", selector, gname);
diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h
index 54510de5e8c..e3ed8cb072a 100644
--- a/drivers/pinctrl/pinconf.h
+++ b/drivers/pinctrl/pinconf.h
@@ -19,11 +19,6 @@ int pinconf_map_to_setting(struct pinctrl_map const *map,
19 struct pinctrl_setting *setting); 19 struct pinctrl_setting *setting);
20void pinconf_free_setting(struct pinctrl_setting const *setting); 20void pinconf_free_setting(struct pinctrl_setting const *setting);
21int pinconf_apply_setting(struct pinctrl_setting const *setting); 21int pinconf_apply_setting(struct pinctrl_setting const *setting);
22void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map);
23void pinconf_show_setting(struct seq_file *s,
24 struct pinctrl_setting const *setting);
25void pinconf_init_device_debugfs(struct dentry *devroot,
26 struct pinctrl_dev *pctldev);
27 22
28/* 23/*
29 * You will only be interested in these if you're using PINCONF 24 * You will only be interested in these if you're using PINCONF
@@ -61,6 +56,18 @@ static inline int pinconf_apply_setting(struct pinctrl_setting const *setting)
61 return 0; 56 return 0;
62} 57}
63 58
59#endif
60
61#if defined(CONFIG_PINCONF) && defined(CONFIG_DEBUG_FS)
62
63void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map);
64void pinconf_show_setting(struct seq_file *s,
65 struct pinctrl_setting const *setting);
66void pinconf_init_device_debugfs(struct dentry *devroot,
67 struct pinctrl_dev *pctldev);
68
69#else
70
64static inline void pinconf_show_map(struct seq_file *s, 71static inline void pinconf_show_map(struct seq_file *s,
65 struct pinctrl_map const *map) 72 struct pinctrl_map const *map)
66{ 73{
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index 0797eba3e33..55697a5d748 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -174,7 +174,7 @@ struct u300_gpio_confdata {
174 174
175 175
176/* Initial configuration */ 176/* Initial configuration */
177static const struct __initdata u300_gpio_confdata 177static const struct __initconst u300_gpio_confdata
178bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { 178bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
179 /* Port 0, pins 0-7 */ 179 /* Port 0, pins 0-7 */
180 { 180 {
@@ -255,7 +255,7 @@ bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
255 } 255 }
256}; 256};
257 257
258static const struct __initdata u300_gpio_confdata 258static const struct __initconst u300_gpio_confdata
259bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { 259bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
260 /* Port 0, pins 0-7 */ 260 /* Port 0, pins 0-7 */
261 { 261 {
diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c
new file mode 100644
index 00000000000..8faf613ff1b
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx.c
@@ -0,0 +1,627 @@
1/*
2 * Core driver for the imx pin controller
3 *
4 * Copyright (C) 2012 Freescale Semiconductor, Inc.
5 * Copyright (C) 2012 Linaro Ltd.
6 *
7 * Author: Dong Aisheng <dong.aisheng@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/pinctrl/machine.h>
22#include <linux/pinctrl/pinconf.h>
23#include <linux/pinctrl/pinctrl.h>
24#include <linux/pinctrl/pinmux.h>
25#include <linux/slab.h>
26
27#include "core.h"
28#include "pinctrl-imx.h"
29
30#define IMX_PMX_DUMP(info, p, m, c, n) \
31{ \
32 int i, j; \
33 printk("Format: Pin Mux Config\n"); \
34 for (i = 0; i < n; i++) { \
35 j = p[i]; \
36 printk("%s %d 0x%lx\n", \
37 info->pins[j].name, \
38 m[i], c[i]); \
39 } \
40}
41
42/* The bits in CONFIG cell defined in binding doc*/
43#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
44#define IMX_PAD_SION 0x40000000 /* set SION */
45
46/**
47 * @dev: a pointer back to containing device
48 * @base: the offset to the controller in virtual memory
49 */
50struct imx_pinctrl {
51 struct device *dev;
52 struct pinctrl_dev *pctl;
53 void __iomem *base;
54 const struct imx_pinctrl_soc_info *info;
55};
56
57static const struct imx_pin_reg *imx_find_pin_reg(
58 const struct imx_pinctrl_soc_info *info,
59 unsigned pin, bool is_mux, unsigned mux)
60{
61 const struct imx_pin_reg *pin_reg = NULL;
62 int i;
63
64 for (i = 0; i < info->npin_regs; i++) {
65 pin_reg = &info->pin_regs[i];
66 if (pin_reg->pid != pin)
67 continue;
68 if (!is_mux)
69 break;
70 else if (pin_reg->mux_mode == (mux & IMX_MUX_MASK))
71 break;
72 }
73
74 if (!pin_reg) {
75 dev_err(info->dev, "Pin(%s): unable to find pin reg map\n",
76 info->pins[pin].name);
77 return NULL;
78 }
79
80 return pin_reg;
81}
82
83static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
84 const struct imx_pinctrl_soc_info *info,
85 const char *name)
86{
87 const struct imx_pin_group *grp = NULL;
88 int i;
89
90 for (i = 0; i < info->ngroups; i++) {
91 if (!strcmp(info->groups[i].name, name)) {
92 grp = &info->groups[i];
93 break;
94 }
95 }
96
97 return grp;
98}
99
100static int imx_get_groups_count(struct pinctrl_dev *pctldev)
101{
102 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
103 const struct imx_pinctrl_soc_info *info = ipctl->info;
104
105 return info->ngroups;
106}
107
108static const char *imx_get_group_name(struct pinctrl_dev *pctldev,
109 unsigned selector)
110{
111 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
112 const struct imx_pinctrl_soc_info *info = ipctl->info;
113
114 return info->groups[selector].name;
115}
116
117static int imx_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
118 const unsigned **pins,
119 unsigned *npins)
120{
121 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
122 const struct imx_pinctrl_soc_info *info = ipctl->info;
123
124 if (selector >= info->ngroups)
125 return -EINVAL;
126
127 *pins = info->groups[selector].pins;
128 *npins = info->groups[selector].npins;
129
130 return 0;
131}
132
133static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
134 unsigned offset)
135{
136 seq_printf(s, "%s", dev_name(pctldev->dev));
137}
138
139static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
140 struct device_node *np,
141 struct pinctrl_map **map, unsigned *num_maps)
142{
143 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
144 const struct imx_pinctrl_soc_info *info = ipctl->info;
145 const struct imx_pin_group *grp;
146 struct pinctrl_map *new_map;
147 struct device_node *parent;
148 int map_num = 1;
149 int i;
150
151 /*
152 * first find the group of this node and check if we need create
153 * config maps for pins
154 */
155 grp = imx_pinctrl_find_group_by_name(info, np->name);
156 if (!grp) {
157 dev_err(info->dev, "unable to find group for node %s\n",
158 np->name);
159 return -EINVAL;
160 }
161
162 for (i = 0; i < grp->npins; i++) {
163 if (!(grp->configs[i] & IMX_NO_PAD_CTL))
164 map_num++;
165 }
166
167 new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
168 if (!new_map)
169 return -ENOMEM;
170
171 *map = new_map;
172 *num_maps = map_num;
173
174 /* create mux map */
175 parent = of_get_parent(np);
176 if (!parent)
177 return -EINVAL;
178 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
179 new_map[0].data.mux.function = parent->name;
180 new_map[0].data.mux.group = np->name;
181 of_node_put(parent);
182
183 /* create config map */
184 new_map++;
185 for (i = 0; i < grp->npins; i++) {
186 if (!(grp->configs[i] & IMX_NO_PAD_CTL)) {
187 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
188 new_map[i].data.configs.group_or_pin =
189 pin_get_name(pctldev, grp->pins[i]);
190 new_map[i].data.configs.configs = &grp->configs[i];
191 new_map[i].data.configs.num_configs = 1;
192 }
193 }
194
195 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
196 new_map->data.mux.function, new_map->data.mux.group, map_num);
197
198 return 0;
199}
200
201static void imx_dt_free_map(struct pinctrl_dev *pctldev,
202 struct pinctrl_map *map, unsigned num_maps)
203{
204 int i;
205
206 for (i = 0; i < num_maps; i++)
207 kfree(map);
208}
209
210static struct pinctrl_ops imx_pctrl_ops = {
211 .get_groups_count = imx_get_groups_count,
212 .get_group_name = imx_get_group_name,
213 .get_group_pins = imx_get_group_pins,
214 .pin_dbg_show = imx_pin_dbg_show,
215 .dt_node_to_map = imx_dt_node_to_map,
216 .dt_free_map = imx_dt_free_map,
217
218};
219
220static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
221 unsigned group)
222{
223 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
224 const struct imx_pinctrl_soc_info *info = ipctl->info;
225 const struct imx_pin_reg *pin_reg;
226 const unsigned *pins, *mux;
227 unsigned int npins, pin_id;
228 int i;
229
230 /*
231 * Configure the mux mode for each pin in the group for a specific
232 * function.
233 */
234 pins = info->groups[group].pins;
235 npins = info->groups[group].npins;
236 mux = info->groups[group].mux_mode;
237
238 WARN_ON(!pins || !npins || !mux);
239
240 dev_dbg(ipctl->dev, "enable function %s group %s\n",
241 info->functions[selector].name, info->groups[group].name);
242
243 for (i = 0; i < npins; i++) {
244 pin_id = pins[i];
245
246 pin_reg = imx_find_pin_reg(info, pin_id, 1, mux[i]);
247 if (!pin_reg)
248 return -EINVAL;
249
250 if (!pin_reg->mux_reg) {
251 dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
252 info->pins[pin_id].name);
253 return -EINVAL;
254 }
255
256 writel(mux[i], ipctl->base + pin_reg->mux_reg);
257 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
258 pin_reg->mux_reg, mux[i]);
259
260 /* some pins also need select input setting, set it if found */
261 if (pin_reg->input_reg) {
262 writel(pin_reg->input_val, ipctl->base + pin_reg->input_reg);
263 dev_dbg(ipctl->dev,
264 "==>select_input: offset 0x%x val 0x%x\n",
265 pin_reg->input_reg, pin_reg->input_val);
266 }
267 }
268
269 return 0;
270}
271
272static void imx_pmx_disable(struct pinctrl_dev *pctldev, unsigned func_selector,
273 unsigned group_selector)
274{
275 /* nothing to do here */
276}
277
278static int imx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
279{
280 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
281 const struct imx_pinctrl_soc_info *info = ipctl->info;
282
283 return info->nfunctions;
284}
285
286static const char *imx_pmx_get_func_name(struct pinctrl_dev *pctldev,
287 unsigned selector)
288{
289 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
290 const struct imx_pinctrl_soc_info *info = ipctl->info;
291
292 return info->functions[selector].name;
293}
294
295static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
296 const char * const **groups,
297 unsigned * const num_groups)
298{
299 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
300 const struct imx_pinctrl_soc_info *info = ipctl->info;
301
302 *groups = info->functions[selector].groups;
303 *num_groups = info->functions[selector].num_groups;
304
305 return 0;
306}
307
308static struct pinmux_ops imx_pmx_ops = {
309 .get_functions_count = imx_pmx_get_funcs_count,
310 .get_function_name = imx_pmx_get_func_name,
311 .get_function_groups = imx_pmx_get_groups,
312 .enable = imx_pmx_enable,
313 .disable = imx_pmx_disable,
314};
315
316static int imx_pinconf_get(struct pinctrl_dev *pctldev,
317 unsigned pin_id, unsigned long *config)
318{
319 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
320 const struct imx_pinctrl_soc_info *info = ipctl->info;
321 const struct imx_pin_reg *pin_reg;
322
323 pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
324 if (!pin_reg)
325 return -EINVAL;
326
327 if (!pin_reg->conf_reg) {
328 dev_err(info->dev, "Pin(%s) does not support config function\n",
329 info->pins[pin_id].name);
330 return -EINVAL;
331 }
332
333 *config = readl(ipctl->base + pin_reg->conf_reg);
334
335 return 0;
336}
337
338static int imx_pinconf_set(struct pinctrl_dev *pctldev,
339 unsigned pin_id, unsigned long config)
340{
341 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
342 const struct imx_pinctrl_soc_info *info = ipctl->info;
343 const struct imx_pin_reg *pin_reg;
344
345 pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
346 if (!pin_reg)
347 return -EINVAL;
348
349 if (!pin_reg->conf_reg) {
350 dev_err(info->dev, "Pin(%s) does not support config function\n",
351 info->pins[pin_id].name);
352 return -EINVAL;
353 }
354
355 dev_dbg(ipctl->dev, "pinconf set pin %s\n",
356 info->pins[pin_id].name);
357
358 writel(config, ipctl->base + pin_reg->conf_reg);
359 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
360 pin_reg->conf_reg, config);
361
362 return 0;
363}
364
365static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
366 struct seq_file *s, unsigned pin_id)
367{
368 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
369 const struct imx_pinctrl_soc_info *info = ipctl->info;
370 const struct imx_pin_reg *pin_reg;
371 unsigned long config;
372
373 pin_reg = imx_find_pin_reg(info, pin_id, 0, 0);
374 if (!pin_reg || !pin_reg->conf_reg) {
375 seq_printf(s, "N/A");
376 return;
377 }
378
379 config = readl(ipctl->base + pin_reg->conf_reg);
380 seq_printf(s, "0x%lx", config);
381}
382
383static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
384 struct seq_file *s, unsigned group)
385{
386 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
387 const struct imx_pinctrl_soc_info *info = ipctl->info;
388 struct imx_pin_group *grp;
389 unsigned long config;
390 const char *name;
391 int i, ret;
392
393 if (group > info->ngroups)
394 return;
395
396 seq_printf(s, "\n");
397 grp = &info->groups[group];
398 for (i = 0; i < grp->npins; i++) {
399 name = pin_get_name(pctldev, grp->pins[i]);
400 ret = imx_pinconf_get(pctldev, grp->pins[i], &config);
401 if (ret)
402 return;
403 seq_printf(s, "%s: 0x%lx", name, config);
404 }
405}
406
407struct pinconf_ops imx_pinconf_ops = {
408 .pin_config_get = imx_pinconf_get,
409 .pin_config_set = imx_pinconf_set,
410 .pin_config_dbg_show = imx_pinconf_dbg_show,
411 .pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
412};
413
414static struct pinctrl_desc imx_pinctrl_desc = {
415 .pctlops = &imx_pctrl_ops,
416 .pmxops = &imx_pmx_ops,
417 .confops = &imx_pinconf_ops,
418 .owner = THIS_MODULE,
419};
420
421/* decode pin id and mux from pin function id got from device tree*/
422static int imx_pinctrl_get_pin_id_and_mux(const struct imx_pinctrl_soc_info *info,
423 unsigned int pin_func_id, unsigned int *pin_id,
424 unsigned int *mux)
425{
426 if (pin_func_id > info->npin_regs)
427 return -EINVAL;
428
429 *pin_id = info->pin_regs[pin_func_id].pid;
430 *mux = info->pin_regs[pin_func_id].mux_mode;
431
432 return 0;
433}
434
435static int __devinit imx_pinctrl_parse_groups(struct device_node *np,
436 struct imx_pin_group *grp,
437 struct imx_pinctrl_soc_info *info,
438 u32 index)
439{
440 unsigned int pin_func_id;
441 int ret, size;
442 const const __be32 *list;
443 int i, j;
444 u32 config;
445
446 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
447
448 /* Initialise group */
449 grp->name = np->name;
450
451 /*
452 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
453 * do sanity check and calculate pins number
454 */
455 list = of_get_property(np, "fsl,pins", &size);
456 /* we do not check return since it's safe node passed down */
457 size /= sizeof(*list);
458 if (!size || size % 2) {
459 dev_err(info->dev, "wrong pins number or pins and configs should be pairs\n");
460 return -EINVAL;
461 }
462
463 grp->npins = size / 2;
464 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
465 GFP_KERNEL);
466 grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
467 GFP_KERNEL);
468 grp->configs = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned long),
469 GFP_KERNEL);
470 for (i = 0, j = 0; i < size; i += 2, j++) {
471 pin_func_id = be32_to_cpu(*list++);
472 ret = imx_pinctrl_get_pin_id_and_mux(info, pin_func_id,
473 &grp->pins[j], &grp->mux_mode[j]);
474 if (ret) {
475 dev_err(info->dev, "get invalid pin function id\n");
476 return -EINVAL;
477 }
478 /* SION bit is in mux register */
479 config = be32_to_cpu(*list++);
480 if (config & IMX_PAD_SION)
481 grp->mux_mode[j] |= IOMUXC_CONFIG_SION;
482 grp->configs[j] = config & ~IMX_PAD_SION;
483 }
484
485#ifdef DEBUG
486 IMX_PMX_DUMP(info, grp->pins, grp->mux_mode, grp->configs, grp->npins);
487#endif
488 return 0;
489}
490
491static int __devinit imx_pinctrl_parse_functions(struct device_node *np,
492 struct imx_pinctrl_soc_info *info, u32 index)
493{
494 struct device_node *child;
495 struct imx_pmx_func *func;
496 struct imx_pin_group *grp;
497 int ret;
498 static u32 grp_index;
499 u32 i = 0;
500
501 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
502
503 func = &info->functions[index];
504
505 /* Initialise function */
506 func->name = np->name;
507 func->num_groups = of_get_child_count(np);
508 if (func->num_groups <= 0) {
509 dev_err(info->dev, "no groups defined\n");
510 return -EINVAL;
511 }
512 func->groups = devm_kzalloc(info->dev,
513 func->num_groups * sizeof(char *), GFP_KERNEL);
514
515 for_each_child_of_node(np, child) {
516 func->groups[i] = child->name;
517 grp = &info->groups[grp_index++];
518 ret = imx_pinctrl_parse_groups(child, grp, info, i++);
519 if (ret)
520 return ret;
521 }
522
523 return 0;
524}
525
526static int __devinit imx_pinctrl_probe_dt(struct platform_device *pdev,
527 struct imx_pinctrl_soc_info *info)
528{
529 struct device_node *np = pdev->dev.of_node;
530 struct device_node *child;
531 int ret;
532 u32 nfuncs = 0;
533 u32 i = 0;
534
535 if (!np)
536 return -ENODEV;
537
538 nfuncs = of_get_child_count(np);
539 if (nfuncs <= 0) {
540 dev_err(&pdev->dev, "no functions defined\n");
541 return -EINVAL;
542 }
543
544 info->nfunctions = nfuncs;
545 info->functions = devm_kzalloc(&pdev->dev, nfuncs * sizeof(struct imx_pmx_func),
546 GFP_KERNEL);
547 if (!info->functions)
548 return -ENOMEM;
549
550 info->ngroups = 0;
551 for_each_child_of_node(np, child)
552 info->ngroups += of_get_child_count(child);
553 info->groups = devm_kzalloc(&pdev->dev, info->ngroups * sizeof(struct imx_pin_group),
554 GFP_KERNEL);
555 if (!info->groups)
556 return -ENOMEM;
557
558 for_each_child_of_node(np, child) {
559 ret = imx_pinctrl_parse_functions(child, info, i++);
560 if (ret) {
561 dev_err(&pdev->dev, "failed to parse function\n");
562 return ret;
563 }
564 }
565
566 return 0;
567}
568
569int __devinit imx_pinctrl_probe(struct platform_device *pdev,
570 struct imx_pinctrl_soc_info *info)
571{
572 struct imx_pinctrl *ipctl;
573 struct resource *res;
574 int ret;
575
576 if (!info || !info->pins || !info->npins
577 || !info->pin_regs || !info->npin_regs) {
578 dev_err(&pdev->dev, "wrong pinctrl info\n");
579 return -EINVAL;
580 }
581 info->dev = &pdev->dev;
582
583 /* Create state holders etc for this driver */
584 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
585 if (!ipctl)
586 return -ENOMEM;
587
588 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
589 if (!res)
590 return -ENOENT;
591
592 ipctl->base = devm_request_and_ioremap(&pdev->dev, res);
593 if (!ipctl->base)
594 return -EBUSY;
595
596 imx_pinctrl_desc.name = dev_name(&pdev->dev);
597 imx_pinctrl_desc.pins = info->pins;
598 imx_pinctrl_desc.npins = info->npins;
599
600 ret = imx_pinctrl_probe_dt(pdev, info);
601 if (ret) {
602 dev_err(&pdev->dev, "fail to probe dt properties\n");
603 return ret;
604 }
605
606 ipctl->info = info;
607 ipctl->dev = info->dev;
608 platform_set_drvdata(pdev, ipctl);
609 ipctl->pctl = pinctrl_register(&imx_pinctrl_desc, &pdev->dev, ipctl);
610 if (!ipctl->pctl) {
611 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
612 return -EINVAL;
613 }
614
615 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
616
617 return 0;
618}
619
620int __devexit imx_pinctrl_remove(struct platform_device *pdev)
621{
622 struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);
623
624 pinctrl_unregister(ipctl->pctl);
625
626 return 0;
627}
diff --git a/drivers/pinctrl/pinctrl-imx.h b/drivers/pinctrl/pinctrl-imx.h
new file mode 100644
index 00000000000..9b65e7828f1
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx.h
@@ -0,0 +1,106 @@
1/*
2 * IMX pinmux core definitions
3 *
4 * Copyright (C) 2012 Freescale Semiconductor, Inc.
5 * Copyright (C) 2012 Linaro Ltd.
6 *
7 * Author: Dong Aisheng <dong.aisheng@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef __DRIVERS_PINCTRL_IMX_H
16#define __DRIVERS_PINCTRL_IMX_H
17
18struct platform_device;
19
20/**
21 * struct imx_pin_group - describes an IMX pin group
22 * @name: the name of this specific pin group
23 * @pins: an array of discrete physical pins used in this group, taken
24 * from the driver-local pin enumeration space
25 * @npins: the number of pins in this group array, i.e. the number of
26 * elements in .pins so we can iterate over that array
27 * @mux_mode: the mux mode for each pin in this group. The size of this
28 * array is the same as pins.
29 * @configs: the config for each pin in this group. The size of this
30 * array is the same as pins.
31 */
32struct imx_pin_group {
33 const char *name;
34 unsigned int *pins;
35 unsigned npins;
36 unsigned int *mux_mode;
37 unsigned long *configs;
38};
39
40/**
41 * struct imx_pmx_func - describes IMX pinmux functions
42 * @name: the name of this specific function
43 * @groups: corresponding pin groups
44 * @num_groups: the number of groups
45 */
46struct imx_pmx_func {
47 const char *name;
48 const char **groups;
49 unsigned num_groups;
50};
51
52/**
53 * struct imx_pin_reg - describe a pin reg map
54 * The last 3 members are used for select input setting
55 * @pid: pin id
56 * @mux_reg: mux register offset
57 * @conf_reg: config register offset
58 * @mux_mode: mux mode
59 * @input_reg: select input register offset for this mux if any
60 * 0 if no select input setting needed.
61 * @input_val: the value set to select input register
62 */
63struct imx_pin_reg {
64 u16 pid;
65 u16 mux_reg;
66 u16 conf_reg;
67 u8 mux_mode;
68 u16 input_reg;
69 u8 input_val;
70};
71
72struct imx_pinctrl_soc_info {
73 struct device *dev;
74 const struct pinctrl_pin_desc *pins;
75 unsigned int npins;
76 const struct imx_pin_reg *pin_regs;
77 unsigned int npin_regs;
78 struct imx_pin_group *groups;
79 unsigned int ngroups;
80 struct imx_pmx_func *functions;
81 unsigned int nfunctions;
82};
83
84#define NO_MUX 0x0
85#define NO_PAD 0x0
86
87#define IMX_PIN_REG(id, conf, mux, mode, input, val) \
88 { \
89 .pid = id, \
90 .conf_reg = conf, \
91 .mux_reg = mux, \
92 .mux_mode = mode, \
93 .input_reg = input, \
94 .input_val = val, \
95 }
96
97#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
98
99#define PAD_CTL_MASK(len) ((1 << len) - 1)
100#define IMX_MUX_MASK 0x7
101#define IOMUXC_CONFIG_SION (0x1 << 4)
102
103int imx_pinctrl_probe(struct platform_device *pdev,
104 struct imx_pinctrl_soc_info *info);
105int imx_pinctrl_remove(struct platform_device *pdev);
106#endif /* __DRIVERS_PINCTRL_IMX_H */
diff --git a/drivers/pinctrl/pinctrl-imx23.c b/drivers/pinctrl/pinctrl-imx23.c
new file mode 100644
index 00000000000..75d3eff9429
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx23.c
@@ -0,0 +1,305 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/of_device.h>
15#include <linux/pinctrl/pinctrl.h>
16#include "pinctrl-mxs.h"
17
18enum imx23_pin_enum {
19 GPMI_D00 = PINID(0, 0),
20 GPMI_D01 = PINID(0, 1),
21 GPMI_D02 = PINID(0, 2),
22 GPMI_D03 = PINID(0, 3),
23 GPMI_D04 = PINID(0, 4),
24 GPMI_D05 = PINID(0, 5),
25 GPMI_D06 = PINID(0, 6),
26 GPMI_D07 = PINID(0, 7),
27 GPMI_D08 = PINID(0, 8),
28 GPMI_D09 = PINID(0, 9),
29 GPMI_D10 = PINID(0, 10),
30 GPMI_D11 = PINID(0, 11),
31 GPMI_D12 = PINID(0, 12),
32 GPMI_D13 = PINID(0, 13),
33 GPMI_D14 = PINID(0, 14),
34 GPMI_D15 = PINID(0, 15),
35 GPMI_CLE = PINID(0, 16),
36 GPMI_ALE = PINID(0, 17),
37 GPMI_CE2N = PINID(0, 18),
38 GPMI_RDY0 = PINID(0, 19),
39 GPMI_RDY1 = PINID(0, 20),
40 GPMI_RDY2 = PINID(0, 21),
41 GPMI_RDY3 = PINID(0, 22),
42 GPMI_WPN = PINID(0, 23),
43 GPMI_WRN = PINID(0, 24),
44 GPMI_RDN = PINID(0, 25),
45 AUART1_CTS = PINID(0, 26),
46 AUART1_RTS = PINID(0, 27),
47 AUART1_RX = PINID(0, 28),
48 AUART1_TX = PINID(0, 29),
49 I2C_SCL = PINID(0, 30),
50 I2C_SDA = PINID(0, 31),
51 LCD_D00 = PINID(1, 0),
52 LCD_D01 = PINID(1, 1),
53 LCD_D02 = PINID(1, 2),
54 LCD_D03 = PINID(1, 3),
55 LCD_D04 = PINID(1, 4),
56 LCD_D05 = PINID(1, 5),
57 LCD_D06 = PINID(1, 6),
58 LCD_D07 = PINID(1, 7),
59 LCD_D08 = PINID(1, 8),
60 LCD_D09 = PINID(1, 9),
61 LCD_D10 = PINID(1, 10),
62 LCD_D11 = PINID(1, 11),
63 LCD_D12 = PINID(1, 12),
64 LCD_D13 = PINID(1, 13),
65 LCD_D14 = PINID(1, 14),
66 LCD_D15 = PINID(1, 15),
67 LCD_D16 = PINID(1, 16),
68 LCD_D17 = PINID(1, 17),
69 LCD_RESET = PINID(1, 18),
70 LCD_RS = PINID(1, 19),
71 LCD_WR = PINID(1, 20),
72 LCD_CS = PINID(1, 21),
73 LCD_DOTCK = PINID(1, 22),
74 LCD_ENABLE = PINID(1, 23),
75 LCD_HSYNC = PINID(1, 24),
76 LCD_VSYNC = PINID(1, 25),
77 PWM0 = PINID(1, 26),
78 PWM1 = PINID(1, 27),
79 PWM2 = PINID(1, 28),
80 PWM3 = PINID(1, 29),
81 PWM4 = PINID(1, 30),
82 SSP1_CMD = PINID(2, 0),
83 SSP1_DETECT = PINID(2, 1),
84 SSP1_DATA0 = PINID(2, 2),
85 SSP1_DATA1 = PINID(2, 3),
86 SSP1_DATA2 = PINID(2, 4),
87 SSP1_DATA3 = PINID(2, 5),
88 SSP1_SCK = PINID(2, 6),
89 ROTARYA = PINID(2, 7),
90 ROTARYB = PINID(2, 8),
91 EMI_A00 = PINID(2, 9),
92 EMI_A01 = PINID(2, 10),
93 EMI_A02 = PINID(2, 11),
94 EMI_A03 = PINID(2, 12),
95 EMI_A04 = PINID(2, 13),
96 EMI_A05 = PINID(2, 14),
97 EMI_A06 = PINID(2, 15),
98 EMI_A07 = PINID(2, 16),
99 EMI_A08 = PINID(2, 17),
100 EMI_A09 = PINID(2, 18),
101 EMI_A10 = PINID(2, 19),
102 EMI_A11 = PINID(2, 20),
103 EMI_A12 = PINID(2, 21),
104 EMI_BA0 = PINID(2, 22),
105 EMI_BA1 = PINID(2, 23),
106 EMI_CASN = PINID(2, 24),
107 EMI_CE0N = PINID(2, 25),
108 EMI_CE1N = PINID(2, 26),
109 GPMI_CE1N = PINID(2, 27),
110 GPMI_CE0N = PINID(2, 28),
111 EMI_CKE = PINID(2, 29),
112 EMI_RASN = PINID(2, 30),
113 EMI_WEN = PINID(2, 31),
114 EMI_D00 = PINID(3, 0),
115 EMI_D01 = PINID(3, 1),
116 EMI_D02 = PINID(3, 2),
117 EMI_D03 = PINID(3, 3),
118 EMI_D04 = PINID(3, 4),
119 EMI_D05 = PINID(3, 5),
120 EMI_D06 = PINID(3, 6),
121 EMI_D07 = PINID(3, 7),
122 EMI_D08 = PINID(3, 8),
123 EMI_D09 = PINID(3, 9),
124 EMI_D10 = PINID(3, 10),
125 EMI_D11 = PINID(3, 11),
126 EMI_D12 = PINID(3, 12),
127 EMI_D13 = PINID(3, 13),
128 EMI_D14 = PINID(3, 14),
129 EMI_D15 = PINID(3, 15),
130 EMI_DQM0 = PINID(3, 16),
131 EMI_DQM1 = PINID(3, 17),
132 EMI_DQS0 = PINID(3, 18),
133 EMI_DQS1 = PINID(3, 19),
134 EMI_CLK = PINID(3, 20),
135 EMI_CLKN = PINID(3, 21),
136};
137
138static const struct pinctrl_pin_desc imx23_pins[] = {
139 MXS_PINCTRL_PIN(GPMI_D00),
140 MXS_PINCTRL_PIN(GPMI_D01),
141 MXS_PINCTRL_PIN(GPMI_D02),
142 MXS_PINCTRL_PIN(GPMI_D03),
143 MXS_PINCTRL_PIN(GPMI_D04),
144 MXS_PINCTRL_PIN(GPMI_D05),
145 MXS_PINCTRL_PIN(GPMI_D06),
146 MXS_PINCTRL_PIN(GPMI_D07),
147 MXS_PINCTRL_PIN(GPMI_D08),
148 MXS_PINCTRL_PIN(GPMI_D09),
149 MXS_PINCTRL_PIN(GPMI_D10),
150 MXS_PINCTRL_PIN(GPMI_D11),
151 MXS_PINCTRL_PIN(GPMI_D12),
152 MXS_PINCTRL_PIN(GPMI_D13),
153 MXS_PINCTRL_PIN(GPMI_D14),
154 MXS_PINCTRL_PIN(GPMI_D15),
155 MXS_PINCTRL_PIN(GPMI_CLE),
156 MXS_PINCTRL_PIN(GPMI_ALE),
157 MXS_PINCTRL_PIN(GPMI_CE2N),
158 MXS_PINCTRL_PIN(GPMI_RDY0),
159 MXS_PINCTRL_PIN(GPMI_RDY1),
160 MXS_PINCTRL_PIN(GPMI_RDY2),
161 MXS_PINCTRL_PIN(GPMI_RDY3),
162 MXS_PINCTRL_PIN(GPMI_WPN),
163 MXS_PINCTRL_PIN(GPMI_WRN),
164 MXS_PINCTRL_PIN(GPMI_RDN),
165 MXS_PINCTRL_PIN(AUART1_CTS),
166 MXS_PINCTRL_PIN(AUART1_RTS),
167 MXS_PINCTRL_PIN(AUART1_RX),
168 MXS_PINCTRL_PIN(AUART1_TX),
169 MXS_PINCTRL_PIN(I2C_SCL),
170 MXS_PINCTRL_PIN(I2C_SDA),
171 MXS_PINCTRL_PIN(LCD_D00),
172 MXS_PINCTRL_PIN(LCD_D01),
173 MXS_PINCTRL_PIN(LCD_D02),
174 MXS_PINCTRL_PIN(LCD_D03),
175 MXS_PINCTRL_PIN(LCD_D04),
176 MXS_PINCTRL_PIN(LCD_D05),
177 MXS_PINCTRL_PIN(LCD_D06),
178 MXS_PINCTRL_PIN(LCD_D07),
179 MXS_PINCTRL_PIN(LCD_D08),
180 MXS_PINCTRL_PIN(LCD_D09),
181 MXS_PINCTRL_PIN(LCD_D10),
182 MXS_PINCTRL_PIN(LCD_D11),
183 MXS_PINCTRL_PIN(LCD_D12),
184 MXS_PINCTRL_PIN(LCD_D13),
185 MXS_PINCTRL_PIN(LCD_D14),
186 MXS_PINCTRL_PIN(LCD_D15),
187 MXS_PINCTRL_PIN(LCD_D16),
188 MXS_PINCTRL_PIN(LCD_D17),
189 MXS_PINCTRL_PIN(LCD_RESET),
190 MXS_PINCTRL_PIN(LCD_RS),
191 MXS_PINCTRL_PIN(LCD_WR),
192 MXS_PINCTRL_PIN(LCD_CS),
193 MXS_PINCTRL_PIN(LCD_DOTCK),
194 MXS_PINCTRL_PIN(LCD_ENABLE),
195 MXS_PINCTRL_PIN(LCD_HSYNC),
196 MXS_PINCTRL_PIN(LCD_VSYNC),
197 MXS_PINCTRL_PIN(PWM0),
198 MXS_PINCTRL_PIN(PWM1),
199 MXS_PINCTRL_PIN(PWM2),
200 MXS_PINCTRL_PIN(PWM3),
201 MXS_PINCTRL_PIN(PWM4),
202 MXS_PINCTRL_PIN(SSP1_CMD),
203 MXS_PINCTRL_PIN(SSP1_DETECT),
204 MXS_PINCTRL_PIN(SSP1_DATA0),
205 MXS_PINCTRL_PIN(SSP1_DATA1),
206 MXS_PINCTRL_PIN(SSP1_DATA2),
207 MXS_PINCTRL_PIN(SSP1_DATA3),
208 MXS_PINCTRL_PIN(SSP1_SCK),
209 MXS_PINCTRL_PIN(ROTARYA),
210 MXS_PINCTRL_PIN(ROTARYB),
211 MXS_PINCTRL_PIN(EMI_A00),
212 MXS_PINCTRL_PIN(EMI_A01),
213 MXS_PINCTRL_PIN(EMI_A02),
214 MXS_PINCTRL_PIN(EMI_A03),
215 MXS_PINCTRL_PIN(EMI_A04),
216 MXS_PINCTRL_PIN(EMI_A05),
217 MXS_PINCTRL_PIN(EMI_A06),
218 MXS_PINCTRL_PIN(EMI_A07),
219 MXS_PINCTRL_PIN(EMI_A08),
220 MXS_PINCTRL_PIN(EMI_A09),
221 MXS_PINCTRL_PIN(EMI_A10),
222 MXS_PINCTRL_PIN(EMI_A11),
223 MXS_PINCTRL_PIN(EMI_A12),
224 MXS_PINCTRL_PIN(EMI_BA0),
225 MXS_PINCTRL_PIN(EMI_BA1),
226 MXS_PINCTRL_PIN(EMI_CASN),
227 MXS_PINCTRL_PIN(EMI_CE0N),
228 MXS_PINCTRL_PIN(EMI_CE1N),
229 MXS_PINCTRL_PIN(GPMI_CE1N),
230 MXS_PINCTRL_PIN(GPMI_CE0N),
231 MXS_PINCTRL_PIN(EMI_CKE),
232 MXS_PINCTRL_PIN(EMI_RASN),
233 MXS_PINCTRL_PIN(EMI_WEN),
234 MXS_PINCTRL_PIN(EMI_D00),
235 MXS_PINCTRL_PIN(EMI_D01),
236 MXS_PINCTRL_PIN(EMI_D02),
237 MXS_PINCTRL_PIN(EMI_D03),
238 MXS_PINCTRL_PIN(EMI_D04),
239 MXS_PINCTRL_PIN(EMI_D05),
240 MXS_PINCTRL_PIN(EMI_D06),
241 MXS_PINCTRL_PIN(EMI_D07),
242 MXS_PINCTRL_PIN(EMI_D08),
243 MXS_PINCTRL_PIN(EMI_D09),
244 MXS_PINCTRL_PIN(EMI_D10),
245 MXS_PINCTRL_PIN(EMI_D11),
246 MXS_PINCTRL_PIN(EMI_D12),
247 MXS_PINCTRL_PIN(EMI_D13),
248 MXS_PINCTRL_PIN(EMI_D14),
249 MXS_PINCTRL_PIN(EMI_D15),
250 MXS_PINCTRL_PIN(EMI_DQM0),
251 MXS_PINCTRL_PIN(EMI_DQM1),
252 MXS_PINCTRL_PIN(EMI_DQS0),
253 MXS_PINCTRL_PIN(EMI_DQS1),
254 MXS_PINCTRL_PIN(EMI_CLK),
255 MXS_PINCTRL_PIN(EMI_CLKN),
256};
257
258static struct mxs_regs imx23_regs = {
259 .muxsel = 0x100,
260 .drive = 0x200,
261 .pull = 0x400,
262};
263
264static struct mxs_pinctrl_soc_data imx23_pinctrl_data = {
265 .regs = &imx23_regs,
266 .pins = imx23_pins,
267 .npins = ARRAY_SIZE(imx23_pins),
268};
269
270static int __devinit imx23_pinctrl_probe(struct platform_device *pdev)
271{
272 return mxs_pinctrl_probe(pdev, &imx23_pinctrl_data);
273}
274
275static struct of_device_id imx23_pinctrl_of_match[] __devinitdata = {
276 { .compatible = "fsl,imx23-pinctrl", },
277 { /* sentinel */ }
278};
279MODULE_DEVICE_TABLE(of, imx23_pinctrl_of_match);
280
281static struct platform_driver imx23_pinctrl_driver = {
282 .driver = {
283 .name = "imx23-pinctrl",
284 .owner = THIS_MODULE,
285 .of_match_table = imx23_pinctrl_of_match,
286 },
287 .probe = imx23_pinctrl_probe,
288 .remove = __devexit_p(mxs_pinctrl_remove),
289};
290
291static int __init imx23_pinctrl_init(void)
292{
293 return platform_driver_register(&imx23_pinctrl_driver);
294}
295arch_initcall(imx23_pinctrl_init);
296
297static void __exit imx23_pinctrl_exit(void)
298{
299 platform_driver_unregister(&imx23_pinctrl_driver);
300}
301module_exit(imx23_pinctrl_exit);
302
303MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
304MODULE_DESCRIPTION("Freescale i.MX23 pinctrl driver");
305MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-imx28.c b/drivers/pinctrl/pinctrl-imx28.c
new file mode 100644
index 00000000000..b973026811a
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx28.c
@@ -0,0 +1,421 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/of_device.h>
15#include <linux/pinctrl/pinctrl.h>
16#include "pinctrl-mxs.h"
17
18enum imx28_pin_enum {
19 GPMI_D00 = PINID(0, 0),
20 GPMI_D01 = PINID(0, 1),
21 GPMI_D02 = PINID(0, 2),
22 GPMI_D03 = PINID(0, 3),
23 GPMI_D04 = PINID(0, 4),
24 GPMI_D05 = PINID(0, 5),
25 GPMI_D06 = PINID(0, 6),
26 GPMI_D07 = PINID(0, 7),
27 GPMI_CE0N = PINID(0, 16),
28 GPMI_CE1N = PINID(0, 17),
29 GPMI_CE2N = PINID(0, 18),
30 GPMI_CE3N = PINID(0, 19),
31 GPMI_RDY0 = PINID(0, 20),
32 GPMI_RDY1 = PINID(0, 21),
33 GPMI_RDY2 = PINID(0, 22),
34 GPMI_RDY3 = PINID(0, 23),
35 GPMI_RDN = PINID(0, 24),
36 GPMI_WRN = PINID(0, 25),
37 GPMI_ALE = PINID(0, 26),
38 GPMI_CLE = PINID(0, 27),
39 GPMI_RESETN = PINID(0, 28),
40 LCD_D00 = PINID(1, 0),
41 LCD_D01 = PINID(1, 1),
42 LCD_D02 = PINID(1, 2),
43 LCD_D03 = PINID(1, 3),
44 LCD_D04 = PINID(1, 4),
45 LCD_D05 = PINID(1, 5),
46 LCD_D06 = PINID(1, 6),
47 LCD_D07 = PINID(1, 7),
48 LCD_D08 = PINID(1, 8),
49 LCD_D09 = PINID(1, 9),
50 LCD_D10 = PINID(1, 10),
51 LCD_D11 = PINID(1, 11),
52 LCD_D12 = PINID(1, 12),
53 LCD_D13 = PINID(1, 13),
54 LCD_D14 = PINID(1, 14),
55 LCD_D15 = PINID(1, 15),
56 LCD_D16 = PINID(1, 16),
57 LCD_D17 = PINID(1, 17),
58 LCD_D18 = PINID(1, 18),
59 LCD_D19 = PINID(1, 19),
60 LCD_D20 = PINID(1, 20),
61 LCD_D21 = PINID(1, 21),
62 LCD_D22 = PINID(1, 22),
63 LCD_D23 = PINID(1, 23),
64 LCD_RD_E = PINID(1, 24),
65 LCD_WR_RWN = PINID(1, 25),
66 LCD_RS = PINID(1, 26),
67 LCD_CS = PINID(1, 27),
68 LCD_VSYNC = PINID(1, 28),
69 LCD_HSYNC = PINID(1, 29),
70 LCD_DOTCLK = PINID(1, 30),
71 LCD_ENABLE = PINID(1, 31),
72 SSP0_DATA0 = PINID(2, 0),
73 SSP0_DATA1 = PINID(2, 1),
74 SSP0_DATA2 = PINID(2, 2),
75 SSP0_DATA3 = PINID(2, 3),
76 SSP0_DATA4 = PINID(2, 4),
77 SSP0_DATA5 = PINID(2, 5),
78 SSP0_DATA6 = PINID(2, 6),
79 SSP0_DATA7 = PINID(2, 7),
80 SSP0_CMD = PINID(2, 8),
81 SSP0_DETECT = PINID(2, 9),
82 SSP0_SCK = PINID(2, 10),
83 SSP1_SCK = PINID(2, 12),
84 SSP1_CMD = PINID(2, 13),
85 SSP1_DATA0 = PINID(2, 14),
86 SSP1_DATA3 = PINID(2, 15),
87 SSP2_SCK = PINID(2, 16),
88 SSP2_MOSI = PINID(2, 17),
89 SSP2_MISO = PINID(2, 18),
90 SSP2_SS0 = PINID(2, 19),
91 SSP2_SS1 = PINID(2, 20),
92 SSP2_SS2 = PINID(2, 21),
93 SSP3_SCK = PINID(2, 24),
94 SSP3_MOSI = PINID(2, 25),
95 SSP3_MISO = PINID(2, 26),
96 SSP3_SS0 = PINID(2, 27),
97 AUART0_RX = PINID(3, 0),
98 AUART0_TX = PINID(3, 1),
99 AUART0_CTS = PINID(3, 2),
100 AUART0_RTS = PINID(3, 3),
101 AUART1_RX = PINID(3, 4),
102 AUART1_TX = PINID(3, 5),
103 AUART1_CTS = PINID(3, 6),
104 AUART1_RTS = PINID(3, 7),
105 AUART2_RX = PINID(3, 8),
106 AUART2_TX = PINID(3, 9),
107 AUART2_CTS = PINID(3, 10),
108 AUART2_RTS = PINID(3, 11),
109 AUART3_RX = PINID(3, 12),
110 AUART3_TX = PINID(3, 13),
111 AUART3_CTS = PINID(3, 14),
112 AUART3_RTS = PINID(3, 15),
113 PWM0 = PINID(3, 16),
114 PWM1 = PINID(3, 17),
115 PWM2 = PINID(3, 18),
116 SAIF0_MCLK = PINID(3, 20),
117 SAIF0_LRCLK = PINID(3, 21),
118 SAIF0_BITCLK = PINID(3, 22),
119 SAIF0_SDATA0 = PINID(3, 23),
120 I2C0_SCL = PINID(3, 24),
121 I2C0_SDA = PINID(3, 25),
122 SAIF1_SDATA0 = PINID(3, 26),
123 SPDIF = PINID(3, 27),
124 PWM3 = PINID(3, 28),
125 PWM4 = PINID(3, 29),
126 LCD_RESET = PINID(3, 30),
127 ENET0_MDC = PINID(4, 0),
128 ENET0_MDIO = PINID(4, 1),
129 ENET0_RX_EN = PINID(4, 2),
130 ENET0_RXD0 = PINID(4, 3),
131 ENET0_RXD1 = PINID(4, 4),
132 ENET0_TX_CLK = PINID(4, 5),
133 ENET0_TX_EN = PINID(4, 6),
134 ENET0_TXD0 = PINID(4, 7),
135 ENET0_TXD1 = PINID(4, 8),
136 ENET0_RXD2 = PINID(4, 9),
137 ENET0_RXD3 = PINID(4, 10),
138 ENET0_TXD2 = PINID(4, 11),
139 ENET0_TXD3 = PINID(4, 12),
140 ENET0_RX_CLK = PINID(4, 13),
141 ENET0_COL = PINID(4, 14),
142 ENET0_CRS = PINID(4, 15),
143 ENET_CLK = PINID(4, 16),
144 JTAG_RTCK = PINID(4, 20),
145 EMI_D00 = PINID(5, 0),
146 EMI_D01 = PINID(5, 1),
147 EMI_D02 = PINID(5, 2),
148 EMI_D03 = PINID(5, 3),
149 EMI_D04 = PINID(5, 4),
150 EMI_D05 = PINID(5, 5),
151 EMI_D06 = PINID(5, 6),
152 EMI_D07 = PINID(5, 7),
153 EMI_D08 = PINID(5, 8),
154 EMI_D09 = PINID(5, 9),
155 EMI_D10 = PINID(5, 10),
156 EMI_D11 = PINID(5, 11),
157 EMI_D12 = PINID(5, 12),
158 EMI_D13 = PINID(5, 13),
159 EMI_D14 = PINID(5, 14),
160 EMI_D15 = PINID(5, 15),
161 EMI_ODT0 = PINID(5, 16),
162 EMI_DQM0 = PINID(5, 17),
163 EMI_ODT1 = PINID(5, 18),
164 EMI_DQM1 = PINID(5, 19),
165 EMI_DDR_OPEN_FB = PINID(5, 20),
166 EMI_CLK = PINID(5, 21),
167 EMI_DQS0 = PINID(5, 22),
168 EMI_DQS1 = PINID(5, 23),
169 EMI_DDR_OPEN = PINID(5, 26),
170 EMI_A00 = PINID(6, 0),
171 EMI_A01 = PINID(6, 1),
172 EMI_A02 = PINID(6, 2),
173 EMI_A03 = PINID(6, 3),
174 EMI_A04 = PINID(6, 4),
175 EMI_A05 = PINID(6, 5),
176 EMI_A06 = PINID(6, 6),
177 EMI_A07 = PINID(6, 7),
178 EMI_A08 = PINID(6, 8),
179 EMI_A09 = PINID(6, 9),
180 EMI_A10 = PINID(6, 10),
181 EMI_A11 = PINID(6, 11),
182 EMI_A12 = PINID(6, 12),
183 EMI_A13 = PINID(6, 13),
184 EMI_A14 = PINID(6, 14),
185 EMI_BA0 = PINID(6, 16),
186 EMI_BA1 = PINID(6, 17),
187 EMI_BA2 = PINID(6, 18),
188 EMI_CASN = PINID(6, 19),
189 EMI_RASN = PINID(6, 20),
190 EMI_WEN = PINID(6, 21),
191 EMI_CE0N = PINID(6, 22),
192 EMI_CE1N = PINID(6, 23),
193 EMI_CKE = PINID(6, 24),
194};
195
196static const struct pinctrl_pin_desc imx28_pins[] = {
197 MXS_PINCTRL_PIN(GPMI_D00),
198 MXS_PINCTRL_PIN(GPMI_D01),
199 MXS_PINCTRL_PIN(GPMI_D02),
200 MXS_PINCTRL_PIN(GPMI_D03),
201 MXS_PINCTRL_PIN(GPMI_D04),
202 MXS_PINCTRL_PIN(GPMI_D05),
203 MXS_PINCTRL_PIN(GPMI_D06),
204 MXS_PINCTRL_PIN(GPMI_D07),
205 MXS_PINCTRL_PIN(GPMI_CE0N),
206 MXS_PINCTRL_PIN(GPMI_CE1N),
207 MXS_PINCTRL_PIN(GPMI_CE2N),
208 MXS_PINCTRL_PIN(GPMI_CE3N),
209 MXS_PINCTRL_PIN(GPMI_RDY0),
210 MXS_PINCTRL_PIN(GPMI_RDY1),
211 MXS_PINCTRL_PIN(GPMI_RDY2),
212 MXS_PINCTRL_PIN(GPMI_RDY3),
213 MXS_PINCTRL_PIN(GPMI_RDN),
214 MXS_PINCTRL_PIN(GPMI_WRN),
215 MXS_PINCTRL_PIN(GPMI_ALE),
216 MXS_PINCTRL_PIN(GPMI_CLE),
217 MXS_PINCTRL_PIN(GPMI_RESETN),
218 MXS_PINCTRL_PIN(LCD_D00),
219 MXS_PINCTRL_PIN(LCD_D01),
220 MXS_PINCTRL_PIN(LCD_D02),
221 MXS_PINCTRL_PIN(LCD_D03),
222 MXS_PINCTRL_PIN(LCD_D04),
223 MXS_PINCTRL_PIN(LCD_D05),
224 MXS_PINCTRL_PIN(LCD_D06),
225 MXS_PINCTRL_PIN(LCD_D07),
226 MXS_PINCTRL_PIN(LCD_D08),
227 MXS_PINCTRL_PIN(LCD_D09),
228 MXS_PINCTRL_PIN(LCD_D10),
229 MXS_PINCTRL_PIN(LCD_D11),
230 MXS_PINCTRL_PIN(LCD_D12),
231 MXS_PINCTRL_PIN(LCD_D13),
232 MXS_PINCTRL_PIN(LCD_D14),
233 MXS_PINCTRL_PIN(LCD_D15),
234 MXS_PINCTRL_PIN(LCD_D16),
235 MXS_PINCTRL_PIN(LCD_D17),
236 MXS_PINCTRL_PIN(LCD_D18),
237 MXS_PINCTRL_PIN(LCD_D19),
238 MXS_PINCTRL_PIN(LCD_D20),
239 MXS_PINCTRL_PIN(LCD_D21),
240 MXS_PINCTRL_PIN(LCD_D22),
241 MXS_PINCTRL_PIN(LCD_D23),
242 MXS_PINCTRL_PIN(LCD_RD_E),
243 MXS_PINCTRL_PIN(LCD_WR_RWN),
244 MXS_PINCTRL_PIN(LCD_RS),
245 MXS_PINCTRL_PIN(LCD_CS),
246 MXS_PINCTRL_PIN(LCD_VSYNC),
247 MXS_PINCTRL_PIN(LCD_HSYNC),
248 MXS_PINCTRL_PIN(LCD_DOTCLK),
249 MXS_PINCTRL_PIN(LCD_ENABLE),
250 MXS_PINCTRL_PIN(SSP0_DATA0),
251 MXS_PINCTRL_PIN(SSP0_DATA1),
252 MXS_PINCTRL_PIN(SSP0_DATA2),
253 MXS_PINCTRL_PIN(SSP0_DATA3),
254 MXS_PINCTRL_PIN(SSP0_DATA4),
255 MXS_PINCTRL_PIN(SSP0_DATA5),
256 MXS_PINCTRL_PIN(SSP0_DATA6),
257 MXS_PINCTRL_PIN(SSP0_DATA7),
258 MXS_PINCTRL_PIN(SSP0_CMD),
259 MXS_PINCTRL_PIN(SSP0_DETECT),
260 MXS_PINCTRL_PIN(SSP0_SCK),
261 MXS_PINCTRL_PIN(SSP1_SCK),
262 MXS_PINCTRL_PIN(SSP1_CMD),
263 MXS_PINCTRL_PIN(SSP1_DATA0),
264 MXS_PINCTRL_PIN(SSP1_DATA3),
265 MXS_PINCTRL_PIN(SSP2_SCK),
266 MXS_PINCTRL_PIN(SSP2_MOSI),
267 MXS_PINCTRL_PIN(SSP2_MISO),
268 MXS_PINCTRL_PIN(SSP2_SS0),
269 MXS_PINCTRL_PIN(SSP2_SS1),
270 MXS_PINCTRL_PIN(SSP2_SS2),
271 MXS_PINCTRL_PIN(SSP3_SCK),
272 MXS_PINCTRL_PIN(SSP3_MOSI),
273 MXS_PINCTRL_PIN(SSP3_MISO),
274 MXS_PINCTRL_PIN(SSP3_SS0),
275 MXS_PINCTRL_PIN(AUART0_RX),
276 MXS_PINCTRL_PIN(AUART0_TX),
277 MXS_PINCTRL_PIN(AUART0_CTS),
278 MXS_PINCTRL_PIN(AUART0_RTS),
279 MXS_PINCTRL_PIN(AUART1_RX),
280 MXS_PINCTRL_PIN(AUART1_TX),
281 MXS_PINCTRL_PIN(AUART1_CTS),
282 MXS_PINCTRL_PIN(AUART1_RTS),
283 MXS_PINCTRL_PIN(AUART2_RX),
284 MXS_PINCTRL_PIN(AUART2_TX),
285 MXS_PINCTRL_PIN(AUART2_CTS),
286 MXS_PINCTRL_PIN(AUART2_RTS),
287 MXS_PINCTRL_PIN(AUART3_RX),
288 MXS_PINCTRL_PIN(AUART3_TX),
289 MXS_PINCTRL_PIN(AUART3_CTS),
290 MXS_PINCTRL_PIN(AUART3_RTS),
291 MXS_PINCTRL_PIN(PWM0),
292 MXS_PINCTRL_PIN(PWM1),
293 MXS_PINCTRL_PIN(PWM2),
294 MXS_PINCTRL_PIN(SAIF0_MCLK),
295 MXS_PINCTRL_PIN(SAIF0_LRCLK),
296 MXS_PINCTRL_PIN(SAIF0_BITCLK),
297 MXS_PINCTRL_PIN(SAIF0_SDATA0),
298 MXS_PINCTRL_PIN(I2C0_SCL),
299 MXS_PINCTRL_PIN(I2C0_SDA),
300 MXS_PINCTRL_PIN(SAIF1_SDATA0),
301 MXS_PINCTRL_PIN(SPDIF),
302 MXS_PINCTRL_PIN(PWM3),
303 MXS_PINCTRL_PIN(PWM4),
304 MXS_PINCTRL_PIN(LCD_RESET),
305 MXS_PINCTRL_PIN(ENET0_MDC),
306 MXS_PINCTRL_PIN(ENET0_MDIO),
307 MXS_PINCTRL_PIN(ENET0_RX_EN),
308 MXS_PINCTRL_PIN(ENET0_RXD0),
309 MXS_PINCTRL_PIN(ENET0_RXD1),
310 MXS_PINCTRL_PIN(ENET0_TX_CLK),
311 MXS_PINCTRL_PIN(ENET0_TX_EN),
312 MXS_PINCTRL_PIN(ENET0_TXD0),
313 MXS_PINCTRL_PIN(ENET0_TXD1),
314 MXS_PINCTRL_PIN(ENET0_RXD2),
315 MXS_PINCTRL_PIN(ENET0_RXD3),
316 MXS_PINCTRL_PIN(ENET0_TXD2),
317 MXS_PINCTRL_PIN(ENET0_TXD3),
318 MXS_PINCTRL_PIN(ENET0_RX_CLK),
319 MXS_PINCTRL_PIN(ENET0_COL),
320 MXS_PINCTRL_PIN(ENET0_CRS),
321 MXS_PINCTRL_PIN(ENET_CLK),
322 MXS_PINCTRL_PIN(JTAG_RTCK),
323 MXS_PINCTRL_PIN(EMI_D00),
324 MXS_PINCTRL_PIN(EMI_D01),
325 MXS_PINCTRL_PIN(EMI_D02),
326 MXS_PINCTRL_PIN(EMI_D03),
327 MXS_PINCTRL_PIN(EMI_D04),
328 MXS_PINCTRL_PIN(EMI_D05),
329 MXS_PINCTRL_PIN(EMI_D06),
330 MXS_PINCTRL_PIN(EMI_D07),
331 MXS_PINCTRL_PIN(EMI_D08),
332 MXS_PINCTRL_PIN(EMI_D09),
333 MXS_PINCTRL_PIN(EMI_D10),
334 MXS_PINCTRL_PIN(EMI_D11),
335 MXS_PINCTRL_PIN(EMI_D12),
336 MXS_PINCTRL_PIN(EMI_D13),
337 MXS_PINCTRL_PIN(EMI_D14),
338 MXS_PINCTRL_PIN(EMI_D15),
339 MXS_PINCTRL_PIN(EMI_ODT0),
340 MXS_PINCTRL_PIN(EMI_DQM0),
341 MXS_PINCTRL_PIN(EMI_ODT1),
342 MXS_PINCTRL_PIN(EMI_DQM1),
343 MXS_PINCTRL_PIN(EMI_DDR_OPEN_FB),
344 MXS_PINCTRL_PIN(EMI_CLK),
345 MXS_PINCTRL_PIN(EMI_DQS0),
346 MXS_PINCTRL_PIN(EMI_DQS1),
347 MXS_PINCTRL_PIN(EMI_DDR_OPEN),
348 MXS_PINCTRL_PIN(EMI_A00),
349 MXS_PINCTRL_PIN(EMI_A01),
350 MXS_PINCTRL_PIN(EMI_A02),
351 MXS_PINCTRL_PIN(EMI_A03),
352 MXS_PINCTRL_PIN(EMI_A04),
353 MXS_PINCTRL_PIN(EMI_A05),
354 MXS_PINCTRL_PIN(EMI_A06),
355 MXS_PINCTRL_PIN(EMI_A07),
356 MXS_PINCTRL_PIN(EMI_A08),
357 MXS_PINCTRL_PIN(EMI_A09),
358 MXS_PINCTRL_PIN(EMI_A10),
359 MXS_PINCTRL_PIN(EMI_A11),
360 MXS_PINCTRL_PIN(EMI_A12),
361 MXS_PINCTRL_PIN(EMI_A13),
362 MXS_PINCTRL_PIN(EMI_A14),
363 MXS_PINCTRL_PIN(EMI_BA0),
364 MXS_PINCTRL_PIN(EMI_BA1),
365 MXS_PINCTRL_PIN(EMI_BA2),
366 MXS_PINCTRL_PIN(EMI_CASN),
367 MXS_PINCTRL_PIN(EMI_RASN),
368 MXS_PINCTRL_PIN(EMI_WEN),
369 MXS_PINCTRL_PIN(EMI_CE0N),
370 MXS_PINCTRL_PIN(EMI_CE1N),
371 MXS_PINCTRL_PIN(EMI_CKE),
372};
373
374static struct mxs_regs imx28_regs = {
375 .muxsel = 0x100,
376 .drive = 0x300,
377 .pull = 0x600,
378};
379
380static struct mxs_pinctrl_soc_data imx28_pinctrl_data = {
381 .regs = &imx28_regs,
382 .pins = imx28_pins,
383 .npins = ARRAY_SIZE(imx28_pins),
384};
385
386static int __devinit imx28_pinctrl_probe(struct platform_device *pdev)
387{
388 return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data);
389}
390
391static struct of_device_id imx28_pinctrl_of_match[] __devinitdata = {
392 { .compatible = "fsl,imx28-pinctrl", },
393 { /* sentinel */ }
394};
395MODULE_DEVICE_TABLE(of, imx28_pinctrl_of_match);
396
397static struct platform_driver imx28_pinctrl_driver = {
398 .driver = {
399 .name = "imx28-pinctrl",
400 .owner = THIS_MODULE,
401 .of_match_table = imx28_pinctrl_of_match,
402 },
403 .probe = imx28_pinctrl_probe,
404 .remove = __devexit_p(mxs_pinctrl_remove),
405};
406
407static int __init imx28_pinctrl_init(void)
408{
409 return platform_driver_register(&imx28_pinctrl_driver);
410}
411arch_initcall(imx28_pinctrl_init);
412
413static void __exit imx28_pinctrl_exit(void)
414{
415 platform_driver_unregister(&imx28_pinctrl_driver);
416}
417module_exit(imx28_pinctrl_exit);
418
419MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
420MODULE_DESCRIPTION("Freescale i.MX28 pinctrl driver");
421MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-imx6q.c b/drivers/pinctrl/pinctrl-imx6q.c
new file mode 100644
index 00000000000..7737d4d71a3
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx6q.c
@@ -0,0 +1,2331 @@
1/*
2 * imx6q pinctrl driver based on imx pinmux core
3 *
4 * Copyright (C) 2012 Freescale Semiconductor, Inc.
5 * Copyright (C) 2012 Linaro, Inc.
6 *
7 * Author: Dong Aisheng <dong.aisheng@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/pinctrl/pinctrl.h>
22
23#include "pinctrl-imx.h"
24
25enum imx6q_pads {
26 MX6Q_PAD_SD2_DAT1 = 0,
27 MX6Q_PAD_SD2_DAT2 = 1,
28 MX6Q_PAD_SD2_DAT0 = 2,
29 MX6Q_PAD_RGMII_TXC = 3,
30 MX6Q_PAD_RGMII_TD0 = 4,
31 MX6Q_PAD_RGMII_TD1 = 5,
32 MX6Q_PAD_RGMII_TD2 = 6,
33 MX6Q_PAD_RGMII_TD3 = 7,
34 MX6Q_PAD_RGMII_RX_CTL = 8,
35 MX6Q_PAD_RGMII_RD0 = 9,
36 MX6Q_PAD_RGMII_TX_CTL = 10,
37 MX6Q_PAD_RGMII_RD1 = 11,
38 MX6Q_PAD_RGMII_RD2 = 12,
39 MX6Q_PAD_RGMII_RD3 = 13,
40 MX6Q_PAD_RGMII_RXC = 14,
41 MX6Q_PAD_EIM_A25 = 15,
42 MX6Q_PAD_EIM_EB2 = 16,
43 MX6Q_PAD_EIM_D16 = 17,
44 MX6Q_PAD_EIM_D17 = 18,
45 MX6Q_PAD_EIM_D18 = 19,
46 MX6Q_PAD_EIM_D19 = 20,
47 MX6Q_PAD_EIM_D20 = 21,
48 MX6Q_PAD_EIM_D21 = 22,
49 MX6Q_PAD_EIM_D22 = 23,
50 MX6Q_PAD_EIM_D23 = 24,
51 MX6Q_PAD_EIM_EB3 = 25,
52 MX6Q_PAD_EIM_D24 = 26,
53 MX6Q_PAD_EIM_D25 = 27,
54 MX6Q_PAD_EIM_D26 = 28,
55 MX6Q_PAD_EIM_D27 = 29,
56 MX6Q_PAD_EIM_D28 = 30,
57 MX6Q_PAD_EIM_D29 = 31,
58 MX6Q_PAD_EIM_D30 = 32,
59 MX6Q_PAD_EIM_D31 = 33,
60 MX6Q_PAD_EIM_A24 = 34,
61 MX6Q_PAD_EIM_A23 = 35,
62 MX6Q_PAD_EIM_A22 = 36,
63 MX6Q_PAD_EIM_A21 = 37,
64 MX6Q_PAD_EIM_A20 = 38,
65 MX6Q_PAD_EIM_A19 = 39,
66 MX6Q_PAD_EIM_A18 = 40,
67 MX6Q_PAD_EIM_A17 = 41,
68 MX6Q_PAD_EIM_A16 = 42,
69 MX6Q_PAD_EIM_CS0 = 43,
70 MX6Q_PAD_EIM_CS1 = 44,
71 MX6Q_PAD_EIM_OE = 45,
72 MX6Q_PAD_EIM_RW = 46,
73 MX6Q_PAD_EIM_LBA = 47,
74 MX6Q_PAD_EIM_EB0 = 48,
75 MX6Q_PAD_EIM_EB1 = 49,
76 MX6Q_PAD_EIM_DA0 = 50,
77 MX6Q_PAD_EIM_DA1 = 51,
78 MX6Q_PAD_EIM_DA2 = 52,
79 MX6Q_PAD_EIM_DA3 = 53,
80 MX6Q_PAD_EIM_DA4 = 54,
81 MX6Q_PAD_EIM_DA5 = 55,
82 MX6Q_PAD_EIM_DA6 = 56,
83 MX6Q_PAD_EIM_DA7 = 57,
84 MX6Q_PAD_EIM_DA8 = 58,
85 MX6Q_PAD_EIM_DA9 = 59,
86 MX6Q_PAD_EIM_DA10 = 60,
87 MX6Q_PAD_EIM_DA11 = 61,
88 MX6Q_PAD_EIM_DA12 = 62,
89 MX6Q_PAD_EIM_DA13 = 63,
90 MX6Q_PAD_EIM_DA14 = 64,
91 MX6Q_PAD_EIM_DA15 = 65,
92 MX6Q_PAD_EIM_WAIT = 66,
93 MX6Q_PAD_EIM_BCLK = 67,
94 MX6Q_PAD_DI0_DISP_CLK = 68,
95 MX6Q_PAD_DI0_PIN15 = 69,
96 MX6Q_PAD_DI0_PIN2 = 70,
97 MX6Q_PAD_DI0_PIN3 = 71,
98 MX6Q_PAD_DI0_PIN4 = 72,
99 MX6Q_PAD_DISP0_DAT0 = 73,
100 MX6Q_PAD_DISP0_DAT1 = 74,
101 MX6Q_PAD_DISP0_DAT2 = 75,
102 MX6Q_PAD_DISP0_DAT3 = 76,
103 MX6Q_PAD_DISP0_DAT4 = 77,
104 MX6Q_PAD_DISP0_DAT5 = 78,
105 MX6Q_PAD_DISP0_DAT6 = 79,
106 MX6Q_PAD_DISP0_DAT7 = 80,
107 MX6Q_PAD_DISP0_DAT8 = 81,
108 MX6Q_PAD_DISP0_DAT9 = 82,
109 MX6Q_PAD_DISP0_DAT10 = 83,
110 MX6Q_PAD_DISP0_DAT11 = 84,
111 MX6Q_PAD_DISP0_DAT12 = 85,
112 MX6Q_PAD_DISP0_DAT13 = 86,
113 MX6Q_PAD_DISP0_DAT14 = 87,
114 MX6Q_PAD_DISP0_DAT15 = 88,
115 MX6Q_PAD_DISP0_DAT16 = 89,
116 MX6Q_PAD_DISP0_DAT17 = 90,
117 MX6Q_PAD_DISP0_DAT18 = 91,
118 MX6Q_PAD_DISP0_DAT19 = 92,
119 MX6Q_PAD_DISP0_DAT20 = 93,
120 MX6Q_PAD_DISP0_DAT21 = 94,
121 MX6Q_PAD_DISP0_DAT22 = 95,
122 MX6Q_PAD_DISP0_DAT23 = 96,
123 MX6Q_PAD_ENET_MDIO = 97,
124 MX6Q_PAD_ENET_REF_CLK = 98,
125 MX6Q_PAD_ENET_RX_ER = 99,
126 MX6Q_PAD_ENET_CRS_DV = 100,
127 MX6Q_PAD_ENET_RXD1 = 101,
128 MX6Q_PAD_ENET_RXD0 = 102,
129 MX6Q_PAD_ENET_TX_EN = 103,
130 MX6Q_PAD_ENET_TXD1 = 104,
131 MX6Q_PAD_ENET_TXD0 = 105,
132 MX6Q_PAD_ENET_MDC = 106,
133 MX6Q_PAD_DRAM_D40 = 107,
134 MX6Q_PAD_DRAM_D41 = 108,
135 MX6Q_PAD_DRAM_D42 = 109,
136 MX6Q_PAD_DRAM_D43 = 110,
137 MX6Q_PAD_DRAM_D44 = 111,
138 MX6Q_PAD_DRAM_D45 = 112,
139 MX6Q_PAD_DRAM_D46 = 113,
140 MX6Q_PAD_DRAM_D47 = 114,
141 MX6Q_PAD_DRAM_SDQS5 = 115,
142 MX6Q_PAD_DRAM_DQM5 = 116,
143 MX6Q_PAD_DRAM_D32 = 117,
144 MX6Q_PAD_DRAM_D33 = 118,
145 MX6Q_PAD_DRAM_D34 = 119,
146 MX6Q_PAD_DRAM_D35 = 120,
147 MX6Q_PAD_DRAM_D36 = 121,
148 MX6Q_PAD_DRAM_D37 = 122,
149 MX6Q_PAD_DRAM_D38 = 123,
150 MX6Q_PAD_DRAM_D39 = 124,
151 MX6Q_PAD_DRAM_DQM4 = 125,
152 MX6Q_PAD_DRAM_SDQS4 = 126,
153 MX6Q_PAD_DRAM_D24 = 127,
154 MX6Q_PAD_DRAM_D25 = 128,
155 MX6Q_PAD_DRAM_D26 = 129,
156 MX6Q_PAD_DRAM_D27 = 130,
157 MX6Q_PAD_DRAM_D28 = 131,
158 MX6Q_PAD_DRAM_D29 = 132,
159 MX6Q_PAD_DRAM_SDQS3 = 133,
160 MX6Q_PAD_DRAM_D30 = 134,
161 MX6Q_PAD_DRAM_D31 = 135,
162 MX6Q_PAD_DRAM_DQM3 = 136,
163 MX6Q_PAD_DRAM_D16 = 137,
164 MX6Q_PAD_DRAM_D17 = 138,
165 MX6Q_PAD_DRAM_D18 = 139,
166 MX6Q_PAD_DRAM_D19 = 140,
167 MX6Q_PAD_DRAM_D20 = 141,
168 MX6Q_PAD_DRAM_D21 = 142,
169 MX6Q_PAD_DRAM_D22 = 143,
170 MX6Q_PAD_DRAM_SDQS2 = 144,
171 MX6Q_PAD_DRAM_D23 = 145,
172 MX6Q_PAD_DRAM_DQM2 = 146,
173 MX6Q_PAD_DRAM_A0 = 147,
174 MX6Q_PAD_DRAM_A1 = 148,
175 MX6Q_PAD_DRAM_A2 = 149,
176 MX6Q_PAD_DRAM_A3 = 150,
177 MX6Q_PAD_DRAM_A4 = 151,
178 MX6Q_PAD_DRAM_A5 = 152,
179 MX6Q_PAD_DRAM_A6 = 153,
180 MX6Q_PAD_DRAM_A7 = 154,
181 MX6Q_PAD_DRAM_A8 = 155,
182 MX6Q_PAD_DRAM_A9 = 156,
183 MX6Q_PAD_DRAM_A10 = 157,
184 MX6Q_PAD_DRAM_A11 = 158,
185 MX6Q_PAD_DRAM_A12 = 159,
186 MX6Q_PAD_DRAM_A13 = 160,
187 MX6Q_PAD_DRAM_A14 = 161,
188 MX6Q_PAD_DRAM_A15 = 162,
189 MX6Q_PAD_DRAM_CAS = 163,
190 MX6Q_PAD_DRAM_CS0 = 164,
191 MX6Q_PAD_DRAM_CS1 = 165,
192 MX6Q_PAD_DRAM_RAS = 166,
193 MX6Q_PAD_DRAM_RESET = 167,
194 MX6Q_PAD_DRAM_SDBA0 = 168,
195 MX6Q_PAD_DRAM_SDBA1 = 169,
196 MX6Q_PAD_DRAM_SDCLK_0 = 170,
197 MX6Q_PAD_DRAM_SDBA2 = 171,
198 MX6Q_PAD_DRAM_SDCKE0 = 172,
199 MX6Q_PAD_DRAM_SDCLK_1 = 173,
200 MX6Q_PAD_DRAM_SDCKE1 = 174,
201 MX6Q_PAD_DRAM_SDODT0 = 175,
202 MX6Q_PAD_DRAM_SDODT1 = 176,
203 MX6Q_PAD_DRAM_SDWE = 177,
204 MX6Q_PAD_DRAM_D0 = 178,
205 MX6Q_PAD_DRAM_D1 = 179,
206 MX6Q_PAD_DRAM_D2 = 180,
207 MX6Q_PAD_DRAM_D3 = 181,
208 MX6Q_PAD_DRAM_D4 = 182,
209 MX6Q_PAD_DRAM_D5 = 183,
210 MX6Q_PAD_DRAM_SDQS0 = 184,
211 MX6Q_PAD_DRAM_D6 = 185,
212 MX6Q_PAD_DRAM_D7 = 186,
213 MX6Q_PAD_DRAM_DQM0 = 187,
214 MX6Q_PAD_DRAM_D8 = 188,
215 MX6Q_PAD_DRAM_D9 = 189,
216 MX6Q_PAD_DRAM_D10 = 190,
217 MX6Q_PAD_DRAM_D11 = 191,
218 MX6Q_PAD_DRAM_D12 = 192,
219 MX6Q_PAD_DRAM_D13 = 193,
220 MX6Q_PAD_DRAM_D14 = 194,
221 MX6Q_PAD_DRAM_SDQS1 = 195,
222 MX6Q_PAD_DRAM_D15 = 196,
223 MX6Q_PAD_DRAM_DQM1 = 197,
224 MX6Q_PAD_DRAM_D48 = 198,
225 MX6Q_PAD_DRAM_D49 = 199,
226 MX6Q_PAD_DRAM_D50 = 200,
227 MX6Q_PAD_DRAM_D51 = 201,
228 MX6Q_PAD_DRAM_D52 = 202,
229 MX6Q_PAD_DRAM_D53 = 203,
230 MX6Q_PAD_DRAM_D54 = 204,
231 MX6Q_PAD_DRAM_D55 = 205,
232 MX6Q_PAD_DRAM_SDQS6 = 206,
233 MX6Q_PAD_DRAM_DQM6 = 207,
234 MX6Q_PAD_DRAM_D56 = 208,
235 MX6Q_PAD_DRAM_SDQS7 = 209,
236 MX6Q_PAD_DRAM_D57 = 210,
237 MX6Q_PAD_DRAM_D58 = 211,
238 MX6Q_PAD_DRAM_D59 = 212,
239 MX6Q_PAD_DRAM_D60 = 213,
240 MX6Q_PAD_DRAM_DQM7 = 214,
241 MX6Q_PAD_DRAM_D61 = 215,
242 MX6Q_PAD_DRAM_D62 = 216,
243 MX6Q_PAD_DRAM_D63 = 217,
244 MX6Q_PAD_KEY_COL0 = 218,
245 MX6Q_PAD_KEY_ROW0 = 219,
246 MX6Q_PAD_KEY_COL1 = 220,
247 MX6Q_PAD_KEY_ROW1 = 221,
248 MX6Q_PAD_KEY_COL2 = 222,
249 MX6Q_PAD_KEY_ROW2 = 223,
250 MX6Q_PAD_KEY_COL3 = 224,
251 MX6Q_PAD_KEY_ROW3 = 225,
252 MX6Q_PAD_KEY_COL4 = 226,
253 MX6Q_PAD_KEY_ROW4 = 227,
254 MX6Q_PAD_GPIO_0 = 228,
255 MX6Q_PAD_GPIO_1 = 229,
256 MX6Q_PAD_GPIO_9 = 230,
257 MX6Q_PAD_GPIO_3 = 231,
258 MX6Q_PAD_GPIO_6 = 232,
259 MX6Q_PAD_GPIO_2 = 233,
260 MX6Q_PAD_GPIO_4 = 234,
261 MX6Q_PAD_GPIO_5 = 235,
262 MX6Q_PAD_GPIO_7 = 236,
263 MX6Q_PAD_GPIO_8 = 237,
264 MX6Q_PAD_GPIO_16 = 238,
265 MX6Q_PAD_GPIO_17 = 239,
266 MX6Q_PAD_GPIO_18 = 240,
267 MX6Q_PAD_GPIO_19 = 241,
268 MX6Q_PAD_CSI0_PIXCLK = 242,
269 MX6Q_PAD_CSI0_MCLK = 243,
270 MX6Q_PAD_CSI0_DATA_EN = 244,
271 MX6Q_PAD_CSI0_VSYNC = 245,
272 MX6Q_PAD_CSI0_DAT4 = 246,
273 MX6Q_PAD_CSI0_DAT5 = 247,
274 MX6Q_PAD_CSI0_DAT6 = 248,
275 MX6Q_PAD_CSI0_DAT7 = 249,
276 MX6Q_PAD_CSI0_DAT8 = 250,
277 MX6Q_PAD_CSI0_DAT9 = 251,
278 MX6Q_PAD_CSI0_DAT10 = 252,
279 MX6Q_PAD_CSI0_DAT11 = 253,
280 MX6Q_PAD_CSI0_DAT12 = 254,
281 MX6Q_PAD_CSI0_DAT13 = 255,
282 MX6Q_PAD_CSI0_DAT14 = 256,
283 MX6Q_PAD_CSI0_DAT15 = 257,
284 MX6Q_PAD_CSI0_DAT16 = 258,
285 MX6Q_PAD_CSI0_DAT17 = 259,
286 MX6Q_PAD_CSI0_DAT18 = 260,
287 MX6Q_PAD_CSI0_DAT19 = 261,
288 MX6Q_PAD_JTAG_TMS = 262,
289 MX6Q_PAD_JTAG_MOD = 263,
290 MX6Q_PAD_JTAG_TRSTB = 264,
291 MX6Q_PAD_JTAG_TDI = 265,
292 MX6Q_PAD_JTAG_TCK = 266,
293 MX6Q_PAD_JTAG_TDO = 267,
294 MX6Q_PAD_LVDS1_TX3_P = 268,
295 MX6Q_PAD_LVDS1_TX2_P = 269,
296 MX6Q_PAD_LVDS1_CLK_P = 270,
297 MX6Q_PAD_LVDS1_TX1_P = 271,
298 MX6Q_PAD_LVDS1_TX0_P = 272,
299 MX6Q_PAD_LVDS0_TX3_P = 273,
300 MX6Q_PAD_LVDS0_CLK_P = 274,
301 MX6Q_PAD_LVDS0_TX2_P = 275,
302 MX6Q_PAD_LVDS0_TX1_P = 276,
303 MX6Q_PAD_LVDS0_TX0_P = 277,
304 MX6Q_PAD_TAMPER = 278,
305 MX6Q_PAD_PMIC_ON_REQ = 279,
306 MX6Q_PAD_PMIC_STBY_REQ = 280,
307 MX6Q_PAD_POR_B = 281,
308 MX6Q_PAD_BOOT_MODE1 = 282,
309 MX6Q_PAD_RESET_IN_B = 283,
310 MX6Q_PAD_BOOT_MODE0 = 284,
311 MX6Q_PAD_TEST_MODE = 285,
312 MX6Q_PAD_SD3_DAT7 = 286,
313 MX6Q_PAD_SD3_DAT6 = 287,
314 MX6Q_PAD_SD3_DAT5 = 288,
315 MX6Q_PAD_SD3_DAT4 = 289,
316 MX6Q_PAD_SD3_CMD = 290,
317 MX6Q_PAD_SD3_CLK = 291,
318 MX6Q_PAD_SD3_DAT0 = 292,
319 MX6Q_PAD_SD3_DAT1 = 293,
320 MX6Q_PAD_SD3_DAT2 = 294,
321 MX6Q_PAD_SD3_DAT3 = 295,
322 MX6Q_PAD_SD3_RST = 296,
323 MX6Q_PAD_NANDF_CLE = 297,
324 MX6Q_PAD_NANDF_ALE = 298,
325 MX6Q_PAD_NANDF_WP_B = 299,
326 MX6Q_PAD_NANDF_RB0 = 300,
327 MX6Q_PAD_NANDF_CS0 = 301,
328 MX6Q_PAD_NANDF_CS1 = 302,
329 MX6Q_PAD_NANDF_CS2 = 303,
330 MX6Q_PAD_NANDF_CS3 = 304,
331 MX6Q_PAD_SD4_CMD = 305,
332 MX6Q_PAD_SD4_CLK = 306,
333 MX6Q_PAD_NANDF_D0 = 307,
334 MX6Q_PAD_NANDF_D1 = 308,
335 MX6Q_PAD_NANDF_D2 = 309,
336 MX6Q_PAD_NANDF_D3 = 310,
337 MX6Q_PAD_NANDF_D4 = 311,
338 MX6Q_PAD_NANDF_D5 = 312,
339 MX6Q_PAD_NANDF_D6 = 313,
340 MX6Q_PAD_NANDF_D7 = 314,
341 MX6Q_PAD_SD4_DAT0 = 315,
342 MX6Q_PAD_SD4_DAT1 = 316,
343 MX6Q_PAD_SD4_DAT2 = 317,
344 MX6Q_PAD_SD4_DAT3 = 318,
345 MX6Q_PAD_SD4_DAT4 = 319,
346 MX6Q_PAD_SD4_DAT5 = 320,
347 MX6Q_PAD_SD4_DAT6 = 321,
348 MX6Q_PAD_SD4_DAT7 = 322,
349 MX6Q_PAD_SD1_DAT1 = 323,
350 MX6Q_PAD_SD1_DAT0 = 324,
351 MX6Q_PAD_SD1_DAT3 = 325,
352 MX6Q_PAD_SD1_CMD = 326,
353 MX6Q_PAD_SD1_DAT2 = 327,
354 MX6Q_PAD_SD1_CLK = 328,
355 MX6Q_PAD_SD2_CLK = 329,
356 MX6Q_PAD_SD2_CMD = 330,
357 MX6Q_PAD_SD2_DAT3 = 331,
358};
359
360/* imx6q register maps */
361static struct imx_pin_reg imx6q_pin_regs[] = {
362 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
363 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 1, 0x0834, 0), /* MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 */
364 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__WEIM_WEIM_CS_2 */
365 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 3, 0x07C8, 0), /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
366 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 4, 0x08F0, 0), /* MX6Q_PAD_SD2_DAT1__KPP_COL_7 */
367 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__GPIO_1_14 */
368 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__CCM_WAIT */
369 IMX_PIN_REG(MX6Q_PAD_SD2_DAT1, 0x0360, 0x004C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT1__ANATOP_TESTO_0 */
370 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
371 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 1, 0x0838, 0), /* MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 */
372 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 2, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__WEIM_WEIM_CS_3 */
373 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 3, 0x07B8, 0), /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
374 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 4, 0x08F8, 0), /* MX6Q_PAD_SD2_DAT2__KPP_ROW_6 */
375 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__GPIO_1_13 */
376 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__CCM_STOP */
377 IMX_PIN_REG(MX6Q_PAD_SD2_DAT2, 0x0364, 0x0050, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT2__ANATOP_TESTO_1 */
378 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
379 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 1, 0x082C, 0), /* MX6Q_PAD_SD2_DAT0__ECSPI5_MISO */
380 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 3, 0x07B4, 0), /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
381 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 4, 0x08FC, 0), /* MX6Q_PAD_SD2_DAT0__KPP_ROW_7 */
382 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__GPIO_1_15 */
383 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__DCIC2_DCIC_OUT */
384 IMX_PIN_REG(MX6Q_PAD_SD2_DAT0, 0x0368, 0x0054, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT0__TESTO_2 */
385 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA */
386 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
387 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 2, 0x0918, 0), /* MX6Q_PAD_RGMII_TXC__SPDIF_SPDIF_EXTCLK */
388 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__GPIO_6_19 */
389 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__MIPI_CORE_DPHY_IN_0 */
390 IMX_PIN_REG(MX6Q_PAD_RGMII_TXC, 0x036C, 0x0058, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TXC__ANATOP_24M_OUT */
391 IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_HSI_CRL_TX_RDY */
392 IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
393 IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__GPIO_6_20 */
394 IMX_PIN_REG(MX6Q_PAD_RGMII_TD0, 0x0370, 0x005C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD0__MIPI_CORE_DPHY_IN_1 */
395 IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_HSI_CRL_RX_FLG */
396 IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
397 IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__GPIO_6_21 */
398 IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__MIPI_CORE_DPHY_IN_2 */
399 IMX_PIN_REG(MX6Q_PAD_RGMII_TD1, 0x0374, 0x0060, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD1__CCM_PLL3_BYP */
400 IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_HSI_CRL_RX_DTA */
401 IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
402 IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__GPIO_6_22 */
403 IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__MIPI_CORE_DPHY_IN_3 */
404 IMX_PIN_REG(MX6Q_PAD_RGMII_TD2, 0x0378, 0x0064, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_TD2__CCM_PLL2_BYP */
405 IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_HSI_CRL_RX_WAK */
406 IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
407 IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__GPIO_6_23 */
408 IMX_PIN_REG(MX6Q_PAD_RGMII_TD3, 0x037C, 0x0068, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TD3__MIPI_CORE_DPHY_IN_4 */
409 IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA */
410 IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 1, 0x0858, 0), /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
411 IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 */
412 IMX_PIN_REG(MX6Q_PAD_RGMII_RX_CTL, 0x0380, 0x006C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RX_CTL__MIPI_DPHY_IN_5 */
413 IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_HSI_CRL_RX_RDY */
414 IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 1, 0x0848, 0), /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
415 IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__GPIO_6_25 */
416 IMX_PIN_REG(MX6Q_PAD_RGMII_RD0, 0x0384, 0x0070, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD0__MIPI_CORE_DPHY_IN_6 */
417 IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE */
418 IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 1, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
419 IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__GPIO_6_26 */
420 IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_TX_CTL__CORE_DPHY_IN_7 */
421 IMX_PIN_REG(MX6Q_PAD_RGMII_TX_CTL, 0x0388, 0x0074, 7, 0x083C, 0), /* MX6Q_PAD_RGMII_TX_CTL__ANATOP_REF_OUT */
422 IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__MIPI_HSI_CTRL_TX_FL */
423 IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 1, 0x084C, 0), /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
424 IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__GPIO_6_27 */
425 IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__CORE_DPHY_TEST_IN_8 */
426 IMX_PIN_REG(MX6Q_PAD_RGMII_RD1, 0x038C, 0x0078, 7, 0x0000, 0), /* MX6Q_PAD_RGMII_RD1__SJC_FAIL */
427 IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_HSI_CRL_TX_DTA */
428 IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 1, 0x0850, 0), /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
429 IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__GPIO_6_28 */
430 IMX_PIN_REG(MX6Q_PAD_RGMII_RD2, 0x0390, 0x007C, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD2__MIPI_CORE_DPHY_IN_9 */
431 IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_HSI_CRL_TX_WAK */
432 IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 1, 0x0854, 0), /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
433 IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__GPIO_6_29 */
434 IMX_PIN_REG(MX6Q_PAD_RGMII_RD3, 0x0394, 0x0080, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RD3__MIPI_CORE_DPHY_IN10 */
435 IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 0, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE */
436 IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 1, 0x0844, 0), /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
437 IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 5, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__GPIO_6_30 */
438 IMX_PIN_REG(MX6Q_PAD_RGMII_RXC, 0x0398, 0x0084, 6, 0x0000, 0), /* MX6Q_PAD_RGMII_RXC__MIPI_CORE_DPHY_IN11 */
439 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A25__WEIM_WEIM_A_25 */
440 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI4_SS1 */
441 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 2, 0x0000, 0), /* MX6Q_PAD_EIM_A25__ECSPI2_RDY */
442 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 */
443 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS */
444 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A25__GPIO_5_2 */
445 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 6, 0x088C, 0), /* MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE */
446 IMX_PIN_REG(MX6Q_PAD_EIM_A25, 0x039C, 0x0088, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A25__PL301_PER1_HBURST_0 */
447 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__WEIM_WEIM_EB_2 */
448 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 1, 0x0800, 0), /* MX6Q_PAD_EIM_EB2__ECSPI1_SS0 */
449 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 2, 0x07EC, 0), /* MX6Q_PAD_EIM_EB2__CCM_DI1_EXT_CLK */
450 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 3, 0x08D4, 0), /* MX6Q_PAD_EIM_EB2__IPU2_CSI1_D_19 */
451 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 4, 0x0890, 0), /* MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL */
452 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__GPIO_2_30 */
453 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 6, 0x08A0, 0), /* MX6Q_PAD_EIM_EB2__I2C2_SCL */
454 IMX_PIN_REG(MX6Q_PAD_EIM_EB2, 0x03A0, 0x008C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 */
455 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16 */
456 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 1, 0x07F4, 0), /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
457 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D16__IPU1_DI0_PIN5 */
458 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 3, 0x08D0, 0), /* MX6Q_PAD_EIM_D16__IPU2_CSI1_D_18 */
459 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 4, 0x0894, 0), /* MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA */
460 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D16__GPIO_3_16 */
461 IMX_PIN_REG(MX6Q_PAD_EIM_D16, 0x03A4, 0x0090, 6, 0x08A4, 0), /* MX6Q_PAD_EIM_D16__I2C2_SDA */
462 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 */
463 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 1, 0x07F8, 0), /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
464 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D17__IPU1_DI0_PIN6 */
465 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 3, 0x08E0, 0), /* MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK */
466 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D17__DCIC1_DCIC_OUT */
467 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D17__GPIO_3_17 */
468 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 6, 0x08A8, 0), /* MX6Q_PAD_EIM_D17__I2C3_SCL */
469 IMX_PIN_REG(MX6Q_PAD_EIM_D17, 0x03A8, 0x0094, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D17__PL301_PER1_HBURST_1 */
470 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18 */
471 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 1, 0x07FC, 0), /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
472 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI0_PIN7 */
473 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 3, 0x08CC, 0), /* MX6Q_PAD_EIM_D18__IPU2_CSI1_D_17 */
474 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS */
475 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D18__GPIO_3_18 */
476 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 6, 0x08AC, 0), /* MX6Q_PAD_EIM_D18__I2C3_SDA */
477 IMX_PIN_REG(MX6Q_PAD_EIM_D18, 0x03AC, 0x0098, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D18__PL301_PER1_HBURST_2 */
478 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19 */
479 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 1, 0x0804, 0), /* MX6Q_PAD_EIM_D19__ECSPI1_SS1 */
480 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D19__IPU1_DI0_PIN8 */
481 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 3, 0x08C8, 0), /* MX6Q_PAD_EIM_D19__IPU2_CSI1_D_16 */
482 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 4, 0x091C, 0), /* MX6Q_PAD_EIM_D19__UART1_CTS */
483 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
484 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D19__EPIT1_EPITO */
485 IMX_PIN_REG(MX6Q_PAD_EIM_D19, 0x03B0, 0x009C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D19__PL301_PER1_HRESP */
486 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20 */
487 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 1, 0x0824, 0), /* MX6Q_PAD_EIM_D20__ECSPI4_SS0 */
488 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 */
489 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 3, 0x08C4, 0), /* MX6Q_PAD_EIM_D20__IPU2_CSI1_D_15 */
490 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 4, 0x091C, 1), /* MX6Q_PAD_EIM_D20__UART1_RTS */
491 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D20__GPIO_3_20 */
492 IMX_PIN_REG(MX6Q_PAD_EIM_D20, 0x03B4, 0x00A0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D20__EPIT2_EPITO */
493 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21 */
494 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D21__ECSPI4_SCLK */
495 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 */
496 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 3, 0x08B4, 0), /* MX6Q_PAD_EIM_D21__IPU2_CSI1_D_11 */
497 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 4, 0x0944, 0), /* MX6Q_PAD_EIM_D21__USBOH3_USBOTG_OC */
498 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D21__GPIO_3_21 */
499 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 6, 0x0898, 0), /* MX6Q_PAD_EIM_D21__I2C1_SCL */
500 IMX_PIN_REG(MX6Q_PAD_EIM_D21, 0x03B8, 0x00A4, 7, 0x0914, 0), /* MX6Q_PAD_EIM_D21__SPDIF_IN1 */
501 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22 */
502 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D22__ECSPI4_MISO */
503 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D22__IPU1_DI0_PIN1 */
504 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 3, 0x08B0, 0), /* MX6Q_PAD_EIM_D22__IPU2_CSI1_D_10 */
505 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D22__USBOH3_USBOTG_PWR */
506 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
507 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D22__SPDIF_OUT1 */
508 IMX_PIN_REG(MX6Q_PAD_EIM_D22, 0x03BC, 0x00A8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D22__PL301_PER1_HWRITE */
509 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23 */
510 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS */
511 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 2, 0x092C, 0), /* MX6Q_PAD_EIM_D23__UART3_CTS */
512 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D23__UART1_DCD */
513 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 4, 0x08D8, 0), /* MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN */
514 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
515 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN2 */
516 IMX_PIN_REG(MX6Q_PAD_EIM_D23, 0x03C0, 0x00AC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 */
517 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__WEIM_WEIM_EB_3 */
518 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__ECSPI4_RDY */
519 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 2, 0x092C, 1), /* MX6Q_PAD_EIM_EB3__UART3_RTS */
520 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__UART1_RI */
521 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 4, 0x08DC, 0), /* MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC */
522 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__GPIO_2_31 */
523 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN3 */
524 IMX_PIN_REG(MX6Q_PAD_EIM_EB3, 0x03C4, 0x00B0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB3__SRC_BT_CFG_31 */
525 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24 */
526 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI4_SS2 */
527 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART3_TXD */
528 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 3, 0x0808, 0), /* MX6Q_PAD_EIM_D24__ECSPI1_SS2 */
529 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D24__ECSPI2_SS2 */
530 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D24__GPIO_3_24 */
531 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 6, 0x07D8, 0), /* MX6Q_PAD_EIM_D24__AUDMUX_AUD5_RXFS */
532 IMX_PIN_REG(MX6Q_PAD_EIM_D24, 0x03C8, 0x00B4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D24__UART1_DTR */
533 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25 */
534 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI4_SS3 */
535 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 2, 0x0930, 1), /* MX6Q_PAD_EIM_D25__UART3_RXD */
536 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 3, 0x080C, 0), /* MX6Q_PAD_EIM_D25__ECSPI1_SS3 */
537 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D25__ECSPI2_SS3 */
538 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
539 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 6, 0x07D4, 0), /* MX6Q_PAD_EIM_D25__AUDMUX_AUD5_RXC */
540 IMX_PIN_REG(MX6Q_PAD_EIM_D25, 0x03CC, 0x00B8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D25__UART1_DSR */
541 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26 */
542 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 */
543 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1 */
544 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 3, 0x08C0, 0), /* MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14 */
545 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_D26__UART2_TXD */
546 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D26__GPIO_3_26 */
547 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_SISG_2 */
548 IMX_PIN_REG(MX6Q_PAD_EIM_D26, 0x03D0, 0x00BC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22 */
549 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27 */
550 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 */
551 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0 */
552 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 3, 0x08BC, 0), /* MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13 */
553 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 4, 0x0928, 1), /* MX6Q_PAD_EIM_D27__UART2_RXD */
554 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D27__GPIO_3_27 */
555 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_SISG_3 */
556 IMX_PIN_REG(MX6Q_PAD_EIM_D27, 0x03D4, 0x00C0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D27__IPU1_DISP1_DAT_23 */
557 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 */
558 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 1, 0x089C, 0), /* MX6Q_PAD_EIM_D28__I2C1_SDA */
559 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D28__ECSPI4_MOSI */
560 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 3, 0x08B8, 0), /* MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 */
561 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 4, 0x0924, 0), /* MX6Q_PAD_EIM_D28__UART2_CTS */
562 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D28__GPIO_3_28 */
563 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG */
564 IMX_PIN_REG(MX6Q_PAD_EIM_D28, 0x03D8, 0x00C4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 */
565 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29 */
566 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 */
567 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 2, 0x0824, 1), /* MX6Q_PAD_EIM_D29__ECSPI4_SS0 */
568 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 4, 0x0924, 1), /* MX6Q_PAD_EIM_D29__UART2_RTS */
569 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D29__GPIO_3_29 */
570 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 6, 0x08E4, 0), /* MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC */
571 IMX_PIN_REG(MX6Q_PAD_EIM_D29, 0x03DC, 0x00C8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 */
572 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30 */
573 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DISP1_DAT_21 */
574 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 */
575 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D30__IPU1_CSI0_D_3 */
576 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 4, 0x092C, 2), /* MX6Q_PAD_EIM_D30__UART3_CTS */
577 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D30__GPIO_3_30 */
578 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 6, 0x0948, 0), /* MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC */
579 IMX_PIN_REG(MX6Q_PAD_EIM_D30, 0x03E0, 0x00CC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D30__PL301_PER1_HPROT_0 */
580 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31 */
581 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DISP1_DAT_20 */
582 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 2, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 */
583 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_D31__IPU1_CSI0_D_2 */
584 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 4, 0x092C, 3), /* MX6Q_PAD_EIM_D31__UART3_RTS */
585 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_D31__GPIO_3_31 */
586 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_D31__USBOH3_USBH1_PWR */
587 IMX_PIN_REG(MX6Q_PAD_EIM_D31, 0x03E4, 0x00D0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_D31__PL301_PER1_HPROT_1 */
588 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24 */
589 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_DISP1_DAT_19 */
590 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 2, 0x08D4, 1), /* MX6Q_PAD_EIM_A24__IPU2_CSI1_D_19 */
591 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU2_SISG_2 */
592 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A24__IPU1_SISG_2 */
593 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A24__GPIO_5_4 */
594 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A24__PL301_PER1_HPROT_2 */
595 IMX_PIN_REG(MX6Q_PAD_EIM_A24, 0x03E8, 0x00D4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A24__SRC_BT_CFG_24 */
596 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23 */
597 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_DISP1_DAT_18 */
598 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 2, 0x08D0, 1), /* MX6Q_PAD_EIM_A23__IPU2_CSI1_D_18 */
599 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU2_SISG_3 */
600 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A23__IPU1_SISG_3 */
601 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A23__GPIO_6_6 */
602 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A23__PL301_PER1_HPROT_3 */
603 IMX_PIN_REG(MX6Q_PAD_EIM_A23, 0x03EC, 0x00D8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A23__SRC_BT_CFG_23 */
604 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22 */
605 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A22__IPU1_DISP1_DAT_17 */
606 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 2, 0x08CC, 1), /* MX6Q_PAD_EIM_A22__IPU2_CSI1_D_17 */
607 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A22__GPIO_2_16 */
608 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A22__TPSMP_HDATA_0 */
609 IMX_PIN_REG(MX6Q_PAD_EIM_A22, 0x03F0, 0x00DC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A22__SRC_BT_CFG_22 */
610 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21 */
611 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A21__IPU1_DISP1_DAT_16 */
612 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 2, 0x08C8, 1), /* MX6Q_PAD_EIM_A21__IPU2_CSI1_D_16 */
613 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A21__RESERVED_RESERVED */
614 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A21__MIPI_CORE_DPHY_OUT_18 */
615 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A21__GPIO_2_17 */
616 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A21__TPSMP_HDATA_1 */
617 IMX_PIN_REG(MX6Q_PAD_EIM_A21, 0x03F4, 0x00E0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A21__SRC_BT_CFG_21 */
618 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20 */
619 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A20__IPU1_DISP1_DAT_15 */
620 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 2, 0x08C4, 1), /* MX6Q_PAD_EIM_A20__IPU2_CSI1_D_15 */
621 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A20__RESERVED_RESERVED */
622 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A20__MIPI_CORE_DPHY_OUT_19 */
623 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A20__GPIO_2_18 */
624 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A20__TPSMP_HDATA_2 */
625 IMX_PIN_REG(MX6Q_PAD_EIM_A20, 0x03F8, 0x00E4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A20__SRC_BT_CFG_20 */
626 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19 */
627 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A19__IPU1_DISP1_DAT_14 */
628 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 2, 0x08C0, 1), /* MX6Q_PAD_EIM_A19__IPU2_CSI1_D_14 */
629 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A19__RESERVED_RESERVED */
630 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A19__MIPI_CORE_DPHY_OUT_20 */
631 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A19__GPIO_2_19 */
632 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A19__TPSMP_HDATA_3 */
633 IMX_PIN_REG(MX6Q_PAD_EIM_A19, 0x03FC, 0x00E8, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A19__SRC_BT_CFG_19 */
634 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18 */
635 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A18__IPU1_DISP1_DAT_13 */
636 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 2, 0x08BC, 1), /* MX6Q_PAD_EIM_A18__IPU2_CSI1_D_13 */
637 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A18__RESERVED_RESERVED */
638 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A18__MIPI_CORE_DPHY_OUT_21 */
639 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A18__GPIO_2_20 */
640 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A18__TPSMP_HDATA_4 */
641 IMX_PIN_REG(MX6Q_PAD_EIM_A18, 0x0400, 0x00EC, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A18__SRC_BT_CFG_18 */
642 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17 */
643 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A17__IPU1_DISP1_DAT_12 */
644 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 2, 0x08B8, 1), /* MX6Q_PAD_EIM_A17__IPU2_CSI1_D_12 */
645 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 3, 0x0000, 0), /* MX6Q_PAD_EIM_A17__RESERVED_RESERVED */
646 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A17__MIPI_CORE_DPHY_OUT_22 */
647 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A17__GPIO_2_21 */
648 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A17__TPSMP_HDATA_5 */
649 IMX_PIN_REG(MX6Q_PAD_EIM_A17, 0x0404, 0x00F0, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A17__SRC_BT_CFG_17 */
650 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 0, 0x0000, 0), /* MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16 */
651 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 1, 0x0000, 0), /* MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK */
652 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 2, 0x08E0, 1), /* MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK */
653 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 4, 0x0000, 0), /* MX6Q_PAD_EIM_A16__MIPI_CORE_DPHY_OUT_23 */
654 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 5, 0x0000, 0), /* MX6Q_PAD_EIM_A16__GPIO_2_22 */
655 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 6, 0x0000, 0), /* MX6Q_PAD_EIM_A16__TPSMP_HDATA_6 */
656 IMX_PIN_REG(MX6Q_PAD_EIM_A16, 0x0408, 0x00F4, 7, 0x0000, 0), /* MX6Q_PAD_EIM_A16__SRC_BT_CFG_16 */
657 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0 */
658 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN5 */
659 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 2, 0x0810, 0), /* MX6Q_PAD_EIM_CS0__ECSPI2_SCLK */
660 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__MIPI_CORE_DPHY_OUT_24 */
661 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__GPIO_2_23 */
662 IMX_PIN_REG(MX6Q_PAD_EIM_CS0, 0x040C, 0x00F8, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS0__TPSMP_HDATA_7 */
663 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 0, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__WEIM_WEIM_CS_1 */
664 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 1, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN6 */
665 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 2, 0x0818, 0), /* MX6Q_PAD_EIM_CS1__ECSPI2_MOSI */
666 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 4, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__MIPI_CORE_DPHY_OUT_25 */
667 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 5, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__GPIO_2_24 */
668 IMX_PIN_REG(MX6Q_PAD_EIM_CS1, 0x0410, 0x00FC, 6, 0x0000, 0), /* MX6Q_PAD_EIM_CS1__TPSMP_HDATA_8 */
669 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 0, 0x0000, 0), /* MX6Q_PAD_EIM_OE__WEIM_WEIM_OE */
670 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 1, 0x0000, 0), /* MX6Q_PAD_EIM_OE__IPU1_DI1_PIN7 */
671 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 2, 0x0814, 0), /* MX6Q_PAD_EIM_OE__ECSPI2_MISO */
672 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 4, 0x0000, 0), /* MX6Q_PAD_EIM_OE__MIPI_CORE_DPHY_OUT_26 */
673 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 5, 0x0000, 0), /* MX6Q_PAD_EIM_OE__GPIO_2_25 */
674 IMX_PIN_REG(MX6Q_PAD_EIM_OE, 0x0414, 0x0100, 6, 0x0000, 0), /* MX6Q_PAD_EIM_OE__TPSMP_HDATA_9 */
675 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 0, 0x0000, 0), /* MX6Q_PAD_EIM_RW__WEIM_WEIM_RW */
676 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 1, 0x0000, 0), /* MX6Q_PAD_EIM_RW__IPU1_DI1_PIN8 */
677 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 2, 0x081C, 0), /* MX6Q_PAD_EIM_RW__ECSPI2_SS0 */
678 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 4, 0x0000, 0), /* MX6Q_PAD_EIM_RW__MIPI_CORE_DPHY_OUT_27 */
679 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 5, 0x0000, 0), /* MX6Q_PAD_EIM_RW__GPIO_2_26 */
680 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 6, 0x0000, 0), /* MX6Q_PAD_EIM_RW__TPSMP_HDATA_10 */
681 IMX_PIN_REG(MX6Q_PAD_EIM_RW, 0x0418, 0x0104, 7, 0x0000, 0), /* MX6Q_PAD_EIM_RW__SRC_BT_CFG_29 */
682 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 0, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA */
683 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 1, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 */
684 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 2, 0x0820, 0), /* MX6Q_PAD_EIM_LBA__ECSPI2_SS1 */
685 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 5, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__GPIO_2_27 */
686 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 6, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__TPSMP_HDATA_11 */
687 IMX_PIN_REG(MX6Q_PAD_EIM_LBA, 0x041C, 0x0108, 7, 0x0000, 0), /* MX6Q_PAD_EIM_LBA__SRC_BT_CFG_26 */
688 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__WEIM_WEIM_EB_0 */
689 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__IPU1_DISP1_DAT_11 */
690 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 2, 0x08B4, 1), /* MX6Q_PAD_EIM_EB0__IPU2_CSI1_D_11 */
691 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__MIPI_CORE_DPHY_OUT_0 */
692 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 4, 0x07F0, 0), /* MX6Q_PAD_EIM_EB0__CCM_PMIC_RDY */
693 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__GPIO_2_28 */
694 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__TPSMP_HDATA_12 */
695 IMX_PIN_REG(MX6Q_PAD_EIM_EB0, 0x0420, 0x010C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB0__SRC_BT_CFG_27 */
696 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 0, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__WEIM_WEIM_EB_1 */
697 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 1, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__IPU1_DISP1_DAT_10 */
698 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 2, 0x08B0, 1), /* MX6Q_PAD_EIM_EB1__IPU2_CSI1_D_10 */
699 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 3, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__MIPI_CORE_DPHY__OUT_1 */
700 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 5, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__GPIO_2_29 */
701 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 6, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__TPSMP_HDATA_13 */
702 IMX_PIN_REG(MX6Q_PAD_EIM_EB1, 0x0424, 0x0110, 7, 0x0000, 0), /* MX6Q_PAD_EIM_EB1__SRC_BT_CFG_28 */
703 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 */
704 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU1_DISP1_DAT_9 */
705 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__IPU2_CSI1_D_9 */
706 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__MIPI_CORE_DPHY__OUT_2 */
707 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__GPIO_3_0 */
708 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__TPSMP_HDATA_14 */
709 IMX_PIN_REG(MX6Q_PAD_EIM_DA0, 0x0428, 0x0114, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA0__SRC_BT_CFG_0 */
710 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1 */
711 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU1_DISP1_DAT_8 */
712 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__IPU2_CSI1_D_8 */
713 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__MIPI_CORE_DPHY_OUT_3 */
714 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__USBPHY1_TX_LS_MODE */
715 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__GPIO_3_1 */
716 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__TPSMP_HDATA_15 */
717 IMX_PIN_REG(MX6Q_PAD_EIM_DA1, 0x042C, 0x0118, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA1__SRC_BT_CFG_1 */
718 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2 */
719 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU1_DISP1_DAT_7 */
720 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__IPU2_CSI1_D_7 */
721 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__MIPI_CORE_DPHY_OUT_4 */
722 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__USBPHY1_TX_HS_MODE */
723 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__GPIO_3_2 */
724 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__TPSMP_HDATA_16 */
725 IMX_PIN_REG(MX6Q_PAD_EIM_DA2, 0x0430, 0x011C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA2__SRC_BT_CFG_2 */
726 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3 */
727 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU1_DISP1_DAT_6 */
728 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__IPU2_CSI1_D_6 */
729 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__MIPI_CORE_DPHY_OUT_5 */
730 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__USBPHY1_TX_HIZ */
731 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__GPIO_3_3 */
732 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__TPSMP_HDATA_17 */
733 IMX_PIN_REG(MX6Q_PAD_EIM_DA3, 0x0434, 0x0120, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA3__SRC_BT_CFG_3 */
734 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4 */
735 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU1_DISP1_DAT_5 */
736 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__IPU2_CSI1_D_5 */
737 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__MIPI_CORE_DPHY_OUT_6 */
738 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__ANATOP_USBPHY1_TX_EN */
739 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__GPIO_3_4 */
740 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__TPSMP_HDATA_18 */
741 IMX_PIN_REG(MX6Q_PAD_EIM_DA4, 0x0438, 0x0124, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA4__SRC_BT_CFG_4 */
742 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5 */
743 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU1_DISP1_DAT_4 */
744 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__IPU2_CSI1_D_4 */
745 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__MIPI_CORE_DPHY_OUT_7 */
746 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__ANATOP_USBPHY1_TX_DP */
747 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__GPIO_3_5 */
748 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__TPSMP_HDATA_19 */
749 IMX_PIN_REG(MX6Q_PAD_EIM_DA5, 0x043C, 0x0128, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA5__SRC_BT_CFG_5 */
750 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6 */
751 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU1_DISP1_DAT_3 */
752 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__IPU2_CSI1_D_3 */
753 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__MIPI_CORE_DPHY_OUT_8 */
754 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__ANATOP_USBPHY1_TX_DN */
755 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__GPIO_3_6 */
756 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__TPSMP_HDATA_20 */
757 IMX_PIN_REG(MX6Q_PAD_EIM_DA6, 0x0440, 0x012C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA6__SRC_BT_CFG_6 */
758 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7 */
759 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU1_DISP1_DAT_2 */
760 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__IPU2_CSI1_D_2 */
761 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__MIPI_CORE_DPHY_OUT_9 */
762 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__GPIO_3_7 */
763 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__TPSMP_HDATA_21 */
764 IMX_PIN_REG(MX6Q_PAD_EIM_DA7, 0x0444, 0x0130, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA7__SRC_BT_CFG_7 */
765 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8 */
766 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU1_DISP1_DAT_1 */
767 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__IPU2_CSI1_D_1 */
768 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__MIPI_CORE_DPHY_OUT_10 */
769 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__GPIO_3_8 */
770 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__TPSMP_HDATA_22 */
771 IMX_PIN_REG(MX6Q_PAD_EIM_DA8, 0x0448, 0x0134, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA8__SRC_BT_CFG_8 */
772 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9 */
773 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU1_DISP1_DAT_0 */
774 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__IPU2_CSI1_D_0 */
775 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__MIPI_CORE_DPHY_OUT_11 */
776 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__GPIO_3_9 */
777 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__TPSMP_HDATA_23 */
778 IMX_PIN_REG(MX6Q_PAD_EIM_DA9, 0x044C, 0x0138, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA9__SRC_BT_CFG_9 */
779 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10 */
780 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 */
781 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 2, 0x08D8, 1), /* MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN */
782 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__MIPI_CORE_DPHY_OUT12 */
783 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__GPIO_3_10 */
784 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__TPSMP_HDATA_24 */
785 IMX_PIN_REG(MX6Q_PAD_EIM_DA10, 0x0450, 0x013C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA10__SRC_BT_CFG_10 */
786 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11 */
787 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN2 */
788 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 2, 0x08DC, 1), /* MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC */
789 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__MIPI_CORE_DPHY_OUT13 */
790 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SDMA_DBG_EVT_CHN_6 */
791 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__GPIO_3_11 */
792 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__TPSMP_HDATA_25 */
793 IMX_PIN_REG(MX6Q_PAD_EIM_DA11, 0x0454, 0x0140, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA11__SRC_BT_CFG_11 */
794 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12 */
795 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN3 */
796 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 2, 0x08E4, 1), /* MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC */
797 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__MIPI_CORE_DPHY_OUT14 */
798 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SDMA_DEBUG_EVT_CHN_3 */
799 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__GPIO_3_12 */
800 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__TPSMP_HDATA_26 */
801 IMX_PIN_REG(MX6Q_PAD_EIM_DA12, 0x0458, 0x0144, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA12__SRC_BT_CFG_12 */
802 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13 */
803 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS */
804 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 2, 0x07EC, 1), /* MX6Q_PAD_EIM_DA13__CCM_DI1_EXT_CLK */
805 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__MIPI_CORE_DPHY_OUT15 */
806 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SDMA_DEBUG_EVT_CHN_4 */
807 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__GPIO_3_13 */
808 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__TPSMP_HDATA_27 */
809 IMX_PIN_REG(MX6Q_PAD_EIM_DA13, 0x045C, 0x0148, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA13__SRC_BT_CFG_13 */
810 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14 */
811 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS */
812 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__CCM_DI0_EXT_CLK */
813 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__MIPI_CORE_DPHY_OUT16 */
814 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 4, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SDMA_DEBUG_EVT_CHN_5 */
815 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__GPIO_3_14 */
816 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__TPSMP_HDATA_28 */
817 IMX_PIN_REG(MX6Q_PAD_EIM_DA14, 0x0460, 0x014C, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA14__SRC_BT_CFG_14 */
818 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 0, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15 */
819 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 1, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN1 */
820 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 2, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN4 */
821 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 3, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__MIPI_CORE_DPHY_OUT17 */
822 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 5, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__GPIO_3_15 */
823 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 6, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__TPSMP_HDATA_29 */
824 IMX_PIN_REG(MX6Q_PAD_EIM_DA15, 0x0464, 0x0150, 7, 0x0000, 0), /* MX6Q_PAD_EIM_DA15__SRC_BT_CFG_15 */
825 IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 0, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT */
826 IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 1, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__WEIM_WEIM_DTACK_B */
827 IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 5, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__GPIO_5_0 */
828 IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 6, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__TPSMP_HDATA_30 */
829 IMX_PIN_REG(MX6Q_PAD_EIM_WAIT, 0x0468, 0x0154, 7, 0x0000, 0), /* MX6Q_PAD_EIM_WAIT__SRC_BT_CFG_25 */
830 IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 0, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK */
831 IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 1, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 */
832 IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 5, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__GPIO_6_31 */
833 IMX_PIN_REG(MX6Q_PAD_EIM_BCLK, 0x046C, 0x0158, 6, 0x0000, 0), /* MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31 */
834 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DSP_CLK */
835 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DSP_CLK */
836 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 3, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 */
837 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 */
838 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16 */
839 IMX_PIN_REG(MX6Q_PAD_DI0_DISP_CLK, 0x0470, 0x015C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0 */
840 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 */
841 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 */
842 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC */
843 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 */
844 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 */
845 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__GPIO_4_17 */
846 IMX_PIN_REG(MX6Q_PAD_DI0_PIN15, 0x0474, 0x0160, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 */
847 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2 */
848 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2 */
849 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD */
850 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30 */
851 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__SDMA_DBG_CORE_STA_2 */
852 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__GPIO_4_18 */
853 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2 */
854 IMX_PIN_REG(MX6Q_PAD_DI0_PIN2, 0x0478, 0x0164, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9 */
855 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3 */
856 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3 */
857 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS */
858 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 3, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 */
859 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__SDMA_DBG_CORE_STA_3 */
860 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__GPIO_4_19 */
861 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 */
862 IMX_PIN_REG(MX6Q_PAD_DI0_PIN3, 0x047C, 0x0168, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN3__PL301_PER1_HADDR_10 */
863 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 0, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4 */
864 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 1, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN4 */
865 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 2, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD */
866 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 3, 0x094C, 0), /* MX6Q_PAD_DI0_PIN4__USDHC1_WP */
867 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 4, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD */
868 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 5, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__GPIO_4_20 */
869 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 6, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 */
870 IMX_PIN_REG(MX6Q_PAD_DI0_PIN4, 0x0480, 0x016C, 7, 0x0000, 0), /* MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11 */
871 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 */
872 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0 */
873 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK */
874 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 */
875 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN */
876 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__GPIO_4_21 */
877 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT0, 0x0484, 0x0170, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 */
878 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 */
879 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1 */
880 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI */
881 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 */
882 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__SDMA_DBG_EVT_CHNSL */
883 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__GPIO_4_22 */
884 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6 */
885 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT1, 0x0488, 0x0174, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 */
886 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 */
887 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 */
888 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO */
889 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 */
890 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__SDMA_DEBUG_MODE */
891 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__GPIO_4_23 */
892 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7 */
893 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT2, 0x048C, 0x0178, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 */
894 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 */
895 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 */
896 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 */
897 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 */
898 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__SDMA_DBG_BUS_ERROR */
899 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__GPIO_4_24 */
900 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 */
901 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT3, 0x0490, 0x017C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 */
902 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 */
903 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 */
904 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 */
905 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 */
906 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB */
907 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__GPIO_4_25 */
908 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 */
909 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT4, 0x0494, 0x0180, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 */
910 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 */
911 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 */
912 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 */
913 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS */
914 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__SDMA_DBG_MCH_DMBUS */
915 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__GPIO_4_26 */
916 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10 */
917 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT5, 0x0498, 0x0184, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 */
918 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 */
919 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 */
920 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 */
921 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC */
922 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__SDMA_DBG_RTBUF_WRT */
923 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__GPIO_4_27 */
924 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11 */
925 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT6, 0x049C, 0x0188, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 */
926 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 */
927 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 */
928 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY */
929 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 */
930 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__SDMA_DBG_EVT_CHN_0 */
931 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__GPIO_4_28 */
932 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12 */
933 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT7, 0x04A0, 0x018C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 */
934 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 */
935 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 */
936 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PWM1_PWMO */
937 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B */
938 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__SDMA_DBG_EVT_CHN_1 */
939 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__GPIO_4_29 */
940 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13 */
941 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT8, 0x04A4, 0x0190, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 */
942 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 */
943 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 */
944 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 2, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PWM2_PWMO */
945 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B */
946 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__SDMA_DBG_EVT_CHN_2 */
947 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__GPIO_4_30 */
948 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14 */
949 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT9, 0x04A8, 0x0194, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 */
950 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 */
951 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 */
952 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6 */
953 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 */
954 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__GPIO_4_31 */
955 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15 */
956 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT10, 0x04AC, 0x0198, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 */
957 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 */
958 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 */
959 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 */
960 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 */
961 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__GPIO_5_5 */
962 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16 */
963 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT11, 0x04B0, 0x019C, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 */
964 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 */
965 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 */
966 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 3, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED */
967 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 */
968 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__GPIO_5_6 */
969 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17 */
970 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT12, 0x04B4, 0x01A0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 */
971 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 */
972 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 */
973 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 3, 0x07D8, 1), /* MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS */
974 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 */
975 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__GPIO_5_7 */
976 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18 */
977 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT13, 0x04B8, 0x01A4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 */
978 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 */
979 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 */
980 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 3, 0x07D4, 1), /* MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC */
981 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 */
982 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__GPIO_5_8 */
983 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT14, 0x04BC, 0x01A8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19 */
984 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 */
985 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 */
986 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 2, 0x0804, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 */
987 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 3, 0x0820, 1), /* MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 */
988 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__SDMA_DBG_EVT_CHN2 */
989 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__GPIO_5_9 */
990 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20 */
991 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT15, 0x04C0, 0x01AC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 */
992 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 */
993 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 */
994 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 2, 0x0818, 1), /* MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI */
995 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 3, 0x07DC, 0), /* MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC */
996 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 4, 0x090C, 0), /* MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 */
997 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__GPIO_5_10 */
998 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21 */
999 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT16, 0x04C4, 0x01B0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 */
1000 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 */
1001 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 */
1002 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 2, 0x0814, 1), /* MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO */
1003 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 3, 0x07D0, 0), /* MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD */
1004 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 4, 0x0910, 0), /* MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 */
1005 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__GPIO_5_11 */
1006 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22 */
1007 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT17, 0x04C8, 0x01B4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 */
1008 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 */
1009 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 */
1010 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 2, 0x081C, 1), /* MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 */
1011 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 3, 0x07E0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS */
1012 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 4, 0x07C0, 0), /* MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS */
1013 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__GPIO_5_12 */
1014 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23 */
1015 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT18, 0x04CC, 0x01B8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2 */
1016 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 */
1017 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 */
1018 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 2, 0x0810, 1), /* MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK */
1019 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 3, 0x07CC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD */
1020 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 4, 0x07BC, 0), /* MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC */
1021 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__GPIO_5_13 */
1022 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24 */
1023 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT19, 0x04D0, 0x01BC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3 */
1024 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 */
1025 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 */
1026 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 2, 0x07F4, 1), /* MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK */
1027 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 3, 0x07C4, 0), /* MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC */
1028 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__SDMA_DBG_EVT_CHN7 */
1029 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__GPIO_5_14 */
1030 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25 */
1031 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT20, 0x04D4, 0x01C0, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 */
1032 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 */
1033 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 */
1034 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 2, 0x07FC, 1), /* MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI */
1035 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 3, 0x07B8, 1), /* MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD */
1036 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__SDMA_DBG_BUS_DEV0 */
1037 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__GPIO_5_15 */
1038 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26 */
1039 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT21, 0x04D8, 0x01C4, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 */
1040 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 */
1041 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 */
1042 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 2, 0x07F8, 1), /* MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO */
1043 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 3, 0x07C8, 1), /* MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS */
1044 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__SDMA_DBG_BUS_DEV1 */
1045 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__GPIO_5_16 */
1046 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27 */
1047 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT22, 0x04DC, 0x01C8, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 */
1048 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 0, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 */
1049 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 1, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 */
1050 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 2, 0x0800, 1), /* MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 */
1051 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 3, 0x07B4, 1), /* MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD */
1052 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 4, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__SDMA_DBG_BUS_DEV2 */
1053 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 5, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__GPIO_5_17 */
1054 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 6, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__MMDC_DEBUG_28 */
1055 IMX_PIN_REG(MX6Q_PAD_DISP0_DAT23, 0x04E0, 0x01CC, 7, 0x0000, 0), /* MX6Q_PAD_DISP0_DAT23__PL301_PER1_HADR31 */
1056 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED */
1057 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 1, 0x0840, 0), /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
1058 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 2, 0x086C, 0), /* MX6Q_PAD_ENET_MDIO__ESAI1_SCKR */
1059 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 3, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEV3 */
1060 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__ENET_1588_EVT1_OUT */
1061 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__GPIO_1_22 */
1062 IMX_PIN_REG(MX6Q_PAD_ENET_MDIO, 0x04E4, 0x01D0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDIO__SPDIF_PLOCK */
1063 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__RESERVED_RSRVED */
1064 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
1065 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 2, 0x085C, 0), /* MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR */
1066 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SDMA_DBGBUS_DEV4 */
1067 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__GPIO_1_23 */
1068 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__SPDIF_SRCLK */
1069 IMX_PIN_REG(MX6Q_PAD_ENET_REF_CLK, 0x04E8, 0x01D4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_REF_CLK__USBPHY1_RX_SQH */
1070 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_RX_ER */
1071 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 2, 0x0864, 0), /* MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR */
1072 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 3, 0x0914, 1), /* MX6Q_PAD_ENET_RX_ER__SPDIF_IN1 */
1073 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__ENET_1588_EVT2_OUT */
1074 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__GPIO_1_24 */
1075 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__PHY_TDI */
1076 IMX_PIN_REG(MX6Q_PAD_ENET_RX_ER, 0x04EC, 0x01D8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RX_ER__USBPHY1_RX_HS_RXD */
1077 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 0, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__RESERVED_RSRVED */
1078 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 1, 0x0858, 1), /* MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN */
1079 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 2, 0x0870, 0), /* MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT */
1080 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 3, 0x0918, 1), /* MX6Q_PAD_ENET_CRS_DV__SPDIF_EXTCLK */
1081 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 */
1082 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__PHY_TDO */
1083 IMX_PIN_REG(MX6Q_PAD_ENET_CRS_DV, 0x04F0, 0x01DC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_CRS_DV__USBPHY1_RX_FS_RXD */
1084 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 0, 0x0908, 0), /* MX6Q_PAD_ENET_RXD1__MLB_MLBSIG */
1085 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 1, 0x084C, 1), /* MX6Q_PAD_ENET_RXD1__ENET_RDATA_1 */
1086 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 2, 0x0860, 0), /* MX6Q_PAD_ENET_RXD1__ESAI1_FST */
1087 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 4, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__ENET_1588_EVT3_OUT */
1088 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__GPIO_1_26 */
1089 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__PHY_TCK */
1090 IMX_PIN_REG(MX6Q_PAD_ENET_RXD1, 0x04F4, 0x01E0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD1__USBPHY1_RX_DISCON */
1091 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 0, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__OSC32K_32K_OUT */
1092 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 1, 0x0848, 1), /* MX6Q_PAD_ENET_RXD0__ENET_RDATA_0 */
1093 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 2, 0x0868, 0), /* MX6Q_PAD_ENET_RXD0__ESAI1_HCKT */
1094 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 3, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__SPDIF_OUT1 */
1095 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__GPIO_1_27 */
1096 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__PHY_TMS */
1097 IMX_PIN_REG(MX6Q_PAD_ENET_RXD0, 0x04F8, 0x01E4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_RXD0__USBPHY1_PLL_CK20DIV */
1098 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__RESERVED_RSRVED */
1099 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__ENET_TX_EN */
1100 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 2, 0x0880, 0), /* MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2 */
1101 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__GPIO_1_28 */
1102 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__SATA_PHY_TDI */
1103 IMX_PIN_REG(MX6Q_PAD_ENET_TX_EN, 0x04FC, 0x01E8, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TX_EN__USBPHY2_RX_SQH */
1104 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 0, 0x0900, 0), /* MX6Q_PAD_ENET_TXD1__MLB_MLBCLK */
1105 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_TDATA_1 */
1106 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 2, 0x087C, 0), /* MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3 */
1107 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 4, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN */
1108 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__GPIO_1_29 */
1109 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__SATA_PHY_TDO */
1110 IMX_PIN_REG(MX6Q_PAD_ENET_TXD1, 0x0500, 0x01EC, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD1__USBPHY2_RX_HS_RXD */
1111 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 0, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__RESERVED_RSRVED */
1112 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 1, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__ENET_TDATA_0 */
1113 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 2, 0x0884, 0), /* MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1 */
1114 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 5, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__GPIO_1_30 */
1115 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 6, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__SATA_PHY_TCK */
1116 IMX_PIN_REG(MX6Q_PAD_ENET_TXD0, 0x0504, 0x01F0, 7, 0x0000, 0), /* MX6Q_PAD_ENET_TXD0__USBPHY2_RX_FS_RXD */
1117 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 0, 0x0904, 0), /* MX6Q_PAD_ENET_MDC__MLB_MLBDAT */
1118 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 1, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_MDC */
1119 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 2, 0x0888, 0), /* MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 */
1120 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 4, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN */
1121 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 5, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__GPIO_1_31 */
1122 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 6, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__SATA_PHY_TMS */
1123 IMX_PIN_REG(MX6Q_PAD_ENET_MDC, 0x0508, 0x01F4, 7, 0x0000, 0), /* MX6Q_PAD_ENET_MDC__USBPHY2_RX_DISCON */
1124 IMX_PIN_REG(MX6Q_PAD_DRAM_D40, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D40__MMDC_DRAM_D_40 */
1125 IMX_PIN_REG(MX6Q_PAD_DRAM_D41, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D41__MMDC_DRAM_D_41 */
1126 IMX_PIN_REG(MX6Q_PAD_DRAM_D42, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D42__MMDC_DRAM_D_42 */
1127 IMX_PIN_REG(MX6Q_PAD_DRAM_D43, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D43__MMDC_DRAM_D_43 */
1128 IMX_PIN_REG(MX6Q_PAD_DRAM_D44, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D44__MMDC_DRAM_D_44 */
1129 IMX_PIN_REG(MX6Q_PAD_DRAM_D45, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D45__MMDC_DRAM_D_45 */
1130 IMX_PIN_REG(MX6Q_PAD_DRAM_D46, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D46__MMDC_DRAM_D_46 */
1131 IMX_PIN_REG(MX6Q_PAD_DRAM_D47, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D47__MMDC_DRAM_D_47 */
1132 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS5, 0x050C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS5__MMDC_DRAM_SDQS_5 */
1133 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM5, 0x0510, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM5__MMDC_DRAM_DQM_5 */
1134 IMX_PIN_REG(MX6Q_PAD_DRAM_D32, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D32__MMDC_DRAM_D_32 */
1135 IMX_PIN_REG(MX6Q_PAD_DRAM_D33, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D33__MMDC_DRAM_D_33 */
1136 IMX_PIN_REG(MX6Q_PAD_DRAM_D34, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D34__MMDC_DRAM_D_34 */
1137 IMX_PIN_REG(MX6Q_PAD_DRAM_D35, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D35__MMDC_DRAM_D_35 */
1138 IMX_PIN_REG(MX6Q_PAD_DRAM_D36, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D36__MMDC_DRAM_D_36 */
1139 IMX_PIN_REG(MX6Q_PAD_DRAM_D37, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D37__MMDC_DRAM_D_37 */
1140 IMX_PIN_REG(MX6Q_PAD_DRAM_D38, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D38__MMDC_DRAM_D_38 */
1141 IMX_PIN_REG(MX6Q_PAD_DRAM_D39, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D39__MMDC_DRAM_D_39 */
1142 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM4, 0x0514, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM4__MMDC_DRAM_DQM_4 */
1143 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS4, 0x0518, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS4__MMDC_DRAM_SDQS_4 */
1144 IMX_PIN_REG(MX6Q_PAD_DRAM_D24, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D24__MMDC_DRAM_D_24 */
1145 IMX_PIN_REG(MX6Q_PAD_DRAM_D25, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D25__MMDC_DRAM_D_25 */
1146 IMX_PIN_REG(MX6Q_PAD_DRAM_D26, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D26__MMDC_DRAM_D_26 */
1147 IMX_PIN_REG(MX6Q_PAD_DRAM_D27, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D27__MMDC_DRAM_D_27 */
1148 IMX_PIN_REG(MX6Q_PAD_DRAM_D28, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D28__MMDC_DRAM_D_28 */
1149 IMX_PIN_REG(MX6Q_PAD_DRAM_D29, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D29__MMDC_DRAM_D_29 */
1150 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS3, 0x051C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 */
1151 IMX_PIN_REG(MX6Q_PAD_DRAM_D30, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D30__MMDC_DRAM_D_30 */
1152 IMX_PIN_REG(MX6Q_PAD_DRAM_D31, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D31__MMDC_DRAM_D_31 */
1153 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM3, 0x0520, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 */
1154 IMX_PIN_REG(MX6Q_PAD_DRAM_D16, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D16__MMDC_DRAM_D_16 */
1155 IMX_PIN_REG(MX6Q_PAD_DRAM_D17, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D17__MMDC_DRAM_D_17 */
1156 IMX_PIN_REG(MX6Q_PAD_DRAM_D18, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D18__MMDC_DRAM_D_18 */
1157 IMX_PIN_REG(MX6Q_PAD_DRAM_D19, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D19__MMDC_DRAM_D_19 */
1158 IMX_PIN_REG(MX6Q_PAD_DRAM_D20, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D20__MMDC_DRAM_D_20 */
1159 IMX_PIN_REG(MX6Q_PAD_DRAM_D21, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D21__MMDC_DRAM_D_21 */
1160 IMX_PIN_REG(MX6Q_PAD_DRAM_D22, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D22__MMDC_DRAM_D_22 */
1161 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS2, 0x0524, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 */
1162 IMX_PIN_REG(MX6Q_PAD_DRAM_D23, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D23__MMDC_DRAM_D_23 */
1163 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM2, 0x0528, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 */
1164 IMX_PIN_REG(MX6Q_PAD_DRAM_A0, 0x052C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A0__MMDC_DRAM_A_0 */
1165 IMX_PIN_REG(MX6Q_PAD_DRAM_A1, 0x0530, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A1__MMDC_DRAM_A_1 */
1166 IMX_PIN_REG(MX6Q_PAD_DRAM_A2, 0x0534, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A2__MMDC_DRAM_A_2 */
1167 IMX_PIN_REG(MX6Q_PAD_DRAM_A3, 0x0538, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A3__MMDC_DRAM_A_3 */
1168 IMX_PIN_REG(MX6Q_PAD_DRAM_A4, 0x053C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A4__MMDC_DRAM_A_4 */
1169 IMX_PIN_REG(MX6Q_PAD_DRAM_A5, 0x0540, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A5__MMDC_DRAM_A_5 */
1170 IMX_PIN_REG(MX6Q_PAD_DRAM_A6, 0x0544, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A6__MMDC_DRAM_A_6 */
1171 IMX_PIN_REG(MX6Q_PAD_DRAM_A7, 0x0548, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A7__MMDC_DRAM_A_7 */
1172 IMX_PIN_REG(MX6Q_PAD_DRAM_A8, 0x054C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A8__MMDC_DRAM_A_8 */
1173 IMX_PIN_REG(MX6Q_PAD_DRAM_A9, 0x0550, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A9__MMDC_DRAM_A_9 */
1174 IMX_PIN_REG(MX6Q_PAD_DRAM_A10, 0x0554, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A10__MMDC_DRAM_A_10 */
1175 IMX_PIN_REG(MX6Q_PAD_DRAM_A11, 0x0558, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A11__MMDC_DRAM_A_11 */
1176 IMX_PIN_REG(MX6Q_PAD_DRAM_A12, 0x055C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A12__MMDC_DRAM_A_12 */
1177 IMX_PIN_REG(MX6Q_PAD_DRAM_A13, 0x0560, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A13__MMDC_DRAM_A_13 */
1178 IMX_PIN_REG(MX6Q_PAD_DRAM_A14, 0x0564, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A14__MMDC_DRAM_A_14 */
1179 IMX_PIN_REG(MX6Q_PAD_DRAM_A15, 0x0568, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_A15__MMDC_DRAM_A_15 */
1180 IMX_PIN_REG(MX6Q_PAD_DRAM_CAS, 0x056C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CAS__MMDC_DRAM_CAS */
1181 IMX_PIN_REG(MX6Q_PAD_DRAM_CS0, 0x0570, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS0__MMDC_DRAM_CS_0 */
1182 IMX_PIN_REG(MX6Q_PAD_DRAM_CS1, 0x0574, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_CS1__MMDC_DRAM_CS_1 */
1183 IMX_PIN_REG(MX6Q_PAD_DRAM_RAS, 0x0578, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RAS__MMDC_DRAM_RAS */
1184 IMX_PIN_REG(MX6Q_PAD_DRAM_RESET, 0x057C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_RESET__MMDC_DRAM_RESET */
1185 IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA0, 0x0580, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 */
1186 IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA1, 0x0584, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 */
1187 IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_0, 0x0588, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 */
1188 IMX_PIN_REG(MX6Q_PAD_DRAM_SDBA2, 0x058C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 */
1189 IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE0, 0x0590, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 */
1190 IMX_PIN_REG(MX6Q_PAD_DRAM_SDCLK_1, 0x0594, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCLK_1__MMDC_DRAM_SDCLK1 */
1191 IMX_PIN_REG(MX6Q_PAD_DRAM_SDCKE1, 0x0598, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 */
1192 IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT0, 0x059C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 */
1193 IMX_PIN_REG(MX6Q_PAD_DRAM_SDODT1, 0x05A0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 */
1194 IMX_PIN_REG(MX6Q_PAD_DRAM_SDWE, 0x05A4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDWE__MMDC_DRAM_SDWE */
1195 IMX_PIN_REG(MX6Q_PAD_DRAM_D0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D0__MMDC_DRAM_D_0 */
1196 IMX_PIN_REG(MX6Q_PAD_DRAM_D1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D1__MMDC_DRAM_D_1 */
1197 IMX_PIN_REG(MX6Q_PAD_DRAM_D2, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D2__MMDC_DRAM_D_2 */
1198 IMX_PIN_REG(MX6Q_PAD_DRAM_D3, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D3__MMDC_DRAM_D_3 */
1199 IMX_PIN_REG(MX6Q_PAD_DRAM_D4, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D4__MMDC_DRAM_D_4 */
1200 IMX_PIN_REG(MX6Q_PAD_DRAM_D5, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D5__MMDC_DRAM_D_5 */
1201 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS0, 0x05A8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 */
1202 IMX_PIN_REG(MX6Q_PAD_DRAM_D6, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D6__MMDC_DRAM_D_6 */
1203 IMX_PIN_REG(MX6Q_PAD_DRAM_D7, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D7__MMDC_DRAM_D_7 */
1204 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM0, 0x05AC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 */
1205 IMX_PIN_REG(MX6Q_PAD_DRAM_D8, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D8__MMDC_DRAM_D_8 */
1206 IMX_PIN_REG(MX6Q_PAD_DRAM_D9, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D9__MMDC_DRAM_D_9 */
1207 IMX_PIN_REG(MX6Q_PAD_DRAM_D10, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D10__MMDC_DRAM_D_10 */
1208 IMX_PIN_REG(MX6Q_PAD_DRAM_D11, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D11__MMDC_DRAM_D_11 */
1209 IMX_PIN_REG(MX6Q_PAD_DRAM_D12, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D12__MMDC_DRAM_D_12 */
1210 IMX_PIN_REG(MX6Q_PAD_DRAM_D13, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D13__MMDC_DRAM_D_13 */
1211 IMX_PIN_REG(MX6Q_PAD_DRAM_D14, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D14__MMDC_DRAM_D_14 */
1212 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS1, 0x05B0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 */
1213 IMX_PIN_REG(MX6Q_PAD_DRAM_D15, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D15__MMDC_DRAM_D_15 */
1214 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM1, 0x05B4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 */
1215 IMX_PIN_REG(MX6Q_PAD_DRAM_D48, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D48__MMDC_DRAM_D_48 */
1216 IMX_PIN_REG(MX6Q_PAD_DRAM_D49, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D49__MMDC_DRAM_D_49 */
1217 IMX_PIN_REG(MX6Q_PAD_DRAM_D50, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D50__MMDC_DRAM_D_50 */
1218 IMX_PIN_REG(MX6Q_PAD_DRAM_D51, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D51__MMDC_DRAM_D_51 */
1219 IMX_PIN_REG(MX6Q_PAD_DRAM_D52, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D52__MMDC_DRAM_D_52 */
1220 IMX_PIN_REG(MX6Q_PAD_DRAM_D53, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D53__MMDC_DRAM_D_53 */
1221 IMX_PIN_REG(MX6Q_PAD_DRAM_D54, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D54__MMDC_DRAM_D_54 */
1222 IMX_PIN_REG(MX6Q_PAD_DRAM_D55, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D55__MMDC_DRAM_D_55 */
1223 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS6, 0x05B8, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS6__MMDC_DRAM_SDQS_6 */
1224 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM6, 0x05BC, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM6__MMDC_DRAM_DQM_6 */
1225 IMX_PIN_REG(MX6Q_PAD_DRAM_D56, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D56__MMDC_DRAM_D_56 */
1226 IMX_PIN_REG(MX6Q_PAD_DRAM_SDQS7, 0x05C0, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_SDQS7__MMDC_DRAM_SDQS_7 */
1227 IMX_PIN_REG(MX6Q_PAD_DRAM_D57, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D57__MMDC_DRAM_D_57 */
1228 IMX_PIN_REG(MX6Q_PAD_DRAM_D58, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D58__MMDC_DRAM_D_58 */
1229 IMX_PIN_REG(MX6Q_PAD_DRAM_D59, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D59__MMDC_DRAM_D_59 */
1230 IMX_PIN_REG(MX6Q_PAD_DRAM_D60, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D60__MMDC_DRAM_D_60 */
1231 IMX_PIN_REG(MX6Q_PAD_DRAM_DQM7, 0x05C4, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_DQM7__MMDC_DRAM_DQM_7 */
1232 IMX_PIN_REG(MX6Q_PAD_DRAM_D61, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D61__MMDC_DRAM_D_61 */
1233 IMX_PIN_REG(MX6Q_PAD_DRAM_D62, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D62__MMDC_DRAM_D_62 */
1234 IMX_PIN_REG(MX6Q_PAD_DRAM_D63, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_DRAM_D63__MMDC_DRAM_D_63 */
1235 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 0, 0x07F4, 2), /* MX6Q_PAD_KEY_COL0__ECSPI1_SCLK */
1236 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 1, 0x0854, 1), /* MX6Q_PAD_KEY_COL0__ENET_RDATA_3 */
1237 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 2, 0x07DC, 1), /* MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
1238 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__KPP_COL_0 */
1239 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__UART4_TXD */
1240 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__GPIO_4_6 */
1241 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT */
1242 IMX_PIN_REG(MX6Q_PAD_KEY_COL0, 0x05C8, 0x01F8, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST */
1243 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 0, 0x07FC, 2), /* MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI */
1244 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__ENET_TDATA_3 */
1245 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 2, 0x07D0, 1), /* MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
1246 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__KPP_ROW_0 */
1247 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 4, 0x0938, 1), /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
1248 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__GPIO_4_7 */
1249 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT */
1250 IMX_PIN_REG(MX6Q_PAD_KEY_ROW0, 0x05CC, 0x01FC, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW0__PL301_PER1_HADR_0 */
1251 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 0, 0x07F8, 2), /* MX6Q_PAD_KEY_COL1__ECSPI1_MISO */
1252 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 1, 0x0840, 1), /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
1253 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 2, 0x07E0, 1), /* MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
1254 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__KPP_COL_1 */
1255 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__UART5_TXD */
1256 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__GPIO_4_8 */
1257 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__USDHC1_VSELECT */
1258 IMX_PIN_REG(MX6Q_PAD_KEY_COL1, 0x05D0, 0x0200, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1 */
1259 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 0, 0x0800, 2), /* MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 */
1260 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__ENET_COL */
1261 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 2, 0x07CC, 1), /* MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
1262 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__KPP_ROW_1 */
1263 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 4, 0x0940, 1), /* MX6Q_PAD_KEY_ROW1__UART5_RXD */
1264 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__GPIO_4_9 */
1265 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT */
1266 IMX_PIN_REG(MX6Q_PAD_KEY_ROW1, 0x05D4, 0x0204, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW1__PL301_PER1_HADDR_2 */
1267 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 0, 0x0804, 2), /* MX6Q_PAD_KEY_COL2__ECSPI1_SS1 */
1268 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 1, 0x0850, 1), /* MX6Q_PAD_KEY_COL2__ENET_RDATA_2 */
1269 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 2, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__CAN1_TXCAN */
1270 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__KPP_COL_2 */
1271 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 4, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__ENET_MDC */
1272 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__GPIO_4_10 */
1273 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__USBOH3_H1_PWRCTL_WKP */
1274 IMX_PIN_REG(MX6Q_PAD_KEY_COL2, 0x05D8, 0x0208, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL2__PL301_PER1_HADDR_3 */
1275 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 0, 0x0808, 1), /* MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 */
1276 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__ENET_TDATA_2 */
1277 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 2, 0x07E4, 0), /* MX6Q_PAD_KEY_ROW2__CAN1_RXCAN */
1278 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__KPP_ROW_2 */
1279 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 4, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__USDHC2_VSELECT */
1280 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__GPIO_4_11 */
1281 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 6, 0x088C, 1), /* MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE */
1282 IMX_PIN_REG(MX6Q_PAD_KEY_ROW2, 0x05DC, 0x020C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW2__PL301_PER1_HADR_4 */
1283 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 0, 0x080C, 1), /* MX6Q_PAD_KEY_COL3__ECSPI1_SS3 */
1284 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__ENET_CRS */
1285 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 2, 0x0890, 1), /* MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL */
1286 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__KPP_COL_3 */
1287 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 4, 0x08A0, 1), /* MX6Q_PAD_KEY_COL3__I2C2_SCL */
1288 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__GPIO_4_12 */
1289 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 6, 0x0914, 2), /* MX6Q_PAD_KEY_COL3__SPDIF_IN1 */
1290 IMX_PIN_REG(MX6Q_PAD_KEY_COL3, 0x05E0, 0x0210, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL3__PL301_PER1_HADR_5 */
1291 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 0, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__OSC32K_32K_OUT */
1292 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 1, 0x07B0, 0), /* MX6Q_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK */
1293 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 2, 0x0894, 1), /* MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA */
1294 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__KPP_ROW_3 */
1295 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 4, 0x08A4, 1), /* MX6Q_PAD_KEY_ROW3__I2C2_SDA */
1296 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__GPIO_4_13 */
1297 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT */
1298 IMX_PIN_REG(MX6Q_PAD_KEY_ROW3, 0x05E4, 0x0214, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW3__PL301_PER1_HADR_6 */
1299 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 0, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__CAN2_TXCAN */
1300 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 1, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__IPU1_SISG_4 */
1301 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 2, 0x0944, 1), /* MX6Q_PAD_KEY_COL4__USBOH3_USBOTG_OC */
1302 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 3, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__KPP_COL_4 */
1303 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 4, 0x093C, 0), /* MX6Q_PAD_KEY_COL4__UART5_RTS */
1304 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 5, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__GPIO_4_14 */
1305 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 6, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__MMDC_DEBUG_49 */
1306 IMX_PIN_REG(MX6Q_PAD_KEY_COL4, 0x05E8, 0x0218, 7, 0x0000, 0), /* MX6Q_PAD_KEY_COL4__PL301_PER1_HADDR_7 */
1307 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 0, 0x07E8, 0), /* MX6Q_PAD_KEY_ROW4__CAN2_RXCAN */
1308 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 1, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__IPU1_SISG_5 */
1309 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 2, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__USBOH3_USBOTG_PWR */
1310 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 3, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__KPP_ROW_4 */
1311 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 4, 0x093C, 1), /* MX6Q_PAD_KEY_ROW4__UART5_CTS */
1312 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 5, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__GPIO_4_15 */
1313 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 6, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__MMDC_DEBUG_50 */
1314 IMX_PIN_REG(MX6Q_PAD_KEY_ROW4, 0x05EC, 0x021C, 7, 0x0000, 0), /* MX6Q_PAD_KEY_ROW4__PL301_PER1_HADR_8 */
1315 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 0, 0x0000, 0), /* MX6Q_PAD_GPIO_0__CCM_CLKO */
1316 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 2, 0x08E8, 0), /* MX6Q_PAD_GPIO_0__KPP_COL_5 */
1317 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 3, 0x07B0, 1), /* MX6Q_PAD_GPIO_0__ASRC_ASRC_EXT_CLK */
1318 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_0__EPIT1_EPITO */
1319 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_0__GPIO_1_0 */
1320 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_0__USBOH3_USBH1_PWR */
1321 IMX_PIN_REG(MX6Q_PAD_GPIO_0, 0x05F0, 0x0220, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_0__SNVS_HP_WRAP_SNVS_VIO5 */
1322 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 0, 0x086C, 1), /* MX6Q_PAD_GPIO_1__ESAI1_SCKR */
1323 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_1__WDOG2_WDOG_B */
1324 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 2, 0x08F4, 0), /* MX6Q_PAD_GPIO_1__KPP_ROW_5 */
1325 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_1__PWM2_PWMO */
1326 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_1__GPIO_1_1 */
1327 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_1__USDHC1_CD */
1328 IMX_PIN_REG(MX6Q_PAD_GPIO_1, 0x05F4, 0x0224, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_1__SRC_TESTER_ACK */
1329 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 0, 0x085C, 1), /* MX6Q_PAD_GPIO_9__ESAI1_FSR */
1330 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_9__WDOG1_WDOG_B */
1331 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 2, 0x08EC, 0), /* MX6Q_PAD_GPIO_9__KPP_COL_6 */
1332 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_9__CCM_REF_EN_B */
1333 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_9__PWM1_PWMO */
1334 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_9__GPIO_1_9 */
1335 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 6, 0x094C, 1), /* MX6Q_PAD_GPIO_9__USDHC1_WP */
1336 IMX_PIN_REG(MX6Q_PAD_GPIO_9, 0x05F8, 0x0228, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_9__SRC_EARLY_RST */
1337 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 0, 0x0864, 1), /* MX6Q_PAD_GPIO_3__ESAI1_HCKR */
1338 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_3__OBSERVE_MUX_INT_OUT0 */
1339 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 2, 0x08A8, 1), /* MX6Q_PAD_GPIO_3__I2C3_SCL */
1340 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_3__ANATOP_24M_OUT */
1341 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_3__CCM_CLKO2 */
1342 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_3__GPIO_1_3 */
1343 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 6, 0x0948, 1), /* MX6Q_PAD_GPIO_3__USBOH3_USBH1_OC */
1344 IMX_PIN_REG(MX6Q_PAD_GPIO_3, 0x05FC, 0x022C, 7, 0x0900, 1), /* MX6Q_PAD_GPIO_3__MLB_MLBCLK */
1345 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 0, 0x0870, 1), /* MX6Q_PAD_GPIO_6__ESAI1_SCKT */
1346 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_6__OBSERVE_MUX_INT_OUT1 */
1347 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 2, 0x08AC, 1), /* MX6Q_PAD_GPIO_6__I2C3_SDA */
1348 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 */
1349 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB */
1350 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_6__GPIO_1_6 */
1351 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_6__USDHC2_LCTL */
1352 IMX_PIN_REG(MX6Q_PAD_GPIO_6, 0x0600, 0x0230, 7, 0x0908, 1), /* MX6Q_PAD_GPIO_6__MLB_MLBSIG */
1353 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 0, 0x0860, 1), /* MX6Q_PAD_GPIO_2__ESAI1_FST */
1354 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_2__OBSERVE_MUX_INT_OUT2 */
1355 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 2, 0x08F8, 1), /* MX6Q_PAD_GPIO_2__KPP_ROW_6 */
1356 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CCM_CCM_OUT_1 */
1357 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 */
1358 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_2__GPIO_1_2 */
1359 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_2__USDHC2_WP */
1360 IMX_PIN_REG(MX6Q_PAD_GPIO_2, 0x0604, 0x0234, 7, 0x0904, 1), /* MX6Q_PAD_GPIO_2__MLB_MLBDAT */
1361 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 0, 0x0868, 1), /* MX6Q_PAD_GPIO_4__ESAI1_HCKT */
1362 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OBSERVE_MUX_INT_OUT3 */
1363 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 2, 0x08F0, 1), /* MX6Q_PAD_GPIO_4__KPP_COL_7 */
1364 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CCM_CCM_OUT_2 */
1365 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 */
1366 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_4__GPIO_1_4 */
1367 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_4__USDHC2_CD */
1368 IMX_PIN_REG(MX6Q_PAD_GPIO_4, 0x0608, 0x0238, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_4__OCOTP_CRL_WRAR_FUSE_LA */
1369 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 0, 0x087C, 1), /* MX6Q_PAD_GPIO_5__ESAI1_TX2_RX3 */
1370 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_5__OBSERVE_MUX_INT_OUT4 */
1371 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 2, 0x08FC, 1), /* MX6Q_PAD_GPIO_5__KPP_ROW_7 */
1372 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CCM_CLKO */
1373 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 */
1374 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_5__GPIO_1_5 */
1375 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 6, 0x08A8, 2), /* MX6Q_PAD_GPIO_5__I2C3_SCL */
1376 IMX_PIN_REG(MX6Q_PAD_GPIO_5, 0x060C, 0x023C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_5__CHEETAH_EVENTI */
1377 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 0, 0x0884, 1), /* MX6Q_PAD_GPIO_7__ESAI1_TX4_RX1 */
1378 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_7__ECSPI5_RDY */
1379 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_7__EPIT1_EPITO */
1380 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_7__CAN1_TXCAN */
1381 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_7__UART2_TXD */
1382 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_7__GPIO_1_7 */
1383 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_7__SPDIF_PLOCK */
1384 IMX_PIN_REG(MX6Q_PAD_GPIO_7, 0x0610, 0x0240, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE */
1385 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 0, 0x0888, 1), /* MX6Q_PAD_GPIO_8__ESAI1_TX5_RX0 */
1386 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT */
1387 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_8__EPIT2_EPITO */
1388 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 3, 0x07E4, 1), /* MX6Q_PAD_GPIO_8__CAN1_RXCAN */
1389 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 4, 0x0928, 3), /* MX6Q_PAD_GPIO_8__UART2_RXD */
1390 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_8__GPIO_1_8 */
1391 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_8__SPDIF_SRCLK */
1392 IMX_PIN_REG(MX6Q_PAD_GPIO_8, 0x0614, 0x0244, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_8__USBOH3_OTG_PWRCTL_WAK */
1393 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 0, 0x0880, 1), /* MX6Q_PAD_GPIO_16__ESAI1_TX3_RX2 */
1394 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN */
1395 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 2, 0x083C, 1), /* MX6Q_PAD_GPIO_16__ENET_ETHERNET_REF_OUT */
1396 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_16__USDHC1_LCTL */
1397 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 4, 0x0914, 3), /* MX6Q_PAD_GPIO_16__SPDIF_IN1 */
1398 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_16__GPIO_7_11 */
1399 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 6, 0x08AC, 2), /* MX6Q_PAD_GPIO_16__I2C3_SDA */
1400 IMX_PIN_REG(MX6Q_PAD_GPIO_16, 0x0618, 0x0248, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_16__SJC_DE_B */
1401 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 0, 0x0874, 0), /* MX6Q_PAD_GPIO_17__ESAI1_TX0 */
1402 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN */
1403 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 2, 0x07F0, 1), /* MX6Q_PAD_GPIO_17__CCM_PMIC_RDY */
1404 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 3, 0x090C, 1), /* MX6Q_PAD_GPIO_17__SDMA_SDMA_EXT_EVENT_0 */
1405 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SPDIF_OUT1 */
1406 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_17__GPIO_7_12 */
1407 IMX_PIN_REG(MX6Q_PAD_GPIO_17, 0x061C, 0x024C, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_17__SJC_JTAG_ACT */
1408 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 0, 0x0878, 0), /* MX6Q_PAD_GPIO_18__ESAI1_TX1 */
1409 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 1, 0x0844, 1), /* MX6Q_PAD_GPIO_18__ENET_RX_CLK */
1410 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_18__USDHC3_VSELECT */
1411 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 3, 0x0910, 1), /* MX6Q_PAD_GPIO_18__SDMA_SDMA_EXT_EVENT_1 */
1412 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 4, 0x07B0, 2), /* MX6Q_PAD_GPIO_18__ASRC_ASRC_EXT_CLK */
1413 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_18__GPIO_7_13 */
1414 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SNVS_HP_WRA_SNVS_VIO5 */
1415 IMX_PIN_REG(MX6Q_PAD_GPIO_18, 0x0620, 0x0250, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_18__SRC_SYSTEM_RST */
1416 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 0, 0x08E8, 1), /* MX6Q_PAD_GPIO_19__KPP_COL_5 */
1417 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 1, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT */
1418 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 2, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SPDIF_OUT1 */
1419 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 3, 0x0000, 0), /* MX6Q_PAD_GPIO_19__CCM_CLKO */
1420 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 4, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ECSPI1_RDY */
1421 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 5, 0x0000, 0), /* MX6Q_PAD_GPIO_19__GPIO_4_5 */
1422 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 6, 0x0000, 0), /* MX6Q_PAD_GPIO_19__ENET_TX_ER */
1423 IMX_PIN_REG(MX6Q_PAD_GPIO_19, 0x0624, 0x0254, 7, 0x0000, 0), /* MX6Q_PAD_GPIO_19__SRC_INT_BOOT */
1424 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK */
1425 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__PCIE_CTRL_MUX_12 */
1426 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 */
1427 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__GPIO_5_18 */
1428 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK___MMDC_DEBUG_29 */
1429 IMX_PIN_REG(MX6Q_PAD_CSI0_PIXCLK, 0x0628, 0x0258, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_PIXCLK__CHEETAH_EVENTO */
1430 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC */
1431 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__PCIE_CTRL_MUX_13 */
1432 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CCM_CLKO */
1433 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 */
1434 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__GPIO_5_19 */
1435 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__MMDC_MMDC_DEBUG_30 */
1436 IMX_PIN_REG(MX6Q_PAD_CSI0_MCLK, 0x062C, 0x025C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_MCLK__CHEETAH_TRCTL */
1437 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DA_EN */
1438 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__WEIM_WEIM_D_0 */
1439 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__PCIE_CTRL_MUX_14 */
1440 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 */
1441 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__GPIO_5_20 */
1442 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__MMDC_DEBUG_31 */
1443 IMX_PIN_REG(MX6Q_PAD_CSI0_DATA_EN, 0x0630, 0x0260, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DATA_EN__CHEETAH_TRCLK */
1444 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC */
1445 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__WEIM_WEIM_D_1 */
1446 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__PCIE_CTRL_MUX_15 */
1447 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 */
1448 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__GPIO_5_21 */
1449 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__MMDC_DEBUG_32 */
1450 IMX_PIN_REG(MX6Q_PAD_CSI0_VSYNC, 0x0634, 0x0264, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_VSYNC__CHEETAH_TRACE_0 */
1451 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_D_4 */
1452 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__WEIM_WEIM_D_2 */
1453 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 2, 0x07F4, 3), /* MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK */
1454 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 3, 0x08E8, 2), /* MX6Q_PAD_CSI0_DAT4__KPP_COL_5 */
1455 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC */
1456 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__GPIO_5_22 */
1457 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__MMDC_DEBUG_43 */
1458 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT4, 0x0638, 0x0268, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT4__CHEETAH_TRACE_1 */
1459 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_D_5 */
1460 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__WEIM_WEIM_D_3 */
1461 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 2, 0x07FC, 3), /* MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI */
1462 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 3, 0x08F4, 1), /* MX6Q_PAD_CSI0_DAT5__KPP_ROW_5 */
1463 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD */
1464 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__GPIO_5_23 */
1465 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__MMDC_MMDC_DEBUG_44 */
1466 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT5, 0x063C, 0x026C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT5__CHEETAH_TRACE_2 */
1467 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_D_6 */
1468 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__WEIM_WEIM_D_4 */
1469 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 2, 0x07F8, 3), /* MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO */
1470 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 3, 0x08EC, 1), /* MX6Q_PAD_CSI0_DAT6__KPP_COL_6 */
1471 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS */
1472 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__GPIO_5_24 */
1473 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__MMDC_MMDC_DEBUG_45 */
1474 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT6, 0x0640, 0x0270, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT6__CHEETAH_TRACE_3 */
1475 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_D_7 */
1476 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__WEIM_WEIM_D_5 */
1477 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 2, 0x0800, 3), /* MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 */
1478 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 3, 0x08F8, 2), /* MX6Q_PAD_CSI0_DAT7__KPP_ROW_6 */
1479 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD */
1480 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__GPIO_5_25 */
1481 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__MMDC_MMDC_DEBUG_46 */
1482 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT7, 0x0644, 0x0274, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT7__CHEETAH_TRACE_4 */
1483 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8 */
1484 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__WEIM_WEIM_D_6 */
1485 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 2, 0x0810, 2), /* MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK */
1486 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 3, 0x08F0, 2), /* MX6Q_PAD_CSI0_DAT8__KPP_COL_7 */
1487 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 4, 0x089C, 1), /* MX6Q_PAD_CSI0_DAT8__I2C1_SDA */
1488 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__GPIO_5_26 */
1489 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 */
1490 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT8, 0x0648, 0x0278, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT8__CHEETAH_TRACE_5 */
1491 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9 */
1492 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__WEIM_WEIM_D_7 */
1493 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 2, 0x0818, 2), /* MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI */
1494 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 3, 0x08FC, 2), /* MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 */
1495 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 4, 0x0898, 1), /* MX6Q_PAD_CSI0_DAT9__I2C1_SCL */
1496 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__GPIO_5_27 */
1497 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 */
1498 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT9, 0x064C, 0x027C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT9__CHEETAH_TRACE_6 */
1499 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10 */
1500 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC */
1501 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 2, 0x0814, 2), /* MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO */
1502 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
1503 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 */
1504 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__GPIO_5_28 */
1505 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33 */
1506 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT10, 0x0650, 0x0280, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT10__CHEETAH_TRACE_7 */
1507 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11 */
1508 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS */
1509 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 2, 0x081C, 2), /* MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 */
1510 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 3, 0x0920, 1), /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
1511 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 */
1512 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__GPIO_5_29 */
1513 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__MMDC_MMDC_DEBUG_34 */
1514 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT11, 0x0654, 0x0284, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT11__CHEETAH_TRACE_8 */
1515 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12 */
1516 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8 */
1517 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16 */
1518 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__UART4_TXD */
1519 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 */
1520 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__GPIO_5_30 */
1521 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35 */
1522 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT12, 0x0658, 0x0288, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT12__CHEETAH_TRACE_9 */
1523 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13 */
1524 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9 */
1525 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17 */
1526 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 3, 0x0938, 3), /* MX6Q_PAD_CSI0_DAT13__UART4_RXD */
1527 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 */
1528 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__GPIO_5_31 */
1529 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__MMDC_MMDC_DEBUG_36 */
1530 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT13, 0x065C, 0x028C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT13__CHEETAH_TRACE_10 */
1531 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14 */
1532 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10 */
1533 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18 */
1534 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 3, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__UART5_TXD */
1535 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 */
1536 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__GPIO_6_0 */
1537 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37 */
1538 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT14, 0x0660, 0x0290, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT14__CHEETAH_TRACE_11 */
1539 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15 */
1540 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11 */
1541 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19 */
1542 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 3, 0x0940, 3), /* MX6Q_PAD_CSI0_DAT15__UART5_RXD */
1543 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 */
1544 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__GPIO_6_1 */
1545 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__MMDC_MMDC_DEBUG_38 */
1546 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT15, 0x0664, 0x0294, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT15__CHEETAH_TRACE_12 */
1547 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16 */
1548 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__WEIM_WEIM_D_12 */
1549 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__PCIE_CTRL_MUX_20 */
1550 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 3, 0x0934, 0), /* MX6Q_PAD_CSI0_DAT16__UART4_RTS */
1551 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 */
1552 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__GPIO_6_2 */
1553 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__MMDC_MMDC_DEBUG_39 */
1554 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT16, 0x0668, 0x0298, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT16__CHEETAH_TRACE_13 */
1555 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17 */
1556 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__WEIM_WEIM_D_13 */
1557 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__PCIE_CTRL_MUX_21 */
1558 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 3, 0x0934, 1), /* MX6Q_PAD_CSI0_DAT17__UART4_CTS */
1559 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 */
1560 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__GPIO_6_3 */
1561 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__MMDC_MMDC_DEBUG_40 */
1562 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT17, 0x066C, 0x029C, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT17__CHEETAH_TRACE_14 */
1563 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18 */
1564 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__WEIM_WEIM_D_14 */
1565 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__PCIE_CTRL_MUX_22 */
1566 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 3, 0x093C, 2), /* MX6Q_PAD_CSI0_DAT18__UART5_RTS */
1567 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 */
1568 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__GPIO_6_4 */
1569 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__MMDC_MMDC_DEBUG_41 */
1570 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT18, 0x0670, 0x02A0, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT18__CHEETAH_TRACE_15 */
1571 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 0, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19 */
1572 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 1, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__WEIM_WEIM_D_15 */
1573 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 2, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__PCIE_CTRL_MUX_23 */
1574 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 3, 0x093C, 3), /* MX6Q_PAD_CSI0_DAT19__UART5_CTS */
1575 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 4, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 */
1576 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 5, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__GPIO_6_5 */
1577 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 6, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__MMDC_MMDC_DEBUG_42 */
1578 IMX_PIN_REG(MX6Q_PAD_CSI0_DAT19, 0x0674, 0x02A4, 7, 0x0000, 0), /* MX6Q_PAD_CSI0_DAT19__ANATOP_TESTO_9 */
1579 IMX_PIN_REG(MX6Q_PAD_JTAG_TMS, 0x0678, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TMS__SJC_TMS */
1580 IMX_PIN_REG(MX6Q_PAD_JTAG_MOD, 0x067C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_MOD__SJC_MOD */
1581 IMX_PIN_REG(MX6Q_PAD_JTAG_TRSTB, 0x0680, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TRSTB__SJC_TRSTB */
1582 IMX_PIN_REG(MX6Q_PAD_JTAG_TDI, 0x0684, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDI__SJC_TDI */
1583 IMX_PIN_REG(MX6Q_PAD_JTAG_TCK, 0x0688, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TCK__SJC_TCK */
1584 IMX_PIN_REG(MX6Q_PAD_JTAG_TDO, 0x068C, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_JTAG_TDO__SJC_TDO */
1585 IMX_PIN_REG(MX6Q_PAD_LVDS1_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 */
1586 IMX_PIN_REG(MX6Q_PAD_LVDS1_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 */
1587 IMX_PIN_REG(MX6Q_PAD_LVDS1_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK */
1588 IMX_PIN_REG(MX6Q_PAD_LVDS1_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 */
1589 IMX_PIN_REG(MX6Q_PAD_LVDS1_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 */
1590 IMX_PIN_REG(MX6Q_PAD_LVDS0_TX3_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 */
1591 IMX_PIN_REG(MX6Q_PAD_LVDS0_CLK_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK */
1592 IMX_PIN_REG(MX6Q_PAD_LVDS0_TX2_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 */
1593 IMX_PIN_REG(MX6Q_PAD_LVDS0_TX1_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 */
1594 IMX_PIN_REG(MX6Q_PAD_LVDS0_TX0_P, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 */
1595 IMX_PIN_REG(MX6Q_PAD_TAMPER, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TAMPER__SNVS_LP_WRAP_SNVS_TD1 */
1596 IMX_PIN_REG(MX6Q_PAD_PMIC_ON_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_ON_REQ__SNVS_LPWRAP_WKALM */
1597 IMX_PIN_REG(MX6Q_PAD_PMIC_STBY_REQ, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_PMIC_STBY_REQ__CCM_PMIC_STBYRQ */
1598 IMX_PIN_REG(MX6Q_PAD_POR_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_POR_B__SRC_POR_B */
1599 IMX_PIN_REG(MX6Q_PAD_BOOT_MODE1, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 */
1600 IMX_PIN_REG(MX6Q_PAD_RESET_IN_B, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_RESET_IN_B__SRC_RESET_B */
1601 IMX_PIN_REG(MX6Q_PAD_BOOT_MODE0, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 */
1602 IMX_PIN_REG(MX6Q_PAD_TEST_MODE, NO_PAD, NO_MUX, 0, 0x0000, 0), /* MX6Q_PAD_TEST_MODE__TCU_TEST_MODE */
1603 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
1604 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__UART1_TXD */
1605 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24 */
1606 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0 */
1607 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0 */
1608 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__GPIO_6_17 */
1609 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12 */
1610 IMX_PIN_REG(MX6Q_PAD_SD3_DAT7, 0x0690, 0x02A8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV */
1611 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
1612 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 1, 0x0920, 3), /* MX6Q_PAD_SD3_DAT6__UART1_RXD */
1613 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25 */
1614 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 */
1615 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__USBOH3_UH2_DFD_OUT_1 */
1616 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__GPIO_6_18 */
1617 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__MIPI_CORE_DPHY_IN_13 */
1618 IMX_PIN_REG(MX6Q_PAD_SD3_DAT6, 0x0694, 0x02AC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10 */
1619 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
1620 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 1, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__UART2_TXD */
1621 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26 */
1622 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2 */
1623 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2 */
1624 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
1625 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14 */
1626 IMX_PIN_REG(MX6Q_PAD_SD3_DAT5, 0x0698, 0x02B0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11 */
1627 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
1628 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 1, 0x0928, 5), /* MX6Q_PAD_SD3_DAT4__UART2_RXD */
1629 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27 */
1630 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3 */
1631 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__USBOH3_UH2_DFD_OUT_3 */
1632 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
1633 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__MIPI_CORE_DPHY_IN_15 */
1634 IMX_PIN_REG(MX6Q_PAD_SD3_DAT4, 0x069C, 0x02B4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT4__ANATOP_TESTO_12 */
1635 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
1636 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 1, 0x0924, 2), /* MX6Q_PAD_SD3_CMD__UART2_CTS */
1637 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__CAN1_TXCAN */
1638 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH3_DFD_OUT_4 */
1639 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__USBOH3_UH2_DFD_OUT_4 */
1640 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__GPIO_7_2 */
1641 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__MIPI_CORE_DPHY_IN_16 */
1642 IMX_PIN_REG(MX6Q_PAD_SD3_CMD, 0x06A0, 0x02B8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CMD__ANATOP_TESTO_13 */
1643 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
1644 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 1, 0x0924, 3), /* MX6Q_PAD_SD3_CLK__UART2_RTS */
1645 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 2, 0x07E4, 2), /* MX6Q_PAD_SD3_CLK__CAN1_RXCAN */
1646 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH3_DFD_OUT_5 */
1647 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__USBOH3_UH2_DFD_OUT_5 */
1648 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__GPIO_7_3 */
1649 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__MIPI_CORE_DPHY_IN_17 */
1650 IMX_PIN_REG(MX6Q_PAD_SD3_CLK, 0x06A4, 0x02BC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_CLK__ANATOP_TESTO_14 */
1651 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
1652 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 1, 0x091C, 2), /* MX6Q_PAD_SD3_DAT0__UART1_CTS */
1653 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__CAN2_TXCAN */
1654 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH3_DFD_OUT_6 */
1655 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__USBOH3_UH2_DFD_OUT_6 */
1656 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__GPIO_7_4 */
1657 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__MIPI_CORE_DPHY_IN_18 */
1658 IMX_PIN_REG(MX6Q_PAD_SD3_DAT0, 0x06A8, 0x02C0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT0__ANATOP_TESTO_15 */
1659 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
1660 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 1, 0x091C, 3), /* MX6Q_PAD_SD3_DAT1__UART1_RTS */
1661 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 2, 0x07E8, 1), /* MX6Q_PAD_SD3_DAT1__CAN2_RXCAN */
1662 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH3_DFD_OUT_7 */
1663 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__USBOH3_UH2_DFD_OUT_7 */
1664 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__GPIO_7_5 */
1665 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__MIPI_CORE_DPHY_IN_19 */
1666 IMX_PIN_REG(MX6Q_PAD_SD3_DAT1, 0x06AC, 0x02C4, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT1__ANATOP_TESTI_0 */
1667 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
1668 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__PCIE_CTRL_MUX_28 */
1669 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH3_DFD_OUT_8 */
1670 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__USBOH3_UH2_DFD_OUT_8 */
1671 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__GPIO_7_6 */
1672 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__MIPI_CORE_DPHY_IN_20 */
1673 IMX_PIN_REG(MX6Q_PAD_SD3_DAT2, 0x06B0, 0x02C8, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT2__ANATOP_TESTI_1 */
1674 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 0, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
1675 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 1, 0x092C, 4), /* MX6Q_PAD_SD3_DAT3__UART3_CTS */
1676 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 2, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__PCIE_CTRL_MUX_29 */
1677 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 3, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH3_DFD_OUT_9 */
1678 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 4, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__USBOH3_UH2_DFD_OUT_9 */
1679 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 5, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__GPIO_7_7 */
1680 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 6, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__MIPI_CORE_DPHY_IN_21 */
1681 IMX_PIN_REG(MX6Q_PAD_SD3_DAT3, 0x06B4, 0x02CC, 7, 0x0000, 0), /* MX6Q_PAD_SD3_DAT3__ANATOP_TESTI_2 */
1682 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 0, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USDHC3_RST */
1683 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 1, 0x092C, 5), /* MX6Q_PAD_SD3_RST__UART3_RTS */
1684 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 2, 0x0000, 0), /* MX6Q_PAD_SD3_RST__PCIE_CTRL_MUX_30 */
1685 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 3, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH3_DFD_OUT_10 */
1686 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 4, 0x0000, 0), /* MX6Q_PAD_SD3_RST__USBOH3_UH2_DFD_OUT_10 */
1687 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 5, 0x0000, 0), /* MX6Q_PAD_SD3_RST__GPIO_7_8 */
1688 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 6, 0x0000, 0), /* MX6Q_PAD_SD3_RST__MIPI_CORE_DPHY_IN_22 */
1689 IMX_PIN_REG(MX6Q_PAD_SD3_RST, 0x06B8, 0x02D0, 7, 0x0000, 0), /* MX6Q_PAD_SD3_RST__ANATOP_ANATOP_TESTI_3 */
1690 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
1691 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__IPU2_SISG_4 */
1692 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__PCIE_CTRL_MUX_31 */
1693 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH3_DFD_OT11 */
1694 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__USBOH3_UH2_DFD_OT11 */
1695 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__GPIO_6_7 */
1696 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__MIPI_CORE_DPHY_IN23 */
1697 IMX_PIN_REG(MX6Q_PAD_NANDF_CLE, 0x06BC, 0x02D4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CLE__TPSMP_HTRANS_0 */
1698 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
1699 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USDHC4_RST */
1700 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__PCIE_CTRL_MUX_0 */
1701 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH3_DFD_OT12 */
1702 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__USBOH3_UH2_DFD_OT12 */
1703 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__GPIO_6_8 */
1704 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__MIPI_CR_DPHY_IN_24 */
1705 IMX_PIN_REG(MX6Q_PAD_NANDF_ALE, 0x06C0, 0x02D8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_ALE__TPSMP_HTRANS_1 */
1706 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
1707 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__IPU2_SISG_5 */
1708 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PCIE_CTRL__MUX_1 */
1709 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH3_DFDOT13 */
1710 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__USBOH3_UH2_DFDOT13 */
1711 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__GPIO_6_9 */
1712 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__MIPI_CR_DPHY_OUT32 */
1713 IMX_PIN_REG(MX6Q_PAD_NANDF_WP_B, 0x06C4, 0x02DC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_WP_B__PL301_PER1_HSIZE_0 */
1714 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
1715 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN1 */
1716 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PCIE_CTRL_MUX_2 */
1717 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH3_DFD_OT14 */
1718 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__USBOH3_UH2_DFD_OT14 */
1719 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__GPIO_6_10 */
1720 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__MIPI_CR_DPHY_OUT_33 */
1721 IMX_PIN_REG(MX6Q_PAD_NANDF_RB0, 0x06C8, 0x02E0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_RB0__PL301_PER1_HSIZE_1 */
1722 IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
1723 IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH3_DFD_OT15 */
1724 IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__USBOH3_UH2_DFD_OT15 */
1725 IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
1726 IMX_PIN_REG(MX6Q_PAD_NANDF_CS0, 0x06CC, 0x02E4, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS0__PL301_PER1_HSIZE_2 */
1727 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
1728 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC4_VSELECT */
1729 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__USDHC3_VSELECT */
1730 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PCIE_CTRL_MUX_3 */
1731 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
1732 IMX_PIN_REG(MX6Q_PAD_NANDF_CS1, 0x06D0, 0x02E8, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS1__PL301_PER1_HRDYOUT */
1733 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
1734 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU1_SISG_0 */
1735 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 2, 0x0874, 1), /* MX6Q_PAD_NANDF_CS2__ESAI1_TX0 */
1736 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__WEIM_WEIM_CRE */
1737 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__CCM_CLKO2 */
1738 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__GPIO_6_15 */
1739 IMX_PIN_REG(MX6Q_PAD_NANDF_CS2, 0x06D4, 0x02EC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS2__IPU2_SISG_0 */
1740 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
1741 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU1_SISG_1 */
1742 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 2, 0x0878, 1), /* MX6Q_PAD_NANDF_CS3__ESAI1_TX1 */
1743 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__WEIM_WEIM_A_26 */
1744 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__PCIE_CTRL_MUX_4 */
1745 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__GPIO_6_16 */
1746 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__IPU2_SISG_1 */
1747 IMX_PIN_REG(MX6Q_PAD_NANDF_CS3, 0x06D8, 0x02F0, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_CS3__TPSMP_CLK */
1748 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
1749 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
1750 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 2, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__UART3_TXD */
1751 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5 */
1752 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__GPIO_7_9 */
1753 IMX_PIN_REG(MX6Q_PAD_SD4_CMD, 0x06DC, 0x02F4, 7, 0x0000, 0), /* MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR */
1754 IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 0, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
1755 IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 1, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
1756 IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 2, 0x0930, 3), /* MX6Q_PAD_SD4_CLK__UART3_RXD */
1757 IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 4, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6 */
1758 IMX_PIN_REG(MX6Q_PAD_SD4_CLK, 0x06E0, 0x02F8, 5, 0x0000, 0), /* MX6Q_PAD_SD4_CLK__GPIO_7_10 */
1759 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
1760 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USDHC1_DAT4 */
1761 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPU3D_GPU_DBG_OUT_0 */
1762 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH2_DFD_OUT16 */
1763 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__USBOH3_UH3_DFD_OUT16 */
1764 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
1765 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU1_IPU_DIAG_BUS_0 */
1766 IMX_PIN_REG(MX6Q_PAD_NANDF_D0, 0x06E4, 0x02FC, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D0__IPU2_IPU_DIAG_BUS_0 */
1767 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
1768 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USDHC1_DAT5 */
1769 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPU3D_GPU_DEBUG_OUT1 */
1770 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH2_DFD_OUT17 */
1771 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__USBOH3_UH3_DFD_OUT17 */
1772 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
1773 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU1_IPU_DIAG_BUS_1 */
1774 IMX_PIN_REG(MX6Q_PAD_NANDF_D1, 0x06E8, 0x0300, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D1__IPU2_IPU_DIAG_BUS_1 */
1775 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
1776 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USDHC1_DAT6 */
1777 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPU3D_GPU_DBG_OUT_2 */
1778 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH2_DFD_OUT18 */
1779 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__USBOH3_UH3_DFD_OUT18 */
1780 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
1781 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU1_IPU_DIAG_BUS_2 */
1782 IMX_PIN_REG(MX6Q_PAD_NANDF_D2, 0x06EC, 0x0304, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D2__IPU2_IPU_DIAG_BUS_2 */
1783 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
1784 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USDHC1_DAT7 */
1785 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPU3D_GPU_DBG_OUT_3 */
1786 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH2_DFD_OUT19 */
1787 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__USBOH3_UH3_DFD_OUT19 */
1788 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
1789 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU1_IPU_DIAG_BUS_3 */
1790 IMX_PIN_REG(MX6Q_PAD_NANDF_D3, 0x06F0, 0x0308, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D3__IPU2_IPU_DIAG_BUS_3 */
1791 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
1792 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
1793 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPU3D_GPU_DBG_OUT_4 */
1794 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH2_DFD_OUT20 */
1795 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__USBOH3_UH3_DFD_OUT20 */
1796 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__GPIO_2_4 */
1797 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU1_IPU_DIAG_BUS_4 */
1798 IMX_PIN_REG(MX6Q_PAD_NANDF_D4, 0x06F4, 0x030C, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D4__IPU2_IPU_DIAG_BUS_4 */
1799 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
1800 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
1801 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPU3D_GPU_DBG_OUT_5 */
1802 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH2_DFD_OUT21 */
1803 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__USBOH3_UH3_DFD_OUT21 */
1804 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__GPIO_2_5 */
1805 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU1_IPU_DIAG_BUS_5 */
1806 IMX_PIN_REG(MX6Q_PAD_NANDF_D5, 0x06F8, 0x0310, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D5__IPU2_IPU_DIAG_BUS_5 */
1807 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
1808 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
1809 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPU3D_GPU_DBG_OUT_6 */
1810 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH2_DFD_OUT22 */
1811 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__USBOH3_UH3_DFD_OUT22 */
1812 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
1813 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU1_IPU_DIAG_BUS_6 */
1814 IMX_PIN_REG(MX6Q_PAD_NANDF_D6, 0x06FC, 0x0314, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D6__IPU2_IPU_DIAG_BUS_6 */
1815 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 0, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
1816 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 1, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
1817 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 2, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPU3D_GPU_DBG_OUT_7 */
1818 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 3, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH2_DFD_OUT23 */
1819 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 4, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__USBOH3_UH3_DFD_OUT23 */
1820 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 5, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
1821 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 6, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU1_IPU_DIAG_BUS_7 */
1822 IMX_PIN_REG(MX6Q_PAD_NANDF_D7, 0x0700, 0x0318, 7, 0x0000, 0), /* MX6Q_PAD_NANDF_D7__IPU2_IPU_DIAG_BUS_7 */
1823 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_D8 */
1824 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
1825 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
1826 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH2_DFD_OUT24 */
1827 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__USBOH3_UH3_DFD_OUT24 */
1828 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__GPIO_2_8 */
1829 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU1_IPU_DIAG_BUS_8 */
1830 IMX_PIN_REG(MX6Q_PAD_SD4_DAT0, 0x0704, 0x031C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT0__IPU2_IPU_DIAG_BUS_8 */
1831 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__RAWNAND_D9 */
1832 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
1833 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__PWM3_PWMO */
1834 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH2_DFD_OUT25 */
1835 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__USBOH3_UH3_DFD_OUT25 */
1836 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__GPIO_2_9 */
1837 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU1_IPU_DIAG_BUS_9 */
1838 IMX_PIN_REG(MX6Q_PAD_SD4_DAT1, 0x0708, 0x0320, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT1__IPU2_IPU_DIAG_BUS_9 */
1839 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__RAWNAND_D10 */
1840 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
1841 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__PWM4_PWMO */
1842 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH2_DFD_OUT26 */
1843 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__USBOH3_UH3_DFD_OUT26 */
1844 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__GPIO_2_10 */
1845 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU1_IPU_DIAG_BUS_10 */
1846 IMX_PIN_REG(MX6Q_PAD_SD4_DAT2, 0x070C, 0x0324, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT2__IPU2_IPU_DIAG_BUS_10 */
1847 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__RAWNAND_D11 */
1848 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
1849 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH2_DFD_OUT27 */
1850 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__USBOH3_UH3_DFD_OUT27 */
1851 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__GPIO_2_11 */
1852 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU1_IPU_DIAG_BUS_11 */
1853 IMX_PIN_REG(MX6Q_PAD_SD4_DAT3, 0x0710, 0x0328, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11 */
1854 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__RAWNAND_D12 */
1855 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
1856 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 2, 0x0928, 6), /* MX6Q_PAD_SD4_DAT4__UART2_RXD */
1857 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28 */
1858 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28 */
1859 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__GPIO_2_12 */
1860 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU1_IPU_DIAG_BUS_12 */
1861 IMX_PIN_REG(MX6Q_PAD_SD4_DAT4, 0x0714, 0x032C, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT4__IPU2_IPU_DIAG_BUS_12 */
1862 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__RAWNAND_D13 */
1863 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
1864 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 2, 0x0924, 4), /* MX6Q_PAD_SD4_DAT5__UART2_RTS */
1865 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH2_DFD_OUT29 */
1866 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__USBOH3_UH3_DFD_OUT29 */
1867 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__GPIO_2_13 */
1868 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU1_IPU_DIAG_BUS_13 */
1869 IMX_PIN_REG(MX6Q_PAD_SD4_DAT5, 0x0718, 0x0330, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT5__IPU2_IPU_DIAG_BUS_13 */
1870 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__RAWNAND_D14 */
1871 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
1872 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 2, 0x0924, 5), /* MX6Q_PAD_SD4_DAT6__UART2_CTS */
1873 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH2_DFD_OUT30 */
1874 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__USBOH3_UH3_DFD_OUT30 */
1875 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__GPIO_2_14 */
1876 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU1_IPU_DIAG_BUS_14 */
1877 IMX_PIN_REG(MX6Q_PAD_SD4_DAT6, 0x071C, 0x0334, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT6__IPU2_IPU_DIAG_BUS_14 */
1878 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 0, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__RAWNAND_D15 */
1879 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 1, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
1880 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 2, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__UART2_TXD */
1881 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 3, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 */
1882 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 4, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 */
1883 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 5, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__GPIO_2_15 */
1884 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 6, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU1_IPU_DIAG_BUS_15 */
1885 IMX_PIN_REG(MX6Q_PAD_SD4_DAT7, 0x0720, 0x0338, 7, 0x0000, 0), /* MX6Q_PAD_SD4_DAT7__IPU2_IPU_DIAG_BUS_15 */
1886 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 */
1887 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 1, 0x0834, 1), /* MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 */
1888 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PWM3_PWMO */
1889 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPT_CAPIN2 */
1890 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__PCIE_CTRL_MUX_7 */
1891 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__GPIO_1_17 */
1892 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0 */
1893 IMX_PIN_REG(MX6Q_PAD_SD1_DAT1, 0x0724, 0x033C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT1__ANATOP_TESTO_8 */
1894 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 */
1895 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 1, 0x082C, 1), /* MX6Q_PAD_SD1_DAT0__ECSPI5_MISO */
1896 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__CAAM_WRAP_RNG_OSCOBS */
1897 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPT_CAPIN1 */
1898 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__PCIE_CTRL_MUX_8 */
1899 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__GPIO_1_16 */
1900 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1 */
1901 IMX_PIN_REG(MX6Q_PAD_SD1_DAT0, 0x0728, 0x0340, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT0__ANATOP_TESTO_7 */
1902 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 */
1903 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 1, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 */
1904 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3 */
1905 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__PWM1_PWMO */
1906 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_B */
1907 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__GPIO_1_21 */
1908 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__WDOG2_WDOG_RST_B_DEB */
1909 IMX_PIN_REG(MX6Q_PAD_SD1_DAT3, 0x072C, 0x0344, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT3__ANATOP_TESTO_6 */
1910 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__USDHC1_CMD */
1911 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 1, 0x0830, 0), /* MX6Q_PAD_SD1_CMD__ECSPI5_MOSI */
1912 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__PWM4_PWMO */
1913 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPT_CMPOUT1 */
1914 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__GPIO_1_18 */
1915 IMX_PIN_REG(MX6Q_PAD_SD1_CMD, 0x0730, 0x0348, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CMD__ANATOP_TESTO_5 */
1916 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 0, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 */
1917 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 1, 0x0838, 1), /* MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 */
1918 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 2, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2 */
1919 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 3, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__PWM2_PWMO */
1920 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 4, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_B */
1921 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 5, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__GPIO_1_19 */
1922 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 6, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__WDOG1_WDOG_RST_B_DEB */
1923 IMX_PIN_REG(MX6Q_PAD_SD1_DAT2, 0x0734, 0x034C, 7, 0x0000, 0), /* MX6Q_PAD_SD1_DAT2__ANATOP_TESTO_4 */
1924 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 0, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__USDHC1_CLK */
1925 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 1, 0x0828, 0), /* MX6Q_PAD_SD1_CLK__ECSPI5_SCLK */
1926 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 2, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT */
1927 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 3, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPT_CLKIN */
1928 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 5, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__GPIO_1_20 */
1929 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 6, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__PHY_DTB_0 */
1930 IMX_PIN_REG(MX6Q_PAD_SD1_CLK, 0x0738, 0x0350, 7, 0x0000, 0), /* MX6Q_PAD_SD1_CLK__SATA_PHY_DTB_0 */
1931 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
1932 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 1, 0x0828, 1), /* MX6Q_PAD_SD2_CLK__ECSPI5_SCLK */
1933 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 2, 0x08E8, 3), /* MX6Q_PAD_SD2_CLK__KPP_COL_5 */
1934 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 3, 0x07C0, 1), /* MX6Q_PAD_SD2_CLK__AUDMUX_AUD4_RXFS */
1935 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PCIE_CTRL_MUX_9 */
1936 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__GPIO_1_10 */
1937 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 6, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__PHY_DTB_1 */
1938 IMX_PIN_REG(MX6Q_PAD_SD2_CLK, 0x073C, 0x0354, 7, 0x0000, 0), /* MX6Q_PAD_SD2_CLK__SATA_PHY_DTB_1 */
1939 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 0, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
1940 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 1, 0x0830, 1), /* MX6Q_PAD_SD2_CMD__ECSPI5_MOSI */
1941 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 2, 0x08F4, 2), /* MX6Q_PAD_SD2_CMD__KPP_ROW_5 */
1942 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 3, 0x07BC, 1), /* MX6Q_PAD_SD2_CMD__AUDMUX_AUD4_RXC */
1943 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 4, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__PCIE_CTRL_MUX_10 */
1944 IMX_PIN_REG(MX6Q_PAD_SD2_CMD, 0x0740, 0x0358, 5, 0x0000, 0), /* MX6Q_PAD_SD2_CMD__GPIO_1_11 */
1945 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 0, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
1946 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 1, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 */
1947 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 2, 0x08EC, 2), /* MX6Q_PAD_SD2_DAT3__KPP_COL_6 */
1948 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 3, 0x07C4, 1), /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
1949 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 4, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__PCIE_CTRL_MUX_11 */
1950 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 5, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__GPIO_1_12 */
1951 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 6, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__SJC_DONE */
1952 IMX_PIN_REG(MX6Q_PAD_SD2_DAT3, 0x0744, 0x035C, 7, 0x0000, 0), /* MX6Q_PAD_SD2_DAT3__ANATOP_TESTO_3 */
1953};
1954
1955/* Pad names for the pinmux subsystem */
1956static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = {
1957 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT1),
1958 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT2),
1959 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT0),
1960 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TXC),
1961 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD0),
1962 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD1),
1963 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD2),
1964 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TD3),
1965 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RX_CTL),
1966 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD0),
1967 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_TX_CTL),
1968 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD1),
1969 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD2),
1970 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RD3),
1971 IMX_PINCTRL_PIN(MX6Q_PAD_RGMII_RXC),
1972 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A25),
1973 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB2),
1974 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D16),
1975 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D17),
1976 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D18),
1977 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D19),
1978 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D20),
1979 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D21),
1980 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D22),
1981 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D23),
1982 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB3),
1983 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D24),
1984 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D25),
1985 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D26),
1986 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D27),
1987 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D28),
1988 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D29),
1989 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D30),
1990 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_D31),
1991 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A24),
1992 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A23),
1993 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A22),
1994 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A21),
1995 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A20),
1996 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A19),
1997 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A18),
1998 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A17),
1999 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_A16),
2000 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS0),
2001 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_CS1),
2002 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_OE),
2003 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_RW),
2004 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_LBA),
2005 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB0),
2006 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_EB1),
2007 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA0),
2008 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA1),
2009 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA2),
2010 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA3),
2011 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA4),
2012 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA5),
2013 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA6),
2014 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA7),
2015 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA8),
2016 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA9),
2017 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA10),
2018 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA11),
2019 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA12),
2020 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA13),
2021 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA14),
2022 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_DA15),
2023 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_WAIT),
2024 IMX_PINCTRL_PIN(MX6Q_PAD_EIM_BCLK),
2025 IMX_PINCTRL_PIN(MX6Q_PAD_DI0_DISP_CLK),
2026 IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN15),
2027 IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN2),
2028 IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN3),
2029 IMX_PINCTRL_PIN(MX6Q_PAD_DI0_PIN4),
2030 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT0),
2031 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT1),
2032 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT2),
2033 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT3),
2034 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT4),
2035 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT5),
2036 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT6),
2037 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT7),
2038 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT8),
2039 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT9),
2040 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT10),
2041 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT11),
2042 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT12),
2043 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT13),
2044 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT14),
2045 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT15),
2046 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT16),
2047 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT17),
2048 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT18),
2049 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT19),
2050 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT20),
2051 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT21),
2052 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT22),
2053 IMX_PINCTRL_PIN(MX6Q_PAD_DISP0_DAT23),
2054 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDIO),
2055 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_REF_CLK),
2056 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RX_ER),
2057 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_CRS_DV),
2058 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD1),
2059 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_RXD0),
2060 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TX_EN),
2061 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD1),
2062 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_TXD0),
2063 IMX_PINCTRL_PIN(MX6Q_PAD_ENET_MDC),
2064 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D40),
2065 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D41),
2066 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D42),
2067 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D43),
2068 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D44),
2069 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D45),
2070 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D46),
2071 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D47),
2072 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS5),
2073 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM5),
2074 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D32),
2075 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D33),
2076 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D34),
2077 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D35),
2078 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D36),
2079 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D37),
2080 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D38),
2081 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D39),
2082 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM4),
2083 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS4),
2084 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D24),
2085 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D25),
2086 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D26),
2087 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D27),
2088 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D28),
2089 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D29),
2090 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS3),
2091 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D30),
2092 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D31),
2093 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM3),
2094 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D16),
2095 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D17),
2096 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D18),
2097 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D19),
2098 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D20),
2099 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D21),
2100 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D22),
2101 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS2),
2102 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D23),
2103 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM2),
2104 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A0),
2105 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A1),
2106 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A2),
2107 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A3),
2108 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A4),
2109 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A5),
2110 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A6),
2111 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A7),
2112 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A8),
2113 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A9),
2114 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A10),
2115 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A11),
2116 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A12),
2117 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A13),
2118 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A14),
2119 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_A15),
2120 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CAS),
2121 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS0),
2122 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_CS1),
2123 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RAS),
2124 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_RESET),
2125 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA0),
2126 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA1),
2127 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_0),
2128 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDBA2),
2129 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE0),
2130 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCLK_1),
2131 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDCKE1),
2132 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT0),
2133 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDODT1),
2134 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDWE),
2135 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D0),
2136 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D1),
2137 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D2),
2138 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D3),
2139 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D4),
2140 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D5),
2141 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS0),
2142 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D6),
2143 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D7),
2144 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM0),
2145 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D8),
2146 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D9),
2147 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D10),
2148 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D11),
2149 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D12),
2150 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D13),
2151 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D14),
2152 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS1),
2153 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D15),
2154 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM1),
2155 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D48),
2156 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D49),
2157 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D50),
2158 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D51),
2159 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D52),
2160 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D53),
2161 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D54),
2162 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D55),
2163 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS6),
2164 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM6),
2165 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D56),
2166 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_SDQS7),
2167 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D57),
2168 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D58),
2169 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D59),
2170 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D60),
2171 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_DQM7),
2172 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D61),
2173 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D62),
2174 IMX_PINCTRL_PIN(MX6Q_PAD_DRAM_D63),
2175 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL0),
2176 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW0),
2177 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL1),
2178 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW1),
2179 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL2),
2180 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW2),
2181 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL3),
2182 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW3),
2183 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_COL4),
2184 IMX_PINCTRL_PIN(MX6Q_PAD_KEY_ROW4),
2185 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_0),
2186 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_1),
2187 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_9),
2188 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_3),
2189 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_6),
2190 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_2),
2191 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_4),
2192 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_5),
2193 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_7),
2194 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_8),
2195 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_16),
2196 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_17),
2197 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_18),
2198 IMX_PINCTRL_PIN(MX6Q_PAD_GPIO_19),
2199 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_PIXCLK),
2200 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_MCLK),
2201 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DATA_EN),
2202 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_VSYNC),
2203 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT4),
2204 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT5),
2205 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT6),
2206 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT7),
2207 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT8),
2208 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT9),
2209 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT10),
2210 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT11),
2211 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT12),
2212 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT13),
2213 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT14),
2214 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT15),
2215 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT16),
2216 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT17),
2217 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT18),
2218 IMX_PINCTRL_PIN(MX6Q_PAD_CSI0_DAT19),
2219 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TMS),
2220 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_MOD),
2221 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TRSTB),
2222 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDI),
2223 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TCK),
2224 IMX_PINCTRL_PIN(MX6Q_PAD_JTAG_TDO),
2225 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX3_P),
2226 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX2_P),
2227 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_CLK_P),
2228 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX1_P),
2229 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS1_TX0_P),
2230 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX3_P),
2231 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_CLK_P),
2232 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX2_P),
2233 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX1_P),
2234 IMX_PINCTRL_PIN(MX6Q_PAD_LVDS0_TX0_P),
2235 IMX_PINCTRL_PIN(MX6Q_PAD_TAMPER),
2236 IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_ON_REQ),
2237 IMX_PINCTRL_PIN(MX6Q_PAD_PMIC_STBY_REQ),
2238 IMX_PINCTRL_PIN(MX6Q_PAD_POR_B),
2239 IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE1),
2240 IMX_PINCTRL_PIN(MX6Q_PAD_RESET_IN_B),
2241 IMX_PINCTRL_PIN(MX6Q_PAD_BOOT_MODE0),
2242 IMX_PINCTRL_PIN(MX6Q_PAD_TEST_MODE),
2243 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT7),
2244 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT6),
2245 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT5),
2246 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT4),
2247 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CMD),
2248 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_CLK),
2249 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT0),
2250 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT1),
2251 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT2),
2252 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_DAT3),
2253 IMX_PINCTRL_PIN(MX6Q_PAD_SD3_RST),
2254 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CLE),
2255 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_ALE),
2256 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_WP_B),
2257 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_RB0),
2258 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS0),
2259 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS1),
2260 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS2),
2261 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_CS3),
2262 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CMD),
2263 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_CLK),
2264 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D0),
2265 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D1),
2266 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D2),
2267 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D3),
2268 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D4),
2269 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D5),
2270 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D6),
2271 IMX_PINCTRL_PIN(MX6Q_PAD_NANDF_D7),
2272 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT0),
2273 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT1),
2274 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT2),
2275 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT3),
2276 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT4),
2277 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT5),
2278 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT6),
2279 IMX_PINCTRL_PIN(MX6Q_PAD_SD4_DAT7),
2280 IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT1),
2281 IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT0),
2282 IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT3),
2283 IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CMD),
2284 IMX_PINCTRL_PIN(MX6Q_PAD_SD1_DAT2),
2285 IMX_PINCTRL_PIN(MX6Q_PAD_SD1_CLK),
2286 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CLK),
2287 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_CMD),
2288 IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT3),
2289};
2290
2291static struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
2292 .pins = imx6q_pinctrl_pads,
2293 .npins = ARRAY_SIZE(imx6q_pinctrl_pads),
2294 .pin_regs = imx6q_pin_regs,
2295 .npin_regs = ARRAY_SIZE(imx6q_pin_regs),
2296};
2297
2298static struct of_device_id imx6q_pinctrl_of_match[] __devinitdata = {
2299 { .compatible = "fsl,imx6q-iomuxc", },
2300 { /* sentinel */ }
2301};
2302
2303static int __devinit imx6q_pinctrl_probe(struct platform_device *pdev)
2304{
2305 return imx_pinctrl_probe(pdev, &imx6q_pinctrl_info);
2306}
2307
2308static struct platform_driver imx6q_pinctrl_driver = {
2309 .driver = {
2310 .name = "imx6q-pinctrl",
2311 .owner = THIS_MODULE,
2312 .of_match_table = of_match_ptr(imx6q_pinctrl_of_match),
2313 },
2314 .probe = imx6q_pinctrl_probe,
2315 .remove = __devexit_p(imx_pinctrl_remove),
2316};
2317
2318static int __init imx6q_pinctrl_init(void)
2319{
2320 return platform_driver_register(&imx6q_pinctrl_driver);
2321}
2322arch_initcall(imx6q_pinctrl_init);
2323
2324static void __exit imx6q_pinctrl_exit(void)
2325{
2326 platform_driver_unregister(&imx6q_pinctrl_driver);
2327}
2328module_exit(imx6q_pinctrl_exit);
2329MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
2330MODULE_DESCRIPTION("Freescale IMX6Q pinctrl driver");
2331MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-mxs.c b/drivers/pinctrl/pinctrl-mxs.c
new file mode 100644
index 00000000000..93cd959971c
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mxs.c
@@ -0,0 +1,508 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/pinctrl/machine.h>
19#include <linux/pinctrl/pinconf.h>
20#include <linux/pinctrl/pinctrl.h>
21#include <linux/pinctrl/pinmux.h>
22#include <linux/platform_device.h>
23#include <linux/slab.h>
24#include "core.h"
25#include "pinctrl-mxs.h"
26
27#define SUFFIX_LEN 4
28
29struct mxs_pinctrl_data {
30 struct device *dev;
31 struct pinctrl_dev *pctl;
32 void __iomem *base;
33 struct mxs_pinctrl_soc_data *soc;
34};
35
36static int mxs_get_groups_count(struct pinctrl_dev *pctldev)
37{
38 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
39
40 return d->soc->ngroups;
41}
42
43static const char *mxs_get_group_name(struct pinctrl_dev *pctldev,
44 unsigned group)
45{
46 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
47
48 return d->soc->groups[group].name;
49}
50
51static int mxs_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
52 const unsigned **pins, unsigned *num_pins)
53{
54 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
55
56 *pins = d->soc->groups[group].pins;
57 *num_pins = d->soc->groups[group].npins;
58
59 return 0;
60}
61
62static void mxs_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
63 unsigned offset)
64{
65 seq_printf(s, " %s", dev_name(pctldev->dev));
66}
67
68static int mxs_dt_node_to_map(struct pinctrl_dev *pctldev,
69 struct device_node *np,
70 struct pinctrl_map **map, unsigned *num_maps)
71{
72 struct pinctrl_map *new_map;
73 char *group;
74 unsigned new_num;
75 unsigned long config = 0;
76 unsigned long *pconfig;
77 int length = strlen(np->name) + SUFFIX_LEN;
78 u32 val;
79 int ret;
80
81 ret = of_property_read_u32(np, "fsl,drive-strength", &val);
82 if (!ret)
83 config = val | MA_PRESENT;
84 ret = of_property_read_u32(np, "fsl,voltage", &val);
85 if (!ret)
86 config |= val << VOL_SHIFT | VOL_PRESENT;
87 ret = of_property_read_u32(np, "fsl,pull-up", &val);
88 if (!ret)
89 config |= val << PULL_SHIFT | PULL_PRESENT;
90
91 new_num = config ? 2 : 1;
92 new_map = kzalloc(sizeof(*new_map) * new_num, GFP_KERNEL);
93 if (!new_map)
94 return -ENOMEM;
95
96 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
97 new_map[0].data.mux.function = np->name;
98
99 /* Compose group name */
100 group = kzalloc(length, GFP_KERNEL);
101 if (!group)
102 return -ENOMEM;
103 of_property_read_u32(np, "reg", &val);
104 snprintf(group, length, "%s.%d", np->name, val);
105 new_map[0].data.mux.group = group;
106
107 if (config) {
108 pconfig = kmemdup(&config, sizeof(config), GFP_KERNEL);
109 if (!pconfig) {
110 ret = -ENOMEM;
111 goto free;
112 }
113
114 new_map[1].type = PIN_MAP_TYPE_CONFIGS_GROUP;
115 new_map[1].data.configs.group_or_pin = group;
116 new_map[1].data.configs.configs = pconfig;
117 new_map[1].data.configs.num_configs = 1;
118 }
119
120 *map = new_map;
121 *num_maps = new_num;
122
123 return 0;
124
125free:
126 kfree(new_map);
127 return ret;
128}
129
130static void mxs_dt_free_map(struct pinctrl_dev *pctldev,
131 struct pinctrl_map *map, unsigned num_maps)
132{
133 int i;
134
135 for (i = 0; i < num_maps; i++) {
136 if (map[i].type == PIN_MAP_TYPE_MUX_GROUP)
137 kfree(map[i].data.mux.group);
138 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
139 kfree(map[i].data.configs.configs);
140 }
141
142 kfree(map);
143}
144
145static struct pinctrl_ops mxs_pinctrl_ops = {
146 .get_groups_count = mxs_get_groups_count,
147 .get_group_name = mxs_get_group_name,
148 .get_group_pins = mxs_get_group_pins,
149 .pin_dbg_show = mxs_pin_dbg_show,
150 .dt_node_to_map = mxs_dt_node_to_map,
151 .dt_free_map = mxs_dt_free_map,
152};
153
154static int mxs_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
155{
156 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
157
158 return d->soc->nfunctions;
159}
160
161static const char *mxs_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
162 unsigned function)
163{
164 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
165
166 return d->soc->functions[function].name;
167}
168
169static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
170 unsigned group,
171 const char * const **groups,
172 unsigned * const num_groups)
173{
174 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
175
176 *groups = d->soc->functions[group].groups;
177 *num_groups = d->soc->functions[group].ngroups;
178
179 return 0;
180}
181
182static int mxs_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned selector,
183 unsigned group)
184{
185 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
186 struct mxs_group *g = &d->soc->groups[group];
187 void __iomem *reg;
188 u8 bank, shift;
189 u16 pin;
190 int i;
191
192 for (i = 0; i < g->npins; i++) {
193 bank = PINID_TO_BANK(g->pins[i]);
194 pin = PINID_TO_PIN(g->pins[i]);
195 reg = d->base + d->soc->regs->muxsel;
196 reg += bank * 0x20 + pin / 16 * 0x10;
197 shift = pin % 16 * 2;
198
199 writel(0x3 << shift, reg + CLR);
200 writel(g->muxsel[i] << shift, reg + SET);
201 }
202
203 return 0;
204}
205
206static void mxs_pinctrl_disable(struct pinctrl_dev *pctldev,
207 unsigned function, unsigned group)
208{
209 /* Nothing to do here */
210}
211
212static struct pinmux_ops mxs_pinmux_ops = {
213 .get_functions_count = mxs_pinctrl_get_funcs_count,
214 .get_function_name = mxs_pinctrl_get_func_name,
215 .get_function_groups = mxs_pinctrl_get_func_groups,
216 .enable = mxs_pinctrl_enable,
217 .disable = mxs_pinctrl_disable,
218};
219
220static int mxs_pinconf_get(struct pinctrl_dev *pctldev,
221 unsigned pin, unsigned long *config)
222{
223 return -ENOTSUPP;
224}
225
226static int mxs_pinconf_set(struct pinctrl_dev *pctldev,
227 unsigned pin, unsigned long config)
228{
229 return -ENOTSUPP;
230}
231
232static int mxs_pinconf_group_get(struct pinctrl_dev *pctldev,
233 unsigned group, unsigned long *config)
234{
235 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
236
237 *config = d->soc->groups[group].config;
238
239 return 0;
240}
241
242static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev,
243 unsigned group, unsigned long config)
244{
245 struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
246 struct mxs_group *g = &d->soc->groups[group];
247 void __iomem *reg;
248 u8 ma, vol, pull, bank, shift;
249 u16 pin;
250 int i;
251
252 ma = CONFIG_TO_MA(config);
253 vol = CONFIG_TO_VOL(config);
254 pull = CONFIG_TO_PULL(config);
255
256 for (i = 0; i < g->npins; i++) {
257 bank = PINID_TO_BANK(g->pins[i]);
258 pin = PINID_TO_PIN(g->pins[i]);
259
260 /* drive */
261 reg = d->base + d->soc->regs->drive;
262 reg += bank * 0x40 + pin / 8 * 0x10;
263
264 /* mA */
265 if (config & MA_PRESENT) {
266 shift = pin % 8 * 4;
267 writel(0x3 << shift, reg + CLR);
268 writel(ma << shift, reg + SET);
269 }
270
271 /* vol */
272 if (config & VOL_PRESENT) {
273 shift = pin % 8 * 4 + 2;
274 if (vol)
275 writel(1 << shift, reg + SET);
276 else
277 writel(1 << shift, reg + CLR);
278 }
279
280 /* pull */
281 if (config & PULL_PRESENT) {
282 reg = d->base + d->soc->regs->pull;
283 reg += bank * 0x10;
284 shift = pin;
285 if (pull)
286 writel(1 << shift, reg + SET);
287 else
288 writel(1 << shift, reg + CLR);
289 }
290 }
291
292 /* cache the config value for mxs_pinconf_group_get() */
293 g->config = config;
294
295 return 0;
296}
297
298static void mxs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
299 struct seq_file *s, unsigned pin)
300{
301 /* Not support */
302}
303
304static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
305 struct seq_file *s, unsigned group)
306{
307 unsigned long config;
308
309 if (!mxs_pinconf_group_get(pctldev, group, &config))
310 seq_printf(s, "0x%lx", config);
311}
312
313struct pinconf_ops mxs_pinconf_ops = {
314 .pin_config_get = mxs_pinconf_get,
315 .pin_config_set = mxs_pinconf_set,
316 .pin_config_group_get = mxs_pinconf_group_get,
317 .pin_config_group_set = mxs_pinconf_group_set,
318 .pin_config_dbg_show = mxs_pinconf_dbg_show,
319 .pin_config_group_dbg_show = mxs_pinconf_group_dbg_show,
320};
321
322static struct pinctrl_desc mxs_pinctrl_desc = {
323 .pctlops = &mxs_pinctrl_ops,
324 .pmxops = &mxs_pinmux_ops,
325 .confops = &mxs_pinconf_ops,
326 .owner = THIS_MODULE,
327};
328
329static int __devinit mxs_pinctrl_parse_group(struct platform_device *pdev,
330 struct device_node *np, int idx,
331 const char **out_name)
332{
333 struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
334 struct mxs_group *g = &d->soc->groups[idx];
335 struct property *prop;
336 const char *propname = "fsl,pinmux-ids";
337 char *group;
338 int length = strlen(np->name) + SUFFIX_LEN;
339 int i;
340 u32 val;
341
342 group = devm_kzalloc(&pdev->dev, length, GFP_KERNEL);
343 if (!group)
344 return -ENOMEM;
345 of_property_read_u32(np, "reg", &val);
346 snprintf(group, length, "%s.%d", np->name, val);
347 g->name = group;
348
349 prop = of_find_property(np, propname, &length);
350 if (!prop)
351 return -EINVAL;
352 g->npins = length / sizeof(u32);
353
354 g->pins = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->pins),
355 GFP_KERNEL);
356 if (!g->pins)
357 return -ENOMEM;
358
359 g->muxsel = devm_kzalloc(&pdev->dev, g->npins * sizeof(*g->muxsel),
360 GFP_KERNEL);
361 if (!g->muxsel)
362 return -ENOMEM;
363
364 of_property_read_u32_array(np, propname, g->pins, g->npins);
365 for (i = 0; i < g->npins; i++) {
366 g->muxsel[i] = MUXID_TO_MUXSEL(g->pins[i]);
367 g->pins[i] = MUXID_TO_PINID(g->pins[i]);
368 }
369
370 *out_name = g->name;
371
372 return 0;
373}
374
375static int __devinit mxs_pinctrl_probe_dt(struct platform_device *pdev,
376 struct mxs_pinctrl_data *d)
377{
378 struct mxs_pinctrl_soc_data *soc = d->soc;
379 struct device_node *np = pdev->dev.of_node;
380 struct device_node *child;
381 struct mxs_function *f;
382 const char *fn, *fnull = "";
383 int i = 0, idxf = 0, idxg = 0;
384 int ret;
385 u32 val;
386
387 child = of_get_next_child(np, NULL);
388 if (!child) {
389 dev_err(&pdev->dev, "no group is defined\n");
390 return -ENOENT;
391 }
392
393 /* Count total functions and groups */
394 fn = fnull;
395 for_each_child_of_node(np, child) {
396 /* Skip pure pinconf node */
397 if (of_property_read_u32(child, "reg", &val))
398 continue;
399 if (strcmp(fn, child->name)) {
400 fn = child->name;
401 soc->nfunctions++;
402 }
403 soc->ngroups++;
404 }
405
406 soc->functions = devm_kzalloc(&pdev->dev, soc->nfunctions *
407 sizeof(*soc->functions), GFP_KERNEL);
408 if (!soc->functions)
409 return -ENOMEM;
410
411 soc->groups = devm_kzalloc(&pdev->dev, soc->ngroups *
412 sizeof(*soc->groups), GFP_KERNEL);
413 if (!soc->groups)
414 return -ENOMEM;
415
416 /* Count groups for each function */
417 fn = fnull;
418 f = &soc->functions[idxf];
419 for_each_child_of_node(np, child) {
420 if (of_property_read_u32(child, "reg", &val))
421 continue;
422 if (strcmp(fn, child->name)) {
423 f = &soc->functions[idxf++];
424 f->name = fn = child->name;
425 }
426 f->ngroups++;
427 };
428
429 /* Get groups for each function */
430 idxf = 0;
431 fn = fnull;
432 for_each_child_of_node(np, child) {
433 if (of_property_read_u32(child, "reg", &val))
434 continue;
435 if (strcmp(fn, child->name)) {
436 f = &soc->functions[idxf++];
437 f->groups = devm_kzalloc(&pdev->dev, f->ngroups *
438 sizeof(*f->groups),
439 GFP_KERNEL);
440 if (!f->groups)
441 return -ENOMEM;
442 fn = child->name;
443 i = 0;
444 }
445 ret = mxs_pinctrl_parse_group(pdev, child, idxg++,
446 &f->groups[i++]);
447 if (ret)
448 return ret;
449 }
450
451 return 0;
452}
453
454int __devinit mxs_pinctrl_probe(struct platform_device *pdev,
455 struct mxs_pinctrl_soc_data *soc)
456{
457 struct device_node *np = pdev->dev.of_node;
458 struct mxs_pinctrl_data *d;
459 int ret;
460
461 d = devm_kzalloc(&pdev->dev, sizeof(*d), GFP_KERNEL);
462 if (!d)
463 return -ENOMEM;
464
465 d->dev = &pdev->dev;
466 d->soc = soc;
467
468 d->base = of_iomap(np, 0);
469 if (!d->base)
470 return -EADDRNOTAVAIL;
471
472 mxs_pinctrl_desc.pins = d->soc->pins;
473 mxs_pinctrl_desc.npins = d->soc->npins;
474 mxs_pinctrl_desc.name = dev_name(&pdev->dev);
475
476 platform_set_drvdata(pdev, d);
477
478 ret = mxs_pinctrl_probe_dt(pdev, d);
479 if (ret) {
480 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
481 goto err;
482 }
483
484 d->pctl = pinctrl_register(&mxs_pinctrl_desc, &pdev->dev, d);
485 if (!d->pctl) {
486 dev_err(&pdev->dev, "Couldn't register MXS pinctrl driver\n");
487 ret = -EINVAL;
488 goto err;
489 }
490
491 return 0;
492
493err:
494 iounmap(d->base);
495 return ret;
496}
497EXPORT_SYMBOL_GPL(mxs_pinctrl_probe);
498
499int __devexit mxs_pinctrl_remove(struct platform_device *pdev)
500{
501 struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
502
503 pinctrl_unregister(d->pctl);
504 iounmap(d->base);
505
506 return 0;
507}
508EXPORT_SYMBOL_GPL(mxs_pinctrl_remove);
diff --git a/drivers/pinctrl/pinctrl-mxs.h b/drivers/pinctrl/pinctrl-mxs.h
new file mode 100644
index 00000000000..fdd88d0bae2
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mxs.h
@@ -0,0 +1,91 @@
1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#ifndef __PINCTRL_MXS_H
13#define __PINCTRL_MXS_H
14
15#include <linux/platform_device.h>
16#include <linux/pinctrl/pinctrl.h>
17
18#define SET 0x4
19#define CLR 0x8
20#define TOG 0xc
21
22#define MXS_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
23#define PINID(bank, pin) ((bank) * 32 + (pin))
24
25/*
26 * pinmux-id bit field definitions
27 *
28 * bank: 15..12 (4)
29 * pin: 11..4 (8)
30 * muxsel: 3..0 (4)
31 */
32#define MUXID_TO_PINID(m) PINID((m) >> 12 & 0xf, (m) >> 4 & 0xff)
33#define MUXID_TO_MUXSEL(m) ((m) & 0xf)
34
35#define PINID_TO_BANK(p) ((p) >> 5)
36#define PINID_TO_PIN(p) ((p) % 32)
37
38/*
39 * pin config bit field definitions
40 *
41 * pull-up: 6..5 (2)
42 * voltage: 4..3 (2)
43 * mA: 2..0 (3)
44 *
45 * MSB of each field is presence bit for the config.
46 */
47#define PULL_PRESENT (1 << 6)
48#define PULL_SHIFT 5
49#define VOL_PRESENT (1 << 4)
50#define VOL_SHIFT 3
51#define MA_PRESENT (1 << 2)
52#define MA_SHIFT 0
53#define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1)
54#define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1)
55#define CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3)
56
57struct mxs_function {
58 const char *name;
59 const char **groups;
60 unsigned ngroups;
61};
62
63struct mxs_group {
64 const char *name;
65 unsigned int *pins;
66 unsigned npins;
67 u8 *muxsel;
68 u8 config;
69};
70
71struct mxs_regs {
72 u16 muxsel;
73 u16 drive;
74 u16 pull;
75};
76
77struct mxs_pinctrl_soc_data {
78 const struct mxs_regs *regs;
79 const struct pinctrl_pin_desc *pins;
80 unsigned npins;
81 struct mxs_function *functions;
82 unsigned nfunctions;
83 struct mxs_group *groups;
84 unsigned ngroups;
85};
86
87int mxs_pinctrl_probe(struct platform_device *pdev,
88 struct mxs_pinctrl_soc_data *soc);
89int mxs_pinctrl_remove(struct platform_device *pdev);
90
91#endif /* __PINCTRL_MXS_H */
diff --git a/drivers/pinctrl/pinctrl-nomadik-db8500.c b/drivers/pinctrl/pinctrl-nomadik-db8500.c
new file mode 100644
index 00000000000..8b2022276f7
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-nomadik-db8500.c
@@ -0,0 +1,857 @@
1#include <linux/kernel.h>
2#include <linux/pinctrl/pinctrl.h>
3#include "pinctrl-nomadik.h"
4
5/* All the pins that can be used for GPIO and some other functions */
6#define _GPIO(offset) (offset)
7
8#define DB8500_PIN_AJ5 _GPIO(0)
9#define DB8500_PIN_AJ3 _GPIO(1)
10#define DB8500_PIN_AH4 _GPIO(2)
11#define DB8500_PIN_AH3 _GPIO(3)
12#define DB8500_PIN_AH6 _GPIO(4)
13#define DB8500_PIN_AG6 _GPIO(5)
14#define DB8500_PIN_AF6 _GPIO(6)
15#define DB8500_PIN_AG5 _GPIO(7)
16#define DB8500_PIN_AD5 _GPIO(8)
17#define DB8500_PIN_AE4 _GPIO(9)
18#define DB8500_PIN_AF5 _GPIO(10)
19#define DB8500_PIN_AG4 _GPIO(11)
20#define DB8500_PIN_AC4 _GPIO(12)
21#define DB8500_PIN_AF3 _GPIO(13)
22#define DB8500_PIN_AE3 _GPIO(14)
23#define DB8500_PIN_AC3 _GPIO(15)
24#define DB8500_PIN_AD3 _GPIO(16)
25#define DB8500_PIN_AD4 _GPIO(17)
26#define DB8500_PIN_AC2 _GPIO(18)
27#define DB8500_PIN_AC1 _GPIO(19)
28#define DB8500_PIN_AB4 _GPIO(20)
29#define DB8500_PIN_AB3 _GPIO(21)
30#define DB8500_PIN_AA3 _GPIO(22)
31#define DB8500_PIN_AA4 _GPIO(23)
32#define DB8500_PIN_AB2 _GPIO(24)
33#define DB8500_PIN_Y4 _GPIO(25)
34#define DB8500_PIN_Y2 _GPIO(26)
35#define DB8500_PIN_AA2 _GPIO(27)
36#define DB8500_PIN_AA1 _GPIO(28)
37#define DB8500_PIN_W2 _GPIO(29)
38#define DB8500_PIN_W3 _GPIO(30)
39#define DB8500_PIN_V3 _GPIO(31)
40#define DB8500_PIN_V2 _GPIO(32)
41#define DB8500_PIN_AF2 _GPIO(33)
42#define DB8500_PIN_AE1 _GPIO(34)
43#define DB8500_PIN_AE2 _GPIO(35)
44#define DB8500_PIN_AG2 _GPIO(36)
45/* Hole */
46#define DB8500_PIN_F3 _GPIO(64)
47#define DB8500_PIN_F1 _GPIO(65)
48#define DB8500_PIN_G3 _GPIO(66)
49#define DB8500_PIN_G2 _GPIO(67)
50#define DB8500_PIN_E1 _GPIO(68)
51#define DB8500_PIN_E2 _GPIO(69)
52#define DB8500_PIN_G5 _GPIO(70)
53#define DB8500_PIN_G4 _GPIO(71)
54#define DB8500_PIN_H4 _GPIO(72)
55#define DB8500_PIN_H3 _GPIO(73)
56#define DB8500_PIN_J3 _GPIO(74)
57#define DB8500_PIN_H2 _GPIO(75)
58#define DB8500_PIN_J2 _GPIO(76)
59#define DB8500_PIN_H1 _GPIO(77)
60#define DB8500_PIN_F4 _GPIO(78)
61#define DB8500_PIN_E3 _GPIO(79)
62#define DB8500_PIN_E4 _GPIO(80)
63#define DB8500_PIN_D2 _GPIO(81)
64#define DB8500_PIN_C1 _GPIO(82)
65#define DB8500_PIN_D3 _GPIO(83)
66#define DB8500_PIN_C2 _GPIO(84)
67#define DB8500_PIN_D5 _GPIO(85)
68#define DB8500_PIN_C6 _GPIO(86)
69#define DB8500_PIN_B3 _GPIO(87)
70#define DB8500_PIN_C4 _GPIO(88)
71#define DB8500_PIN_E6 _GPIO(89)
72#define DB8500_PIN_A3 _GPIO(90)
73#define DB8500_PIN_B6 _GPIO(91)
74#define DB8500_PIN_D6 _GPIO(92)
75#define DB8500_PIN_B7 _GPIO(93)
76#define DB8500_PIN_D7 _GPIO(94)
77#define DB8500_PIN_E8 _GPIO(95)
78#define DB8500_PIN_D8 _GPIO(96)
79#define DB8500_PIN_D9 _GPIO(97)
80/* Hole */
81#define DB8500_PIN_A5 _GPIO(128)
82#define DB8500_PIN_B4 _GPIO(129)
83#define DB8500_PIN_C8 _GPIO(130)
84#define DB8500_PIN_A12 _GPIO(131)
85#define DB8500_PIN_C10 _GPIO(132)
86#define DB8500_PIN_B10 _GPIO(133)
87#define DB8500_PIN_B9 _GPIO(134)
88#define DB8500_PIN_A9 _GPIO(135)
89#define DB8500_PIN_C7 _GPIO(136)
90#define DB8500_PIN_A7 _GPIO(137)
91#define DB8500_PIN_C5 _GPIO(138)
92#define DB8500_PIN_C9 _GPIO(139)
93#define DB8500_PIN_B11 _GPIO(140)
94#define DB8500_PIN_C12 _GPIO(141)
95#define DB8500_PIN_C11 _GPIO(142)
96#define DB8500_PIN_D12 _GPIO(143)
97#define DB8500_PIN_B13 _GPIO(144)
98#define DB8500_PIN_C13 _GPIO(145)
99#define DB8500_PIN_D13 _GPIO(146)
100#define DB8500_PIN_C15 _GPIO(147)
101#define DB8500_PIN_B16 _GPIO(148)
102#define DB8500_PIN_B14 _GPIO(149)
103#define DB8500_PIN_C14 _GPIO(150)
104#define DB8500_PIN_D17 _GPIO(151)
105#define DB8500_PIN_D16 _GPIO(152)
106#define DB8500_PIN_B17 _GPIO(153)
107#define DB8500_PIN_C16 _GPIO(154)
108#define DB8500_PIN_C19 _GPIO(155)
109#define DB8500_PIN_C17 _GPIO(156)
110#define DB8500_PIN_A18 _GPIO(157)
111#define DB8500_PIN_C18 _GPIO(158)
112#define DB8500_PIN_B19 _GPIO(159)
113#define DB8500_PIN_B20 _GPIO(160)
114#define DB8500_PIN_D21 _GPIO(161)
115#define DB8500_PIN_D20 _GPIO(162)
116#define DB8500_PIN_C20 _GPIO(163)
117#define DB8500_PIN_B21 _GPIO(164)
118#define DB8500_PIN_C21 _GPIO(165)
119#define DB8500_PIN_A22 _GPIO(166)
120#define DB8500_PIN_B24 _GPIO(167)
121#define DB8500_PIN_C22 _GPIO(168)
122#define DB8500_PIN_D22 _GPIO(169)
123#define DB8500_PIN_C23 _GPIO(170)
124#define DB8500_PIN_D23 _GPIO(171)
125/* Hole */
126#define DB8500_PIN_AJ27 _GPIO(192)
127#define DB8500_PIN_AH27 _GPIO(193)
128#define DB8500_PIN_AF27 _GPIO(194)
129#define DB8500_PIN_AG28 _GPIO(195)
130#define DB8500_PIN_AG26 _GPIO(196)
131#define DB8500_PIN_AH24 _GPIO(197)
132#define DB8500_PIN_AG25 _GPIO(198)
133#define DB8500_PIN_AH23 _GPIO(199)
134#define DB8500_PIN_AH26 _GPIO(200)
135#define DB8500_PIN_AF24 _GPIO(201)
136#define DB8500_PIN_AF25 _GPIO(202)
137#define DB8500_PIN_AE23 _GPIO(203)
138#define DB8500_PIN_AF23 _GPIO(204)
139#define DB8500_PIN_AG23 _GPIO(205)
140#define DB8500_PIN_AG24 _GPIO(206)
141#define DB8500_PIN_AJ23 _GPIO(207)
142#define DB8500_PIN_AH16 _GPIO(208)
143#define DB8500_PIN_AG15 _GPIO(209)
144#define DB8500_PIN_AJ15 _GPIO(210)
145#define DB8500_PIN_AG14 _GPIO(211)
146#define DB8500_PIN_AF13 _GPIO(212)
147#define DB8500_PIN_AG13 _GPIO(213)
148#define DB8500_PIN_AH15 _GPIO(214)
149#define DB8500_PIN_AH13 _GPIO(215)
150#define DB8500_PIN_AG12 _GPIO(216)
151#define DB8500_PIN_AH12 _GPIO(217)
152#define DB8500_PIN_AH11 _GPIO(218)
153#define DB8500_PIN_AG10 _GPIO(219)
154#define DB8500_PIN_AH10 _GPIO(220)
155#define DB8500_PIN_AJ11 _GPIO(221)
156#define DB8500_PIN_AJ9 _GPIO(222)
157#define DB8500_PIN_AH9 _GPIO(223)
158#define DB8500_PIN_AG9 _GPIO(224)
159#define DB8500_PIN_AG8 _GPIO(225)
160#define DB8500_PIN_AF8 _GPIO(226)
161#define DB8500_PIN_AH7 _GPIO(227)
162#define DB8500_PIN_AJ6 _GPIO(228)
163#define DB8500_PIN_AG7 _GPIO(229)
164#define DB8500_PIN_AF7 _GPIO(230)
165/* Hole */
166#define DB8500_PIN_AF28 _GPIO(256)
167#define DB8500_PIN_AE29 _GPIO(257)
168#define DB8500_PIN_AD29 _GPIO(258)
169#define DB8500_PIN_AC29 _GPIO(259)
170#define DB8500_PIN_AD28 _GPIO(260)
171#define DB8500_PIN_AD26 _GPIO(261)
172#define DB8500_PIN_AE26 _GPIO(262)
173#define DB8500_PIN_AG29 _GPIO(263)
174#define DB8500_PIN_AE27 _GPIO(264)
175#define DB8500_PIN_AD27 _GPIO(265)
176#define DB8500_PIN_AC28 _GPIO(266)
177#define DB8500_PIN_AC27 _GPIO(267)
178
179/*
180 * The names of the pins are denoted by GPIO number and ball name, even
181 * though they can be used for other things than GPIO, this is the first
182 * column in the table of the data sheet and often used on schematics and
183 * such.
184 */
185static const struct pinctrl_pin_desc nmk_db8500_pins[] = {
186 PINCTRL_PIN(DB8500_PIN_AJ5, "GPIO0_AJ5"),
187 PINCTRL_PIN(DB8500_PIN_AJ3, "GPIO1_AJ3"),
188 PINCTRL_PIN(DB8500_PIN_AH4, "GPIO2_AH4"),
189 PINCTRL_PIN(DB8500_PIN_AH3, "GPIO3_AH3"),
190 PINCTRL_PIN(DB8500_PIN_AH6, "GPIO4_AH6"),
191 PINCTRL_PIN(DB8500_PIN_AG6, "GPIO5_AG6"),
192 PINCTRL_PIN(DB8500_PIN_AF6, "GPIO6_AF6"),
193 PINCTRL_PIN(DB8500_PIN_AG5, "GPIO7_AG5"),
194 PINCTRL_PIN(DB8500_PIN_AD5, "GPIO8_AD5"),
195 PINCTRL_PIN(DB8500_PIN_AE4, "GPIO9_AE4"),
196 PINCTRL_PIN(DB8500_PIN_AF5, "GPIO10_AF5"),
197 PINCTRL_PIN(DB8500_PIN_AG4, "GPIO11_AG4"),
198 PINCTRL_PIN(DB8500_PIN_AC4, "GPIO12_AC4"),
199 PINCTRL_PIN(DB8500_PIN_AF3, "GPIO13_AF3"),
200 PINCTRL_PIN(DB8500_PIN_AE3, "GPIO14_AE3"),
201 PINCTRL_PIN(DB8500_PIN_AC3, "GPIO15_AC3"),
202 PINCTRL_PIN(DB8500_PIN_AD3, "GPIO16_AD3"),
203 PINCTRL_PIN(DB8500_PIN_AD4, "GPIO17_AD4"),
204 PINCTRL_PIN(DB8500_PIN_AC2, "GPIO18_AC2"),
205 PINCTRL_PIN(DB8500_PIN_AC1, "GPIO19_AC1"),
206 PINCTRL_PIN(DB8500_PIN_AB4, "GPIO20_AB4"),
207 PINCTRL_PIN(DB8500_PIN_AB3, "GPIO21_AB3"),
208 PINCTRL_PIN(DB8500_PIN_AA3, "GPIO22_AA3"),
209 PINCTRL_PIN(DB8500_PIN_AA4, "GPIO23_AA4"),
210 PINCTRL_PIN(DB8500_PIN_AB2, "GPIO24_AB2"),
211 PINCTRL_PIN(DB8500_PIN_Y4, "GPIO25_Y4"),
212 PINCTRL_PIN(DB8500_PIN_Y2, "GPIO26_Y2"),
213 PINCTRL_PIN(DB8500_PIN_AA2, "GPIO27_AA2"),
214 PINCTRL_PIN(DB8500_PIN_AA1, "GPIO28_AA1"),
215 PINCTRL_PIN(DB8500_PIN_W2, "GPIO29_W2"),
216 PINCTRL_PIN(DB8500_PIN_W3, "GPIO30_W3"),
217 PINCTRL_PIN(DB8500_PIN_V3, "GPIO31_V3"),
218 PINCTRL_PIN(DB8500_PIN_V2, "GPIO32_V2"),
219 PINCTRL_PIN(DB8500_PIN_AF2, "GPIO33_AF2"),
220 PINCTRL_PIN(DB8500_PIN_AE1, "GPIO34_AE1"),
221 PINCTRL_PIN(DB8500_PIN_AE2, "GPIO35_AE2"),
222 PINCTRL_PIN(DB8500_PIN_AG2, "GPIO36_AG2"),
223 /* Hole */
224 PINCTRL_PIN(DB8500_PIN_F3, "GPIO64_F3"),
225 PINCTRL_PIN(DB8500_PIN_F1, "GPIO65_F1"),
226 PINCTRL_PIN(DB8500_PIN_G3, "GPIO66_G3"),
227 PINCTRL_PIN(DB8500_PIN_G2, "GPIO67_G2"),
228 PINCTRL_PIN(DB8500_PIN_E1, "GPIO68_E1"),
229 PINCTRL_PIN(DB8500_PIN_E2, "GPIO69_E2"),
230 PINCTRL_PIN(DB8500_PIN_G5, "GPIO70_G5"),
231 PINCTRL_PIN(DB8500_PIN_G4, "GPIO71_G4"),
232 PINCTRL_PIN(DB8500_PIN_H4, "GPIO72_H4"),
233 PINCTRL_PIN(DB8500_PIN_H3, "GPIO73_H3"),
234 PINCTRL_PIN(DB8500_PIN_J3, "GPIO74_J3"),
235 PINCTRL_PIN(DB8500_PIN_H2, "GPIO75_H2"),
236 PINCTRL_PIN(DB8500_PIN_J2, "GPIO76_J2"),
237 PINCTRL_PIN(DB8500_PIN_H1, "GPIO77_H1"),
238 PINCTRL_PIN(DB8500_PIN_F4, "GPIO78_F4"),
239 PINCTRL_PIN(DB8500_PIN_E3, "GPIO79_E3"),
240 PINCTRL_PIN(DB8500_PIN_E4, "GPIO80_E4"),
241 PINCTRL_PIN(DB8500_PIN_D2, "GPIO81_D2"),
242 PINCTRL_PIN(DB8500_PIN_C1, "GPIO82_C1"),
243 PINCTRL_PIN(DB8500_PIN_D3, "GPIO83_D3"),
244 PINCTRL_PIN(DB8500_PIN_C2, "GPIO84_C2"),
245 PINCTRL_PIN(DB8500_PIN_D5, "GPIO85_D5"),
246 PINCTRL_PIN(DB8500_PIN_C6, "GPIO86_C6"),
247 PINCTRL_PIN(DB8500_PIN_B3, "GPIO87_B3"),
248 PINCTRL_PIN(DB8500_PIN_C4, "GPIO88_C4"),
249 PINCTRL_PIN(DB8500_PIN_E6, "GPIO89_E6"),
250 PINCTRL_PIN(DB8500_PIN_A3, "GPIO90_A3"),
251 PINCTRL_PIN(DB8500_PIN_B6, "GPIO91_B6"),
252 PINCTRL_PIN(DB8500_PIN_D6, "GPIO92_D6"),
253 PINCTRL_PIN(DB8500_PIN_B7, "GPIO93_B7"),
254 PINCTRL_PIN(DB8500_PIN_D7, "GPIO94_D7"),
255 PINCTRL_PIN(DB8500_PIN_E8, "GPIO95_E8"),
256 PINCTRL_PIN(DB8500_PIN_D8, "GPIO96_D8"),
257 PINCTRL_PIN(DB8500_PIN_D9, "GPIO97_D9"),
258 /* Hole */
259 PINCTRL_PIN(DB8500_PIN_A5, "GPIO128_A5"),
260 PINCTRL_PIN(DB8500_PIN_B4, "GPIO129_B4"),
261 PINCTRL_PIN(DB8500_PIN_C8, "GPIO130_C8"),
262 PINCTRL_PIN(DB8500_PIN_A12, "GPIO131_A12"),
263 PINCTRL_PIN(DB8500_PIN_C10, "GPIO132_C10"),
264 PINCTRL_PIN(DB8500_PIN_B10, "GPIO133_B10"),
265 PINCTRL_PIN(DB8500_PIN_B9, "GPIO134_B9"),
266 PINCTRL_PIN(DB8500_PIN_A9, "GPIO135_A9"),
267 PINCTRL_PIN(DB8500_PIN_C7, "GPIO136_C7"),
268 PINCTRL_PIN(DB8500_PIN_A7, "GPIO137_A7"),
269 PINCTRL_PIN(DB8500_PIN_C5, "GPIO138_C5"),
270 PINCTRL_PIN(DB8500_PIN_C9, "GPIO139_C9"),
271 PINCTRL_PIN(DB8500_PIN_B11, "GPIO140_B11"),
272 PINCTRL_PIN(DB8500_PIN_C12, "GPIO141_C12"),
273 PINCTRL_PIN(DB8500_PIN_C11, "GPIO142_C11"),
274 PINCTRL_PIN(DB8500_PIN_D12, "GPIO143_D12"),
275 PINCTRL_PIN(DB8500_PIN_B13, "GPIO144_B13"),
276 PINCTRL_PIN(DB8500_PIN_C13, "GPIO145_C13"),
277 PINCTRL_PIN(DB8500_PIN_D13, "GPIO146_D13"),
278 PINCTRL_PIN(DB8500_PIN_C15, "GPIO147_C15"),
279 PINCTRL_PIN(DB8500_PIN_B16, "GPIO148_B16"),
280 PINCTRL_PIN(DB8500_PIN_B14, "GPIO149_B14"),
281 PINCTRL_PIN(DB8500_PIN_C14, "GPIO150_C14"),
282 PINCTRL_PIN(DB8500_PIN_D17, "GPIO151_D17"),
283 PINCTRL_PIN(DB8500_PIN_D16, "GPIO152_D16"),
284 PINCTRL_PIN(DB8500_PIN_B17, "GPIO153_B17"),
285 PINCTRL_PIN(DB8500_PIN_C16, "GPIO154_C16"),
286 PINCTRL_PIN(DB8500_PIN_C19, "GPIO155_C19"),
287 PINCTRL_PIN(DB8500_PIN_C17, "GPIO156_C17"),
288 PINCTRL_PIN(DB8500_PIN_A18, "GPIO157_A18"),
289 PINCTRL_PIN(DB8500_PIN_C18, "GPIO158_C18"),
290 PINCTRL_PIN(DB8500_PIN_B19, "GPIO159_B19"),
291 PINCTRL_PIN(DB8500_PIN_B20, "GPIO160_B20"),
292 PINCTRL_PIN(DB8500_PIN_D21, "GPIO161_D21"),
293 PINCTRL_PIN(DB8500_PIN_D20, "GPIO162_D20"),
294 PINCTRL_PIN(DB8500_PIN_C20, "GPIO163_C20"),
295 PINCTRL_PIN(DB8500_PIN_B21, "GPIO164_B21"),
296 PINCTRL_PIN(DB8500_PIN_C21, "GPIO165_C21"),
297 PINCTRL_PIN(DB8500_PIN_A22, "GPIO166_A22"),
298 PINCTRL_PIN(DB8500_PIN_B24, "GPIO167_B24"),
299 PINCTRL_PIN(DB8500_PIN_C22, "GPIO168_C22"),
300 PINCTRL_PIN(DB8500_PIN_D22, "GPIO169_D22"),
301 PINCTRL_PIN(DB8500_PIN_C23, "GPIO170_C23"),
302 PINCTRL_PIN(DB8500_PIN_D23, "GPIO171_D23"),
303 /* Hole */
304 PINCTRL_PIN(DB8500_PIN_AJ27, "GPIO192_AJ27"),
305 PINCTRL_PIN(DB8500_PIN_AH27, "GPIO193_AH27"),
306 PINCTRL_PIN(DB8500_PIN_AF27, "GPIO194_AF27"),
307 PINCTRL_PIN(DB8500_PIN_AG28, "GPIO195_AG28"),
308 PINCTRL_PIN(DB8500_PIN_AG26, "GPIO196_AG26"),
309 PINCTRL_PIN(DB8500_PIN_AH24, "GPIO197_AH24"),
310 PINCTRL_PIN(DB8500_PIN_AG25, "GPIO198_AG25"),
311 PINCTRL_PIN(DB8500_PIN_AH23, "GPIO199_AH23"),
312 PINCTRL_PIN(DB8500_PIN_AH26, "GPIO200_AH26"),
313 PINCTRL_PIN(DB8500_PIN_AF24, "GPIO201_AF24"),
314 PINCTRL_PIN(DB8500_PIN_AF25, "GPIO202_AF25"),
315 PINCTRL_PIN(DB8500_PIN_AE23, "GPIO203_AE23"),
316 PINCTRL_PIN(DB8500_PIN_AF23, "GPIO204_AF23"),
317 PINCTRL_PIN(DB8500_PIN_AG23, "GPIO205_AG23"),
318 PINCTRL_PIN(DB8500_PIN_AG24, "GPIO206_AG24"),
319 PINCTRL_PIN(DB8500_PIN_AJ23, "GPIO207_AJ23"),
320 PINCTRL_PIN(DB8500_PIN_AH16, "GPIO208_AH16"),
321 PINCTRL_PIN(DB8500_PIN_AG15, "GPIO209_AG15"),
322 PINCTRL_PIN(DB8500_PIN_AJ15, "GPIO210_AJ15"),
323 PINCTRL_PIN(DB8500_PIN_AG14, "GPIO211_AG14"),
324 PINCTRL_PIN(DB8500_PIN_AF13, "GPIO212_AF13"),
325 PINCTRL_PIN(DB8500_PIN_AG13, "GPIO213_AG13"),
326 PINCTRL_PIN(DB8500_PIN_AH15, "GPIO214_AH15"),
327 PINCTRL_PIN(DB8500_PIN_AH13, "GPIO215_AH13"),
328 PINCTRL_PIN(DB8500_PIN_AG12, "GPIO216_AG12"),
329 PINCTRL_PIN(DB8500_PIN_AH12, "GPIO217_AH12"),
330 PINCTRL_PIN(DB8500_PIN_AH11, "GPIO218_AH11"),
331 PINCTRL_PIN(DB8500_PIN_AG10, "GPIO219_AG10"),
332 PINCTRL_PIN(DB8500_PIN_AH10, "GPIO220_AH10"),
333 PINCTRL_PIN(DB8500_PIN_AJ11, "GPIO221_AJ11"),
334 PINCTRL_PIN(DB8500_PIN_AJ9, "GPIO222_AJ9"),
335 PINCTRL_PIN(DB8500_PIN_AH9, "GPIO223_AH9"),
336 PINCTRL_PIN(DB8500_PIN_AG9, "GPIO224_AG9"),
337 PINCTRL_PIN(DB8500_PIN_AG8, "GPIO225_AG8"),
338 PINCTRL_PIN(DB8500_PIN_AF8, "GPIO226_AF8"),
339 PINCTRL_PIN(DB8500_PIN_AH7, "GPIO227_AH7"),
340 PINCTRL_PIN(DB8500_PIN_AJ6, "GPIO228_AJ6"),
341 PINCTRL_PIN(DB8500_PIN_AG7, "GPIO229_AG7"),
342 PINCTRL_PIN(DB8500_PIN_AF7, "GPIO230_AF7"),
343 /* Hole */
344 PINCTRL_PIN(DB8500_PIN_AF28, "GPIO256_AF28"),
345 PINCTRL_PIN(DB8500_PIN_AE29, "GPIO257_AE29"),
346 PINCTRL_PIN(DB8500_PIN_AD29, "GPIO258_AD29"),
347 PINCTRL_PIN(DB8500_PIN_AC29, "GPIO259_AC29"),
348 PINCTRL_PIN(DB8500_PIN_AD28, "GPIO260_AD28"),
349 PINCTRL_PIN(DB8500_PIN_AD26, "GPIO261_AD26"),
350 PINCTRL_PIN(DB8500_PIN_AE26, "GPIO262_AE26"),
351 PINCTRL_PIN(DB8500_PIN_AG29, "GPIO263_AG29"),
352 PINCTRL_PIN(DB8500_PIN_AE27, "GPIO264_AE27"),
353 PINCTRL_PIN(DB8500_PIN_AD27, "GPIO265_AD27"),
354 PINCTRL_PIN(DB8500_PIN_AC28, "GPIO266_AC28"),
355 PINCTRL_PIN(DB8500_PIN_AC27, "GPIO267_AC27"),
356};
357
358#define DB8500_GPIO_RANGE(a, b, c) { .name = "DB8500", .id = a, .base = b, \
359 .pin_base = b, .npins = c }
360
361/*
362 * This matches the 32-pin gpio chips registered by the GPIO portion. This
363 * cannot be const since we assign the struct gpio_chip * pointer at runtime.
364 */
365static struct pinctrl_gpio_range nmk_db8500_ranges[] = {
366 DB8500_GPIO_RANGE(0, 0, 32),
367 DB8500_GPIO_RANGE(1, 32, 5),
368 DB8500_GPIO_RANGE(2, 64, 32),
369 DB8500_GPIO_RANGE(3, 96, 2),
370 DB8500_GPIO_RANGE(4, 128, 32),
371 DB8500_GPIO_RANGE(5, 160, 12),
372 DB8500_GPIO_RANGE(6, 192, 32),
373 DB8500_GPIO_RANGE(7, 224, 7),
374 DB8500_GPIO_RANGE(8, 256, 12),
375};
376
377/*
378 * Read the pin group names like this:
379 * u0_a_1 = first groups of pins for uart0 on alt function a
380 * i2c2_b_2 = second group of pins for i2c2 on alt function b
381 *
382 * The groups are arranged as sets per altfunction column, so we can
383 * mux in one group at a time by selecting the same altfunction for them
384 * all. When functions require pins on different altfunctions, you need
385 * to combine several groups.
386 */
387
388/* Altfunction A column */
389static const unsigned u0_a_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3,
390 DB8500_PIN_AH4, DB8500_PIN_AH3 };
391static const unsigned u1rxtx_a_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 };
392static const unsigned u1ctsrts_a_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 };
393/* Image processor I2C line, this is driven by image processor firmware */
394static const unsigned ipi2c_a_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 };
395static const unsigned ipi2c_a_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 };
396/* MSP0 can only be on these pins, but TXD and RXD can be flipped */
397static const unsigned msp0txrx_a_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 };
398static const unsigned msp0tfstck_a_1_pins[] = { DB8500_PIN_AF3, DB8500_PIN_AE3 };
399static const unsigned msp0rfsrck_a_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 };
400/* Basic pins of the MMC/SD card 0 interface */
401static const unsigned mc0_a_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1,
402 DB8500_PIN_AB4, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2,
403 DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 };
404/* Often only 4 bits are used, then these are not needed (only used for MMC) */
405static const unsigned mc0_dat47_a_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3,
406 DB8500_PIN_V3, DB8500_PIN_V2};
407static const unsigned mc0dat31dir_a_1_pins[] = { DB8500_PIN_AB3 };
408/* MSP1 can only be on these pins, but TXD and RXD can be flipped */
409static const unsigned msp1txrx_a_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 };
410static const unsigned msp1_a_1_pins[] = { DB8500_PIN_AE1, DB8500_PIN_AE2 };
411/* LCD interface */
412static const unsigned lcdb_a_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1,
413 DB8500_PIN_G3, DB8500_PIN_G2 };
414static const unsigned lcdvsi0_a_1_pins[] = { DB8500_PIN_E1 };
415static const unsigned lcdvsi1_a_1_pins[] = { DB8500_PIN_E2 };
416static const unsigned lcd_d0_d7_a_1_pins[] = {
417 DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3,
418 DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1 };
419/* D8 thru D11 often used as TVOUT lines */
420static const unsigned lcd_d8_d11_a_1_pins[] = { DB8500_PIN_F4,
421 DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2 };
422static const unsigned lcd_d12_d23_a_1_pins[] = {
423 DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5,
424 DB8500_PIN_C6, DB8500_PIN_B3, DB8500_PIN_C4, DB8500_PIN_E6,
425 DB8500_PIN_A3, DB8500_PIN_B6, DB8500_PIN_D6, DB8500_PIN_B7 };
426static const unsigned kp_a_1_pins[] = { DB8500_PIN_D7, DB8500_PIN_E8,
427 DB8500_PIN_D8, DB8500_PIN_D9 };
428static const unsigned kpskaskb_a_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16 };
429static const unsigned kp_a_2_pins[] = {
430 DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17,
431 DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20,
432 DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21,
433 DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 };
434/* MC2 has 8 data lines and no direction control, so only for (e)MMC */
435static const unsigned mc2_a_1_pins[] = { DB8500_PIN_A5, DB8500_PIN_B4,
436 DB8500_PIN_C8, DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10,
437 DB8500_PIN_B9, DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7,
438 DB8500_PIN_C5 };
439static const unsigned ssp1_a_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11,
440 DB8500_PIN_C12, DB8500_PIN_C11 };
441static const unsigned ssp0_a_1_pins[] = { DB8500_PIN_D12, DB8500_PIN_B13,
442 DB8500_PIN_C13, DB8500_PIN_D13 };
443static const unsigned i2c0_a_1_pins[] = { DB8500_PIN_C15, DB8500_PIN_B16 };
444/*
445 * Image processor GPIO pins are named "ipgpio" and have their own
446 * numberspace
447 */
448static const unsigned ipgpio0_a_1_pins[] = { DB8500_PIN_B14 };
449static const unsigned ipgpio1_a_1_pins[] = { DB8500_PIN_C14 };
450/* Three modem pins named RF_PURn, MODEM_STATE and MODEM_PWREN */
451static const unsigned modem_a_1_pins[] = { DB8500_PIN_D22, DB8500_PIN_C23,
452 DB8500_PIN_D23 };
453/*
454 * This MSP cannot switch RX and TX, SCK in a separate group since this
455 * seems to be optional.
456 */
457static const unsigned msp2sck_a_1_pins[] = { DB8500_PIN_AJ27 };
458static const unsigned msp2_a_1_pins[] = { DB8500_PIN_AH27, DB8500_PIN_AF27,
459 DB8500_PIN_AG28, DB8500_PIN_AG26 };
460static const unsigned mc4_a_1_pins[] = { DB8500_PIN_AH24, DB8500_PIN_AG25,
461 DB8500_PIN_AH23, DB8500_PIN_AH26, DB8500_PIN_AF24, DB8500_PIN_AF25,
462 DB8500_PIN_AE23, DB8500_PIN_AF23, DB8500_PIN_AG23, DB8500_PIN_AG24,
463 DB8500_PIN_AJ23 };
464/* MC1 has only 4 data pins, designed for SD or SDIO exclusively */
465static const unsigned mc1_a_1_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AG15,
466 DB8500_PIN_AJ15, DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13,
467 DB8500_PIN_AH15 };
468static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
469 DB8500_PIN_AH12, DB8500_PIN_AH11 };
470static const unsigned hsir_a_1_pins[] = { DB8500_PIN_AG10, DB8500_PIN_AH10 };
471static const unsigned hsit_a_1_pins[] = { DB8500_PIN_AJ11, DB8500_PIN_AJ9,
472 DB8500_PIN_AH9, DB8500_PIN_AG9, DB8500_PIN_AG8, DB8500_PIN_AF8 };
473static const unsigned clkout_a_1_pins[] = { DB8500_PIN_AH7, DB8500_PIN_AJ6 };
474static const unsigned clkout_a_2_pins[] = { DB8500_PIN_AG7, DB8500_PIN_AF7 };
475static const unsigned usb_a_1_pins[] = { DB8500_PIN_AF28, DB8500_PIN_AE29,
476 DB8500_PIN_AD29, DB8500_PIN_AC29, DB8500_PIN_AD28, DB8500_PIN_AD26,
477 DB8500_PIN_AE26, DB8500_PIN_AG29, DB8500_PIN_AE27, DB8500_PIN_AD27,
478 DB8500_PIN_AC28, DB8500_PIN_AC27 };
479
480/* Altfunction B column */
481static const unsigned trig_b_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3 };
482static const unsigned i2c4_b_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 };
483static const unsigned i2c1_b_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 };
484static const unsigned i2c2_b_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 };
485static const unsigned i2c2_b_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 };
486static const unsigned msp0txrx_b_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 };
487static const unsigned i2c1_b_2_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 };
488/* Just RX and TX for UART2 */
489static const unsigned u2rxtx_b_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1 };
490static const unsigned uartmodtx_b_1_pins[] = { DB8500_PIN_AB4 };
491static const unsigned msp0sck_b_1_pins[] = { DB8500_PIN_AB3 };
492static const unsigned uartmodrx_b_1_pins[] = { DB8500_PIN_AA3 };
493static const unsigned stmmod_b_1_pins[] = { DB8500_PIN_AA4, DB8500_PIN_Y4,
494 DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 };
495static const unsigned uartmodrx_b_2_pins[] = { DB8500_PIN_AB2 };
496static const unsigned spi3_b_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3,
497 DB8500_PIN_V3, DB8500_PIN_V2 };
498static const unsigned msp1txrx_b_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 };
499static const unsigned kp_b_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1,
500 DB8500_PIN_G3, DB8500_PIN_G2, DB8500_PIN_E1, DB8500_PIN_E2,
501 DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3,
502 DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1,
503 DB8500_PIN_F4, DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2,
504 DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5 };
505static const unsigned sm_b_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
506 DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
507 DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8,
508 DB8500_PIN_D9, DB8500_PIN_A5, DB8500_PIN_B4, DB8500_PIN_C8,
509 DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10, DB8500_PIN_B9,
510 DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7, DB8500_PIN_C5,
511 DB8500_PIN_C9, DB8500_PIN_B14 };
512/* This chip select pin can be "ps0" in alt B so have it separately */
513static const unsigned smcs0_b_1_pins[] = { DB8500_PIN_E8 };
514static const unsigned ipgpio7_b_1_pins[] = { DB8500_PIN_B11 };
515static const unsigned ipgpio2_b_1_pins[] = { DB8500_PIN_C12 };
516static const unsigned ipgpio3_b_1_pins[] = { DB8500_PIN_C11 };
517static const unsigned lcdaclk_b_1_pins[] = { DB8500_PIN_C14 };
518static const unsigned lcda_b_1_pins[] = { DB8500_PIN_D22,
519 DB8500_PIN_C23, DB8500_PIN_D23 };
520static const unsigned lcd_b_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16,
521 DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17,
522 DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20,
523 DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21,
524 DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 };
525static const unsigned ddrtrig_b_1_pins[] = { DB8500_PIN_AJ27 };
526static const unsigned pwl_b_1_pins[] = { DB8500_PIN_AF25 };
527static const unsigned spi1_b_1_pins[] = { DB8500_PIN_AG15, DB8500_PIN_AF13,
528 DB8500_PIN_AG13, DB8500_PIN_AH15 };
529static const unsigned mc3_b_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
530 DB8500_PIN_AH12, DB8500_PIN_AH11, DB8500_PIN_AG10, DB8500_PIN_AH10,
531 DB8500_PIN_AJ11, DB8500_PIN_AJ9, DB8500_PIN_AH9, DB8500_PIN_AG9,
532 DB8500_PIN_AG8 };
533static const unsigned pwl_b_2_pins[] = { DB8500_PIN_AF8 };
534static const unsigned pwl_b_3_pins[] = { DB8500_PIN_AG7 };
535static const unsigned pwl_b_4_pins[] = { DB8500_PIN_AF7 };
536
537/* Altfunction C column */
538static const unsigned ipjtag_c_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3,
539 DB8500_PIN_AH4, DB8500_PIN_AH3, DB8500_PIN_AH6 };
540static const unsigned ipgpio6_c_1_pins[] = { DB8500_PIN_AG6 };
541static const unsigned ipgpio0_c_1_pins[] = { DB8500_PIN_AF6 };
542static const unsigned ipgpio1_c_1_pins[] = { DB8500_PIN_AG5 };
543static const unsigned ipgpio3_c_1_pins[] = { DB8500_PIN_AF5 };
544static const unsigned ipgpio2_c_1_pins[] = { DB8500_PIN_AG4 };
545static const unsigned slim0_c_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 };
546/* Optional 4-bit Memory Stick interface */
547static const unsigned ms_c_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1,
548 DB8500_PIN_AB3, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2,
549 DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 };
550static const unsigned iptrigout_c_1_pins[] = { DB8500_PIN_AB4 };
551static const unsigned u2rxtx_c_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3 };
552static const unsigned u2ctsrts_c_1_pins[] = { DB8500_PIN_V3, DB8500_PIN_V2 };
553static const unsigned u0_c_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AE1,
554 DB8500_PIN_AE2, DB8500_PIN_AG2 };
555static const unsigned ipgpio4_c_1_pins[] = { DB8500_PIN_F3 };
556static const unsigned ipgpio5_c_1_pins[] = { DB8500_PIN_F1 };
557static const unsigned ipgpio6_c_2_pins[] = { DB8500_PIN_G3 };
558static const unsigned ipgpio7_c_1_pins[] = { DB8500_PIN_G2 };
559static const unsigned smcleale_c_1_pins[] = { DB8500_PIN_E1, DB8500_PIN_E2 };
560static const unsigned stmape_c_1_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4,
561 DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3 };
562static const unsigned u2rxtx_c_2_pins[] = { DB8500_PIN_H2, DB8500_PIN_J2 };
563static const unsigned ipgpio2_c_2_pins[] = { DB8500_PIN_F4 };
564static const unsigned ipgpio3_c_2_pins[] = { DB8500_PIN_E3 };
565static const unsigned ipgpio4_c_2_pins[] = { DB8500_PIN_E4 };
566static const unsigned ipgpio5_c_2_pins[] = { DB8500_PIN_D2 };
567static const unsigned mc5_c_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
568 DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
569 DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8,
570 DB8500_PIN_D9 };
571static const unsigned mc2rstn_c_1_pins[] = { DB8500_PIN_C8 };
572static const unsigned kp_c_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11,
573 DB8500_PIN_C12, DB8500_PIN_C11, DB8500_PIN_D17, DB8500_PIN_D16,
574 DB8500_PIN_C23, DB8500_PIN_D23 };
575static const unsigned smps1_c_1_pins[] = { DB8500_PIN_B14 };
576static const unsigned u2rxtx_c_3_pins[] = { DB8500_PIN_B17, DB8500_PIN_C16 };
577static const unsigned stmape_c_2_pins[] = { DB8500_PIN_C19, DB8500_PIN_C17,
578 DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19 };
579static const unsigned uartmodrx_c_1_pins[] = { DB8500_PIN_D21 };
580static const unsigned uartmodtx_c_1_pins[] = { DB8500_PIN_D20 };
581static const unsigned stmmod_c_1_pins[] = { DB8500_PIN_C20, DB8500_PIN_B21,
582 DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24 };
583static const unsigned usbsim_c_1_pins[] = { DB8500_PIN_D22 };
584static const unsigned mc4rstn_c_1_pins[] = { DB8500_PIN_AF25 };
585static const unsigned clkout_c_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AH12 };
586static const unsigned i2c3_c_1_pins[] = { DB8500_PIN_AG12, DB8500_PIN_AH11 };
587static const unsigned spi0_c_1_pins[] = { DB8500_PIN_AH10, DB8500_PIN_AH9,
588 DB8500_PIN_AG9, DB8500_PIN_AG8 };
589static const unsigned usbsim_c_2_pins[] = { DB8500_PIN_AF8 };
590static const unsigned i2c3_c_2_pins[] = { DB8500_PIN_AG7, DB8500_PIN_AF7 };
591
592/* Other C1 column */
593static const unsigned kp_oc1_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
594 DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
595 DB8500_PIN_D6, DB8500_PIN_B7 };
596static const unsigned spi2_oc1_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
597 DB8500_PIN_AH12, DB8500_PIN_AH11 };
598
599#define DB8500_PIN_GROUP(a,b) { .name = #a, .pins = a##_pins, \
600 .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
601
602static const struct nmk_pingroup nmk_db8500_groups[] = {
603 /* Altfunction A column */
604 DB8500_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A),
605 DB8500_PIN_GROUP(u1rxtx_a_1, NMK_GPIO_ALT_A),
606 DB8500_PIN_GROUP(u1ctsrts_a_1, NMK_GPIO_ALT_A),
607 DB8500_PIN_GROUP(ipi2c_a_1, NMK_GPIO_ALT_A),
608 DB8500_PIN_GROUP(ipi2c_a_2, NMK_GPIO_ALT_A),
609 DB8500_PIN_GROUP(msp0txrx_a_1, NMK_GPIO_ALT_A),
610 DB8500_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A),
611 DB8500_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A),
612 DB8500_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A),
613 DB8500_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A),
614 DB8500_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A),
615 DB8500_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A),
616 DB8500_PIN_GROUP(lcdvsi0_a_1, NMK_GPIO_ALT_A),
617 DB8500_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A),
618 DB8500_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A),
619 DB8500_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A),
620 DB8500_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A),
621 DB8500_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A),
622 DB8500_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A),
623 DB8500_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A),
624 DB8500_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A),
625 DB8500_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
626 DB8500_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A),
627 DB8500_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A),
628 DB8500_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A),
629 DB8500_PIN_GROUP(msp2_a_1, NMK_GPIO_ALT_A),
630 DB8500_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A),
631 DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A),
632 DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A),
633 DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A),
634 DB8500_PIN_GROUP(clkout_a_1, NMK_GPIO_ALT_A),
635 DB8500_PIN_GROUP(clkout_a_2, NMK_GPIO_ALT_A),
636 DB8500_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A),
637 /* Altfunction B column */
638 DB8500_PIN_GROUP(trig_b_1, NMK_GPIO_ALT_B),
639 DB8500_PIN_GROUP(i2c4_b_1, NMK_GPIO_ALT_B),
640 DB8500_PIN_GROUP(i2c1_b_1, NMK_GPIO_ALT_B),
641 DB8500_PIN_GROUP(i2c2_b_1, NMK_GPIO_ALT_B),
642 DB8500_PIN_GROUP(i2c2_b_2, NMK_GPIO_ALT_B),
643 DB8500_PIN_GROUP(msp0txrx_b_1, NMK_GPIO_ALT_B),
644 DB8500_PIN_GROUP(i2c1_b_2, NMK_GPIO_ALT_B),
645 DB8500_PIN_GROUP(u2rxtx_b_1, NMK_GPIO_ALT_B),
646 DB8500_PIN_GROUP(uartmodtx_b_1, NMK_GPIO_ALT_B),
647 DB8500_PIN_GROUP(msp0sck_b_1, NMK_GPIO_ALT_B),
648 DB8500_PIN_GROUP(uartmodrx_b_1, NMK_GPIO_ALT_B),
649 DB8500_PIN_GROUP(stmmod_b_1, NMK_GPIO_ALT_B),
650 DB8500_PIN_GROUP(uartmodrx_b_2, NMK_GPIO_ALT_B),
651 DB8500_PIN_GROUP(spi3_b_1, NMK_GPIO_ALT_B),
652 DB8500_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B),
653 DB8500_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B),
654 DB8500_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B),
655 DB8500_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B),
656 DB8500_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B),
657 DB8500_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B),
658 DB8500_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B),
659 DB8500_PIN_GROUP(lcdaclk_b_1, NMK_GPIO_ALT_B),
660 DB8500_PIN_GROUP(lcda_b_1, NMK_GPIO_ALT_B),
661 DB8500_PIN_GROUP(lcd_b_1, NMK_GPIO_ALT_B),
662 DB8500_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B),
663 DB8500_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B),
664 DB8500_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B),
665 DB8500_PIN_GROUP(mc3_b_1, NMK_GPIO_ALT_B),
666 DB8500_PIN_GROUP(pwl_b_2, NMK_GPIO_ALT_B),
667 DB8500_PIN_GROUP(pwl_b_3, NMK_GPIO_ALT_B),
668 DB8500_PIN_GROUP(pwl_b_4, NMK_GPIO_ALT_B),
669 /* Altfunction C column */
670 DB8500_PIN_GROUP(ipjtag_c_1, NMK_GPIO_ALT_C),
671 DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C),
672 DB8500_PIN_GROUP(ipgpio0_c_1, NMK_GPIO_ALT_C),
673 DB8500_PIN_GROUP(ipgpio1_c_1, NMK_GPIO_ALT_C),
674 DB8500_PIN_GROUP(ipgpio3_c_1, NMK_GPIO_ALT_C),
675 DB8500_PIN_GROUP(ipgpio2_c_1, NMK_GPIO_ALT_C),
676 DB8500_PIN_GROUP(slim0_c_1, NMK_GPIO_ALT_C),
677 DB8500_PIN_GROUP(ms_c_1, NMK_GPIO_ALT_C),
678 DB8500_PIN_GROUP(iptrigout_c_1, NMK_GPIO_ALT_C),
679 DB8500_PIN_GROUP(u2rxtx_c_1, NMK_GPIO_ALT_C),
680 DB8500_PIN_GROUP(u2ctsrts_c_1, NMK_GPIO_ALT_C),
681 DB8500_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C),
682 DB8500_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C),
683 DB8500_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C),
684 DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C),
685 DB8500_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C),
686 DB8500_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C),
687 DB8500_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C),
688 DB8500_PIN_GROUP(u2rxtx_c_2, NMK_GPIO_ALT_C),
689 DB8500_PIN_GROUP(ipgpio2_c_2, NMK_GPIO_ALT_C),
690 DB8500_PIN_GROUP(ipgpio3_c_2, NMK_GPIO_ALT_C),
691 DB8500_PIN_GROUP(ipgpio4_c_2, NMK_GPIO_ALT_C),
692 DB8500_PIN_GROUP(ipgpio5_c_2, NMK_GPIO_ALT_C),
693 DB8500_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C),
694 DB8500_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C),
695 DB8500_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C),
696 DB8500_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C),
697 DB8500_PIN_GROUP(u2rxtx_c_3, NMK_GPIO_ALT_C),
698 DB8500_PIN_GROUP(stmape_c_2, NMK_GPIO_ALT_C),
699 DB8500_PIN_GROUP(uartmodrx_c_1, NMK_GPIO_ALT_C),
700 DB8500_PIN_GROUP(uartmodtx_c_1, NMK_GPIO_ALT_C),
701 DB8500_PIN_GROUP(stmmod_c_1, NMK_GPIO_ALT_C),
702 DB8500_PIN_GROUP(usbsim_c_1, NMK_GPIO_ALT_C),
703 DB8500_PIN_GROUP(mc4rstn_c_1, NMK_GPIO_ALT_C),
704 DB8500_PIN_GROUP(clkout_c_1, NMK_GPIO_ALT_C),
705 DB8500_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C),
706 DB8500_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C),
707 DB8500_PIN_GROUP(usbsim_c_2, NMK_GPIO_ALT_C),
708 DB8500_PIN_GROUP(i2c3_c_2, NMK_GPIO_ALT_C),
709 /* Other alt C1 column, these are still configured as alt C */
710 DB8500_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C),
711 DB8500_PIN_GROUP(spi2_oc1_1, NMK_GPIO_ALT_C),
712};
713
714/* We use this macro to define the groups applicable to a function */
715#define DB8500_FUNC_GROUPS(a, b...) \
716static const char * const a##_groups[] = { b };
717
718DB8500_FUNC_GROUPS(u0, "u0_a_1", "u0_c_1");
719DB8500_FUNC_GROUPS(u1, "u1rxtx_a_1", "u1ctsrts_a_1");
720/*
721 * UART2 can be muxed out with just RX/TX in four places, CTS+RTS is however
722 * only available on two pins in alternative function C
723 */
724DB8500_FUNC_GROUPS(u2, "u2rxtx_b_1", "u2rxtx_c_1", "u2ctsrts_c_1",
725 "u2rxtx_c_2", "u2rxtx_c_3");
726DB8500_FUNC_GROUPS(ipi2c, "ipi2c_a_1", "ipi2c_a_2");
727/*
728 * MSP0 can only be on a certain set of pins, but the TX/RX pins can be
729 * switched around by selecting the altfunction A or B. The SCK pin is
730 * only available on the altfunction B.
731 */
732DB8500_FUNC_GROUPS(msp0, "msp0txrx_a_1", "msp0tfstck_a_1", "msp0rfstck_a_1",
733 "msp0txrx_b_1", "msp0sck_b_1");
734DB8500_FUNC_GROUPS(mc0, "mc0_a_1");
735/* MSP0 can swap RX/TX like MSP0 but has no SCK pin available */
736DB8500_FUNC_GROUPS(msp1, "msp1txrx_a_1", "msp1_a_1", "msp1txrx_b_1");
737DB8500_FUNC_GROUPS(lcdb, "lcdb_a_1");
738DB8500_FUNC_GROUPS(lcd, "lcdvsi0_a_1", "lcdvsi1_a_1", "lcd_d0_d7_a_1",
739 "lcd_d8_d11_a_1", "lcd_d12_d23_a_1", "lcd_b_1");
740DB8500_FUNC_GROUPS(kp, "kp_a_1", "kp_b_1", "kp_c_1", "kp_oc1_1");
741DB8500_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1");
742DB8500_FUNC_GROUPS(ssp1, "ssp1_a_1");
743DB8500_FUNC_GROUPS(ssp0, "ssp0_a_1");
744DB8500_FUNC_GROUPS(i2c0, "i2c0_a_1");
745/* The image processor has 8 GPIO pins that can be muxed out */
746DB8500_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio1_a_1", "ipgpio7_b_1",
747 "ipgpio2_b_1", "ipgpio3_b_1", "ipgpio6_c_1", "ipgpio0_c_1",
748 "ipgpio1_c_1", "ipgpio3_c_1", "ipgpio2_c_1", "ipgpio4_c_1",
749 "ipgpio5_c_1", "ipgpio6_c_2", "ipgpio7_c_1", "ipgpio2_c_2",
750 "ipgpio3_c_2", "ipgpio4_c_2", "ipgpio5_c_2");
751/* MSP2 can not invert the RX/TX pins but has the optional SCK pin */
752DB8500_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2_a_1");
753DB8500_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1");
754DB8500_FUNC_GROUPS(mc1, "mc1_a_1", "mc1dir_a_1");
755DB8500_FUNC_GROUPS(hsi, "hsir1_a_1", "hsit1_a_1");
756DB8500_FUNC_GROUPS(clkout, "clkout_a_1", "clkout_a_2", "clkout_c_1");
757DB8500_FUNC_GROUPS(usb, "usb_a_1");
758DB8500_FUNC_GROUPS(trig, "trig_b_1");
759DB8500_FUNC_GROUPS(i2c4, "i2c4_b_1");
760DB8500_FUNC_GROUPS(i2c1, "i2c1_b_1", "i2c1_b_2");
761DB8500_FUNC_GROUPS(i2c2, "i2c2_b_1", "i2c2_b_2");
762/*
763 * The modem UART can output its RX and TX pins in some different places,
764 * so select one of each.
765 */
766DB8500_FUNC_GROUPS(uartmod, "uartmodtx_b_1", "uartmodrx_b_1", "uartmodrx_b_2",
767 "uartmodrx_c_1", "uartmod_tx_c_1");
768DB8500_FUNC_GROUPS(stmmod, "stmmod_b_1", "stmmod_c_1");
769DB8500_FUNC_GROUPS(spi3, "spi3_b_1");
770/* Select between CS0 on alt B or PS1 on alt C */
771DB8500_FUNC_GROUPS(sm, "sm_b_1", "smcs0_b_1", "smcleale_c_1", "smps1_c_1");
772DB8500_FUNC_GROUPS(lcda, "lcdaclk_b_1", "lcda_b_1");
773DB8500_FUNC_GROUPS(ddrtrig, "ddrtrig_b_1");
774DB8500_FUNC_GROUPS(pwl, "pwl_b_1", "pwl_b_2", "pwl_b_3", "pwl_b_4");
775DB8500_FUNC_GROUPS(spi1, "spi1_b_1");
776DB8500_FUNC_GROUPS(mc3, "mc3_b_1");
777DB8500_FUNC_GROUPS(ipjtag, "ipjtag_c_1");
778DB8500_FUNC_GROUPS(slim0, "slim0_c_1");
779DB8500_FUNC_GROUPS(ms, "ms_c_1");
780DB8500_FUNC_GROUPS(iptrigout, "iptrigout_c_1");
781DB8500_FUNC_GROUPS(stmape, "stmape_c_1", "stmape_c_2");
782DB8500_FUNC_GROUPS(mc5, "mc5_c_1");
783DB8500_FUNC_GROUPS(usbsim, "usbsim_c_1", "usbsim_c_2");
784DB8500_FUNC_GROUPS(i2c3, "i2c3_c_1", "i2c3_c_2");
785DB8500_FUNC_GROUPS(spi0, "spi0_c_1");
786DB8500_FUNC_GROUPS(spi2, "spi2_oc1_1");
787
788#define FUNCTION(fname) \
789 { \
790 .name = #fname, \
791 .groups = fname##_groups, \
792 .ngroups = ARRAY_SIZE(fname##_groups), \
793 }
794
795static const struct nmk_function nmk_db8500_functions[] = {
796 FUNCTION(u0),
797 FUNCTION(u1),
798 FUNCTION(u2),
799 FUNCTION(ipi2c),
800 FUNCTION(msp0),
801 FUNCTION(mc0),
802 FUNCTION(msp1),
803 FUNCTION(lcdb),
804 FUNCTION(lcd),
805 FUNCTION(kp),
806 FUNCTION(mc2),
807 FUNCTION(ssp1),
808 FUNCTION(ssp0),
809 FUNCTION(i2c0),
810 FUNCTION(ipgpio),
811 FUNCTION(msp2),
812 FUNCTION(mc4),
813 FUNCTION(mc1),
814 FUNCTION(hsi),
815 FUNCTION(clkout),
816 FUNCTION(usb),
817 FUNCTION(trig),
818 FUNCTION(i2c4),
819 FUNCTION(i2c1),
820 FUNCTION(i2c2),
821 FUNCTION(uartmod),
822 FUNCTION(stmmod),
823 FUNCTION(spi3),
824 FUNCTION(sm),
825 FUNCTION(lcda),
826 FUNCTION(ddrtrig),
827 FUNCTION(pwl),
828 FUNCTION(spi1),
829 FUNCTION(mc3),
830 FUNCTION(ipjtag),
831 FUNCTION(slim0),
832 FUNCTION(ms),
833 FUNCTION(iptrigout),
834 FUNCTION(stmape),
835 FUNCTION(mc5),
836 FUNCTION(usbsim),
837 FUNCTION(i2c3),
838 FUNCTION(spi0),
839 FUNCTION(spi2),
840};
841
842static const struct nmk_pinctrl_soc_data nmk_db8500_soc = {
843 .gpio_ranges = nmk_db8500_ranges,
844 .gpio_num_ranges = ARRAY_SIZE(nmk_db8500_ranges),
845 .pins = nmk_db8500_pins,
846 .npins = ARRAY_SIZE(nmk_db8500_pins),
847 .functions = nmk_db8500_functions,
848 .nfunctions = ARRAY_SIZE(nmk_db8500_functions),
849 .groups = nmk_db8500_groups,
850 .ngroups = ARRAY_SIZE(nmk_db8500_groups),
851};
852
853void __devinit
854nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
855{
856 *soc = &nmk_db8500_soc;
857}
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
new file mode 100644
index 00000000000..b8e01c3eaa9
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -0,0 +1,1780 @@
1/*
2 * Generic GPIO driver for logic cells found in the Nomadik SoC
3 *
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/device.h>
17#include <linux/platform_device.h>
18#include <linux/io.h>
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/gpio.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/irqdomain.h>
26#include <linux/slab.h>
27#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/pinmux.h>
29#include <linux/pinctrl/pinconf.h>
30/* Since we request GPIOs from ourself */
31#include <linux/pinctrl/consumer.h>
32
33#include <asm/mach/irq.h>
34
35#include <plat/pincfg.h>
36#include <plat/gpio-nomadik.h>
37
38#include "pinctrl-nomadik.h"
39
40/*
41 * The GPIO module in the Nomadik family of Systems-on-Chip is an
42 * AMBA device, managing 32 pins and alternate functions. The logic block
43 * is currently used in the Nomadik and ux500.
44 *
45 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
46 */
47
48#define NMK_GPIO_PER_CHIP 32
49
50struct nmk_gpio_chip {
51 struct gpio_chip chip;
52 struct irq_domain *domain;
53 void __iomem *addr;
54 struct clk *clk;
55 unsigned int bank;
56 unsigned int parent_irq;
57 int secondary_parent_irq;
58 u32 (*get_secondary_status)(unsigned int bank);
59 void (*set_ioforce)(bool enable);
60 spinlock_t lock;
61 bool sleepmode;
62 /* Keep track of configured edges */
63 u32 edge_rising;
64 u32 edge_falling;
65 u32 real_wake;
66 u32 rwimsc;
67 u32 fwimsc;
68 u32 rimsc;
69 u32 fimsc;
70 u32 pull_up;
71 u32 lowemi;
72};
73
74struct nmk_pinctrl {
75 struct device *dev;
76 struct pinctrl_dev *pctl;
77 const struct nmk_pinctrl_soc_data *soc;
78};
79
80static struct nmk_gpio_chip *
81nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
82
83static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
84
85#define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
86
87static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
88 unsigned offset, int gpio_mode)
89{
90 u32 bit = 1 << offset;
91 u32 afunc, bfunc;
92
93 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
94 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
95 if (gpio_mode & NMK_GPIO_ALT_A)
96 afunc |= bit;
97 if (gpio_mode & NMK_GPIO_ALT_B)
98 bfunc |= bit;
99 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
100 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
101}
102
103static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
104 unsigned offset, enum nmk_gpio_slpm mode)
105{
106 u32 bit = 1 << offset;
107 u32 slpm;
108
109 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
110 if (mode == NMK_GPIO_SLPM_NOCHANGE)
111 slpm |= bit;
112 else
113 slpm &= ~bit;
114 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
115}
116
117static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
118 unsigned offset, enum nmk_gpio_pull pull)
119{
120 u32 bit = 1 << offset;
121 u32 pdis;
122
123 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
124 if (pull == NMK_GPIO_PULL_NONE) {
125 pdis |= bit;
126 nmk_chip->pull_up &= ~bit;
127 } else {
128 pdis &= ~bit;
129 }
130
131 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
132
133 if (pull == NMK_GPIO_PULL_UP) {
134 nmk_chip->pull_up |= bit;
135 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
136 } else if (pull == NMK_GPIO_PULL_DOWN) {
137 nmk_chip->pull_up &= ~bit;
138 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
139 }
140}
141
142static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
143 unsigned offset, bool lowemi)
144{
145 u32 bit = BIT(offset);
146 bool enabled = nmk_chip->lowemi & bit;
147
148 if (lowemi == enabled)
149 return;
150
151 if (lowemi)
152 nmk_chip->lowemi |= bit;
153 else
154 nmk_chip->lowemi &= ~bit;
155
156 writel_relaxed(nmk_chip->lowemi,
157 nmk_chip->addr + NMK_GPIO_LOWEMI);
158}
159
160static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
161 unsigned offset)
162{
163 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
164}
165
166static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
167 unsigned offset, int val)
168{
169 if (val)
170 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
171 else
172 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
173}
174
175static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
176 unsigned offset, int val)
177{
178 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
179 __nmk_gpio_set_output(nmk_chip, offset, val);
180}
181
182static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
183 unsigned offset, int gpio_mode,
184 bool glitch)
185{
186 u32 rwimsc = nmk_chip->rwimsc;
187 u32 fwimsc = nmk_chip->fwimsc;
188
189 if (glitch && nmk_chip->set_ioforce) {
190 u32 bit = BIT(offset);
191
192 /* Prevent spurious wakeups */
193 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
194 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
195
196 nmk_chip->set_ioforce(true);
197 }
198
199 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
200
201 if (glitch && nmk_chip->set_ioforce) {
202 nmk_chip->set_ioforce(false);
203
204 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
205 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
206 }
207}
208
209static void
210nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
211{
212 u32 falling = nmk_chip->fimsc & BIT(offset);
213 u32 rising = nmk_chip->rimsc & BIT(offset);
214 int gpio = nmk_chip->chip.base + offset;
215 int irq = NOMADIK_GPIO_TO_IRQ(gpio);
216 struct irq_data *d = irq_get_irq_data(irq);
217
218 if (!rising && !falling)
219 return;
220
221 if (!d || !irqd_irq_disabled(d))
222 return;
223
224 if (rising) {
225 nmk_chip->rimsc &= ~BIT(offset);
226 writel_relaxed(nmk_chip->rimsc,
227 nmk_chip->addr + NMK_GPIO_RIMSC);
228 }
229
230 if (falling) {
231 nmk_chip->fimsc &= ~BIT(offset);
232 writel_relaxed(nmk_chip->fimsc,
233 nmk_chip->addr + NMK_GPIO_FIMSC);
234 }
235
236 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
237}
238
239static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
240 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
241{
242 static const char *afnames[] = {
243 [NMK_GPIO_ALT_GPIO] = "GPIO",
244 [NMK_GPIO_ALT_A] = "A",
245 [NMK_GPIO_ALT_B] = "B",
246 [NMK_GPIO_ALT_C] = "C"
247 };
248 static const char *pullnames[] = {
249 [NMK_GPIO_PULL_NONE] = "none",
250 [NMK_GPIO_PULL_UP] = "up",
251 [NMK_GPIO_PULL_DOWN] = "down",
252 [3] /* illegal */ = "??"
253 };
254 static const char *slpmnames[] = {
255 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
256 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
257 };
258
259 int pin = PIN_NUM(cfg);
260 int pull = PIN_PULL(cfg);
261 int af = PIN_ALT(cfg);
262 int slpm = PIN_SLPM(cfg);
263 int output = PIN_DIR(cfg);
264 int val = PIN_VAL(cfg);
265 bool glitch = af == NMK_GPIO_ALT_C;
266
267 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
268 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
269 output ? "output " : "input",
270 output ? (val ? "high" : "low") : "");
271
272 if (sleep) {
273 int slpm_pull = PIN_SLPM_PULL(cfg);
274 int slpm_output = PIN_SLPM_DIR(cfg);
275 int slpm_val = PIN_SLPM_VAL(cfg);
276
277 af = NMK_GPIO_ALT_GPIO;
278
279 /*
280 * The SLPM_* values are normal values + 1 to allow zero to
281 * mean "same as normal".
282 */
283 if (slpm_pull)
284 pull = slpm_pull - 1;
285 if (slpm_output)
286 output = slpm_output - 1;
287 if (slpm_val)
288 val = slpm_val - 1;
289
290 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
291 pin,
292 slpm_pull ? pullnames[pull] : "same",
293 slpm_output ? (output ? "output" : "input") : "same",
294 slpm_val ? (val ? "high" : "low") : "same");
295 }
296
297 if (output)
298 __nmk_gpio_make_output(nmk_chip, offset, val);
299 else {
300 __nmk_gpio_make_input(nmk_chip, offset);
301 __nmk_gpio_set_pull(nmk_chip, offset, pull);
302 }
303
304 __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg));
305
306 /*
307 * If the pin is switching to altfunc, and there was an interrupt
308 * installed on it which has been lazy disabled, actually mask the
309 * interrupt to prevent spurious interrupts that would occur while the
310 * pin is under control of the peripheral. Only SKE does this.
311 */
312 if (af != NMK_GPIO_ALT_GPIO)
313 nmk_gpio_disable_lazy_irq(nmk_chip, offset);
314
315 /*
316 * If we've backed up the SLPM registers (glitch workaround), modify
317 * the backups since they will be restored.
318 */
319 if (slpmregs) {
320 if (slpm == NMK_GPIO_SLPM_NOCHANGE)
321 slpmregs[nmk_chip->bank] |= BIT(offset);
322 else
323 slpmregs[nmk_chip->bank] &= ~BIT(offset);
324 } else
325 __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
326
327 __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
328}
329
330/*
331 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
332 * - Save SLPM registers
333 * - Set SLPM=0 for the IOs you want to switch and others to 1
334 * - Configure the GPIO registers for the IOs that are being switched
335 * - Set IOFORCE=1
336 * - Modify the AFLSA/B registers for the IOs that are being switched
337 * - Set IOFORCE=0
338 * - Restore SLPM registers
339 * - Any spurious wake up event during switch sequence to be ignored and
340 * cleared
341 */
342static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
343{
344 int i;
345
346 for (i = 0; i < NUM_BANKS; i++) {
347 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
348 unsigned int temp = slpm[i];
349
350 if (!chip)
351 break;
352
353 clk_enable(chip->clk);
354
355 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
356 writel(temp, chip->addr + NMK_GPIO_SLPC);
357 }
358}
359
360static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
361{
362 int i;
363
364 for (i = 0; i < NUM_BANKS; i++) {
365 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
366
367 if (!chip)
368 break;
369
370 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
371
372 clk_disable(chip->clk);
373 }
374}
375
376static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
377{
378 static unsigned int slpm[NUM_BANKS];
379 unsigned long flags;
380 bool glitch = false;
381 int ret = 0;
382 int i;
383
384 for (i = 0; i < num; i++) {
385 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
386 glitch = true;
387 break;
388 }
389 }
390
391 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
392
393 if (glitch) {
394 memset(slpm, 0xff, sizeof(slpm));
395
396 for (i = 0; i < num; i++) {
397 int pin = PIN_NUM(cfgs[i]);
398 int offset = pin % NMK_GPIO_PER_CHIP;
399
400 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
401 slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
402 }
403
404 nmk_gpio_glitch_slpm_init(slpm);
405 }
406
407 for (i = 0; i < num; i++) {
408 struct nmk_gpio_chip *nmk_chip;
409 int pin = PIN_NUM(cfgs[i]);
410
411 nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP];
412 if (!nmk_chip) {
413 ret = -EINVAL;
414 break;
415 }
416
417 clk_enable(nmk_chip->clk);
418 spin_lock(&nmk_chip->lock);
419 __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP,
420 cfgs[i], sleep, glitch ? slpm : NULL);
421 spin_unlock(&nmk_chip->lock);
422 clk_disable(nmk_chip->clk);
423 }
424
425 if (glitch)
426 nmk_gpio_glitch_slpm_restore(slpm);
427
428 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
429
430 return ret;
431}
432
433/**
434 * nmk_config_pin - configure a pin's mux attributes
435 * @cfg: pin confguration
436 *
437 * Configures a pin's mode (alternate function or GPIO), its pull up status,
438 * and its sleep mode based on the specified configuration. The @cfg is
439 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
440 * are constructed using, and can be further enhanced with, the macros in
441 * plat/pincfg.h.
442 *
443 * If a pin's mode is set to GPIO, it is configured as an input to avoid
444 * side-effects. The gpio can be manipulated later using standard GPIO API
445 * calls.
446 */
447int nmk_config_pin(pin_cfg_t cfg, bool sleep)
448{
449 return __nmk_config_pins(&cfg, 1, sleep);
450}
451EXPORT_SYMBOL(nmk_config_pin);
452
453/**
454 * nmk_config_pins - configure several pins at once
455 * @cfgs: array of pin configurations
456 * @num: number of elments in the array
457 *
458 * Configures several pins using nmk_config_pin(). Refer to that function for
459 * further information.
460 */
461int nmk_config_pins(pin_cfg_t *cfgs, int num)
462{
463 return __nmk_config_pins(cfgs, num, false);
464}
465EXPORT_SYMBOL(nmk_config_pins);
466
467int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
468{
469 return __nmk_config_pins(cfgs, num, true);
470}
471EXPORT_SYMBOL(nmk_config_pins_sleep);
472
473/**
474 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
475 * @gpio: pin number
476 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
477 *
478 * This register is actually in the pinmux layer, not the GPIO block itself.
479 * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP
480 * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code).
481 * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is
482 * HIGH, overriding the normal setting defined by GPIO_AFSELx registers.
483 * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit),
484 * the GPIOs return to the normal setting defined by GPIO_AFSELx registers.
485 *
486 * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO
487 * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is
488 * entered) regardless of the altfunction selected. Also wake-up detection is
489 * ENABLED.
490 *
491 * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains
492 * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS
493 * (for altfunction GPIO) or respective on-chip peripherals (for other
494 * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED.
495 *
496 * Note that enable_irq_wake() will automatically enable wakeup detection.
497 */
498int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
499{
500 struct nmk_gpio_chip *nmk_chip;
501 unsigned long flags;
502
503 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
504 if (!nmk_chip)
505 return -EINVAL;
506
507 clk_enable(nmk_chip->clk);
508 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
509 spin_lock(&nmk_chip->lock);
510
511 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode);
512
513 spin_unlock(&nmk_chip->lock);
514 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
515 clk_disable(nmk_chip->clk);
516
517 return 0;
518}
519
520/**
521 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
522 * @gpio: pin number
523 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
524 *
525 * Enables/disables pull up/down on a specified pin. This only takes effect if
526 * the pin is configured as an input (either explicitly or by the alternate
527 * function).
528 *
529 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
530 * configured as an input. Otherwise, due to the way the controller registers
531 * work, this function will change the value output on the pin.
532 */
533int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
534{
535 struct nmk_gpio_chip *nmk_chip;
536 unsigned long flags;
537
538 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
539 if (!nmk_chip)
540 return -EINVAL;
541
542 clk_enable(nmk_chip->clk);
543 spin_lock_irqsave(&nmk_chip->lock, flags);
544 __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull);
545 spin_unlock_irqrestore(&nmk_chip->lock, flags);
546 clk_disable(nmk_chip->clk);
547
548 return 0;
549}
550
551/* Mode functions */
552/**
553 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
554 * @gpio: pin number
555 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
556 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
557 *
558 * Sets the mode of the specified pin to one of the alternate functions or
559 * plain GPIO.
560 */
561int nmk_gpio_set_mode(int gpio, int gpio_mode)
562{
563 struct nmk_gpio_chip *nmk_chip;
564 unsigned long flags;
565
566 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
567 if (!nmk_chip)
568 return -EINVAL;
569
570 clk_enable(nmk_chip->clk);
571 spin_lock_irqsave(&nmk_chip->lock, flags);
572 __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode);
573 spin_unlock_irqrestore(&nmk_chip->lock, flags);
574 clk_disable(nmk_chip->clk);
575
576 return 0;
577}
578EXPORT_SYMBOL(nmk_gpio_set_mode);
579
580int nmk_gpio_get_mode(int gpio)
581{
582 struct nmk_gpio_chip *nmk_chip;
583 u32 afunc, bfunc, bit;
584
585 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
586 if (!nmk_chip)
587 return -EINVAL;
588
589 bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
590
591 clk_enable(nmk_chip->clk);
592
593 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
594 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
595
596 clk_disable(nmk_chip->clk);
597
598 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
599}
600EXPORT_SYMBOL(nmk_gpio_get_mode);
601
602
603/* IRQ functions */
604static inline int nmk_gpio_get_bitmask(int gpio)
605{
606 return 1 << (gpio % NMK_GPIO_PER_CHIP);
607}
608
609static void nmk_gpio_irq_ack(struct irq_data *d)
610{
611 struct nmk_gpio_chip *nmk_chip;
612
613 nmk_chip = irq_data_get_irq_chip_data(d);
614 if (!nmk_chip)
615 return;
616
617 clk_enable(nmk_chip->clk);
618 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
619 clk_disable(nmk_chip->clk);
620}
621
622enum nmk_gpio_irq_type {
623 NORMAL,
624 WAKE,
625};
626
627static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
628 int gpio, enum nmk_gpio_irq_type which,
629 bool enable)
630{
631 u32 bitmask = nmk_gpio_get_bitmask(gpio);
632 u32 *rimscval;
633 u32 *fimscval;
634 u32 rimscreg;
635 u32 fimscreg;
636
637 if (which == NORMAL) {
638 rimscreg = NMK_GPIO_RIMSC;
639 fimscreg = NMK_GPIO_FIMSC;
640 rimscval = &nmk_chip->rimsc;
641 fimscval = &nmk_chip->fimsc;
642 } else {
643 rimscreg = NMK_GPIO_RWIMSC;
644 fimscreg = NMK_GPIO_FWIMSC;
645 rimscval = &nmk_chip->rwimsc;
646 fimscval = &nmk_chip->fwimsc;
647 }
648
649 /* we must individually set/clear the two edges */
650 if (nmk_chip->edge_rising & bitmask) {
651 if (enable)
652 *rimscval |= bitmask;
653 else
654 *rimscval &= ~bitmask;
655 writel(*rimscval, nmk_chip->addr + rimscreg);
656 }
657 if (nmk_chip->edge_falling & bitmask) {
658 if (enable)
659 *fimscval |= bitmask;
660 else
661 *fimscval &= ~bitmask;
662 writel(*fimscval, nmk_chip->addr + fimscreg);
663 }
664}
665
666static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
667 int gpio, bool on)
668{
669 /*
670 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
671 * disabled, since setting SLPM to 1 increases power consumption, and
672 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
673 */
674 if (nmk_chip->sleepmode && on) {
675 __nmk_gpio_set_slpm(nmk_chip, gpio % nmk_chip->chip.base,
676 NMK_GPIO_SLPM_WAKEUP_ENABLE);
677 }
678
679 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
680}
681
682static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
683{
684 struct nmk_gpio_chip *nmk_chip;
685 unsigned long flags;
686 u32 bitmask;
687
688 nmk_chip = irq_data_get_irq_chip_data(d);
689 bitmask = nmk_gpio_get_bitmask(d->hwirq);
690 if (!nmk_chip)
691 return -EINVAL;
692
693 clk_enable(nmk_chip->clk);
694 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
695 spin_lock(&nmk_chip->lock);
696
697 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
698
699 if (!(nmk_chip->real_wake & bitmask))
700 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
701
702 spin_unlock(&nmk_chip->lock);
703 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
704 clk_disable(nmk_chip->clk);
705
706 return 0;
707}
708
709static void nmk_gpio_irq_mask(struct irq_data *d)
710{
711 nmk_gpio_irq_maskunmask(d, false);
712}
713
714static void nmk_gpio_irq_unmask(struct irq_data *d)
715{
716 nmk_gpio_irq_maskunmask(d, true);
717}
718
719static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
720{
721 struct nmk_gpio_chip *nmk_chip;
722 unsigned long flags;
723 u32 bitmask;
724
725 nmk_chip = irq_data_get_irq_chip_data(d);
726 if (!nmk_chip)
727 return -EINVAL;
728 bitmask = nmk_gpio_get_bitmask(d->hwirq);
729
730 clk_enable(nmk_chip->clk);
731 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
732 spin_lock(&nmk_chip->lock);
733
734 if (irqd_irq_disabled(d))
735 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
736
737 if (on)
738 nmk_chip->real_wake |= bitmask;
739 else
740 nmk_chip->real_wake &= ~bitmask;
741
742 spin_unlock(&nmk_chip->lock);
743 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
744 clk_disable(nmk_chip->clk);
745
746 return 0;
747}
748
749static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
750{
751 bool enabled = !irqd_irq_disabled(d);
752 bool wake = irqd_is_wakeup_set(d);
753 struct nmk_gpio_chip *nmk_chip;
754 unsigned long flags;
755 u32 bitmask;
756
757 nmk_chip = irq_data_get_irq_chip_data(d);
758 bitmask = nmk_gpio_get_bitmask(d->hwirq);
759 if (!nmk_chip)
760 return -EINVAL;
761 if (type & IRQ_TYPE_LEVEL_HIGH)
762 return -EINVAL;
763 if (type & IRQ_TYPE_LEVEL_LOW)
764 return -EINVAL;
765
766 clk_enable(nmk_chip->clk);
767 spin_lock_irqsave(&nmk_chip->lock, flags);
768
769 if (enabled)
770 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
771
772 if (enabled || wake)
773 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
774
775 nmk_chip->edge_rising &= ~bitmask;
776 if (type & IRQ_TYPE_EDGE_RISING)
777 nmk_chip->edge_rising |= bitmask;
778
779 nmk_chip->edge_falling &= ~bitmask;
780 if (type & IRQ_TYPE_EDGE_FALLING)
781 nmk_chip->edge_falling |= bitmask;
782
783 if (enabled)
784 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
785
786 if (enabled || wake)
787 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
788
789 spin_unlock_irqrestore(&nmk_chip->lock, flags);
790 clk_disable(nmk_chip->clk);
791
792 return 0;
793}
794
795static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
796{
797 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
798
799 clk_enable(nmk_chip->clk);
800 nmk_gpio_irq_unmask(d);
801 return 0;
802}
803
804static void nmk_gpio_irq_shutdown(struct irq_data *d)
805{
806 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
807
808 nmk_gpio_irq_mask(d);
809 clk_disable(nmk_chip->clk);
810}
811
812static struct irq_chip nmk_gpio_irq_chip = {
813 .name = "Nomadik-GPIO",
814 .irq_ack = nmk_gpio_irq_ack,
815 .irq_mask = nmk_gpio_irq_mask,
816 .irq_unmask = nmk_gpio_irq_unmask,
817 .irq_set_type = nmk_gpio_irq_set_type,
818 .irq_set_wake = nmk_gpio_irq_set_wake,
819 .irq_startup = nmk_gpio_irq_startup,
820 .irq_shutdown = nmk_gpio_irq_shutdown,
821};
822
823static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
824 u32 status)
825{
826 struct nmk_gpio_chip *nmk_chip;
827 struct irq_chip *host_chip = irq_get_chip(irq);
828 unsigned int first_irq;
829
830 chained_irq_enter(host_chip, desc);
831
832 nmk_chip = irq_get_handler_data(irq);
833 first_irq = nmk_chip->domain->revmap_data.legacy.first_irq;
834 while (status) {
835 int bit = __ffs(status);
836
837 generic_handle_irq(first_irq + bit);
838 status &= ~BIT(bit);
839 }
840
841 chained_irq_exit(host_chip, desc);
842}
843
844static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
845{
846 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
847 u32 status;
848
849 clk_enable(nmk_chip->clk);
850 status = readl(nmk_chip->addr + NMK_GPIO_IS);
851 clk_disable(nmk_chip->clk);
852
853 __nmk_gpio_irq_handler(irq, desc, status);
854}
855
856static void nmk_gpio_secondary_irq_handler(unsigned int irq,
857 struct irq_desc *desc)
858{
859 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
860 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
861
862 __nmk_gpio_irq_handler(irq, desc, status);
863}
864
865static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
866{
867 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
868 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
869
870 if (nmk_chip->secondary_parent_irq >= 0) {
871 irq_set_chained_handler(nmk_chip->secondary_parent_irq,
872 nmk_gpio_secondary_irq_handler);
873 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
874 }
875
876 return 0;
877}
878
879/* I/O Functions */
880
881static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
882{
883 /*
884 * Map back to global GPIO space and request muxing, the direction
885 * parameter does not matter for this controller.
886 */
887 int gpio = chip->base + offset;
888
889 return pinctrl_request_gpio(gpio);
890}
891
892static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
893{
894 int gpio = chip->base + offset;
895
896 pinctrl_free_gpio(gpio);
897}
898
899static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
900{
901 struct nmk_gpio_chip *nmk_chip =
902 container_of(chip, struct nmk_gpio_chip, chip);
903
904 clk_enable(nmk_chip->clk);
905
906 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
907
908 clk_disable(nmk_chip->clk);
909
910 return 0;
911}
912
913static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
914{
915 struct nmk_gpio_chip *nmk_chip =
916 container_of(chip, struct nmk_gpio_chip, chip);
917 u32 bit = 1 << offset;
918 int value;
919
920 clk_enable(nmk_chip->clk);
921
922 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
923
924 clk_disable(nmk_chip->clk);
925
926 return value;
927}
928
929static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
930 int val)
931{
932 struct nmk_gpio_chip *nmk_chip =
933 container_of(chip, struct nmk_gpio_chip, chip);
934
935 clk_enable(nmk_chip->clk);
936
937 __nmk_gpio_set_output(nmk_chip, offset, val);
938
939 clk_disable(nmk_chip->clk);
940}
941
942static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
943 int val)
944{
945 struct nmk_gpio_chip *nmk_chip =
946 container_of(chip, struct nmk_gpio_chip, chip);
947
948 clk_enable(nmk_chip->clk);
949
950 __nmk_gpio_make_output(nmk_chip, offset, val);
951
952 clk_disable(nmk_chip->clk);
953
954 return 0;
955}
956
957static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
958{
959 struct nmk_gpio_chip *nmk_chip =
960 container_of(chip, struct nmk_gpio_chip, chip);
961
962 return irq_find_mapping(nmk_chip->domain, offset);
963}
964
965#ifdef CONFIG_DEBUG_FS
966
967#include <linux/seq_file.h>
968
969static void nmk_gpio_dbg_show_one(struct seq_file *s, struct gpio_chip *chip,
970 unsigned offset, unsigned gpio)
971{
972 const char *label = gpiochip_is_requested(chip, offset);
973 struct nmk_gpio_chip *nmk_chip =
974 container_of(chip, struct nmk_gpio_chip, chip);
975 int mode;
976 bool is_out;
977 bool pull;
978 u32 bit = 1 << offset;
979 const char *modes[] = {
980 [NMK_GPIO_ALT_GPIO] = "gpio",
981 [NMK_GPIO_ALT_A] = "altA",
982 [NMK_GPIO_ALT_B] = "altB",
983 [NMK_GPIO_ALT_C] = "altC",
984 };
985
986 clk_enable(nmk_chip->clk);
987 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
988 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
989 mode = nmk_gpio_get_mode(gpio);
990
991 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
992 gpio, label ?: "(none)",
993 is_out ? "out" : "in ",
994 chip->get
995 ? (chip->get(chip, offset) ? "hi" : "lo")
996 : "? ",
997 (mode < 0) ? "unknown" : modes[mode],
998 pull ? "pull" : "none");
999
1000 if (label && !is_out) {
1001 int irq = gpio_to_irq(gpio);
1002 struct irq_desc *desc = irq_to_desc(irq);
1003
1004 /* This races with request_irq(), set_irq_type(),
1005 * and set_irq_wake() ... but those are "rare".
1006 */
1007 if (irq >= 0 && desc->action) {
1008 char *trigger;
1009 u32 bitmask = nmk_gpio_get_bitmask(gpio);
1010
1011 if (nmk_chip->edge_rising & bitmask)
1012 trigger = "edge-rising";
1013 else if (nmk_chip->edge_falling & bitmask)
1014 trigger = "edge-falling";
1015 else
1016 trigger = "edge-undefined";
1017
1018 seq_printf(s, " irq-%d %s%s",
1019 irq, trigger,
1020 irqd_is_wakeup_set(&desc->irq_data)
1021 ? " wakeup" : "");
1022 }
1023 }
1024 clk_disable(nmk_chip->clk);
1025}
1026
1027static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1028{
1029 unsigned i;
1030 unsigned gpio = chip->base;
1031
1032 for (i = 0; i < chip->ngpio; i++, gpio++) {
1033 nmk_gpio_dbg_show_one(s, chip, i, gpio);
1034 seq_printf(s, "\n");
1035 }
1036}
1037
1038#else
1039static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1040 struct gpio_chip *chip,
1041 unsigned offset, unsigned gpio)
1042{
1043}
1044#define nmk_gpio_dbg_show NULL
1045#endif
1046
1047/* This structure is replicated for each GPIO block allocated at probe time */
1048static struct gpio_chip nmk_gpio_template = {
1049 .request = nmk_gpio_request,
1050 .free = nmk_gpio_free,
1051 .direction_input = nmk_gpio_make_input,
1052 .get = nmk_gpio_get_input,
1053 .direction_output = nmk_gpio_make_output,
1054 .set = nmk_gpio_set_output,
1055 .to_irq = nmk_gpio_to_irq,
1056 .dbg_show = nmk_gpio_dbg_show,
1057 .can_sleep = 0,
1058};
1059
1060void nmk_gpio_clocks_enable(void)
1061{
1062 int i;
1063
1064 for (i = 0; i < NUM_BANKS; i++) {
1065 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1066
1067 if (!chip)
1068 continue;
1069
1070 clk_enable(chip->clk);
1071 }
1072}
1073
1074void nmk_gpio_clocks_disable(void)
1075{
1076 int i;
1077
1078 for (i = 0; i < NUM_BANKS; i++) {
1079 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1080
1081 if (!chip)
1082 continue;
1083
1084 clk_disable(chip->clk);
1085 }
1086}
1087
1088/*
1089 * Called from the suspend/resume path to only keep the real wakeup interrupts
1090 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
1091 * and not the rest of the interrupts which we needed to have as wakeups for
1092 * cpuidle.
1093 *
1094 * PM ops are not used since this needs to be done at the end, after all the
1095 * other drivers are done with their suspend callbacks.
1096 */
1097void nmk_gpio_wakeups_suspend(void)
1098{
1099 int i;
1100
1101 for (i = 0; i < NUM_BANKS; i++) {
1102 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1103
1104 if (!chip)
1105 break;
1106
1107 clk_enable(chip->clk);
1108
1109 writel(chip->rwimsc & chip->real_wake,
1110 chip->addr + NMK_GPIO_RWIMSC);
1111 writel(chip->fwimsc & chip->real_wake,
1112 chip->addr + NMK_GPIO_FWIMSC);
1113
1114 clk_disable(chip->clk);
1115 }
1116}
1117
1118void nmk_gpio_wakeups_resume(void)
1119{
1120 int i;
1121
1122 for (i = 0; i < NUM_BANKS; i++) {
1123 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1124
1125 if (!chip)
1126 break;
1127
1128 clk_enable(chip->clk);
1129
1130 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
1131 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
1132
1133 clk_disable(chip->clk);
1134 }
1135}
1136
1137/*
1138 * Read the pull up/pull down status.
1139 * A bit set in 'pull_up' means that pull up
1140 * is selected if pull is enabled in PDIS register.
1141 * Note: only pull up/down set via this driver can
1142 * be detected due to HW limitations.
1143 */
1144void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
1145{
1146 if (gpio_bank < NUM_BANKS) {
1147 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
1148
1149 if (!chip)
1150 return;
1151
1152 *pull_up = chip->pull_up;
1153 }
1154}
1155
1156int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1157 irq_hw_number_t hwirq)
1158{
1159 struct nmk_gpio_chip *nmk_chip = d->host_data;
1160
1161 if (!nmk_chip)
1162 return -EINVAL;
1163
1164 irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq);
1165 set_irq_flags(irq, IRQF_VALID);
1166 irq_set_chip_data(irq, nmk_chip);
1167 irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);
1168
1169 return 0;
1170}
1171
1172const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
1173 .map = nmk_gpio_irq_map,
1174 .xlate = irq_domain_xlate_twocell,
1175};
1176
1177static int __devinit nmk_gpio_probe(struct platform_device *dev)
1178{
1179 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
1180 struct device_node *np = dev->dev.of_node;
1181 struct nmk_gpio_chip *nmk_chip;
1182 struct gpio_chip *chip;
1183 struct resource *res;
1184 struct clk *clk;
1185 int secondary_irq;
1186 void __iomem *base;
1187 int irq;
1188 int ret;
1189
1190 if (!pdata && !np) {
1191 dev_err(&dev->dev, "No platform data or device tree found\n");
1192 return -ENODEV;
1193 }
1194
1195 if (np) {
1196 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
1197 if (!pdata)
1198 return -ENOMEM;
1199
1200 if (of_get_property(np, "supports-sleepmode", NULL))
1201 pdata->supports_sleepmode = true;
1202
1203 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1204 dev_err(&dev->dev, "gpio-bank property not found\n");
1205 ret = -EINVAL;
1206 goto out;
1207 }
1208
1209 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
1210 pdata->num_gpio = NMK_GPIO_PER_CHIP;
1211 }
1212
1213 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1214 if (!res) {
1215 ret = -ENOENT;
1216 goto out;
1217 }
1218
1219 irq = platform_get_irq(dev, 0);
1220 if (irq < 0) {
1221 ret = irq;
1222 goto out;
1223 }
1224
1225 secondary_irq = platform_get_irq(dev, 1);
1226 if (secondary_irq >= 0 && !pdata->get_secondary_status) {
1227 ret = -EINVAL;
1228 goto out;
1229 }
1230
1231 if (request_mem_region(res->start, resource_size(res),
1232 dev_name(&dev->dev)) == NULL) {
1233 ret = -EBUSY;
1234 goto out;
1235 }
1236
1237 base = ioremap(res->start, resource_size(res));
1238 if (!base) {
1239 ret = -ENOMEM;
1240 goto out_release;
1241 }
1242
1243 clk = clk_get(&dev->dev, NULL);
1244 if (IS_ERR(clk)) {
1245 ret = PTR_ERR(clk);
1246 goto out_unmap;
1247 }
1248
1249 nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL);
1250 if (!nmk_chip) {
1251 ret = -ENOMEM;
1252 goto out_clk;
1253 }
1254
1255 /*
1256 * The virt address in nmk_chip->addr is in the nomadik register space,
1257 * so we can simply convert the resource address, without remapping
1258 */
1259 nmk_chip->bank = dev->id;
1260 nmk_chip->clk = clk;
1261 nmk_chip->addr = base;
1262 nmk_chip->chip = nmk_gpio_template;
1263 nmk_chip->parent_irq = irq;
1264 nmk_chip->secondary_parent_irq = secondary_irq;
1265 nmk_chip->get_secondary_status = pdata->get_secondary_status;
1266 nmk_chip->set_ioforce = pdata->set_ioforce;
1267 nmk_chip->sleepmode = pdata->supports_sleepmode;
1268 spin_lock_init(&nmk_chip->lock);
1269
1270 chip = &nmk_chip->chip;
1271 chip->base = pdata->first_gpio;
1272 chip->ngpio = pdata->num_gpio;
1273 chip->label = pdata->name ?: dev_name(&dev->dev);
1274 chip->dev = &dev->dev;
1275 chip->owner = THIS_MODULE;
1276
1277 clk_enable(nmk_chip->clk);
1278 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1279 clk_disable(nmk_chip->clk);
1280
1281#ifdef CONFIG_OF_GPIO
1282 chip->of_node = np;
1283#endif
1284
1285 ret = gpiochip_add(&nmk_chip->chip);
1286 if (ret)
1287 goto out_free;
1288
1289 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1290
1291 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1292
1293 platform_set_drvdata(dev, nmk_chip);
1294
1295 nmk_chip->domain = irq_domain_add_legacy(np, NMK_GPIO_PER_CHIP,
1296 NOMADIK_GPIO_TO_IRQ(pdata->first_gpio),
1297 0, &nmk_gpio_irq_simple_ops, nmk_chip);
1298 if (!nmk_chip->domain) {
1299 pr_err("%s: Failed to create irqdomain\n", np->full_name);
1300 ret = -ENOSYS;
1301 goto out_free;
1302 }
1303
1304 nmk_gpio_init_irq(nmk_chip);
1305
1306 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1307
1308 return 0;
1309
1310out_free:
1311 kfree(nmk_chip);
1312out_clk:
1313 clk_disable(clk);
1314 clk_put(clk);
1315out_unmap:
1316 iounmap(base);
1317out_release:
1318 release_mem_region(res->start, resource_size(res));
1319out:
1320 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
1321 pdata->first_gpio, pdata->first_gpio+31);
1322 if (np)
1323 kfree(pdata);
1324
1325 return ret;
1326}
1327
1328static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1329{
1330 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1331
1332 return npct->soc->ngroups;
1333}
1334
1335static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1336 unsigned selector)
1337{
1338 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1339
1340 return npct->soc->groups[selector].name;
1341}
1342
1343static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1344 const unsigned **pins,
1345 unsigned *num_pins)
1346{
1347 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1348
1349 *pins = npct->soc->groups[selector].pins;
1350 *num_pins = npct->soc->groups[selector].npins;
1351 return 0;
1352}
1353
1354static struct pinctrl_gpio_range *
1355nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
1356{
1357 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1358 int i;
1359
1360 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1361 struct pinctrl_gpio_range *range;
1362
1363 range = &npct->soc->gpio_ranges[i];
1364 if (offset >= range->pin_base &&
1365 offset <= (range->pin_base + range->npins - 1))
1366 return range;
1367 }
1368 return NULL;
1369}
1370
1371static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1372 unsigned offset)
1373{
1374 struct pinctrl_gpio_range *range;
1375 struct gpio_chip *chip;
1376
1377 range = nmk_match_gpio_range(pctldev, offset);
1378 if (!range || !range->gc) {
1379 seq_printf(s, "invalid pin offset");
1380 return;
1381 }
1382 chip = range->gc;
1383 nmk_gpio_dbg_show_one(s, chip, offset - chip->base, offset);
1384}
1385
1386static struct pinctrl_ops nmk_pinctrl_ops = {
1387 .get_groups_count = nmk_get_groups_cnt,
1388 .get_group_name = nmk_get_group_name,
1389 .get_group_pins = nmk_get_group_pins,
1390 .pin_dbg_show = nmk_pin_dbg_show,
1391};
1392
1393static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1394{
1395 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1396
1397 return npct->soc->nfunctions;
1398}
1399
1400static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1401 unsigned function)
1402{
1403 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1404
1405 return npct->soc->functions[function].name;
1406}
1407
1408static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1409 unsigned function,
1410 const char * const **groups,
1411 unsigned * const num_groups)
1412{
1413 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1414
1415 *groups = npct->soc->functions[function].groups;
1416 *num_groups = npct->soc->functions[function].ngroups;
1417
1418 return 0;
1419}
1420
1421static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
1422 unsigned group)
1423{
1424 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1425 const struct nmk_pingroup *g;
1426 static unsigned int slpm[NUM_BANKS];
1427 unsigned long flags;
1428 bool glitch;
1429 int ret = -EINVAL;
1430 int i;
1431
1432 g = &npct->soc->groups[group];
1433
1434 if (g->altsetting < 0)
1435 return -EINVAL;
1436
1437 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1438
1439 /* Handle this special glitch on altfunction C */
1440 glitch = (g->altsetting == NMK_GPIO_ALT_C);
1441
1442 if (glitch) {
1443 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1444
1445 /* Initially don't put any pins to sleep when switching */
1446 memset(slpm, 0xff, sizeof(slpm));
1447
1448 /*
1449 * Then mask the pins that need to be sleeping now when we're
1450 * switching to the ALT C function.
1451 */
1452 for (i = 0; i < g->npins; i++)
1453 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1454 nmk_gpio_glitch_slpm_init(slpm);
1455 }
1456
1457 for (i = 0; i < g->npins; i++) {
1458 struct pinctrl_gpio_range *range;
1459 struct nmk_gpio_chip *nmk_chip;
1460 struct gpio_chip *chip;
1461 unsigned bit;
1462
1463 range = nmk_match_gpio_range(pctldev, g->pins[i]);
1464 if (!range) {
1465 dev_err(npct->dev,
1466 "invalid pin offset %d in group %s at index %d\n",
1467 g->pins[i], g->name, i);
1468 goto out_glitch;
1469 }
1470 if (!range->gc) {
1471 dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1472 g->pins[i], g->name, i);
1473 goto out_glitch;
1474 }
1475 chip = range->gc;
1476 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1477 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1478
1479 clk_enable(nmk_chip->clk);
1480 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1481 /*
1482 * If the pin is switching to altfunc, and there was an
1483 * interrupt installed on it which has been lazy disabled,
1484 * actually mask the interrupt to prevent spurious interrupts
1485 * that would occur while the pin is under control of the
1486 * peripheral. Only SKE does this.
1487 */
1488 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1489
1490 __nmk_gpio_set_mode_safe(nmk_chip, bit, g->altsetting, glitch);
1491 clk_disable(nmk_chip->clk);
1492 }
1493
1494 /* When all pins are successfully reconfigured we get here */
1495 ret = 0;
1496
1497out_glitch:
1498 if (glitch) {
1499 nmk_gpio_glitch_slpm_restore(slpm);
1500 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1501 }
1502
1503 return ret;
1504}
1505
1506static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
1507 unsigned function, unsigned group)
1508{
1509 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1510 const struct nmk_pingroup *g;
1511
1512 g = &npct->soc->groups[group];
1513
1514 if (g->altsetting < 0)
1515 return;
1516
1517 /* Poke out the mux, set the pin to some default state? */
1518 dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
1519}
1520
1521int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1522 struct pinctrl_gpio_range *range,
1523 unsigned offset)
1524{
1525 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1526 struct nmk_gpio_chip *nmk_chip;
1527 struct gpio_chip *chip;
1528 unsigned bit;
1529
1530 if (!range) {
1531 dev_err(npct->dev, "invalid range\n");
1532 return -EINVAL;
1533 }
1534 if (!range->gc) {
1535 dev_err(npct->dev, "missing GPIO chip in range\n");
1536 return -EINVAL;
1537 }
1538 chip = range->gc;
1539 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1540
1541 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1542
1543 clk_enable(nmk_chip->clk);
1544 bit = offset % NMK_GPIO_PER_CHIP;
1545 /* There is no glitch when converting any pin to GPIO */
1546 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1547 clk_disable(nmk_chip->clk);
1548
1549 return 0;
1550}
1551
1552void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1553 struct pinctrl_gpio_range *range,
1554 unsigned offset)
1555{
1556 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1557
1558 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1559 /* Set the pin to some default state, GPIO is usually default */
1560}
1561
1562static struct pinmux_ops nmk_pinmux_ops = {
1563 .get_functions_count = nmk_pmx_get_funcs_cnt,
1564 .get_function_name = nmk_pmx_get_func_name,
1565 .get_function_groups = nmk_pmx_get_func_groups,
1566 .enable = nmk_pmx_enable,
1567 .disable = nmk_pmx_disable,
1568 .gpio_request_enable = nmk_gpio_request_enable,
1569 .gpio_disable_free = nmk_gpio_disable_free,
1570};
1571
1572int nmk_pin_config_get(struct pinctrl_dev *pctldev,
1573 unsigned pin,
1574 unsigned long *config)
1575{
1576 /* Not implemented */
1577 return -EINVAL;
1578}
1579
1580int nmk_pin_config_set(struct pinctrl_dev *pctldev,
1581 unsigned pin,
1582 unsigned long config)
1583{
1584 static const char *pullnames[] = {
1585 [NMK_GPIO_PULL_NONE] = "none",
1586 [NMK_GPIO_PULL_UP] = "up",
1587 [NMK_GPIO_PULL_DOWN] = "down",
1588 [3] /* illegal */ = "??"
1589 };
1590 static const char *slpmnames[] = {
1591 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1592 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1593 };
1594 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1595 struct nmk_gpio_chip *nmk_chip;
1596 struct pinctrl_gpio_range *range;
1597 struct gpio_chip *chip;
1598 unsigned bit;
1599
1600 /*
1601 * The pin config contains pin number and altfunction fields, here
1602 * we just ignore that part. It's being handled by the framework and
1603 * pinmux callback respectively.
1604 */
1605 pin_cfg_t cfg = (pin_cfg_t) config;
1606 int pull = PIN_PULL(cfg);
1607 int slpm = PIN_SLPM(cfg);
1608 int output = PIN_DIR(cfg);
1609 int val = PIN_VAL(cfg);
1610 bool lowemi = PIN_LOWEMI(cfg);
1611 bool gpiomode = PIN_GPIOMODE(cfg);
1612 bool sleep = PIN_SLEEPMODE(cfg);
1613
1614 range = nmk_match_gpio_range(pctldev, pin);
1615 if (!range) {
1616 dev_err(npct->dev, "invalid pin offset %d\n", pin);
1617 return -EINVAL;
1618 }
1619 if (!range->gc) {
1620 dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
1621 pin);
1622 return -EINVAL;
1623 }
1624 chip = range->gc;
1625 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1626
1627 if (sleep) {
1628 int slpm_pull = PIN_SLPM_PULL(cfg);
1629 int slpm_output = PIN_SLPM_DIR(cfg);
1630 int slpm_val = PIN_SLPM_VAL(cfg);
1631
1632 /* All pins go into GPIO mode at sleep */
1633 gpiomode = true;
1634
1635 /*
1636 * The SLPM_* values are normal values + 1 to allow zero to
1637 * mean "same as normal".
1638 */
1639 if (slpm_pull)
1640 pull = slpm_pull - 1;
1641 if (slpm_output)
1642 output = slpm_output - 1;
1643 if (slpm_val)
1644 val = slpm_val - 1;
1645
1646 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
1647 pin,
1648 slpm_pull ? pullnames[pull] : "same",
1649 slpm_output ? (output ? "output" : "input") : "same",
1650 slpm_val ? (val ? "high" : "low") : "same");
1651 }
1652
1653 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1654 pin, cfg, pullnames[pull], slpmnames[slpm],
1655 output ? "output " : "input",
1656 output ? (val ? "high" : "low") : "",
1657 lowemi ? "on" : "off" );
1658
1659 clk_enable(nmk_chip->clk);
1660 bit = pin % NMK_GPIO_PER_CHIP;
1661 if (gpiomode)
1662 /* No glitch when going to GPIO mode */
1663 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1664 if (output)
1665 __nmk_gpio_make_output(nmk_chip, bit, val);
1666 else {
1667 __nmk_gpio_make_input(nmk_chip, bit);
1668 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1669 }
1670 /* TODO: isn't this only applicable on output pins? */
1671 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1672
1673 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1674 clk_disable(nmk_chip->clk);
1675 return 0;
1676}
1677
1678static struct pinconf_ops nmk_pinconf_ops = {
1679 .pin_config_get = nmk_pin_config_get,
1680 .pin_config_set = nmk_pin_config_set,
1681};
1682
1683static struct pinctrl_desc nmk_pinctrl_desc = {
1684 .name = "pinctrl-nomadik",
1685 .pctlops = &nmk_pinctrl_ops,
1686 .pmxops = &nmk_pinmux_ops,
1687 .confops = &nmk_pinconf_ops,
1688 .owner = THIS_MODULE,
1689};
1690
1691static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
1692{
1693 const struct platform_device_id *platid = platform_get_device_id(pdev);
1694 struct nmk_pinctrl *npct;
1695 int i;
1696
1697 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1698 if (!npct)
1699 return -ENOMEM;
1700
1701 /* Poke in other ASIC variants here */
1702 if (platid->driver_data == PINCTRL_NMK_DB8500)
1703 nmk_pinctrl_db8500_init(&npct->soc);
1704
1705 /*
1706 * We need all the GPIO drivers to probe FIRST, or we will not be able
1707 * to obtain references to the struct gpio_chip * for them, and we
1708 * need this to proceed.
1709 */
1710 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1711 if (!nmk_gpio_chips[i]) {
1712 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1713 devm_kfree(&pdev->dev, npct);
1714 return -EPROBE_DEFER;
1715 }
1716 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[i]->chip;
1717 }
1718
1719 nmk_pinctrl_desc.pins = npct->soc->pins;
1720 nmk_pinctrl_desc.npins = npct->soc->npins;
1721 npct->dev = &pdev->dev;
1722 npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
1723 if (!npct->pctl) {
1724 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1725 return -EINVAL;
1726 }
1727
1728 /* We will handle a range of GPIO pins */
1729 for (i = 0; i < npct->soc->gpio_num_ranges; i++)
1730 pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
1731
1732 platform_set_drvdata(pdev, npct);
1733 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1734
1735 return 0;
1736}
1737
1738static const struct of_device_id nmk_gpio_match[] = {
1739 { .compatible = "st,nomadik-gpio", },
1740 {}
1741};
1742
1743static struct platform_driver nmk_gpio_driver = {
1744 .driver = {
1745 .owner = THIS_MODULE,
1746 .name = "gpio",
1747 .of_match_table = nmk_gpio_match,
1748 },
1749 .probe = nmk_gpio_probe,
1750};
1751
1752static const struct platform_device_id nmk_pinctrl_id[] = {
1753 { "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
1754 { "pinctrl-db8500", PINCTRL_NMK_DB8500 },
1755};
1756
1757static struct platform_driver nmk_pinctrl_driver = {
1758 .driver = {
1759 .owner = THIS_MODULE,
1760 .name = "pinctrl-nomadik",
1761 },
1762 .probe = nmk_pinctrl_probe,
1763 .id_table = nmk_pinctrl_id,
1764};
1765
1766static int __init nmk_gpio_init(void)
1767{
1768 int ret;
1769
1770 ret = platform_driver_register(&nmk_gpio_driver);
1771 if (ret)
1772 return ret;
1773 return platform_driver_register(&nmk_pinctrl_driver);
1774}
1775
1776core_initcall(nmk_gpio_init);
1777
1778MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1779MODULE_DESCRIPTION("Nomadik GPIO Driver");
1780MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/pinctrl-nomadik.h b/drivers/pinctrl/pinctrl-nomadik.h
new file mode 100644
index 00000000000..bc91aed7185
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-nomadik.h
@@ -0,0 +1,77 @@
1#ifndef PINCTRL_PINCTRL_NOMADIK_H
2#define PINCTRL_PINCTRL_NOMADIK_H
3
4#include <plat/gpio-nomadik.h>
5
6/* Package definitions */
7#define PINCTRL_NMK_STN8815 0
8#define PINCTRL_NMK_DB8500 1
9
10/**
11 * struct nmk_function - Nomadik pinctrl mux function
12 * @name: The name of the function, exported to pinctrl core.
13 * @groups: An array of pin groups that may select this function.
14 * @ngroups: The number of entries in @groups.
15 */
16struct nmk_function {
17 const char *name;
18 const char * const *groups;
19 unsigned ngroups;
20};
21
22/**
23 * struct nmk_pingroup - describes a Nomadik pin group
24 * @name: the name of this specific pin group
25 * @pins: an array of discrete physical pins used in this group, taken
26 * from the driver-local pin enumeration space
27 * @num_pins: the number of pins in this group array, i.e. the number of
28 * elements in .pins so we can iterate over that array
29 * @altsetting: the altsetting to apply to all pins in this group to
30 * configure them to be used by a function
31 */
32struct nmk_pingroup {
33 const char *name;
34 const unsigned int *pins;
35 const unsigned npins;
36 int altsetting;
37};
38
39/**
40 * struct nmk_pinctrl_soc_data - Nomadik pin controller per-SoC configuration
41 * @gpio_ranges: An array of GPIO ranges for this SoC
42 * @gpio_num_ranges: The number of GPIO ranges for this SoC
43 * @pins: An array describing all pins the pin controller affects.
44 * All pins which are also GPIOs must be listed first within the
45 * array, and be numbered identically to the GPIO controller's
46 * numbering.
47 * @npins: The number of entries in @pins.
48 * @functions: The functions supported on this SoC.
49 * @nfunction: The number of entries in @functions.
50 * @groups: An array describing all pin groups the pin SoC supports.
51 * @ngroups: The number of entries in @groups.
52 */
53struct nmk_pinctrl_soc_data {
54 struct pinctrl_gpio_range *gpio_ranges;
55 unsigned gpio_num_ranges;
56 const struct pinctrl_pin_desc *pins;
57 unsigned npins;
58 const struct nmk_function *functions;
59 unsigned nfunctions;
60 const struct nmk_pingroup *groups;
61 unsigned ngroups;
62};
63
64#ifdef CONFIG_PINCTRL_DB8500
65
66void nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc);
67
68#else
69
70static inline void
71nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
72{
73}
74
75#endif
76
77#endif /* PINCTRL_PINCTRL_NOMADIK_H */
diff --git a/drivers/pinctrl/pinctrl-pxa3xx.c b/drivers/pinctrl/pinctrl-pxa3xx.c
index 079dce0e93e..7644e42ac21 100644
--- a/drivers/pinctrl/pinctrl-pxa3xx.c
+++ b/drivers/pinctrl/pinctrl-pxa3xx.c
@@ -25,20 +25,18 @@ static struct pinctrl_gpio_range pxa3xx_pinctrl_gpio_range = {
25 .pin_base = 0, 25 .pin_base = 0,
26}; 26};
27 27
28static int pxa3xx_list_groups(struct pinctrl_dev *pctrldev, unsigned selector) 28static int pxa3xx_get_groups_count(struct pinctrl_dev *pctrldev)
29{ 29{
30 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); 30 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
31 if (selector >= info->num_grps) 31
32 return -EINVAL; 32 return info->num_grps;
33 return 0;
34} 33}
35 34
36static const char *pxa3xx_get_group_name(struct pinctrl_dev *pctrldev, 35static const char *pxa3xx_get_group_name(struct pinctrl_dev *pctrldev,
37 unsigned selector) 36 unsigned selector)
38{ 37{
39 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); 38 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
40 if (selector >= info->num_grps) 39
41 return NULL;
42 return info->grps[selector].name; 40 return info->grps[selector].name;
43} 41}
44 42
@@ -48,25 +46,23 @@ static int pxa3xx_get_group_pins(struct pinctrl_dev *pctrldev,
48 unsigned *num_pins) 46 unsigned *num_pins)
49{ 47{
50 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); 48 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
51 if (selector >= info->num_grps) 49
52 return -EINVAL;
53 *pins = info->grps[selector].pins; 50 *pins = info->grps[selector].pins;
54 *num_pins = info->grps[selector].npins; 51 *num_pins = info->grps[selector].npins;
55 return 0; 52 return 0;
56} 53}
57 54
58static struct pinctrl_ops pxa3xx_pctrl_ops = { 55static struct pinctrl_ops pxa3xx_pctrl_ops = {
59 .list_groups = pxa3xx_list_groups, 56 .get_groups_count = pxa3xx_get_groups_count,
60 .get_group_name = pxa3xx_get_group_name, 57 .get_group_name = pxa3xx_get_group_name,
61 .get_group_pins = pxa3xx_get_group_pins, 58 .get_group_pins = pxa3xx_get_group_pins,
62}; 59};
63 60
64static int pxa3xx_pmx_list_func(struct pinctrl_dev *pctrldev, unsigned func) 61static int pxa3xx_pmx_get_funcs_count(struct pinctrl_dev *pctrldev)
65{ 62{
66 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev); 63 struct pxa3xx_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
67 if (func >= info->num_funcs) 64
68 return -EINVAL; 65 return info->num_funcs;
69 return 0;
70} 66}
71 67
72static const char *pxa3xx_pmx_get_func_name(struct pinctrl_dev *pctrldev, 68static const char *pxa3xx_pmx_get_func_name(struct pinctrl_dev *pctrldev,
@@ -170,7 +166,7 @@ static int pxa3xx_pmx_request_gpio(struct pinctrl_dev *pctrldev,
170} 166}
171 167
172static struct pinmux_ops pxa3xx_pmx_ops = { 168static struct pinmux_ops pxa3xx_pmx_ops = {
173 .list_functions = pxa3xx_pmx_list_func, 169 .get_functions_count = pxa3xx_pmx_get_funcs_count,
174 .get_function_name = pxa3xx_pmx_get_func_name, 170 .get_function_name = pxa3xx_pmx_get_func_name,
175 .get_function_groups = pxa3xx_pmx_get_groups, 171 .get_function_groups = pxa3xx_pmx_get_groups,
176 .enable = pxa3xx_pmx_enable, 172 .enable = pxa3xx_pmx_enable,
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index 6b3534cc051..ba15b1a29e5 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -853,18 +853,14 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
853 SIRFSOC_PIN_GROUP("gpsgrp", gps_pins), 853 SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
854}; 854};
855 855
856static int sirfsoc_list_groups(struct pinctrl_dev *pctldev, unsigned selector) 856static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
857{ 857{
858 if (selector >= ARRAY_SIZE(sirfsoc_pin_groups)) 858 return ARRAY_SIZE(sirfsoc_pin_groups);
859 return -EINVAL;
860 return 0;
861} 859}
862 860
863static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev, 861static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
864 unsigned selector) 862 unsigned selector)
865{ 863{
866 if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
867 return NULL;
868 return sirfsoc_pin_groups[selector].name; 864 return sirfsoc_pin_groups[selector].name;
869} 865}
870 866
@@ -872,8 +868,6 @@ static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector
872 const unsigned **pins, 868 const unsigned **pins,
873 unsigned *num_pins) 869 unsigned *num_pins)
874{ 870{
875 if (selector >= ARRAY_SIZE(sirfsoc_pin_groups))
876 return -EINVAL;
877 *pins = sirfsoc_pin_groups[selector].pins; 871 *pins = sirfsoc_pin_groups[selector].pins;
878 *num_pins = sirfsoc_pin_groups[selector].num_pins; 872 *num_pins = sirfsoc_pin_groups[selector].num_pins;
879 return 0; 873 return 0;
@@ -886,7 +880,7 @@ static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s
886} 880}
887 881
888static struct pinctrl_ops sirfsoc_pctrl_ops = { 882static struct pinctrl_ops sirfsoc_pctrl_ops = {
889 .list_groups = sirfsoc_list_groups, 883 .get_groups_count = sirfsoc_get_groups_count,
890 .get_group_name = sirfsoc_get_group_name, 884 .get_group_name = sirfsoc_get_group_name,
891 .get_group_pins = sirfsoc_get_group_pins, 885 .get_group_pins = sirfsoc_get_group_pins,
892 .pin_dbg_show = sirfsoc_pin_dbg_show, 886 .pin_dbg_show = sirfsoc_pin_dbg_show,
@@ -1033,11 +1027,9 @@ static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector
1033 sirfsoc_pinmux_endisable(spmx, selector, false); 1027 sirfsoc_pinmux_endisable(spmx, selector, false);
1034} 1028}
1035 1029
1036static int sirfsoc_pinmux_list_funcs(struct pinctrl_dev *pmxdev, unsigned selector) 1030static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
1037{ 1031{
1038 if (selector >= ARRAY_SIZE(sirfsoc_pmx_functions)) 1032 return ARRAY_SIZE(sirfsoc_pmx_functions);
1039 return -EINVAL;
1040 return 0;
1041} 1033}
1042 1034
1043static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev, 1035static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
@@ -1074,9 +1066,9 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
1074} 1066}
1075 1067
1076static struct pinmux_ops sirfsoc_pinmux_ops = { 1068static struct pinmux_ops sirfsoc_pinmux_ops = {
1077 .list_functions = sirfsoc_pinmux_list_funcs,
1078 .enable = sirfsoc_pinmux_enable, 1069 .enable = sirfsoc_pinmux_enable,
1079 .disable = sirfsoc_pinmux_disable, 1070 .disable = sirfsoc_pinmux_disable,
1071 .get_functions_count = sirfsoc_pinmux_get_funcs_count,
1080 .get_function_name = sirfsoc_pinmux_get_func_name, 1072 .get_function_name = sirfsoc_pinmux_get_func_name,
1081 .get_function_groups = sirfsoc_pinmux_get_groups, 1073 .get_function_groups = sirfsoc_pinmux_get_groups,
1082 .gpio_request_enable = sirfsoc_pinmux_request_gpio, 1074 .gpio_request_enable = sirfsoc_pinmux_request_gpio,
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index 9b329688120..b6934867d8d 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Driver for the NVIDIA Tegra pinmux 2 * Driver for the NVIDIA Tegra pinmux
3 * 3 *
4 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Derived from code: 6 * Derived from code:
7 * Copyright (C) 2010 Google, Inc. 7 * Copyright (C) 2010 Google, Inc.
@@ -22,17 +22,19 @@
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/module.h> 24#include <linux/module.h>
25#include <linux/of_device.h> 25#include <linux/of.h>
26#include <linux/platform_device.h>
27#include <linux/pinctrl/machine.h>
26#include <linux/pinctrl/pinctrl.h> 28#include <linux/pinctrl/pinctrl.h>
27#include <linux/pinctrl/pinmux.h> 29#include <linux/pinctrl/pinmux.h>
28#include <linux/pinctrl/pinconf.h> 30#include <linux/pinctrl/pinconf.h>
31#include <linux/slab.h>
29 32
30#include <mach/pinconf-tegra.h> 33#include <mach/pinconf-tegra.h>
31 34
35#include "core.h"
32#include "pinctrl-tegra.h" 36#include "pinctrl-tegra.h"
33 37
34#define DRIVER_NAME "tegra-pinmux-disabled"
35
36struct tegra_pmx { 38struct tegra_pmx {
37 struct device *dev; 39 struct device *dev;
38 struct pinctrl_dev *pctl; 40 struct pinctrl_dev *pctl;
@@ -53,15 +55,11 @@ static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
53 writel(val, pmx->regs[bank] + reg); 55 writel(val, pmx->regs[bank] + reg);
54} 56}
55 57
56static int tegra_pinctrl_list_groups(struct pinctrl_dev *pctldev, 58static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
57 unsigned group)
58{ 59{
59 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 60 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
60 61
61 if (group >= pmx->soc->ngroups) 62 return pmx->soc->ngroups;
62 return -EINVAL;
63
64 return 0;
65} 63}
66 64
67static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 65static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
@@ -69,9 +67,6 @@ static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
69{ 67{
70 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 68 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
71 69
72 if (group >= pmx->soc->ngroups)
73 return NULL;
74
75 return pmx->soc->groups[group].name; 70 return pmx->soc->groups[group].name;
76} 71}
77 72
@@ -82,38 +77,259 @@ static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
82{ 77{
83 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 78 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
84 79
85 if (group >= pmx->soc->ngroups)
86 return -EINVAL;
87
88 *pins = pmx->soc->groups[group].pins; 80 *pins = pmx->soc->groups[group].pins;
89 *num_pins = pmx->soc->groups[group].npins; 81 *num_pins = pmx->soc->groups[group].npins;
90 82
91 return 0; 83 return 0;
92} 84}
93 85
86#ifdef CONFIG_DEBUG_FS
94static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, 87static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
95 struct seq_file *s, 88 struct seq_file *s,
96 unsigned offset) 89 unsigned offset)
97{ 90{
98 seq_printf(s, " " DRIVER_NAME); 91 seq_printf(s, " %s", dev_name(pctldev->dev));
92}
93#endif
94
95static int reserve_map(struct device *dev, struct pinctrl_map **map,
96 unsigned *reserved_maps, unsigned *num_maps,
97 unsigned reserve)
98{
99 unsigned old_num = *reserved_maps;
100 unsigned new_num = *num_maps + reserve;
101 struct pinctrl_map *new_map;
102
103 if (old_num >= new_num)
104 return 0;
105
106 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
107 if (!new_map) {
108 dev_err(dev, "krealloc(map) failed\n");
109 return -ENOMEM;
110 }
111
112 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
113
114 *map = new_map;
115 *reserved_maps = new_num;
116
117 return 0;
118}
119
120static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
121 unsigned *num_maps, const char *group,
122 const char *function)
123{
124 if (WARN_ON(*num_maps == *reserved_maps))
125 return -ENOSPC;
126
127 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
128 (*map)[*num_maps].data.mux.group = group;
129 (*map)[*num_maps].data.mux.function = function;
130 (*num_maps)++;
131
132 return 0;
133}
134
135static int add_map_configs(struct device *dev, struct pinctrl_map **map,
136 unsigned *reserved_maps, unsigned *num_maps,
137 const char *group, unsigned long *configs,
138 unsigned num_configs)
139{
140 unsigned long *dup_configs;
141
142 if (WARN_ON(*num_maps == *reserved_maps))
143 return -ENOSPC;
144
145 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
146 GFP_KERNEL);
147 if (!dup_configs) {
148 dev_err(dev, "kmemdup(configs) failed\n");
149 return -ENOMEM;
150 }
151
152 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
153 (*map)[*num_maps].data.configs.group_or_pin = group;
154 (*map)[*num_maps].data.configs.configs = dup_configs;
155 (*map)[*num_maps].data.configs.num_configs = num_configs;
156 (*num_maps)++;
157
158 return 0;
159}
160
161static int add_config(struct device *dev, unsigned long **configs,
162 unsigned *num_configs, unsigned long config)
163{
164 unsigned old_num = *num_configs;
165 unsigned new_num = old_num + 1;
166 unsigned long *new_configs;
167
168 new_configs = krealloc(*configs, sizeof(*new_configs) * new_num,
169 GFP_KERNEL);
170 if (!new_configs) {
171 dev_err(dev, "krealloc(configs) failed\n");
172 return -ENOMEM;
173 }
174
175 new_configs[old_num] = config;
176
177 *configs = new_configs;
178 *num_configs = new_num;
179
180 return 0;
181}
182
183void tegra_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
184 struct pinctrl_map *map, unsigned num_maps)
185{
186 int i;
187
188 for (i = 0; i < num_maps; i++)
189 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
190 kfree(map[i].data.configs.configs);
191
192 kfree(map);
193}
194
195static const struct cfg_param {
196 const char *property;
197 enum tegra_pinconf_param param;
198} cfg_params[] = {
199 {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL},
200 {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE},
201 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
202 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
203 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
204 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
205 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
206 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
207 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
208 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
209 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
210 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
211 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
212};
213
214int tegra_pinctrl_dt_subnode_to_map(struct device *dev,
215 struct device_node *np,
216 struct pinctrl_map **map,
217 unsigned *reserved_maps,
218 unsigned *num_maps)
219{
220 int ret, i;
221 const char *function;
222 u32 val;
223 unsigned long config;
224 unsigned long *configs = NULL;
225 unsigned num_configs = 0;
226 unsigned reserve;
227 struct property *prop;
228 const char *group;
229
230 ret = of_property_read_string(np, "nvidia,function", &function);
231 if (ret < 0) {
232 /* EINVAL=missing, which is fine since it's optional */
233 if (ret != -EINVAL)
234 dev_err(dev,
235 "could not parse property nvidia,function\n");
236 function = NULL;
237 }
238
239 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
240 ret = of_property_read_u32(np, cfg_params[i].property, &val);
241 if (!ret) {
242 config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
243 ret = add_config(dev, &configs, &num_configs, config);
244 if (ret < 0)
245 goto exit;
246 /* EINVAL=missing, which is fine since it's optional */
247 } else if (ret != -EINVAL) {
248 dev_err(dev, "could not parse property %s\n",
249 cfg_params[i].property);
250 }
251 }
252
253 reserve = 0;
254 if (function != NULL)
255 reserve++;
256 if (num_configs)
257 reserve++;
258 ret = of_property_count_strings(np, "nvidia,pins");
259 if (ret < 0) {
260 dev_err(dev, "could not parse property nvidia,pins\n");
261 goto exit;
262 }
263 reserve *= ret;
264
265 ret = reserve_map(dev, map, reserved_maps, num_maps, reserve);
266 if (ret < 0)
267 goto exit;
268
269 of_property_for_each_string(np, "nvidia,pins", prop, group) {
270 if (function) {
271 ret = add_map_mux(map, reserved_maps, num_maps,
272 group, function);
273 if (ret < 0)
274 goto exit;
275 }
276
277 if (num_configs) {
278 ret = add_map_configs(dev, map, reserved_maps,
279 num_maps, group, configs,
280 num_configs);
281 if (ret < 0)
282 goto exit;
283 }
284 }
285
286 ret = 0;
287
288exit:
289 kfree(configs);
290 return ret;
291}
292
293int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
294 struct device_node *np_config,
295 struct pinctrl_map **map, unsigned *num_maps)
296{
297 unsigned reserved_maps;
298 struct device_node *np;
299 int ret;
300
301 reserved_maps = 0;
302 *map = NULL;
303 *num_maps = 0;
304
305 for_each_child_of_node(np_config, np) {
306 ret = tegra_pinctrl_dt_subnode_to_map(pctldev->dev, np, map,
307 &reserved_maps, num_maps);
308 if (ret < 0) {
309 tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps);
310 return ret;
311 }
312 }
313
314 return 0;
99} 315}
100 316
101static struct pinctrl_ops tegra_pinctrl_ops = { 317static struct pinctrl_ops tegra_pinctrl_ops = {
102 .list_groups = tegra_pinctrl_list_groups, 318 .get_groups_count = tegra_pinctrl_get_groups_count,
103 .get_group_name = tegra_pinctrl_get_group_name, 319 .get_group_name = tegra_pinctrl_get_group_name,
104 .get_group_pins = tegra_pinctrl_get_group_pins, 320 .get_group_pins = tegra_pinctrl_get_group_pins,
321#ifdef CONFIG_DEBUG_FS
105 .pin_dbg_show = tegra_pinctrl_pin_dbg_show, 322 .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
323#endif
324 .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
325 .dt_free_map = tegra_pinctrl_dt_free_map,
106}; 326};
107 327
108static int tegra_pinctrl_list_funcs(struct pinctrl_dev *pctldev, 328static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
109 unsigned function)
110{ 329{
111 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 330 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
112 331
113 if (function >= pmx->soc->nfunctions) 332 return pmx->soc->nfunctions;
114 return -EINVAL;
115
116 return 0;
117} 333}
118 334
119static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev, 335static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
@@ -121,9 +337,6 @@ static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
121{ 337{
122 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 338 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
123 339
124 if (function >= pmx->soc->nfunctions)
125 return NULL;
126
127 return pmx->soc->functions[function].name; 340 return pmx->soc->functions[function].name;
128} 341}
129 342
@@ -134,9 +347,6 @@ static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
134{ 347{
135 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 348 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
136 349
137 if (function >= pmx->soc->nfunctions)
138 return -EINVAL;
139
140 *groups = pmx->soc->functions[function].groups; 350 *groups = pmx->soc->functions[function].groups;
141 *num_groups = pmx->soc->functions[function].ngroups; 351 *num_groups = pmx->soc->functions[function].ngroups;
142 352
@@ -151,18 +361,16 @@ static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
151 int i; 361 int i;
152 u32 val; 362 u32 val;
153 363
154 if (group >= pmx->soc->ngroups)
155 return -EINVAL;
156 g = &pmx->soc->groups[group]; 364 g = &pmx->soc->groups[group];
157 365
158 if (g->mux_reg < 0) 366 if (WARN_ON(g->mux_reg < 0))
159 return -EINVAL; 367 return -EINVAL;
160 368
161 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) { 369 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
162 if (g->funcs[i] == function) 370 if (g->funcs[i] == function)
163 break; 371 break;
164 } 372 }
165 if (i == ARRAY_SIZE(g->funcs)) 373 if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
166 return -EINVAL; 374 return -EINVAL;
167 375
168 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); 376 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
@@ -180,11 +388,9 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
180 const struct tegra_pingroup *g; 388 const struct tegra_pingroup *g;
181 u32 val; 389 u32 val;
182 390
183 if (group >= pmx->soc->ngroups)
184 return;
185 g = &pmx->soc->groups[group]; 391 g = &pmx->soc->groups[group];
186 392
187 if (g->mux_reg < 0) 393 if (WARN_ON(g->mux_reg < 0))
188 return; 394 return;
189 395
190 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); 396 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
@@ -194,7 +400,7 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
194} 400}
195 401
196static struct pinmux_ops tegra_pinmux_ops = { 402static struct pinmux_ops tegra_pinmux_ops = {
197 .list_functions = tegra_pinctrl_list_funcs, 403 .get_functions_count = tegra_pinctrl_get_funcs_count,
198 .get_function_name = tegra_pinctrl_get_func_name, 404 .get_function_name = tegra_pinctrl_get_func_name,
199 .get_function_groups = tegra_pinctrl_get_func_groups, 405 .get_function_groups = tegra_pinctrl_get_func_groups,
200 .enable = tegra_pinctrl_enable, 406 .enable = tegra_pinctrl_enable,
@@ -204,6 +410,7 @@ static struct pinmux_ops tegra_pinmux_ops = {
204static int tegra_pinconf_reg(struct tegra_pmx *pmx, 410static int tegra_pinconf_reg(struct tegra_pmx *pmx,
205 const struct tegra_pingroup *g, 411 const struct tegra_pingroup *g,
206 enum tegra_pinconf_param param, 412 enum tegra_pinconf_param param,
413 bool report_err,
207 s8 *bank, s16 *reg, s8 *bit, s8 *width) 414 s8 *bank, s16 *reg, s8 *bit, s8 *width)
208{ 415{
209 switch (param) { 416 switch (param) {
@@ -291,9 +498,10 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
291 } 498 }
292 499
293 if (*reg < 0) { 500 if (*reg < 0) {
294 dev_err(pmx->dev, 501 if (report_err)
295 "Config param %04x not supported on group %s\n", 502 dev_err(pmx->dev,
296 param, g->name); 503 "Config param %04x not supported on group %s\n",
504 param, g->name);
297 return -ENOTSUPP; 505 return -ENOTSUPP;
298 } 506 }
299 507
@@ -303,12 +511,14 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
303static int tegra_pinconf_get(struct pinctrl_dev *pctldev, 511static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
304 unsigned pin, unsigned long *config) 512 unsigned pin, unsigned long *config)
305{ 513{
514 dev_err(pctldev->dev, "pin_config_get op not supported\n");
306 return -ENOTSUPP; 515 return -ENOTSUPP;
307} 516}
308 517
309static int tegra_pinconf_set(struct pinctrl_dev *pctldev, 518static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
310 unsigned pin, unsigned long config) 519 unsigned pin, unsigned long config)
311{ 520{
521 dev_err(pctldev->dev, "pin_config_set op not supported\n");
312 return -ENOTSUPP; 522 return -ENOTSUPP;
313} 523}
314 524
@@ -324,11 +534,10 @@ static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
324 s16 reg; 534 s16 reg;
325 u32 val, mask; 535 u32 val, mask;
326 536
327 if (group >= pmx->soc->ngroups)
328 return -EINVAL;
329 g = &pmx->soc->groups[group]; 537 g = &pmx->soc->groups[group];
330 538
331 ret = tegra_pinconf_reg(pmx, g, param, &bank, &reg, &bit, &width); 539 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
540 &width);
332 if (ret < 0) 541 if (ret < 0)
333 return ret; 542 return ret;
334 543
@@ -353,11 +562,10 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
353 s16 reg; 562 s16 reg;
354 u32 val, mask; 563 u32 val, mask;
355 564
356 if (group >= pmx->soc->ngroups)
357 return -EINVAL;
358 g = &pmx->soc->groups[group]; 565 g = &pmx->soc->groups[group];
359 566
360 ret = tegra_pinconf_reg(pmx, g, param, &bank, &reg, &bit, &width); 567 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
568 &width);
361 if (ret < 0) 569 if (ret < 0)
362 return ret; 570 return ret;
363 571
@@ -365,8 +573,10 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
365 573
366 /* LOCK can't be cleared */ 574 /* LOCK can't be cleared */
367 if (param == TEGRA_PINCONF_PARAM_LOCK) { 575 if (param == TEGRA_PINCONF_PARAM_LOCK) {
368 if ((val & BIT(bit)) && !arg) 576 if ((val & BIT(bit)) && !arg) {
577 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
369 return -EINVAL; 578 return -EINVAL;
579 }
370 } 580 }
371 581
372 /* Special-case Boolean values; allow any non-zero as true */ 582 /* Special-case Boolean values; allow any non-zero as true */
@@ -375,8 +585,12 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
375 585
376 /* Range-check user-supplied value */ 586 /* Range-check user-supplied value */
377 mask = (1 << width) - 1; 587 mask = (1 << width) - 1;
378 if (arg & ~mask) 588 if (arg & ~mask) {
589 dev_err(pctldev->dev,
590 "config %lx: %x too big for %d bit register\n",
591 config, arg, width);
379 return -EINVAL; 592 return -EINVAL;
593 }
380 594
381 /* Update register */ 595 /* Update register */
382 val &= ~(mask << bit); 596 val &= ~(mask << bit);
@@ -386,23 +600,78 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
386 return 0; 600 return 0;
387} 601}
388 602
603#ifdef CONFIG_DEBUG_FS
389static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev, 604static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
390 struct seq_file *s, unsigned offset) 605 struct seq_file *s, unsigned offset)
391{ 606{
392} 607}
393 608
609static const char *strip_prefix(const char *s)
610{
611 const char *comma = strchr(s, ',');
612 if (!comma)
613 return s;
614
615 return comma + 1;
616}
617
394static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 618static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
395 struct seq_file *s, unsigned selector) 619 struct seq_file *s, unsigned group)
396{ 620{
621 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
622 const struct tegra_pingroup *g;
623 int i, ret;
624 s8 bank, bit, width;
625 s16 reg;
626 u32 val;
627
628 g = &pmx->soc->groups[group];
629
630 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
631 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
632 &bank, &reg, &bit, &width);
633 if (ret < 0)
634 continue;
635
636 val = pmx_readl(pmx, bank, reg);
637 val >>= bit;
638 val &= (1 << width) - 1;
639
640 seq_printf(s, "\n\t%s=%u",
641 strip_prefix(cfg_params[i].property), val);
642 }
397} 643}
398 644
645static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
646 struct seq_file *s,
647 unsigned long config)
648{
649 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
650 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
651 const char *pname = "unknown";
652 int i;
653
654 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
655 if (cfg_params[i].param == param) {
656 pname = cfg_params[i].property;
657 break;
658 }
659 }
660
661 seq_printf(s, "%s=%d", strip_prefix(pname), arg);
662}
663#endif
664
399struct pinconf_ops tegra_pinconf_ops = { 665struct pinconf_ops tegra_pinconf_ops = {
400 .pin_config_get = tegra_pinconf_get, 666 .pin_config_get = tegra_pinconf_get,
401 .pin_config_set = tegra_pinconf_set, 667 .pin_config_set = tegra_pinconf_set,
402 .pin_config_group_get = tegra_pinconf_group_get, 668 .pin_config_group_get = tegra_pinconf_group_get,
403 .pin_config_group_set = tegra_pinconf_group_set, 669 .pin_config_group_set = tegra_pinconf_group_set,
670#ifdef CONFIG_DEBUG_FS
404 .pin_config_dbg_show = tegra_pinconf_dbg_show, 671 .pin_config_dbg_show = tegra_pinconf_dbg_show,
405 .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show, 672 .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
673 .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
674#endif
406}; 675};
407 676
408static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = { 677static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
@@ -412,60 +681,29 @@ static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
412}; 681};
413 682
414static struct pinctrl_desc tegra_pinctrl_desc = { 683static struct pinctrl_desc tegra_pinctrl_desc = {
415 .name = DRIVER_NAME,
416 .pctlops = &tegra_pinctrl_ops, 684 .pctlops = &tegra_pinctrl_ops,
417 .pmxops = &tegra_pinmux_ops, 685 .pmxops = &tegra_pinmux_ops,
418 .confops = &tegra_pinconf_ops, 686 .confops = &tegra_pinconf_ops,
419 .owner = THIS_MODULE, 687 .owner = THIS_MODULE,
420}; 688};
421 689
422static struct of_device_id tegra_pinctrl_of_match[] __devinitdata = { 690int __devinit tegra_pinctrl_probe(struct platform_device *pdev,
423#ifdef CONFIG_PINCTRL_TEGRA20 691 const struct tegra_pinctrl_soc_data *soc_data)
424 {
425 .compatible = "nvidia,tegra20-pinmux-disabled",
426 .data = tegra20_pinctrl_init,
427 },
428#endif
429#ifdef CONFIG_PINCTRL_TEGRA30
430 {
431 .compatible = "nvidia,tegra30-pinmux-disabled",
432 .data = tegra30_pinctrl_init,
433 },
434#endif
435 {},
436};
437
438static int __devinit tegra_pinctrl_probe(struct platform_device *pdev)
439{ 692{
440 const struct of_device_id *match;
441 tegra_pinctrl_soc_initf initf = NULL;
442 struct tegra_pmx *pmx; 693 struct tegra_pmx *pmx;
443 struct resource *res; 694 struct resource *res;
444 int i; 695 int i;
445 696
446 match = of_match_device(tegra_pinctrl_of_match, &pdev->dev);
447 if (match)
448 initf = (tegra_pinctrl_soc_initf)match->data;
449#ifdef CONFIG_PINCTRL_TEGRA20
450 if (!initf)
451 initf = tegra20_pinctrl_init;
452#endif
453 if (!initf) {
454 dev_err(&pdev->dev,
455 "Could not determine SoC-specific init func\n");
456 return -EINVAL;
457 }
458
459 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); 697 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
460 if (!pmx) { 698 if (!pmx) {
461 dev_err(&pdev->dev, "Can't alloc tegra_pmx\n"); 699 dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
462 return -ENOMEM; 700 return -ENOMEM;
463 } 701 }
464 pmx->dev = &pdev->dev; 702 pmx->dev = &pdev->dev;
465 703 pmx->soc = soc_data;
466 (*initf)(&pmx->soc);
467 704
468 tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios; 705 tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
706 tegra_pinctrl_desc.name = dev_name(&pdev->dev);
469 tegra_pinctrl_desc.pins = pmx->soc->pins; 707 tegra_pinctrl_desc.pins = pmx->soc->pins;
470 tegra_pinctrl_desc.npins = pmx->soc->npins; 708 tegra_pinctrl_desc.npins = pmx->soc->npins;
471 709
@@ -520,8 +758,9 @@ static int __devinit tegra_pinctrl_probe(struct platform_device *pdev)
520 758
521 return 0; 759 return 0;
522} 760}
761EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);
523 762
524static int __devexit tegra_pinctrl_remove(struct platform_device *pdev) 763int __devexit tegra_pinctrl_remove(struct platform_device *pdev)
525{ 764{
526 struct tegra_pmx *pmx = platform_get_drvdata(pdev); 765 struct tegra_pmx *pmx = platform_get_drvdata(pdev);
527 766
@@ -530,30 +769,4 @@ static int __devexit tegra_pinctrl_remove(struct platform_device *pdev)
530 769
531 return 0; 770 return 0;
532} 771}
533 772EXPORT_SYMBOL_GPL(tegra_pinctrl_remove);
534static struct platform_driver tegra_pinctrl_driver = {
535 .driver = {
536 .name = DRIVER_NAME,
537 .owner = THIS_MODULE,
538 .of_match_table = tegra_pinctrl_of_match,
539 },
540 .probe = tegra_pinctrl_probe,
541 .remove = __devexit_p(tegra_pinctrl_remove),
542};
543
544static int __init tegra_pinctrl_init(void)
545{
546 return platform_driver_register(&tegra_pinctrl_driver);
547}
548arch_initcall(tegra_pinctrl_init);
549
550static void __exit tegra_pinctrl_exit(void)
551{
552 platform_driver_unregister(&tegra_pinctrl_driver);
553}
554module_exit(tegra_pinctrl_exit);
555
556MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
557MODULE_DESCRIPTION("NVIDIA Tegra pinctrl driver");
558MODULE_LICENSE("GPL v2");
559MODULE_DEVICE_TABLE(of, tegra_pinctrl_of_match);
diff --git a/drivers/pinctrl/pinctrl-tegra.h b/drivers/pinctrl/pinctrl-tegra.h
index 782c795326e..705c007a38c 100644
--- a/drivers/pinctrl/pinctrl-tegra.h
+++ b/drivers/pinctrl/pinctrl-tegra.h
@@ -139,25 +139,8 @@ struct tegra_pinctrl_soc_data {
139 unsigned ngroups; 139 unsigned ngroups;
140}; 140};
141 141
142/** 142int tegra_pinctrl_probe(struct platform_device *pdev,
143 * tegra_pinctrl_soc_initf() - Retrieve pin controller details for a SoC. 143 const struct tegra_pinctrl_soc_data *soc_data);
144 * @soc_data: This pointer must be updated to point at a struct containing 144int tegra_pinctrl_remove(struct platform_device *pdev);
145 * details of the SoC.
146 */
147typedef void (*tegra_pinctrl_soc_initf)(
148 const struct tegra_pinctrl_soc_data **soc_data);
149
150/**
151 * tegra20_pinctrl_init() - Retrieve pin controller details for Tegra20
152 * @soc_data: This pointer will be updated to point at a struct containing
153 * details of Tegra20's pin controller.
154 */
155void tegra20_pinctrl_init(const struct tegra_pinctrl_soc_data **soc_data);
156/**
157 * tegra30_pinctrl_init() - Retrieve pin controller details for Tegra20
158 * @soc_data: This pointer will be updated to point at a struct containing
159 * details of Tegra30's pin controller.
160 */
161void tegra30_pinctrl_init(const struct tegra_pinctrl_soc_data **soc_data);
162 145
163#endif 146#endif
diff --git a/drivers/pinctrl/pinctrl-tegra20.c b/drivers/pinctrl/pinctrl-tegra20.c
index f69ff96aa29..a74f9a56853 100644
--- a/drivers/pinctrl/pinctrl-tegra20.c
+++ b/drivers/pinctrl/pinctrl-tegra20.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Pinctrl data for the NVIDIA Tegra20 pinmux 2 * Pinctrl data for the NVIDIA Tegra20 pinmux
3 * 3 *
4 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Derived from code: 6 * Derived from code:
7 * Copyright (C) 2010 Google, Inc. 7 * Copyright (C) 2010 Google, Inc.
@@ -17,6 +17,8 @@
17 * more details. 17 * more details.
18 */ 18 */
19 19
20#include <linux/module.h>
21#include <linux/of.h>
20#include <linux/platform_device.h> 22#include <linux/platform_device.h>
21#include <linux/pinctrl/pinctrl.h> 23#include <linux/pinctrl/pinctrl.h>
22#include <linux/pinctrl/pinmux.h> 24#include <linux/pinctrl/pinmux.h>
@@ -2854,7 +2856,39 @@ static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {
2854 .ngroups = ARRAY_SIZE(tegra20_groups), 2856 .ngroups = ARRAY_SIZE(tegra20_groups),
2855}; 2857};
2856 2858
2857void __devinit tegra20_pinctrl_init(const struct tegra_pinctrl_soc_data **soc) 2859static int __devinit tegra20_pinctrl_probe(struct platform_device *pdev)
2858{ 2860{
2859 *soc = &tegra20_pinctrl; 2861 return tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
2860} 2862}
2863
2864static struct of_device_id tegra20_pinctrl_of_match[] __devinitdata = {
2865 { .compatible = "nvidia,tegra20-pinmux", },
2866 { },
2867};
2868
2869static struct platform_driver tegra20_pinctrl_driver = {
2870 .driver = {
2871 .name = "tegra20-pinctrl",
2872 .owner = THIS_MODULE,
2873 .of_match_table = tegra20_pinctrl_of_match,
2874 },
2875 .probe = tegra20_pinctrl_probe,
2876 .remove = __devexit_p(tegra_pinctrl_remove),
2877};
2878
2879static int __init tegra20_pinctrl_init(void)
2880{
2881 return platform_driver_register(&tegra20_pinctrl_driver);
2882}
2883arch_initcall(tegra20_pinctrl_init);
2884
2885static void __exit tegra20_pinctrl_exit(void)
2886{
2887 platform_driver_unregister(&tegra20_pinctrl_driver);
2888}
2889module_exit(tegra20_pinctrl_exit);
2890
2891MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
2892MODULE_DESCRIPTION("NVIDIA Tegra20 pinctrl driver");
2893MODULE_LICENSE("GPL v2");
2894MODULE_DEVICE_TABLE(of, tegra20_pinctrl_of_match);
diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c
index 4d7571d4a43..0386fdf0da1 100644
--- a/drivers/pinctrl/pinctrl-tegra30.c
+++ b/drivers/pinctrl/pinctrl-tegra30.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Pinctrl data for the NVIDIA Tegra30 pinmux 2 * Pinctrl data for the NVIDIA Tegra30 pinmux
3 * 3 *
4 * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -13,6 +13,8 @@
13 * more details. 13 * more details.
14 */ 14 */
15 15
16#include <linux/module.h>
17#include <linux/of.h>
16#include <linux/platform_device.h> 18#include <linux/platform_device.h>
17#include <linux/pinctrl/pinctrl.h> 19#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h> 20#include <linux/pinctrl/pinmux.h>
@@ -3720,7 +3722,39 @@ static const struct tegra_pinctrl_soc_data tegra30_pinctrl = {
3720 .ngroups = ARRAY_SIZE(tegra30_groups), 3722 .ngroups = ARRAY_SIZE(tegra30_groups),
3721}; 3723};
3722 3724
3723void __devinit tegra30_pinctrl_init(const struct tegra_pinctrl_soc_data **soc) 3725static int __devinit tegra30_pinctrl_probe(struct platform_device *pdev)
3724{ 3726{
3725 *soc = &tegra30_pinctrl; 3727 return tegra_pinctrl_probe(pdev, &tegra30_pinctrl);
3726} 3728}
3729
3730static struct of_device_id tegra30_pinctrl_of_match[] __devinitdata = {
3731 { .compatible = "nvidia,tegra30-pinmux", },
3732 { },
3733};
3734
3735static struct platform_driver tegra30_pinctrl_driver = {
3736 .driver = {
3737 .name = "tegra30-pinctrl",
3738 .owner = THIS_MODULE,
3739 .of_match_table = tegra30_pinctrl_of_match,
3740 },
3741 .probe = tegra30_pinctrl_probe,
3742 .remove = __devexit_p(tegra_pinctrl_remove),
3743};
3744
3745static int __init tegra30_pinctrl_init(void)
3746{
3747 return platform_driver_register(&tegra30_pinctrl_driver);
3748}
3749arch_initcall(tegra30_pinctrl_init);
3750
3751static void __exit tegra30_pinctrl_exit(void)
3752{
3753 platform_driver_unregister(&tegra30_pinctrl_driver);
3754}
3755module_exit(tegra30_pinctrl_exit);
3756
3757MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
3758MODULE_DESCRIPTION("NVIDIA Tegra30 pinctrl driver");
3759MODULE_LICENSE("GPL v2");
3760MODULE_DEVICE_TABLE(of, tegra30_pinctrl_of_match);
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
index 26eb8ccd72d..05d029911be 100644
--- a/drivers/pinctrl/pinctrl-u300.c
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -836,18 +836,14 @@ static const struct u300_pin_group u300_pin_groups[] = {
836 }, 836 },
837}; 837};
838 838
839static int u300_list_groups(struct pinctrl_dev *pctldev, unsigned selector) 839static int u300_get_groups_count(struct pinctrl_dev *pctldev)
840{ 840{
841 if (selector >= ARRAY_SIZE(u300_pin_groups)) 841 return ARRAY_SIZE(u300_pin_groups);
842 return -EINVAL;
843 return 0;
844} 842}
845 843
846static const char *u300_get_group_name(struct pinctrl_dev *pctldev, 844static const char *u300_get_group_name(struct pinctrl_dev *pctldev,
847 unsigned selector) 845 unsigned selector)
848{ 846{
849 if (selector >= ARRAY_SIZE(u300_pin_groups))
850 return NULL;
851 return u300_pin_groups[selector].name; 847 return u300_pin_groups[selector].name;
852} 848}
853 849
@@ -855,8 +851,6 @@ static int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
855 const unsigned **pins, 851 const unsigned **pins,
856 unsigned *num_pins) 852 unsigned *num_pins)
857{ 853{
858 if (selector >= ARRAY_SIZE(u300_pin_groups))
859 return -EINVAL;
860 *pins = u300_pin_groups[selector].pins; 854 *pins = u300_pin_groups[selector].pins;
861 *num_pins = u300_pin_groups[selector].num_pins; 855 *num_pins = u300_pin_groups[selector].num_pins;
862 return 0; 856 return 0;
@@ -869,7 +863,7 @@ static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
869} 863}
870 864
871static struct pinctrl_ops u300_pctrl_ops = { 865static struct pinctrl_ops u300_pctrl_ops = {
872 .list_groups = u300_list_groups, 866 .get_groups_count = u300_get_groups_count,
873 .get_group_name = u300_get_group_name, 867 .get_group_name = u300_get_group_name,
874 .get_group_pins = u300_get_group_pins, 868 .get_group_pins = u300_get_group_pins,
875 .pin_dbg_show = u300_pin_dbg_show, 869 .pin_dbg_show = u300_pin_dbg_show,
@@ -991,11 +985,9 @@ static void u300_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
991 u300_pmx_endisable(upmx, selector, false); 985 u300_pmx_endisable(upmx, selector, false);
992} 986}
993 987
994static int u300_pmx_list_funcs(struct pinctrl_dev *pctldev, unsigned selector) 988static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
995{ 989{
996 if (selector >= ARRAY_SIZE(u300_pmx_functions)) 990 return ARRAY_SIZE(u300_pmx_functions);
997 return -EINVAL;
998 return 0;
999} 991}
1000 992
1001static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev, 993static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev,
@@ -1014,7 +1006,7 @@ static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
1014} 1006}
1015 1007
1016static struct pinmux_ops u300_pmx_ops = { 1008static struct pinmux_ops u300_pmx_ops = {
1017 .list_functions = u300_pmx_list_funcs, 1009 .get_functions_count = u300_pmx_get_funcs_count,
1018 .get_function_name = u300_pmx_get_func_name, 1010 .get_function_name = u300_pmx_get_func_name,
1019 .get_function_groups = u300_pmx_get_groups, 1011 .get_function_groups = u300_pmx_get_groups,
1020 .enable = u300_pmx_enable, 1012 .enable = u300_pmx_enable,
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index 4e62783a573..220fa492c9f 100644
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -33,22 +33,26 @@
33int pinmux_check_ops(struct pinctrl_dev *pctldev) 33int pinmux_check_ops(struct pinctrl_dev *pctldev)
34{ 34{
35 const struct pinmux_ops *ops = pctldev->desc->pmxops; 35 const struct pinmux_ops *ops = pctldev->desc->pmxops;
36 unsigned nfuncs;
36 unsigned selector = 0; 37 unsigned selector = 0;
37 38
38 /* Check that we implement required operations */ 39 /* Check that we implement required operations */
39 if (!ops->list_functions || 40 if (!ops ||
41 !ops->get_functions_count ||
40 !ops->get_function_name || 42 !ops->get_function_name ||
41 !ops->get_function_groups || 43 !ops->get_function_groups ||
42 !ops->enable || 44 !ops->enable ||
43 !ops->disable) 45 !ops->disable) {
46 dev_err(pctldev->dev, "pinmux ops lacks necessary functions\n");
44 return -EINVAL; 47 return -EINVAL;
45 48 }
46 /* Check that all functions registered have names */ 49 /* Check that all functions registered have names */
47 while (ops->list_functions(pctldev, selector) >= 0) { 50 nfuncs = ops->get_functions_count(pctldev);
51 while (selector < nfuncs) {
48 const char *fname = ops->get_function_name(pctldev, 52 const char *fname = ops->get_function_name(pctldev,
49 selector); 53 selector);
50 if (!fname) { 54 if (!fname) {
51 pr_err("pinmux ops has no name for function%u\n", 55 dev_err(pctldev->dev, "pinmux ops has no name for function%u\n",
52 selector); 56 selector);
53 return -EINVAL; 57 return -EINVAL;
54 } 58 }
@@ -85,20 +89,23 @@ static int pin_request(struct pinctrl_dev *pctldev,
85 const struct pinmux_ops *ops = pctldev->desc->pmxops; 89 const struct pinmux_ops *ops = pctldev->desc->pmxops;
86 int status = -EINVAL; 90 int status = -EINVAL;
87 91
88 dev_dbg(pctldev->dev, "request pin %d for %s\n", pin, owner);
89
90 desc = pin_desc_get(pctldev, pin); 92 desc = pin_desc_get(pctldev, pin);
91 if (desc == NULL) { 93 if (desc == NULL) {
92 dev_err(pctldev->dev, 94 dev_err(pctldev->dev,
93 "pin is not registered so it cannot be requested\n"); 95 "pin %d is not registered so it cannot be requested\n",
96 pin);
94 goto out; 97 goto out;
95 } 98 }
96 99
100 dev_dbg(pctldev->dev, "request pin %d (%s) for %s\n",
101 pin, desc->name, owner);
102
97 if (gpio_range) { 103 if (gpio_range) {
98 /* There's no need to support multiple GPIO requests */ 104 /* There's no need to support multiple GPIO requests */
99 if (desc->gpio_owner) { 105 if (desc->gpio_owner) {
100 dev_err(pctldev->dev, 106 dev_err(pctldev->dev,
101 "pin already requested\n"); 107 "pin %s already requested by %s; cannot claim for %s\n",
108 desc->name, desc->gpio_owner, owner);
102 goto out; 109 goto out;
103 } 110 }
104 111
@@ -106,7 +113,8 @@ static int pin_request(struct pinctrl_dev *pctldev,
106 } else { 113 } else {
107 if (desc->mux_usecount && strcmp(desc->mux_owner, owner)) { 114 if (desc->mux_usecount && strcmp(desc->mux_owner, owner)) {
108 dev_err(pctldev->dev, 115 dev_err(pctldev->dev,
109 "pin already requested\n"); 116 "pin %s already requested by %s; cannot claim for %s\n",
117 desc->name, desc->mux_owner, owner);
110 goto out; 118 goto out;
111 } 119 }
112 120
@@ -139,8 +147,7 @@ static int pin_request(struct pinctrl_dev *pctldev,
139 status = 0; 147 status = 0;
140 148
141 if (status) { 149 if (status) {
142 dev_err(pctldev->dev, "->request on device %s failed for pin %d\n", 150 dev_err(pctldev->dev, "request() failed for pin %d\n", pin);
143 pctldev->desc->name, pin);
144 module_put(pctldev->owner); 151 module_put(pctldev->owner);
145 } 152 }
146 153
@@ -157,7 +164,7 @@ out_free_pin:
157out: 164out:
158 if (status) 165 if (status)
159 dev_err(pctldev->dev, "pin-%d (%s) status %d\n", 166 dev_err(pctldev->dev, "pin-%d (%s) status %d\n",
160 pin, owner, status); 167 pin, owner, status);
161 168
162 return status; 169 return status;
163} 170}
@@ -287,10 +294,11 @@ static int pinmux_func_name_to_selector(struct pinctrl_dev *pctldev,
287 const char *function) 294 const char *function)
288{ 295{
289 const struct pinmux_ops *ops = pctldev->desc->pmxops; 296 const struct pinmux_ops *ops = pctldev->desc->pmxops;
297 unsigned nfuncs = ops->get_functions_count(pctldev);
290 unsigned selector = 0; 298 unsigned selector = 0;
291 299
292 /* See if this pctldev has this function */ 300 /* See if this pctldev has this function */
293 while (ops->list_functions(pctldev, selector) >= 0) { 301 while (selector < nfuncs) {
294 const char *fname = ops->get_function_name(pctldev, 302 const char *fname = ops->get_function_name(pctldev,
295 selector); 303 selector);
296 304
@@ -319,18 +327,32 @@ int pinmux_map_to_setting(struct pinctrl_map const *map,
319 const unsigned *pins; 327 const unsigned *pins;
320 unsigned num_pins; 328 unsigned num_pins;
321 329
322 setting->data.mux.func = 330 if (!pmxops) {
323 pinmux_func_name_to_selector(pctldev, map->data.mux.function); 331 dev_err(pctldev->dev, "does not support mux function\n");
324 if (setting->data.mux.func < 0) 332 return -EINVAL;
325 return setting->data.mux.func; 333 }
334
335 ret = pinmux_func_name_to_selector(pctldev, map->data.mux.function);
336 if (ret < 0) {
337 dev_err(pctldev->dev, "invalid function %s in map table\n",
338 map->data.mux.function);
339 return ret;
340 }
341 setting->data.mux.func = ret;
326 342
327 ret = pmxops->get_function_groups(pctldev, setting->data.mux.func, 343 ret = pmxops->get_function_groups(pctldev, setting->data.mux.func,
328 &groups, &num_groups); 344 &groups, &num_groups);
329 if (ret < 0) 345 if (ret < 0) {
346 dev_err(pctldev->dev, "can't query groups for function %s\n",
347 map->data.mux.function);
330 return ret; 348 return ret;
331 if (!num_groups) 349 }
350 if (!num_groups) {
351 dev_err(pctldev->dev,
352 "function %s can't be selected on any group\n",
353 map->data.mux.function);
332 return -EINVAL; 354 return -EINVAL;
333 355 }
334 if (map->data.mux.group) { 356 if (map->data.mux.group) {
335 bool found = false; 357 bool found = false;
336 group = map->data.mux.group; 358 group = map->data.mux.group;
@@ -340,15 +362,23 @@ int pinmux_map_to_setting(struct pinctrl_map const *map,
340 break; 362 break;
341 } 363 }
342 } 364 }
343 if (!found) 365 if (!found) {
366 dev_err(pctldev->dev,
367 "invalid group \"%s\" for function \"%s\"\n",
368 group, map->data.mux.function);
344 return -EINVAL; 369 return -EINVAL;
370 }
345 } else { 371 } else {
346 group = groups[0]; 372 group = groups[0];
347 } 373 }
348 374
349 setting->data.mux.group = pinctrl_get_group_selector(pctldev, group); 375 ret = pinctrl_get_group_selector(pctldev, group);
350 if (setting->data.mux.group < 0) 376 if (ret < 0) {
351 return setting->data.mux.group; 377 dev_err(pctldev->dev, "invalid group %s in map table\n",
378 map->data.mux.group);
379 return ret;
380 }
381 setting->data.mux.group = ret;
352 382
353 ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, &pins, 383 ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, &pins,
354 &num_pins); 384 &num_pins);
@@ -364,7 +394,7 @@ int pinmux_map_to_setting(struct pinctrl_map const *map,
364 ret = pin_request(pctldev, pins[i], map->dev_name, NULL); 394 ret = pin_request(pctldev, pins[i], map->dev_name, NULL);
365 if (ret) { 395 if (ret) {
366 dev_err(pctldev->dev, 396 dev_err(pctldev->dev,
367 "could not get request pin %d on device %s\n", 397 "could not request pin %d on device %s\n",
368 pins[i], pinctrl_dev_get_name(pctldev)); 398 pins[i], pinctrl_dev_get_name(pctldev));
369 /* On error release all taken pins */ 399 /* On error release all taken pins */
370 i--; /* this pin just failed */ 400 i--; /* this pin just failed */
@@ -477,11 +507,15 @@ static int pinmux_functions_show(struct seq_file *s, void *what)
477{ 507{
478 struct pinctrl_dev *pctldev = s->private; 508 struct pinctrl_dev *pctldev = s->private;
479 const struct pinmux_ops *pmxops = pctldev->desc->pmxops; 509 const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
510 unsigned nfuncs;
480 unsigned func_selector = 0; 511 unsigned func_selector = 0;
481 512
482 mutex_lock(&pinctrl_mutex); 513 if (!pmxops)
514 return 0;
483 515
484 while (pmxops->list_functions(pctldev, func_selector) >= 0) { 516 mutex_lock(&pinctrl_mutex);
517 nfuncs = pmxops->get_functions_count(pctldev);
518 while (func_selector < nfuncs) {
485 const char *func = pmxops->get_function_name(pctldev, 519 const char *func = pmxops->get_function_name(pctldev,
486 func_selector); 520 func_selector);
487 const char * const *groups; 521 const char * const *groups;
@@ -515,6 +549,9 @@ static int pinmux_pins_show(struct seq_file *s, void *what)
515 const struct pinmux_ops *pmxops = pctldev->desc->pmxops; 549 const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
516 unsigned i, pin; 550 unsigned i, pin;
517 551
552 if (!pmxops)
553 return 0;
554
518 seq_puts(s, "Pinmux settings per pin\n"); 555 seq_puts(s, "Pinmux settings per pin\n");
519 seq_puts(s, "Format: pin (name): mux_owner gpio_owner hog?\n"); 556 seq_puts(s, "Format: pin (name): mux_owner gpio_owner hog?\n");
520 557
diff --git a/drivers/pinctrl/pinmux.h b/drivers/pinctrl/pinmux.h
index 6fc47003e95..d1a98b1c9fc 100644
--- a/drivers/pinctrl/pinmux.h
+++ b/drivers/pinctrl/pinmux.h
@@ -31,12 +31,6 @@ void pinmux_free_setting(struct pinctrl_setting const *setting);
31int pinmux_enable_setting(struct pinctrl_setting const *setting); 31int pinmux_enable_setting(struct pinctrl_setting const *setting);
32void pinmux_disable_setting(struct pinctrl_setting const *setting); 32void pinmux_disable_setting(struct pinctrl_setting const *setting);
33 33
34void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map);
35void pinmux_show_setting(struct seq_file *s,
36 struct pinctrl_setting const *setting);
37void pinmux_init_device_debugfs(struct dentry *devroot,
38 struct pinctrl_dev *pctldev);
39
40#else 34#else
41 35
42static inline int pinmux_check_ops(struct pinctrl_dev *pctldev) 36static inline int pinmux_check_ops(struct pinctrl_dev *pctldev)
@@ -89,6 +83,18 @@ static inline void pinmux_disable_setting(
89{ 83{
90} 84}
91 85
86#endif
87
88#if defined(CONFIG_PINMUX) && defined(CONFIG_DEBUG_FS)
89
90void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map);
91void pinmux_show_setting(struct seq_file *s,
92 struct pinctrl_setting const *setting);
93void pinmux_init_device_debugfs(struct dentry *devroot,
94 struct pinctrl_dev *pctldev);
95
96#else
97
92static inline void pinmux_show_map(struct seq_file *s, 98static inline void pinmux_show_map(struct seq_file *s,
93 struct pinctrl_map const *map) 99 struct pinctrl_map const *map)
94{ 100{
diff --git a/drivers/pinctrl/spear/Kconfig b/drivers/pinctrl/spear/Kconfig
new file mode 100644
index 00000000000..6a2596b4f35
--- /dev/null
+++ b/drivers/pinctrl/spear/Kconfig
@@ -0,0 +1,34 @@
1#
2# ST Microelectronics SPEAr PINCTRL drivers
3#
4
5if PLAT_SPEAR
6
7config PINCTRL_SPEAR
8 bool
9 depends on OF
10 select PINMUX
11 help
12 This enables pin control drivers for SPEAr Platform
13
14config PINCTRL_SPEAR3XX
15 bool
16 depends on ARCH_SPEAR3XX
17 select PINCTRL_SPEAR
18
19config PINCTRL_SPEAR300
20 bool "ST Microelectronics SPEAr300 SoC pin controller driver"
21 depends on MACH_SPEAR300
22 select PINCTRL_SPEAR3XX
23
24config PINCTRL_SPEAR310
25 bool "ST Microelectronics SPEAr310 SoC pin controller driver"
26 depends on MACH_SPEAR310
27 select PINCTRL_SPEAR3XX
28
29config PINCTRL_SPEAR320
30 bool "ST Microelectronics SPEAr320 SoC pin controller driver"
31 depends on MACH_SPEAR320
32 select PINCTRL_SPEAR3XX
33
34endif
diff --git a/drivers/pinctrl/spear/Makefile b/drivers/pinctrl/spear/Makefile
new file mode 100644
index 00000000000..15dcb85da22
--- /dev/null
+++ b/drivers/pinctrl/spear/Makefile
@@ -0,0 +1,7 @@
1# SPEAr pinmux support
2
3obj-$(CONFIG_PINCTRL_SPEAR) += pinctrl-spear.o
4obj-$(CONFIG_PINCTRL_SPEAR3XX) += pinctrl-spear3xx.o
5obj-$(CONFIG_PINCTRL_SPEAR300) += pinctrl-spear300.o
6obj-$(CONFIG_PINCTRL_SPEAR310) += pinctrl-spear310.o
7obj-$(CONFIG_PINCTRL_SPEAR320) += pinctrl-spear320.o
diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c
new file mode 100644
index 00000000000..5ae50aadf88
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear.c
@@ -0,0 +1,354 @@
1/*
2 * Driver for the ST Microelectronics SPEAr pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * Inspired from:
8 * - U300 Pinctl drivers
9 * - Tegra Pinctl drivers
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/pinctrl/machine.h>
22#include <linux/pinctrl/pinctrl.h>
23#include <linux/pinctrl/pinmux.h>
24#include <linux/platform_device.h>
25#include <linux/slab.h>
26
27#include "pinctrl-spear.h"
28
29#define DRIVER_NAME "spear-pinmux"
30
31static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg)
32{
33 return readl_relaxed(pmx->vbase + reg);
34}
35
36static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg)
37{
38 writel_relaxed(val, pmx->vbase + reg);
39}
40
41static int set_mode(struct spear_pmx *pmx, int mode)
42{
43 struct spear_pmx_mode *pmx_mode = NULL;
44 int i;
45 u32 val;
46
47 if (!pmx->machdata->pmx_modes || !pmx->machdata->npmx_modes)
48 return -EINVAL;
49
50 for (i = 0; i < pmx->machdata->npmx_modes; i++) {
51 if (pmx->machdata->pmx_modes[i]->mode == (1 << mode)) {
52 pmx_mode = pmx->machdata->pmx_modes[i];
53 break;
54 }
55 }
56
57 if (!pmx_mode)
58 return -EINVAL;
59
60 val = pmx_readl(pmx, pmx_mode->reg);
61 val &= ~pmx_mode->mask;
62 val |= pmx_mode->val;
63 pmx_writel(pmx, val, pmx_mode->reg);
64
65 pmx->machdata->mode = pmx_mode->mode;
66 dev_info(pmx->dev, "Configured Mode: %s with id: %x\n\n",
67 pmx_mode->name ? pmx_mode->name : "no_name",
68 pmx_mode->reg);
69
70 return 0;
71}
72
73void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg)
74{
75 struct spear_pingroup *pgroup;
76 struct spear_modemux *modemux;
77 int i, j, group;
78
79 for (group = 0; group < machdata->ngroups; group++) {
80 pgroup = machdata->groups[group];
81
82 for (i = 0; i < pgroup->nmodemuxs; i++) {
83 modemux = &pgroup->modemuxs[i];
84
85 for (j = 0; j < modemux->nmuxregs; j++)
86 if (modemux->muxregs[j].reg == 0xFFFF)
87 modemux->muxregs[j].reg = reg;
88 }
89 }
90}
91
92static int spear_pinctrl_get_groups_cnt(struct pinctrl_dev *pctldev)
93{
94 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
95
96 return pmx->machdata->ngroups;
97}
98
99static const char *spear_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
100 unsigned group)
101{
102 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
103
104 return pmx->machdata->groups[group]->name;
105}
106
107static int spear_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
108 unsigned group, const unsigned **pins, unsigned *num_pins)
109{
110 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
111
112 *pins = pmx->machdata->groups[group]->pins;
113 *num_pins = pmx->machdata->groups[group]->npins;
114
115 return 0;
116}
117
118static void spear_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
119 struct seq_file *s, unsigned offset)
120{
121 seq_printf(s, " " DRIVER_NAME);
122}
123
124int spear_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
125 struct device_node *np_config,
126 struct pinctrl_map **map, unsigned *num_maps)
127{
128 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
129 struct device_node *np;
130 struct property *prop;
131 const char *function, *group;
132 int ret, index = 0, count = 0;
133
134 /* calculate number of maps required */
135 for_each_child_of_node(np_config, np) {
136 ret = of_property_read_string(np, "st,function", &function);
137 if (ret < 0)
138 return ret;
139
140 ret = of_property_count_strings(np, "st,pins");
141 if (ret < 0)
142 return ret;
143
144 count += ret;
145 }
146
147 if (!count) {
148 dev_err(pmx->dev, "No child nodes passed via DT\n");
149 return -ENODEV;
150 }
151
152 *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
153 if (!*map)
154 return -ENOMEM;
155
156 for_each_child_of_node(np_config, np) {
157 of_property_read_string(np, "st,function", &function);
158 of_property_for_each_string(np, "st,pins", prop, group) {
159 (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
160 (*map)[index].data.mux.group = group;
161 (*map)[index].data.mux.function = function;
162 index++;
163 }
164 }
165
166 *num_maps = count;
167
168 return 0;
169}
170
171void spear_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
172 struct pinctrl_map *map, unsigned num_maps)
173{
174 kfree(map);
175}
176
177static struct pinctrl_ops spear_pinctrl_ops = {
178 .get_groups_count = spear_pinctrl_get_groups_cnt,
179 .get_group_name = spear_pinctrl_get_group_name,
180 .get_group_pins = spear_pinctrl_get_group_pins,
181 .pin_dbg_show = spear_pinctrl_pin_dbg_show,
182 .dt_node_to_map = spear_pinctrl_dt_node_to_map,
183 .dt_free_map = spear_pinctrl_dt_free_map,
184};
185
186static int spear_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
187{
188 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
189
190 return pmx->machdata->nfunctions;
191}
192
193static const char *spear_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
194 unsigned function)
195{
196 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
197
198 return pmx->machdata->functions[function]->name;
199}
200
201static int spear_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
202 unsigned function, const char *const **groups,
203 unsigned * const ngroups)
204{
205 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
206
207 *groups = pmx->machdata->functions[function]->groups;
208 *ngroups = pmx->machdata->functions[function]->ngroups;
209
210 return 0;
211}
212
213static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev,
214 unsigned function, unsigned group, bool enable)
215{
216 struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
217 const struct spear_pingroup *pgroup;
218 const struct spear_modemux *modemux;
219 struct spear_muxreg *muxreg;
220 u32 val, temp;
221 int i, j;
222 bool found = false;
223
224 pgroup = pmx->machdata->groups[group];
225
226 for (i = 0; i < pgroup->nmodemuxs; i++) {
227 modemux = &pgroup->modemuxs[i];
228
229 /* SoC have any modes */
230 if (pmx->machdata->modes_supported) {
231 if (!(pmx->machdata->mode & modemux->modes))
232 continue;
233 }
234
235 found = true;
236 for (j = 0; j < modemux->nmuxregs; j++) {
237 muxreg = &modemux->muxregs[j];
238
239 val = pmx_readl(pmx, muxreg->reg);
240 val &= ~muxreg->mask;
241
242 if (enable)
243 temp = muxreg->val;
244 else
245 temp = ~muxreg->val;
246
247 val |= temp;
248 pmx_writel(pmx, val, muxreg->reg);
249 }
250 }
251
252 if (!found) {
253 dev_err(pmx->dev, "pinmux group: %s not supported\n",
254 pgroup->name);
255 return -ENODEV;
256 }
257
258 return 0;
259}
260
261static int spear_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
262 unsigned group)
263{
264 return spear_pinctrl_endisable(pctldev, function, group, true);
265}
266
267static void spear_pinctrl_disable(struct pinctrl_dev *pctldev,
268 unsigned function, unsigned group)
269{
270 spear_pinctrl_endisable(pctldev, function, group, false);
271}
272
273static struct pinmux_ops spear_pinmux_ops = {
274 .get_functions_count = spear_pinctrl_get_funcs_count,
275 .get_function_name = spear_pinctrl_get_func_name,
276 .get_function_groups = spear_pinctrl_get_func_groups,
277 .enable = spear_pinctrl_enable,
278 .disable = spear_pinctrl_disable,
279};
280
281static struct pinctrl_desc spear_pinctrl_desc = {
282 .name = DRIVER_NAME,
283 .pctlops = &spear_pinctrl_ops,
284 .pmxops = &spear_pinmux_ops,
285 .owner = THIS_MODULE,
286};
287
288int __devinit spear_pinctrl_probe(struct platform_device *pdev,
289 struct spear_pinctrl_machdata *machdata)
290{
291 struct device_node *np = pdev->dev.of_node;
292 struct resource *res;
293 struct spear_pmx *pmx;
294
295 if (!machdata)
296 return -ENODEV;
297
298 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
299 if (!res)
300 return -EINVAL;
301
302 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
303 if (!pmx) {
304 dev_err(&pdev->dev, "Can't alloc spear_pmx\n");
305 return -ENOMEM;
306 }
307
308 pmx->vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
309 if (!pmx->vbase) {
310 dev_err(&pdev->dev, "Couldn't ioremap at index 0\n");
311 return -ENODEV;
312 }
313
314 pmx->dev = &pdev->dev;
315 pmx->machdata = machdata;
316
317 /* configure mode, if supported by SoC */
318 if (machdata->modes_supported) {
319 int mode = 0;
320
321 if (of_property_read_u32(np, "st,pinmux-mode", &mode)) {
322 dev_err(&pdev->dev, "OF: pinmux mode not passed\n");
323 return -EINVAL;
324 }
325
326 if (set_mode(pmx, mode)) {
327 dev_err(&pdev->dev, "OF: Couldn't configure mode: %x\n",
328 mode);
329 return -EINVAL;
330 }
331 }
332
333 platform_set_drvdata(pdev, pmx);
334
335 spear_pinctrl_desc.pins = machdata->pins;
336 spear_pinctrl_desc.npins = machdata->npins;
337
338 pmx->pctl = pinctrl_register(&spear_pinctrl_desc, &pdev->dev, pmx);
339 if (IS_ERR(pmx->pctl)) {
340 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
341 return PTR_ERR(pmx->pctl);
342 }
343
344 return 0;
345}
346
347int __devexit spear_pinctrl_remove(struct platform_device *pdev)
348{
349 struct spear_pmx *pmx = platform_get_drvdata(pdev);
350
351 pinctrl_unregister(pmx->pctl);
352
353 return 0;
354}
diff --git a/drivers/pinctrl/spear/pinctrl-spear.h b/drivers/pinctrl/spear/pinctrl-spear.h
new file mode 100644
index 00000000000..47a6b5b72f9
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear.h
@@ -0,0 +1,142 @@
1/*
2 * Driver header file for the ST Microelectronics SPEAr pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#ifndef __PINMUX_SPEAR_H__
13#define __PINMUX_SPEAR_H__
14
15#include <linux/pinctrl/pinctrl.h>
16#include <linux/types.h>
17
18struct platform_device;
19struct device;
20
21/**
22 * struct spear_pmx_mode - SPEAr pmx mode
23 * @name: name of pmx mode
24 * @mode: mode id
25 * @reg: register for configuring this mode
26 * @mask: mask of this mode in reg
27 * @val: val to be configured at reg after doing (val & mask)
28 */
29struct spear_pmx_mode {
30 const char *const name;
31 u16 mode;
32 u16 reg;
33 u16 mask;
34 u32 val;
35};
36
37/**
38 * struct spear_muxreg - SPEAr mux reg configuration
39 * @reg: register offset
40 * @mask: mask bits
41 * @val: val to be written on mask bits
42 */
43struct spear_muxreg {
44 u16 reg;
45 u32 mask;
46 u32 val;
47};
48
49/**
50 * struct spear_modemux - SPEAr mode mux configuration
51 * @modes: mode ids supported by this group of muxregs
52 * @nmuxregs: number of muxreg configurations to be done for modes
53 * @muxregs: array of muxreg configurations to be done for modes
54 */
55struct spear_modemux {
56 u16 modes;
57 u8 nmuxregs;
58 struct spear_muxreg *muxregs;
59};
60
61/**
62 * struct spear_pingroup - SPEAr pin group configurations
63 * @name: name of pin group
64 * @pins: array containing pin numbers
65 * @npins: size of pins array
66 * @modemuxs: array of modemux configurations for this pin group
67 * @nmodemuxs: size of array modemuxs
68 *
69 * A representation of a group of pins in the SPEAr pin controller. Each group
70 * allows some parameter or parameters to be configured.
71 */
72struct spear_pingroup {
73 const char *name;
74 const unsigned *pins;
75 unsigned npins;
76 struct spear_modemux *modemuxs;
77 unsigned nmodemuxs;
78};
79
80/**
81 * struct spear_function - SPEAr pinctrl mux function
82 * @name: The name of the function, exported to pinctrl core.
83 * @groups: An array of pin groups that may select this function.
84 * @ngroups: The number of entries in @groups.
85 */
86struct spear_function {
87 const char *name;
88 const char *const *groups;
89 unsigned ngroups;
90};
91
92/**
93 * struct spear_pinctrl_machdata - SPEAr pin controller machine driver
94 * configuration
95 * @pins: An array describing all pins the pin controller affects.
96 * All pins which are also GPIOs must be listed first within the *array,
97 * and be numbered identically to the GPIO controller's *numbering.
98 * @npins: The numbmer of entries in @pins.
99 * @functions: An array describing all mux functions the SoC supports.
100 * @nfunctions: The numbmer of entries in @functions.
101 * @groups: An array describing all pin groups the pin SoC supports.
102 * @ngroups: The numbmer of entries in @groups.
103 *
104 * @modes_supported: Does SoC support modes
105 * @mode: mode configured from probe
106 * @pmx_modes: array of modes supported by SoC
107 * @npmx_modes: number of entries in pmx_modes.
108 */
109struct spear_pinctrl_machdata {
110 const struct pinctrl_pin_desc *pins;
111 unsigned npins;
112 struct spear_function **functions;
113 unsigned nfunctions;
114 struct spear_pingroup **groups;
115 unsigned ngroups;
116
117 bool modes_supported;
118 u16 mode;
119 struct spear_pmx_mode **pmx_modes;
120 unsigned npmx_modes;
121};
122
123/**
124 * struct spear_pmx - SPEAr pinctrl mux
125 * @dev: pointer to struct dev of platform_device registered
126 * @pctl: pointer to struct pinctrl_dev
127 * @machdata: pointer to SoC or machine specific structure
128 * @vbase: virtual base address of pinmux controller
129 */
130struct spear_pmx {
131 struct device *dev;
132 struct pinctrl_dev *pctl;
133 struct spear_pinctrl_machdata *machdata;
134 void __iomem *vbase;
135};
136
137/* exported routines */
138void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
139int __devinit spear_pinctrl_probe(struct platform_device *pdev,
140 struct spear_pinctrl_machdata *machdata);
141int __devexit spear_pinctrl_remove(struct platform_device *pdev);
142#endif /* __PINMUX_SPEAR_H__ */
diff --git a/drivers/pinctrl/spear/pinctrl-spear300.c b/drivers/pinctrl/spear/pinctrl-spear300.c
new file mode 100644
index 00000000000..9c82a35e4e7
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear300.c
@@ -0,0 +1,708 @@
1/*
2 * Driver for the ST Microelectronics SPEAr300 pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include "pinctrl-spear3xx.h"
18
19#define DRIVER_NAME "spear300-pinmux"
20
21/* addresses */
22#define PMX_CONFIG_REG 0x00
23#define MODE_CONFIG_REG 0x04
24
25/* modes */
26#define NAND_MODE (1 << 0)
27#define NOR_MODE (1 << 1)
28#define PHOTO_FRAME_MODE (1 << 2)
29#define LEND_IP_PHONE_MODE (1 << 3)
30#define HEND_IP_PHONE_MODE (1 << 4)
31#define LEND_WIFI_PHONE_MODE (1 << 5)
32#define HEND_WIFI_PHONE_MODE (1 << 6)
33#define ATA_PABX_WI2S_MODE (1 << 7)
34#define ATA_PABX_I2S_MODE (1 << 8)
35#define CAML_LCDW_MODE (1 << 9)
36#define CAMU_LCD_MODE (1 << 10)
37#define CAMU_WLCD_MODE (1 << 11)
38#define CAML_LCD_MODE (1 << 12)
39
40static struct spear_pmx_mode pmx_mode_nand = {
41 .name = "nand",
42 .mode = NAND_MODE,
43 .reg = MODE_CONFIG_REG,
44 .mask = 0x0000000F,
45 .val = 0x00,
46};
47
48static struct spear_pmx_mode pmx_mode_nor = {
49 .name = "nor",
50 .mode = NOR_MODE,
51 .reg = MODE_CONFIG_REG,
52 .mask = 0x0000000F,
53 .val = 0x01,
54};
55
56static struct spear_pmx_mode pmx_mode_photo_frame = {
57 .name = "photo frame mode",
58 .mode = PHOTO_FRAME_MODE,
59 .reg = MODE_CONFIG_REG,
60 .mask = 0x0000000F,
61 .val = 0x02,
62};
63
64static struct spear_pmx_mode pmx_mode_lend_ip_phone = {
65 .name = "lend ip phone mode",
66 .mode = LEND_IP_PHONE_MODE,
67 .reg = MODE_CONFIG_REG,
68 .mask = 0x0000000F,
69 .val = 0x03,
70};
71
72static struct spear_pmx_mode pmx_mode_hend_ip_phone = {
73 .name = "hend ip phone mode",
74 .mode = HEND_IP_PHONE_MODE,
75 .reg = MODE_CONFIG_REG,
76 .mask = 0x0000000F,
77 .val = 0x04,
78};
79
80static struct spear_pmx_mode pmx_mode_lend_wifi_phone = {
81 .name = "lend wifi phone mode",
82 .mode = LEND_WIFI_PHONE_MODE,
83 .reg = MODE_CONFIG_REG,
84 .mask = 0x0000000F,
85 .val = 0x05,
86};
87
88static struct spear_pmx_mode pmx_mode_hend_wifi_phone = {
89 .name = "hend wifi phone mode",
90 .mode = HEND_WIFI_PHONE_MODE,
91 .reg = MODE_CONFIG_REG,
92 .mask = 0x0000000F,
93 .val = 0x06,
94};
95
96static struct spear_pmx_mode pmx_mode_ata_pabx_wi2s = {
97 .name = "ata pabx wi2s mode",
98 .mode = ATA_PABX_WI2S_MODE,
99 .reg = MODE_CONFIG_REG,
100 .mask = 0x0000000F,
101 .val = 0x07,
102};
103
104static struct spear_pmx_mode pmx_mode_ata_pabx_i2s = {
105 .name = "ata pabx i2s mode",
106 .mode = ATA_PABX_I2S_MODE,
107 .reg = MODE_CONFIG_REG,
108 .mask = 0x0000000F,
109 .val = 0x08,
110};
111
112static struct spear_pmx_mode pmx_mode_caml_lcdw = {
113 .name = "caml lcdw mode",
114 .mode = CAML_LCDW_MODE,
115 .reg = MODE_CONFIG_REG,
116 .mask = 0x0000000F,
117 .val = 0x0C,
118};
119
120static struct spear_pmx_mode pmx_mode_camu_lcd = {
121 .name = "camu lcd mode",
122 .mode = CAMU_LCD_MODE,
123 .reg = MODE_CONFIG_REG,
124 .mask = 0x0000000F,
125 .val = 0x0D,
126};
127
128static struct spear_pmx_mode pmx_mode_camu_wlcd = {
129 .name = "camu wlcd mode",
130 .mode = CAMU_WLCD_MODE,
131 .reg = MODE_CONFIG_REG,
132 .mask = 0x0000000F,
133 .val = 0xE,
134};
135
136static struct spear_pmx_mode pmx_mode_caml_lcd = {
137 .name = "caml lcd mode",
138 .mode = CAML_LCD_MODE,
139 .reg = MODE_CONFIG_REG,
140 .mask = 0x0000000F,
141 .val = 0x0F,
142};
143
144static struct spear_pmx_mode *spear300_pmx_modes[] = {
145 &pmx_mode_nand,
146 &pmx_mode_nor,
147 &pmx_mode_photo_frame,
148 &pmx_mode_lend_ip_phone,
149 &pmx_mode_hend_ip_phone,
150 &pmx_mode_lend_wifi_phone,
151 &pmx_mode_hend_wifi_phone,
152 &pmx_mode_ata_pabx_wi2s,
153 &pmx_mode_ata_pabx_i2s,
154 &pmx_mode_caml_lcdw,
155 &pmx_mode_camu_lcd,
156 &pmx_mode_camu_wlcd,
157 &pmx_mode_caml_lcd,
158};
159
160/* fsmc_2chips_pins */
161static const unsigned fsmc_2chips_pins[] = { 1, 97 };
162static struct spear_muxreg fsmc_2chips_muxreg[] = {
163 {
164 .reg = PMX_CONFIG_REG,
165 .mask = PMX_FIRDA_MASK,
166 .val = 0,
167 },
168};
169
170static struct spear_modemux fsmc_2chips_modemux[] = {
171 {
172 .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
173 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
174 .muxregs = fsmc_2chips_muxreg,
175 .nmuxregs = ARRAY_SIZE(fsmc_2chips_muxreg),
176 },
177};
178
179static struct spear_pingroup fsmc_2chips_pingroup = {
180 .name = "fsmc_2chips_grp",
181 .pins = fsmc_2chips_pins,
182 .npins = ARRAY_SIZE(fsmc_2chips_pins),
183 .modemuxs = fsmc_2chips_modemux,
184 .nmodemuxs = ARRAY_SIZE(fsmc_2chips_modemux),
185};
186
187/* fsmc_4chips_pins */
188static const unsigned fsmc_4chips_pins[] = { 1, 2, 3, 97 };
189static struct spear_muxreg fsmc_4chips_muxreg[] = {
190 {
191 .reg = PMX_CONFIG_REG,
192 .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
193 .val = 0,
194 },
195};
196
197static struct spear_modemux fsmc_4chips_modemux[] = {
198 {
199 .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
200 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
201 .muxregs = fsmc_4chips_muxreg,
202 .nmuxregs = ARRAY_SIZE(fsmc_4chips_muxreg),
203 },
204};
205
206static struct spear_pingroup fsmc_4chips_pingroup = {
207 .name = "fsmc_4chips_grp",
208 .pins = fsmc_4chips_pins,
209 .npins = ARRAY_SIZE(fsmc_4chips_pins),
210 .modemuxs = fsmc_4chips_modemux,
211 .nmodemuxs = ARRAY_SIZE(fsmc_4chips_modemux),
212};
213
214static const char *const fsmc_grps[] = { "fsmc_2chips_grp", "fsmc_4chips_grp"
215};
216static struct spear_function fsmc_function = {
217 .name = "fsmc",
218 .groups = fsmc_grps,
219 .ngroups = ARRAY_SIZE(fsmc_grps),
220};
221
222/* clcd_lcdmode_pins */
223static const unsigned clcd_lcdmode_pins[] = { 49, 50 };
224static struct spear_muxreg clcd_lcdmode_muxreg[] = {
225 {
226 .reg = PMX_CONFIG_REG,
227 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
228 .val = 0,
229 },
230};
231
232static struct spear_modemux clcd_lcdmode_modemux[] = {
233 {
234 .modes = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
235 CAMU_LCD_MODE | CAML_LCD_MODE,
236 .muxregs = clcd_lcdmode_muxreg,
237 .nmuxregs = ARRAY_SIZE(clcd_lcdmode_muxreg),
238 },
239};
240
241static struct spear_pingroup clcd_lcdmode_pingroup = {
242 .name = "clcd_lcdmode_grp",
243 .pins = clcd_lcdmode_pins,
244 .npins = ARRAY_SIZE(clcd_lcdmode_pins),
245 .modemuxs = clcd_lcdmode_modemux,
246 .nmodemuxs = ARRAY_SIZE(clcd_lcdmode_modemux),
247};
248
249/* clcd_pfmode_pins */
250static const unsigned clcd_pfmode_pins[] = { 47, 48, 49, 50 };
251static struct spear_muxreg clcd_pfmode_muxreg[] = {
252 {
253 .reg = PMX_CONFIG_REG,
254 .mask = PMX_TIMER_2_3_MASK,
255 .val = 0,
256 },
257};
258
259static struct spear_modemux clcd_pfmode_modemux[] = {
260 {
261 .modes = PHOTO_FRAME_MODE,
262 .muxregs = clcd_pfmode_muxreg,
263 .nmuxregs = ARRAY_SIZE(clcd_pfmode_muxreg),
264 },
265};
266
267static struct spear_pingroup clcd_pfmode_pingroup = {
268 .name = "clcd_pfmode_grp",
269 .pins = clcd_pfmode_pins,
270 .npins = ARRAY_SIZE(clcd_pfmode_pins),
271 .modemuxs = clcd_pfmode_modemux,
272 .nmodemuxs = ARRAY_SIZE(clcd_pfmode_modemux),
273};
274
275static const char *const clcd_grps[] = { "clcd_lcdmode_grp", "clcd_pfmode_grp"
276};
277static struct spear_function clcd_function = {
278 .name = "clcd",
279 .groups = clcd_grps,
280 .ngroups = ARRAY_SIZE(clcd_grps),
281};
282
283/* tdm_pins */
284static const unsigned tdm_pins[] = { 34, 35, 36, 37, 38 };
285static struct spear_muxreg tdm_muxreg[] = {
286 {
287 .reg = PMX_CONFIG_REG,
288 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
289 .val = 0,
290 },
291};
292
293static struct spear_modemux tdm_modemux[] = {
294 {
295 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
296 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
297 | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
298 | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
299 | CAMU_WLCD_MODE | CAML_LCD_MODE,
300 .muxregs = tdm_muxreg,
301 .nmuxregs = ARRAY_SIZE(tdm_muxreg),
302 },
303};
304
305static struct spear_pingroup tdm_pingroup = {
306 .name = "tdm_grp",
307 .pins = tdm_pins,
308 .npins = ARRAY_SIZE(tdm_pins),
309 .modemuxs = tdm_modemux,
310 .nmodemuxs = ARRAY_SIZE(tdm_modemux),
311};
312
313static const char *const tdm_grps[] = { "tdm_grp" };
314static struct spear_function tdm_function = {
315 .name = "tdm",
316 .groups = tdm_grps,
317 .ngroups = ARRAY_SIZE(tdm_grps),
318};
319
320/* i2c_clk_pins */
321static const unsigned i2c_clk_pins[] = { 45, 46, 47, 48 };
322static struct spear_muxreg i2c_clk_muxreg[] = {
323 {
324 .reg = PMX_CONFIG_REG,
325 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
326 .val = 0,
327 },
328};
329
330static struct spear_modemux i2c_clk_modemux[] = {
331 {
332 .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
333 LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
334 ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | CAML_LCDW_MODE
335 | CAML_LCD_MODE,
336 .muxregs = i2c_clk_muxreg,
337 .nmuxregs = ARRAY_SIZE(i2c_clk_muxreg),
338 },
339};
340
341static struct spear_pingroup i2c_clk_pingroup = {
342 .name = "i2c_clk_grp_grp",
343 .pins = i2c_clk_pins,
344 .npins = ARRAY_SIZE(i2c_clk_pins),
345 .modemuxs = i2c_clk_modemux,
346 .nmodemuxs = ARRAY_SIZE(i2c_clk_modemux),
347};
348
349static const char *const i2c_grps[] = { "i2c_clk_grp" };
350static struct spear_function i2c_function = {
351 .name = "i2c1",
352 .groups = i2c_grps,
353 .ngroups = ARRAY_SIZE(i2c_grps),
354};
355
356/* caml_pins */
357static const unsigned caml_pins[] = { 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 };
358static struct spear_muxreg caml_muxreg[] = {
359 {
360 .reg = PMX_CONFIG_REG,
361 .mask = PMX_MII_MASK,
362 .val = 0,
363 },
364};
365
366static struct spear_modemux caml_modemux[] = {
367 {
368 .modes = CAML_LCDW_MODE | CAML_LCD_MODE,
369 .muxregs = caml_muxreg,
370 .nmuxregs = ARRAY_SIZE(caml_muxreg),
371 },
372};
373
374static struct spear_pingroup caml_pingroup = {
375 .name = "caml_grp",
376 .pins = caml_pins,
377 .npins = ARRAY_SIZE(caml_pins),
378 .modemuxs = caml_modemux,
379 .nmodemuxs = ARRAY_SIZE(caml_modemux),
380};
381
382/* camu_pins */
383static const unsigned camu_pins[] = { 16, 17, 18, 19, 20, 21, 45, 46, 47, 48 };
384static struct spear_muxreg camu_muxreg[] = {
385 {
386 .reg = PMX_CONFIG_REG,
387 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | PMX_MII_MASK,
388 .val = 0,
389 },
390};
391
392static struct spear_modemux camu_modemux[] = {
393 {
394 .modes = CAMU_LCD_MODE | CAMU_WLCD_MODE,
395 .muxregs = camu_muxreg,
396 .nmuxregs = ARRAY_SIZE(camu_muxreg),
397 },
398};
399
400static struct spear_pingroup camu_pingroup = {
401 .name = "camu_grp",
402 .pins = camu_pins,
403 .npins = ARRAY_SIZE(camu_pins),
404 .modemuxs = camu_modemux,
405 .nmodemuxs = ARRAY_SIZE(camu_modemux),
406};
407
408static const char *const cam_grps[] = { "caml_grp", "camu_grp" };
409static struct spear_function cam_function = {
410 .name = "cam",
411 .groups = cam_grps,
412 .ngroups = ARRAY_SIZE(cam_grps),
413};
414
415/* dac_pins */
416static const unsigned dac_pins[] = { 43, 44 };
417static struct spear_muxreg dac_muxreg[] = {
418 {
419 .reg = PMX_CONFIG_REG,
420 .mask = PMX_TIMER_0_1_MASK,
421 .val = 0,
422 },
423};
424
425static struct spear_modemux dac_modemux[] = {
426 {
427 .modes = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
428 | CAMU_WLCD_MODE | CAML_LCD_MODE,
429 .muxregs = dac_muxreg,
430 .nmuxregs = ARRAY_SIZE(dac_muxreg),
431 },
432};
433
434static struct spear_pingroup dac_pingroup = {
435 .name = "dac_grp",
436 .pins = dac_pins,
437 .npins = ARRAY_SIZE(dac_pins),
438 .modemuxs = dac_modemux,
439 .nmodemuxs = ARRAY_SIZE(dac_modemux),
440};
441
442static const char *const dac_grps[] = { "dac_grp" };
443static struct spear_function dac_function = {
444 .name = "dac",
445 .groups = dac_grps,
446 .ngroups = ARRAY_SIZE(dac_grps),
447};
448
449/* i2s_pins */
450static const unsigned i2s_pins[] = { 39, 40, 41, 42 };
451static struct spear_muxreg i2s_muxreg[] = {
452 {
453 .reg = PMX_CONFIG_REG,
454 .mask = PMX_UART0_MODEM_MASK,
455 .val = 0,
456 },
457};
458
459static struct spear_modemux i2s_modemux[] = {
460 {
461 .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
462 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
463 ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
464 | CAMU_WLCD_MODE | CAML_LCD_MODE,
465 .muxregs = i2s_muxreg,
466 .nmuxregs = ARRAY_SIZE(i2s_muxreg),
467 },
468};
469
470static struct spear_pingroup i2s_pingroup = {
471 .name = "i2s_grp",
472 .pins = i2s_pins,
473 .npins = ARRAY_SIZE(i2s_pins),
474 .modemuxs = i2s_modemux,
475 .nmodemuxs = ARRAY_SIZE(i2s_modemux),
476};
477
478static const char *const i2s_grps[] = { "i2s_grp" };
479static struct spear_function i2s_function = {
480 .name = "i2s",
481 .groups = i2s_grps,
482 .ngroups = ARRAY_SIZE(i2s_grps),
483};
484
485/* sdhci_4bit_pins */
486static const unsigned sdhci_4bit_pins[] = { 28, 29, 30, 31, 32, 33 };
487static struct spear_muxreg sdhci_4bit_muxreg[] = {
488 {
489 .reg = PMX_CONFIG_REG,
490 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
491 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
492 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
493 .val = 0,
494 },
495};
496
497static struct spear_modemux sdhci_4bit_modemux[] = {
498 {
499 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
500 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
501 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
502 CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE,
503 .muxregs = sdhci_4bit_muxreg,
504 .nmuxregs = ARRAY_SIZE(sdhci_4bit_muxreg),
505 },
506};
507
508static struct spear_pingroup sdhci_4bit_pingroup = {
509 .name = "sdhci_4bit_grp",
510 .pins = sdhci_4bit_pins,
511 .npins = ARRAY_SIZE(sdhci_4bit_pins),
512 .modemuxs = sdhci_4bit_modemux,
513 .nmodemuxs = ARRAY_SIZE(sdhci_4bit_modemux),
514};
515
516/* sdhci_8bit_pins */
517static const unsigned sdhci_8bit_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
518 33 };
519static struct spear_muxreg sdhci_8bit_muxreg[] = {
520 {
521 .reg = PMX_CONFIG_REG,
522 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
523 PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
524 PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
525 .val = 0,
526 },
527};
528
529static struct spear_modemux sdhci_8bit_modemux[] = {
530 {
531 .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
532 HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
533 HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
534 CAMU_WLCD_MODE | CAML_LCD_MODE,
535 .muxregs = sdhci_8bit_muxreg,
536 .nmuxregs = ARRAY_SIZE(sdhci_8bit_muxreg),
537 },
538};
539
540static struct spear_pingroup sdhci_8bit_pingroup = {
541 .name = "sdhci_8bit_grp",
542 .pins = sdhci_8bit_pins,
543 .npins = ARRAY_SIZE(sdhci_8bit_pins),
544 .modemuxs = sdhci_8bit_modemux,
545 .nmodemuxs = ARRAY_SIZE(sdhci_8bit_modemux),
546};
547
548static const char *const sdhci_grps[] = { "sdhci_4bit_grp", "sdhci_8bit_grp" };
549static struct spear_function sdhci_function = {
550 .name = "sdhci",
551 .groups = sdhci_grps,
552 .ngroups = ARRAY_SIZE(sdhci_grps),
553};
554
555/* gpio1_0_to_3_pins */
556static const unsigned gpio1_0_to_3_pins[] = { 39, 40, 41, 42 };
557static struct spear_muxreg gpio1_0_to_3_muxreg[] = {
558 {
559 .reg = PMX_CONFIG_REG,
560 .mask = PMX_UART0_MODEM_MASK,
561 .val = 0,
562 },
563};
564
565static struct spear_modemux gpio1_0_to_3_modemux[] = {
566 {
567 .modes = PHOTO_FRAME_MODE,
568 .muxregs = gpio1_0_to_3_muxreg,
569 .nmuxregs = ARRAY_SIZE(gpio1_0_to_3_muxreg),
570 },
571};
572
573static struct spear_pingroup gpio1_0_to_3_pingroup = {
574 .name = "gpio1_0_to_3_grp",
575 .pins = gpio1_0_to_3_pins,
576 .npins = ARRAY_SIZE(gpio1_0_to_3_pins),
577 .modemuxs = gpio1_0_to_3_modemux,
578 .nmodemuxs = ARRAY_SIZE(gpio1_0_to_3_modemux),
579};
580
581/* gpio1_4_to_7_pins */
582static const unsigned gpio1_4_to_7_pins[] = { 43, 44, 45, 46 };
583
584static struct spear_muxreg gpio1_4_to_7_muxreg[] = {
585 {
586 .reg = PMX_CONFIG_REG,
587 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
588 .val = 0,
589 },
590};
591
592static struct spear_modemux gpio1_4_to_7_modemux[] = {
593 {
594 .modes = PHOTO_FRAME_MODE,
595 .muxregs = gpio1_4_to_7_muxreg,
596 .nmuxregs = ARRAY_SIZE(gpio1_4_to_7_muxreg),
597 },
598};
599
600static struct spear_pingroup gpio1_4_to_7_pingroup = {
601 .name = "gpio1_4_to_7_grp",
602 .pins = gpio1_4_to_7_pins,
603 .npins = ARRAY_SIZE(gpio1_4_to_7_pins),
604 .modemuxs = gpio1_4_to_7_modemux,
605 .nmodemuxs = ARRAY_SIZE(gpio1_4_to_7_modemux),
606};
607
608static const char *const gpio1_grps[] = { "gpio1_0_to_3_grp", "gpio1_4_to_7_grp"
609};
610static struct spear_function gpio1_function = {
611 .name = "gpio1",
612 .groups = gpio1_grps,
613 .ngroups = ARRAY_SIZE(gpio1_grps),
614};
615
616/* pingroups */
617static struct spear_pingroup *spear300_pingroups[] = {
618 SPEAR3XX_COMMON_PINGROUPS,
619 &fsmc_2chips_pingroup,
620 &fsmc_4chips_pingroup,
621 &clcd_lcdmode_pingroup,
622 &clcd_pfmode_pingroup,
623 &tdm_pingroup,
624 &i2c_clk_pingroup,
625 &caml_pingroup,
626 &camu_pingroup,
627 &dac_pingroup,
628 &i2s_pingroup,
629 &sdhci_4bit_pingroup,
630 &sdhci_8bit_pingroup,
631 &gpio1_0_to_3_pingroup,
632 &gpio1_4_to_7_pingroup,
633};
634
635/* functions */
636static struct spear_function *spear300_functions[] = {
637 SPEAR3XX_COMMON_FUNCTIONS,
638 &fsmc_function,
639 &clcd_function,
640 &tdm_function,
641 &i2c_function,
642 &cam_function,
643 &dac_function,
644 &i2s_function,
645 &sdhci_function,
646 &gpio1_function,
647};
648
649static struct of_device_id spear300_pinctrl_of_match[] __devinitdata = {
650 {
651 .compatible = "st,spear300-pinmux",
652 },
653 {},
654};
655
656static int __devinit spear300_pinctrl_probe(struct platform_device *pdev)
657{
658 int ret;
659
660 spear3xx_machdata.groups = spear300_pingroups;
661 spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups);
662 spear3xx_machdata.functions = spear300_functions;
663 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear300_functions);
664
665 spear3xx_machdata.modes_supported = true;
666 spear3xx_machdata.pmx_modes = spear300_pmx_modes;
667 spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear300_pmx_modes);
668
669 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
670
671 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
672 if (ret)
673 return ret;
674
675 return 0;
676}
677
678static int __devexit spear300_pinctrl_remove(struct platform_device *pdev)
679{
680 return spear_pinctrl_remove(pdev);
681}
682
683static struct platform_driver spear300_pinctrl_driver = {
684 .driver = {
685 .name = DRIVER_NAME,
686 .owner = THIS_MODULE,
687 .of_match_table = spear300_pinctrl_of_match,
688 },
689 .probe = spear300_pinctrl_probe,
690 .remove = __devexit_p(spear300_pinctrl_remove),
691};
692
693static int __init spear300_pinctrl_init(void)
694{
695 return platform_driver_register(&spear300_pinctrl_driver);
696}
697arch_initcall(spear300_pinctrl_init);
698
699static void __exit spear300_pinctrl_exit(void)
700{
701 platform_driver_unregister(&spear300_pinctrl_driver);
702}
703module_exit(spear300_pinctrl_exit);
704
705MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
706MODULE_DESCRIPTION("ST Microelectronics SPEAr300 pinctrl driver");
707MODULE_LICENSE("GPL v2");
708MODULE_DEVICE_TABLE(of, spear300_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear310.c b/drivers/pinctrl/spear/pinctrl-spear310.c
new file mode 100644
index 00000000000..1a970760512
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear310.c
@@ -0,0 +1,431 @@
1/*
2 * Driver for the ST Microelectronics SPEAr310 pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include "pinctrl-spear3xx.h"
18
19#define DRIVER_NAME "spear310-pinmux"
20
21/* addresses */
22#define PMX_CONFIG_REG 0x08
23
24/* emi_cs_0_to_5_pins */
25static const unsigned emi_cs_0_to_5_pins[] = { 45, 46, 47, 48, 49, 50 };
26static struct spear_muxreg emi_cs_0_to_5_muxreg[] = {
27 {
28 .reg = PMX_CONFIG_REG,
29 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
30 .val = 0,
31 },
32};
33
34static struct spear_modemux emi_cs_0_to_5_modemux[] = {
35 {
36 .muxregs = emi_cs_0_to_5_muxreg,
37 .nmuxregs = ARRAY_SIZE(emi_cs_0_to_5_muxreg),
38 },
39};
40
41static struct spear_pingroup emi_cs_0_to_5_pingroup = {
42 .name = "emi_cs_0_to_5_grp",
43 .pins = emi_cs_0_to_5_pins,
44 .npins = ARRAY_SIZE(emi_cs_0_to_5_pins),
45 .modemuxs = emi_cs_0_to_5_modemux,
46 .nmodemuxs = ARRAY_SIZE(emi_cs_0_to_5_modemux),
47};
48
49static const char *const emi_cs_0_to_5_grps[] = { "emi_cs_0_to_5_grp" };
50static struct spear_function emi_cs_0_to_5_function = {
51 .name = "emi",
52 .groups = emi_cs_0_to_5_grps,
53 .ngroups = ARRAY_SIZE(emi_cs_0_to_5_grps),
54};
55
56/* uart1_pins */
57static const unsigned uart1_pins[] = { 0, 1 };
58static struct spear_muxreg uart1_muxreg[] = {
59 {
60 .reg = PMX_CONFIG_REG,
61 .mask = PMX_FIRDA_MASK,
62 .val = 0,
63 },
64};
65
66static struct spear_modemux uart1_modemux[] = {
67 {
68 .muxregs = uart1_muxreg,
69 .nmuxregs = ARRAY_SIZE(uart1_muxreg),
70 },
71};
72
73static struct spear_pingroup uart1_pingroup = {
74 .name = "uart1_grp",
75 .pins = uart1_pins,
76 .npins = ARRAY_SIZE(uart1_pins),
77 .modemuxs = uart1_modemux,
78 .nmodemuxs = ARRAY_SIZE(uart1_modemux),
79};
80
81static const char *const uart1_grps[] = { "uart1_grp" };
82static struct spear_function uart1_function = {
83 .name = "uart1",
84 .groups = uart1_grps,
85 .ngroups = ARRAY_SIZE(uart1_grps),
86};
87
88/* uart2_pins */
89static const unsigned uart2_pins[] = { 43, 44 };
90static struct spear_muxreg uart2_muxreg[] = {
91 {
92 .reg = PMX_CONFIG_REG,
93 .mask = PMX_TIMER_0_1_MASK,
94 .val = 0,
95 },
96};
97
98static struct spear_modemux uart2_modemux[] = {
99 {
100 .muxregs = uart2_muxreg,
101 .nmuxregs = ARRAY_SIZE(uart2_muxreg),
102 },
103};
104
105static struct spear_pingroup uart2_pingroup = {
106 .name = "uart2_grp",
107 .pins = uart2_pins,
108 .npins = ARRAY_SIZE(uart2_pins),
109 .modemuxs = uart2_modemux,
110 .nmodemuxs = ARRAY_SIZE(uart2_modemux),
111};
112
113static const char *const uart2_grps[] = { "uart2_grp" };
114static struct spear_function uart2_function = {
115 .name = "uart2",
116 .groups = uart2_grps,
117 .ngroups = ARRAY_SIZE(uart2_grps),
118};
119
120/* uart3_pins */
121static const unsigned uart3_pins[] = { 37, 38 };
122static struct spear_muxreg uart3_muxreg[] = {
123 {
124 .reg = PMX_CONFIG_REG,
125 .mask = PMX_UART0_MODEM_MASK,
126 .val = 0,
127 },
128};
129
130static struct spear_modemux uart3_modemux[] = {
131 {
132 .muxregs = uart3_muxreg,
133 .nmuxregs = ARRAY_SIZE(uart3_muxreg),
134 },
135};
136
137static struct spear_pingroup uart3_pingroup = {
138 .name = "uart3_grp",
139 .pins = uart3_pins,
140 .npins = ARRAY_SIZE(uart3_pins),
141 .modemuxs = uart3_modemux,
142 .nmodemuxs = ARRAY_SIZE(uart3_modemux),
143};
144
145static const char *const uart3_grps[] = { "uart3_grp" };
146static struct spear_function uart3_function = {
147 .name = "uart3",
148 .groups = uart3_grps,
149 .ngroups = ARRAY_SIZE(uart3_grps),
150};
151
152/* uart4_pins */
153static const unsigned uart4_pins[] = { 39, 40 };
154static struct spear_muxreg uart4_muxreg[] = {
155 {
156 .reg = PMX_CONFIG_REG,
157 .mask = PMX_UART0_MODEM_MASK,
158 .val = 0,
159 },
160};
161
162static struct spear_modemux uart4_modemux[] = {
163 {
164 .muxregs = uart4_muxreg,
165 .nmuxregs = ARRAY_SIZE(uart4_muxreg),
166 },
167};
168
169static struct spear_pingroup uart4_pingroup = {
170 .name = "uart4_grp",
171 .pins = uart4_pins,
172 .npins = ARRAY_SIZE(uart4_pins),
173 .modemuxs = uart4_modemux,
174 .nmodemuxs = ARRAY_SIZE(uart4_modemux),
175};
176
177static const char *const uart4_grps[] = { "uart4_grp" };
178static struct spear_function uart4_function = {
179 .name = "uart4",
180 .groups = uart4_grps,
181 .ngroups = ARRAY_SIZE(uart4_grps),
182};
183
184/* uart5_pins */
185static const unsigned uart5_pins[] = { 41, 42 };
186static struct spear_muxreg uart5_muxreg[] = {
187 {
188 .reg = PMX_CONFIG_REG,
189 .mask = PMX_UART0_MODEM_MASK,
190 .val = 0,
191 },
192};
193
194static struct spear_modemux uart5_modemux[] = {
195 {
196 .muxregs = uart5_muxreg,
197 .nmuxregs = ARRAY_SIZE(uart5_muxreg),
198 },
199};
200
201static struct spear_pingroup uart5_pingroup = {
202 .name = "uart5_grp",
203 .pins = uart5_pins,
204 .npins = ARRAY_SIZE(uart5_pins),
205 .modemuxs = uart5_modemux,
206 .nmodemuxs = ARRAY_SIZE(uart5_modemux),
207};
208
209static const char *const uart5_grps[] = { "uart5_grp" };
210static struct spear_function uart5_function = {
211 .name = "uart5",
212 .groups = uart5_grps,
213 .ngroups = ARRAY_SIZE(uart5_grps),
214};
215
216/* fsmc_pins */
217static const unsigned fsmc_pins[] = { 34, 35, 36 };
218static struct spear_muxreg fsmc_muxreg[] = {
219 {
220 .reg = PMX_CONFIG_REG,
221 .mask = PMX_SSP_CS_MASK,
222 .val = 0,
223 },
224};
225
226static struct spear_modemux fsmc_modemux[] = {
227 {
228 .muxregs = fsmc_muxreg,
229 .nmuxregs = ARRAY_SIZE(fsmc_muxreg),
230 },
231};
232
233static struct spear_pingroup fsmc_pingroup = {
234 .name = "fsmc_grp",
235 .pins = fsmc_pins,
236 .npins = ARRAY_SIZE(fsmc_pins),
237 .modemuxs = fsmc_modemux,
238 .nmodemuxs = ARRAY_SIZE(fsmc_modemux),
239};
240
241static const char *const fsmc_grps[] = { "fsmc_grp" };
242static struct spear_function fsmc_function = {
243 .name = "fsmc",
244 .groups = fsmc_grps,
245 .ngroups = ARRAY_SIZE(fsmc_grps),
246};
247
248/* rs485_0_pins */
249static const unsigned rs485_0_pins[] = { 19, 20, 21, 22, 23 };
250static struct spear_muxreg rs485_0_muxreg[] = {
251 {
252 .reg = PMX_CONFIG_REG,
253 .mask = PMX_MII_MASK,
254 .val = 0,
255 },
256};
257
258static struct spear_modemux rs485_0_modemux[] = {
259 {
260 .muxregs = rs485_0_muxreg,
261 .nmuxregs = ARRAY_SIZE(rs485_0_muxreg),
262 },
263};
264
265static struct spear_pingroup rs485_0_pingroup = {
266 .name = "rs485_0_grp",
267 .pins = rs485_0_pins,
268 .npins = ARRAY_SIZE(rs485_0_pins),
269 .modemuxs = rs485_0_modemux,
270 .nmodemuxs = ARRAY_SIZE(rs485_0_modemux),
271};
272
273static const char *const rs485_0_grps[] = { "rs485_0" };
274static struct spear_function rs485_0_function = {
275 .name = "rs485_0",
276 .groups = rs485_0_grps,
277 .ngroups = ARRAY_SIZE(rs485_0_grps),
278};
279
280/* rs485_1_pins */
281static const unsigned rs485_1_pins[] = { 14, 15, 16, 17, 18 };
282static struct spear_muxreg rs485_1_muxreg[] = {
283 {
284 .reg = PMX_CONFIG_REG,
285 .mask = PMX_MII_MASK,
286 .val = 0,
287 },
288};
289
290static struct spear_modemux rs485_1_modemux[] = {
291 {
292 .muxregs = rs485_1_muxreg,
293 .nmuxregs = ARRAY_SIZE(rs485_1_muxreg),
294 },
295};
296
297static struct spear_pingroup rs485_1_pingroup = {
298 .name = "rs485_1_grp",
299 .pins = rs485_1_pins,
300 .npins = ARRAY_SIZE(rs485_1_pins),
301 .modemuxs = rs485_1_modemux,
302 .nmodemuxs = ARRAY_SIZE(rs485_1_modemux),
303};
304
305static const char *const rs485_1_grps[] = { "rs485_1" };
306static struct spear_function rs485_1_function = {
307 .name = "rs485_1",
308 .groups = rs485_1_grps,
309 .ngroups = ARRAY_SIZE(rs485_1_grps),
310};
311
312/* tdm_pins */
313static const unsigned tdm_pins[] = { 10, 11, 12, 13 };
314static struct spear_muxreg tdm_muxreg[] = {
315 {
316 .reg = PMX_CONFIG_REG,
317 .mask = PMX_MII_MASK,
318 .val = 0,
319 },
320};
321
322static struct spear_modemux tdm_modemux[] = {
323 {
324 .muxregs = tdm_muxreg,
325 .nmuxregs = ARRAY_SIZE(tdm_muxreg),
326 },
327};
328
329static struct spear_pingroup tdm_pingroup = {
330 .name = "tdm_grp",
331 .pins = tdm_pins,
332 .npins = ARRAY_SIZE(tdm_pins),
333 .modemuxs = tdm_modemux,
334 .nmodemuxs = ARRAY_SIZE(tdm_modemux),
335};
336
337static const char *const tdm_grps[] = { "tdm_grp" };
338static struct spear_function tdm_function = {
339 .name = "tdm",
340 .groups = tdm_grps,
341 .ngroups = ARRAY_SIZE(tdm_grps),
342};
343
344/* pingroups */
345static struct spear_pingroup *spear310_pingroups[] = {
346 SPEAR3XX_COMMON_PINGROUPS,
347 &emi_cs_0_to_5_pingroup,
348 &uart1_pingroup,
349 &uart2_pingroup,
350 &uart3_pingroup,
351 &uart4_pingroup,
352 &uart5_pingroup,
353 &fsmc_pingroup,
354 &rs485_0_pingroup,
355 &rs485_1_pingroup,
356 &tdm_pingroup,
357};
358
359/* functions */
360static struct spear_function *spear310_functions[] = {
361 SPEAR3XX_COMMON_FUNCTIONS,
362 &emi_cs_0_to_5_function,
363 &uart1_function,
364 &uart2_function,
365 &uart3_function,
366 &uart4_function,
367 &uart5_function,
368 &fsmc_function,
369 &rs485_0_function,
370 &rs485_1_function,
371 &tdm_function,
372};
373
374static struct of_device_id spear310_pinctrl_of_match[] __devinitdata = {
375 {
376 .compatible = "st,spear310-pinmux",
377 },
378 {},
379};
380
381static int __devinit spear310_pinctrl_probe(struct platform_device *pdev)
382{
383 int ret;
384
385 spear3xx_machdata.groups = spear310_pingroups;
386 spear3xx_machdata.ngroups = ARRAY_SIZE(spear310_pingroups);
387 spear3xx_machdata.functions = spear310_functions;
388 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear310_functions);
389
390 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
391
392 spear3xx_machdata.modes_supported = false;
393
394 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
395 if (ret)
396 return ret;
397
398 return 0;
399}
400
401static int __devexit spear310_pinctrl_remove(struct platform_device *pdev)
402{
403 return spear_pinctrl_remove(pdev);
404}
405
406static struct platform_driver spear310_pinctrl_driver = {
407 .driver = {
408 .name = DRIVER_NAME,
409 .owner = THIS_MODULE,
410 .of_match_table = spear310_pinctrl_of_match,
411 },
412 .probe = spear310_pinctrl_probe,
413 .remove = __devexit_p(spear310_pinctrl_remove),
414};
415
416static int __init spear310_pinctrl_init(void)
417{
418 return platform_driver_register(&spear310_pinctrl_driver);
419}
420arch_initcall(spear310_pinctrl_init);
421
422static void __exit spear310_pinctrl_exit(void)
423{
424 platform_driver_unregister(&spear310_pinctrl_driver);
425}
426module_exit(spear310_pinctrl_exit);
427
428MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
429MODULE_DESCRIPTION("ST Microelectronics SPEAr310 pinctrl driver");
430MODULE_LICENSE("GPL v2");
431MODULE_DEVICE_TABLE(of, SPEAr310_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear320.c b/drivers/pinctrl/spear/pinctrl-spear320.c
new file mode 100644
index 00000000000..de726e6c283
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear320.c
@@ -0,0 +1,3468 @@
1/*
2 * Driver for the ST Microelectronics SPEAr320 pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include "pinctrl-spear3xx.h"
18
19#define DRIVER_NAME "spear320-pinmux"
20
21/* addresses */
22#define PMX_CONFIG_REG 0x0C
23#define MODE_CONFIG_REG 0x10
24#define MODE_EXT_CONFIG_REG 0x18
25
26/* modes */
27#define AUTO_NET_SMII_MODE (1 << 0)
28#define AUTO_NET_MII_MODE (1 << 1)
29#define AUTO_EXP_MODE (1 << 2)
30#define SMALL_PRINTERS_MODE (1 << 3)
31#define EXTENDED_MODE (1 << 4)
32
33static struct spear_pmx_mode pmx_mode_auto_net_smii = {
34 .name = "Automation Networking SMII mode",
35 .mode = AUTO_NET_SMII_MODE,
36 .reg = MODE_CONFIG_REG,
37 .mask = 0x00000007,
38 .val = 0x0,
39};
40
41static struct spear_pmx_mode pmx_mode_auto_net_mii = {
42 .name = "Automation Networking MII mode",
43 .mode = AUTO_NET_MII_MODE,
44 .reg = MODE_CONFIG_REG,
45 .mask = 0x00000007,
46 .val = 0x1,
47};
48
49static struct spear_pmx_mode pmx_mode_auto_exp = {
50 .name = "Automation Expanded mode",
51 .mode = AUTO_EXP_MODE,
52 .reg = MODE_CONFIG_REG,
53 .mask = 0x00000007,
54 .val = 0x2,
55};
56
57static struct spear_pmx_mode pmx_mode_small_printers = {
58 .name = "Small Printers mode",
59 .mode = SMALL_PRINTERS_MODE,
60 .reg = MODE_CONFIG_REG,
61 .mask = 0x00000007,
62 .val = 0x3,
63};
64
65static struct spear_pmx_mode pmx_mode_extended = {
66 .name = "extended mode",
67 .mode = EXTENDED_MODE,
68 .reg = MODE_EXT_CONFIG_REG,
69 .mask = 0x00000001,
70 .val = 0x1,
71};
72
73static struct spear_pmx_mode *spear320_pmx_modes[] = {
74 &pmx_mode_auto_net_smii,
75 &pmx_mode_auto_net_mii,
76 &pmx_mode_auto_exp,
77 &pmx_mode_small_printers,
78 &pmx_mode_extended,
79};
80
81/* Extended mode registers and their offsets */
82#define EXT_CTRL_REG 0x0018
83 #define MII_MDIO_MASK (1 << 4)
84 #define MII_MDIO_10_11_VAL 0
85 #define MII_MDIO_81_VAL (1 << 4)
86 #define EMI_FSMC_DYNAMIC_MUX_MASK (1 << 5)
87 #define MAC_MODE_MII 0
88 #define MAC_MODE_RMII 1
89 #define MAC_MODE_SMII 2
90 #define MAC_MODE_SS_SMII 3
91 #define MAC_MODE_MASK 0x3
92 #define MAC1_MODE_SHIFT 16
93 #define MAC2_MODE_SHIFT 18
94
95#define IP_SEL_PAD_0_9_REG 0x00A4
96 #define PMX_PL_0_1_MASK (0x3F << 0)
97 #define PMX_UART2_PL_0_1_VAL 0x0
98 #define PMX_I2C2_PL_0_1_VAL (0x4 | (0x4 << 3))
99
100 #define PMX_PL_2_3_MASK (0x3F << 6)
101 #define PMX_I2C2_PL_2_3_VAL 0x0
102 #define PMX_UART6_PL_2_3_VAL ((0x1 << 6) | (0x1 << 9))
103 #define PMX_UART1_ENH_PL_2_3_VAL ((0x4 << 6) | (0x4 << 9))
104
105 #define PMX_PL_4_5_MASK (0x3F << 12)
106 #define PMX_UART5_PL_4_5_VAL ((0x1 << 12) | (0x1 << 15))
107 #define PMX_UART1_ENH_PL_4_5_VAL ((0x4 << 12) | (0x4 << 15))
108 #define PMX_PL_5_MASK (0x7 << 15)
109 #define PMX_TOUCH_Y_PL_5_VAL 0x0
110
111 #define PMX_PL_6_7_MASK (0x3F << 18)
112 #define PMX_PL_6_MASK (0x7 << 18)
113 #define PMX_PL_7_MASK (0x7 << 21)
114 #define PMX_UART4_PL_6_7_VAL ((0x1 << 18) | (0x1 << 21))
115 #define PMX_PWM_3_PL_6_VAL (0x2 << 18)
116 #define PMX_PWM_2_PL_7_VAL (0x2 << 21)
117 #define PMX_UART1_ENH_PL_6_7_VAL ((0x4 << 18) | (0x4 << 21))
118
119 #define PMX_PL_8_9_MASK (0x3F << 24)
120 #define PMX_UART3_PL_8_9_VAL ((0x1 << 24) | (0x1 << 27))
121 #define PMX_PWM_0_1_PL_8_9_VAL ((0x2 << 24) | (0x2 << 27))
122 #define PMX_I2C1_PL_8_9_VAL ((0x4 << 24) | (0x4 << 27))
123
124#define IP_SEL_PAD_10_19_REG 0x00A8
125 #define PMX_PL_10_11_MASK (0x3F << 0)
126 #define PMX_SMII_PL_10_11_VAL 0
127 #define PMX_RMII_PL_10_11_VAL ((0x4 << 0) | (0x4 << 3))
128
129 #define PMX_PL_12_MASK (0x7 << 6)
130 #define PMX_PWM3_PL_12_VAL 0
131 #define PMX_SDHCI_CD_PL_12_VAL (0x4 << 6)
132
133 #define PMX_PL_13_14_MASK (0x3F << 9)
134 #define PMX_PL_13_MASK (0x7 << 9)
135 #define PMX_PL_14_MASK (0x7 << 12)
136 #define PMX_SSP2_PL_13_14_15_16_VAL 0
137 #define PMX_UART4_PL_13_14_VAL ((0x1 << 9) | (0x1 << 12))
138 #define PMX_RMII_PL_13_14_VAL ((0x4 << 9) | (0x4 << 12))
139 #define PMX_PWM2_PL_13_VAL (0x2 << 9)
140 #define PMX_PWM1_PL_14_VAL (0x2 << 12)
141
142 #define PMX_PL_15_MASK (0x7 << 15)
143 #define PMX_PWM0_PL_15_VAL (0x2 << 15)
144 #define PMX_PL_15_16_MASK (0x3F << 15)
145 #define PMX_UART3_PL_15_16_VAL ((0x1 << 15) | (0x1 << 18))
146 #define PMX_RMII_PL_15_16_VAL ((0x4 << 15) | (0x4 << 18))
147
148 #define PMX_PL_17_18_MASK (0x3F << 21)
149 #define PMX_SSP1_PL_17_18_19_20_VAL 0
150 #define PMX_RMII_PL_17_18_VAL ((0x4 << 21) | (0x4 << 24))
151
152 #define PMX_PL_19_MASK (0x7 << 27)
153 #define PMX_I2C2_PL_19_VAL (0x1 << 27)
154 #define PMX_RMII_PL_19_VAL (0x4 << 27)
155
156#define IP_SEL_PAD_20_29_REG 0x00AC
157 #define PMX_PL_20_MASK (0x7 << 0)
158 #define PMX_I2C2_PL_20_VAL (0x1 << 0)
159 #define PMX_RMII_PL_20_VAL (0x4 << 0)
160
161 #define PMX_PL_21_TO_27_MASK (0x1FFFFF << 3)
162 #define PMX_SMII_PL_21_TO_27_VAL 0
163 #define PMX_RMII_PL_21_TO_27_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15) | (0x4 << 18) | (0x4 << 21))
164
165 #define PMX_PL_28_29_MASK (0x3F << 24)
166 #define PMX_PL_28_MASK (0x7 << 24)
167 #define PMX_PL_29_MASK (0x7 << 27)
168 #define PMX_UART1_PL_28_29_VAL 0
169 #define PMX_PWM_3_PL_28_VAL (0x4 << 24)
170 #define PMX_PWM_2_PL_29_VAL (0x4 << 27)
171
172#define IP_SEL_PAD_30_39_REG 0x00B0
173 #define PMX_PL_30_31_MASK (0x3F << 0)
174 #define PMX_CAN1_PL_30_31_VAL (0)
175 #define PMX_PL_30_MASK (0x7 << 0)
176 #define PMX_PL_31_MASK (0x7 << 3)
177 #define PMX_PWM1_EXT_PL_30_VAL (0x4 << 0)
178 #define PMX_PWM0_EXT_PL_31_VAL (0x4 << 3)
179 #define PMX_UART1_ENH_PL_31_VAL (0x3 << 3)
180
181 #define PMX_PL_32_33_MASK (0x3F << 6)
182 #define PMX_CAN0_PL_32_33_VAL 0
183 #define PMX_UART1_ENH_PL_32_33_VAL ((0x3 << 6) | (0x3 << 9))
184 #define PMX_SSP2_PL_32_33_VAL ((0x4 << 6) | (0x4 << 9))
185
186 #define PMX_PL_34_MASK (0x7 << 12)
187 #define PMX_PWM2_PL_34_VAL 0
188 #define PMX_UART1_ENH_PL_34_VAL (0x2 << 12)
189 #define PMX_SSP2_PL_34_VAL (0x4 << 12)
190
191 #define PMX_PL_35_MASK (0x7 << 15)
192 #define PMX_I2S_REF_CLK_PL_35_VAL 0
193 #define PMX_UART1_ENH_PL_35_VAL (0x2 << 15)
194 #define PMX_SSP2_PL_35_VAL (0x4 << 15)
195
196 #define PMX_PL_36_MASK (0x7 << 18)
197 #define PMX_TOUCH_X_PL_36_VAL 0
198 #define PMX_UART1_ENH_PL_36_VAL (0x2 << 18)
199 #define PMX_SSP1_PL_36_VAL (0x4 << 18)
200
201 #define PMX_PL_37_38_MASK (0x3F << 21)
202 #define PMX_PWM0_1_PL_37_38_VAL 0
203 #define PMX_UART5_PL_37_38_VAL ((0x2 << 21) | (0x2 << 24))
204 #define PMX_SSP1_PL_37_38_VAL ((0x4 << 21) | (0x4 << 24))
205
206 #define PMX_PL_39_MASK (0x7 << 27)
207 #define PMX_I2S_PL_39_VAL 0
208 #define PMX_UART4_PL_39_VAL (0x2 << 27)
209 #define PMX_SSP1_PL_39_VAL (0x4 << 27)
210
211#define IP_SEL_PAD_40_49_REG 0x00B4
212 #define PMX_PL_40_MASK (0x7 << 0)
213 #define PMX_I2S_PL_40_VAL 0
214 #define PMX_UART4_PL_40_VAL (0x2 << 0)
215 #define PMX_PWM3_PL_40_VAL (0x4 << 0)
216
217 #define PMX_PL_41_42_MASK (0x3F << 3)
218 #define PMX_PL_41_MASK (0x7 << 3)
219 #define PMX_PL_42_MASK (0x7 << 6)
220 #define PMX_I2S_PL_41_42_VAL 0
221 #define PMX_UART3_PL_41_42_VAL ((0x2 << 3) | (0x2 << 6))
222 #define PMX_PWM2_PL_41_VAL (0x4 << 3)
223 #define PMX_PWM1_PL_42_VAL (0x4 << 6)
224
225 #define PMX_PL_43_MASK (0x7 << 9)
226 #define PMX_SDHCI_PL_43_VAL 0
227 #define PMX_UART1_ENH_PL_43_VAL (0x2 << 9)
228 #define PMX_PWM0_PL_43_VAL (0x4 << 9)
229
230 #define PMX_PL_44_45_MASK (0x3F << 12)
231 #define PMX_SDHCI_PL_44_45_VAL 0
232 #define PMX_UART1_ENH_PL_44_45_VAL ((0x2 << 12) | (0x2 << 15))
233 #define PMX_SSP2_PL_44_45_VAL ((0x4 << 12) | (0x4 << 15))
234
235 #define PMX_PL_46_47_MASK (0x3F << 18)
236 #define PMX_SDHCI_PL_46_47_VAL 0
237 #define PMX_FSMC_EMI_PL_46_47_VAL ((0x2 << 18) | (0x2 << 21))
238 #define PMX_SSP2_PL_46_47_VAL ((0x4 << 18) | (0x4 << 21))
239
240 #define PMX_PL_48_49_MASK (0x3F << 24)
241 #define PMX_SDHCI_PL_48_49_VAL 0
242 #define PMX_FSMC_EMI_PL_48_49_VAL ((0x2 << 24) | (0x2 << 27))
243 #define PMX_SSP1_PL_48_49_VAL ((0x4 << 24) | (0x4 << 27))
244
245#define IP_SEL_PAD_50_59_REG 0x00B8
246 #define PMX_PL_50_51_MASK (0x3F << 0)
247 #define PMX_EMI_PL_50_51_VAL ((0x2 << 0) | (0x2 << 3))
248 #define PMX_SSP1_PL_50_51_VAL ((0x4 << 0) | (0x4 << 3))
249 #define PMX_PL_50_MASK (0x7 << 0)
250 #define PMX_PL_51_MASK (0x7 << 3)
251 #define PMX_SDHCI_PL_50_VAL 0
252 #define PMX_SDHCI_CD_PL_51_VAL 0
253
254 #define PMX_PL_52_53_MASK (0x3F << 6)
255 #define PMX_FSMC_PL_52_53_VAL 0
256 #define PMX_EMI_PL_52_53_VAL ((0x2 << 6) | (0x2 << 9))
257 #define PMX_UART3_PL_52_53_VAL ((0x4 << 6) | (0x4 << 9))
258
259 #define PMX_PL_54_55_56_MASK (0x1FF << 12)
260 #define PMX_FSMC_EMI_PL_54_55_56_VAL ((0x2 << 12) | (0x2 << 15) | (0x2 << 18))
261
262 #define PMX_PL_57_MASK (0x7 << 21)
263 #define PMX_FSMC_PL_57_VAL 0
264 #define PMX_PWM3_PL_57_VAL (0x4 << 21)
265
266 #define PMX_PL_58_59_MASK (0x3F << 24)
267 #define PMX_PL_58_MASK (0x7 << 24)
268 #define PMX_PL_59_MASK (0x7 << 27)
269 #define PMX_FSMC_EMI_PL_58_59_VAL ((0x2 << 24) | (0x2 << 27))
270 #define PMX_PWM2_PL_58_VAL (0x4 << 24)
271 #define PMX_PWM1_PL_59_VAL (0x4 << 27)
272
273#define IP_SEL_PAD_60_69_REG 0x00BC
274 #define PMX_PL_60_MASK (0x7 << 0)
275 #define PMX_FSMC_PL_60_VAL 0
276 #define PMX_PWM0_PL_60_VAL (0x4 << 0)
277
278 #define PMX_PL_61_TO_64_MASK (0xFFF << 3)
279 #define PMX_FSMC_PL_61_TO_64_VAL ((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12))
280 #define PMX_SSP2_PL_61_TO_64_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12))
281
282 #define PMX_PL_65_TO_68_MASK (0xFFF << 15)
283 #define PMX_FSMC_PL_65_TO_68_VAL ((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24))
284 #define PMX_SSP1_PL_65_TO_68_VAL ((0x4 << 15) | (0x4 << 18) | (0x4 << 21) | (0x4 << 24))
285
286 #define PMX_PL_69_MASK (0x7 << 27)
287 #define PMX_CLCD_PL_69_VAL (0)
288 #define PMX_EMI_PL_69_VAL (0x2 << 27)
289 #define PMX_SPP_PL_69_VAL (0x3 << 27)
290 #define PMX_UART5_PL_69_VAL (0x4 << 27)
291
292#define IP_SEL_PAD_70_79_REG 0x00C0
293 #define PMX_PL_70_MASK (0x7 << 0)
294 #define PMX_CLCD_PL_70_VAL (0)
295 #define PMX_FSMC_EMI_PL_70_VAL (0x2 << 0)
296 #define PMX_SPP_PL_70_VAL (0x3 << 0)
297 #define PMX_UART5_PL_70_VAL (0x4 << 0)
298
299 #define PMX_PL_71_72_MASK (0x3F << 3)
300 #define PMX_CLCD_PL_71_72_VAL (0)
301 #define PMX_FSMC_EMI_PL_71_72_VAL ((0x2 << 3) | (0x2 << 6))
302 #define PMX_SPP_PL_71_72_VAL ((0x3 << 3) | (0x3 << 6))
303 #define PMX_UART4_PL_71_72_VAL ((0x4 << 3) | (0x4 << 6))
304
305 #define PMX_PL_73_MASK (0x7 << 9)
306 #define PMX_CLCD_PL_73_VAL (0)
307 #define PMX_FSMC_EMI_PL_73_VAL (0x2 << 9)
308 #define PMX_SPP_PL_73_VAL (0x3 << 9)
309 #define PMX_UART3_PL_73_VAL (0x4 << 9)
310
311 #define PMX_PL_74_MASK (0x7 << 12)
312 #define PMX_CLCD_PL_74_VAL (0)
313 #define PMX_EMI_PL_74_VAL (0x2 << 12)
314 #define PMX_SPP_PL_74_VAL (0x3 << 12)
315 #define PMX_UART3_PL_74_VAL (0x4 << 12)
316
317 #define PMX_PL_75_76_MASK (0x3F << 15)
318 #define PMX_CLCD_PL_75_76_VAL (0)
319 #define PMX_EMI_PL_75_76_VAL ((0x2 << 15) | (0x2 << 18))
320 #define PMX_SPP_PL_75_76_VAL ((0x3 << 15) | (0x3 << 18))
321 #define PMX_I2C2_PL_75_76_VAL ((0x4 << 15) | (0x4 << 18))
322
323 #define PMX_PL_77_78_79_MASK (0x1FF << 21)
324 #define PMX_CLCD_PL_77_78_79_VAL (0)
325 #define PMX_EMI_PL_77_78_79_VAL ((0x2 << 21) | (0x2 << 24) | (0x2 << 27))
326 #define PMX_SPP_PL_77_78_79_VAL ((0x3 << 21) | (0x3 << 24) | (0x3 << 27))
327 #define PMX_RS485_PL_77_78_79_VAL ((0x4 << 21) | (0x4 << 24) | (0x4 << 27))
328
329#define IP_SEL_PAD_80_89_REG 0x00C4
330 #define PMX_PL_80_TO_85_MASK (0x3FFFF << 0)
331 #define PMX_CLCD_PL_80_TO_85_VAL 0
332 #define PMX_MII2_PL_80_TO_85_VAL ((0x1 << 0) | (0x1 << 3) | (0x1 << 6) | (0x1 << 9) | (0x1 << 12) | (0x1 << 15))
333 #define PMX_EMI_PL_80_TO_85_VAL ((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15))
334 #define PMX_SPP_PL_80_TO_85_VAL ((0x3 << 0) | (0x3 << 3) | (0x3 << 6) | (0x3 << 9) | (0x3 << 12) | (0x3 << 15))
335 #define PMX_UART1_ENH_PL_80_TO_85_VAL ((0x4 << 0) | (0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15))
336
337 #define PMX_PL_86_87_MASK (0x3F << 18)
338 #define PMX_PL_86_MASK (0x7 << 18)
339 #define PMX_PL_87_MASK (0x7 << 21)
340 #define PMX_CLCD_PL_86_87_VAL 0
341 #define PMX_MII2_PL_86_87_VAL ((0x1 << 18) | (0x1 << 21))
342 #define PMX_EMI_PL_86_87_VAL ((0x2 << 18) | (0x2 << 21))
343 #define PMX_PWM3_PL_86_VAL (0x4 << 18)
344 #define PMX_PWM2_PL_87_VAL (0x4 << 21)
345
346 #define PMX_PL_88_89_MASK (0x3F << 24)
347 #define PMX_CLCD_PL_88_89_VAL 0
348 #define PMX_MII2_PL_88_89_VAL ((0x1 << 24) | (0x1 << 27))
349 #define PMX_EMI_PL_88_89_VAL ((0x2 << 24) | (0x2 << 27))
350 #define PMX_UART6_PL_88_89_VAL ((0x3 << 24) | (0x3 << 27))
351 #define PMX_PWM0_1_PL_88_89_VAL ((0x4 << 24) | (0x4 << 27))
352
353#define IP_SEL_PAD_90_99_REG 0x00C8
354 #define PMX_PL_90_91_MASK (0x3F << 0)
355 #define PMX_CLCD_PL_90_91_VAL 0
356 #define PMX_MII2_PL_90_91_VAL ((0x1 << 0) | (0x1 << 3))
357 #define PMX_EMI1_PL_90_91_VAL ((0x2 << 0) | (0x2 << 3))
358 #define PMX_UART5_PL_90_91_VAL ((0x3 << 0) | (0x3 << 3))
359 #define PMX_SSP2_PL_90_91_VAL ((0x4 << 0) | (0x4 << 3))
360
361 #define PMX_PL_92_93_MASK (0x3F << 6)
362 #define PMX_CLCD_PL_92_93_VAL 0
363 #define PMX_MII2_PL_92_93_VAL ((0x1 << 6) | (0x1 << 9))
364 #define PMX_EMI1_PL_92_93_VAL ((0x2 << 6) | (0x2 << 9))
365 #define PMX_UART4_PL_92_93_VAL ((0x3 << 6) | (0x3 << 9))
366 #define PMX_SSP2_PL_92_93_VAL ((0x4 << 6) | (0x4 << 9))
367
368 #define PMX_PL_94_95_MASK (0x3F << 12)
369 #define PMX_CLCD_PL_94_95_VAL 0
370 #define PMX_MII2_PL_94_95_VAL ((0x1 << 12) | (0x1 << 15))
371 #define PMX_EMI1_PL_94_95_VAL ((0x2 << 12) | (0x2 << 15))
372 #define PMX_UART3_PL_94_95_VAL ((0x3 << 12) | (0x3 << 15))
373 #define PMX_SSP1_PL_94_95_VAL ((0x4 << 12) | (0x4 << 15))
374
375 #define PMX_PL_96_97_MASK (0x3F << 18)
376 #define PMX_CLCD_PL_96_97_VAL 0
377 #define PMX_MII2_PL_96_97_VAL ((0x1 << 18) | (0x1 << 21))
378 #define PMX_EMI1_PL_96_97_VAL ((0x2 << 18) | (0x2 << 21))
379 #define PMX_I2C2_PL_96_97_VAL ((0x3 << 18) | (0x3 << 21))
380 #define PMX_SSP1_PL_96_97_VAL ((0x4 << 18) | (0x4 << 21))
381
382 #define PMX_PL_98_MASK (0x7 << 24)
383 #define PMX_CLCD_PL_98_VAL 0
384 #define PMX_I2C1_PL_98_VAL (0x2 << 24)
385 #define PMX_UART3_PL_98_VAL (0x4 << 24)
386
387 #define PMX_PL_99_MASK (0x7 << 27)
388 #define PMX_SDHCI_PL_99_VAL 0
389 #define PMX_I2C1_PL_99_VAL (0x2 << 27)
390 #define PMX_UART3_PL_99_VAL (0x4 << 27)
391
392#define IP_SEL_MIX_PAD_REG 0x00CC
393 #define PMX_PL_100_101_MASK (0x3F << 0)
394 #define PMX_SDHCI_PL_100_101_VAL 0
395 #define PMX_UART4_PL_100_101_VAL ((0x4 << 0) | (0x4 << 3))
396
397 #define PMX_SSP1_PORT_SEL_MASK (0x7 << 8)
398 #define PMX_SSP1_PORT_94_TO_97_VAL 0
399 #define PMX_SSP1_PORT_65_TO_68_VAL (0x1 << 8)
400 #define PMX_SSP1_PORT_48_TO_51_VAL (0x2 << 8)
401 #define PMX_SSP1_PORT_36_TO_39_VAL (0x3 << 8)
402 #define PMX_SSP1_PORT_17_TO_20_VAL (0x4 << 8)
403
404 #define PMX_SSP2_PORT_SEL_MASK (0x7 << 11)
405 #define PMX_SSP2_PORT_90_TO_93_VAL 0
406 #define PMX_SSP2_PORT_61_TO_64_VAL (0x1 << 11)
407 #define PMX_SSP2_PORT_44_TO_47_VAL (0x2 << 11)
408 #define PMX_SSP2_PORT_32_TO_35_VAL (0x3 << 11)
409 #define PMX_SSP2_PORT_13_TO_16_VAL (0x4 << 11)
410
411 #define PMX_UART1_ENH_PORT_SEL_MASK (0x3 << 14)
412 #define PMX_UART1_ENH_PORT_81_TO_85_VAL 0
413 #define PMX_UART1_ENH_PORT_44_45_34_36_VAL (0x1 << 14)
414 #define PMX_UART1_ENH_PORT_32_TO_34_36_VAL (0x2 << 14)
415 #define PMX_UART1_ENH_PORT_3_TO_5_7_VAL (0x3 << 14)
416
417 #define PMX_UART3_PORT_SEL_MASK (0x7 << 16)
418 #define PMX_UART3_PORT_94_VAL 0
419 #define PMX_UART3_PORT_73_VAL (0x1 << 16)
420 #define PMX_UART3_PORT_52_VAL (0x2 << 16)
421 #define PMX_UART3_PORT_41_VAL (0x3 << 16)
422 #define PMX_UART3_PORT_15_VAL (0x4 << 16)
423 #define PMX_UART3_PORT_8_VAL (0x5 << 16)
424 #define PMX_UART3_PORT_99_VAL (0x6 << 16)
425
426 #define PMX_UART4_PORT_SEL_MASK (0x7 << 19)
427 #define PMX_UART4_PORT_92_VAL 0
428 #define PMX_UART4_PORT_71_VAL (0x1 << 19)
429 #define PMX_UART4_PORT_39_VAL (0x2 << 19)
430 #define PMX_UART4_PORT_13_VAL (0x3 << 19)
431 #define PMX_UART4_PORT_6_VAL (0x4 << 19)
432 #define PMX_UART4_PORT_101_VAL (0x5 << 19)
433
434 #define PMX_UART5_PORT_SEL_MASK (0x3 << 22)
435 #define PMX_UART5_PORT_90_VAL 0
436 #define PMX_UART5_PORT_69_VAL (0x1 << 22)
437 #define PMX_UART5_PORT_37_VAL (0x2 << 22)
438 #define PMX_UART5_PORT_4_VAL (0x3 << 22)
439
440 #define PMX_UART6_PORT_SEL_MASK (0x1 << 24)
441 #define PMX_UART6_PORT_88_VAL 0
442 #define PMX_UART6_PORT_2_VAL (0x1 << 24)
443
444 #define PMX_I2C1_PORT_SEL_MASK (0x1 << 25)
445 #define PMX_I2C1_PORT_8_9_VAL 0
446 #define PMX_I2C1_PORT_98_99_VAL (0x1 << 25)
447
448 #define PMX_I2C2_PORT_SEL_MASK (0x3 << 26)
449 #define PMX_I2C2_PORT_96_97_VAL 0
450 #define PMX_I2C2_PORT_75_76_VAL (0x1 << 26)
451 #define PMX_I2C2_PORT_19_20_VAL (0x2 << 26)
452 #define PMX_I2C2_PORT_2_3_VAL (0x3 << 26)
453 #define PMX_I2C2_PORT_0_1_VAL (0x4 << 26)
454
455 #define PMX_SDHCI_CD_PORT_SEL_MASK (0x1 << 29)
456 #define PMX_SDHCI_CD_PORT_12_VAL 0
457 #define PMX_SDHCI_CD_PORT_51_VAL (0x1 << 29)
458
459/* Pad multiplexing for CLCD device */
460static const unsigned clcd_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78,
461 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96,
462 97 };
463static struct spear_muxreg clcd_muxreg[] = {
464 {
465 .reg = IP_SEL_PAD_60_69_REG,
466 .mask = PMX_PL_69_MASK,
467 .val = PMX_CLCD_PL_69_VAL,
468 }, {
469 .reg = IP_SEL_PAD_70_79_REG,
470 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
471 PMX_PL_74_MASK | PMX_PL_75_76_MASK |
472 PMX_PL_77_78_79_MASK,
473 .val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL |
474 PMX_CLCD_PL_73_VAL | PMX_CLCD_PL_74_VAL |
475 PMX_CLCD_PL_75_76_VAL | PMX_CLCD_PL_77_78_79_VAL,
476 }, {
477 .reg = IP_SEL_PAD_80_89_REG,
478 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
479 PMX_PL_88_89_MASK,
480 .val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL |
481 PMX_CLCD_PL_88_89_VAL,
482 }, {
483 .reg = IP_SEL_PAD_90_99_REG,
484 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
485 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK | PMX_PL_98_MASK,
486 .val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL |
487 PMX_CLCD_PL_94_95_VAL | PMX_CLCD_PL_96_97_VAL |
488 PMX_CLCD_PL_98_VAL,
489 },
490};
491
492static struct spear_modemux clcd_modemux[] = {
493 {
494 .modes = EXTENDED_MODE,
495 .muxregs = clcd_muxreg,
496 .nmuxregs = ARRAY_SIZE(clcd_muxreg),
497 },
498};
499
500static struct spear_pingroup clcd_pingroup = {
501 .name = "clcd_grp",
502 .pins = clcd_pins,
503 .npins = ARRAY_SIZE(clcd_pins),
504 .modemuxs = clcd_modemux,
505 .nmodemuxs = ARRAY_SIZE(clcd_modemux),
506};
507
508static const char *const clcd_grps[] = { "clcd_grp" };
509static struct spear_function clcd_function = {
510 .name = "clcd",
511 .groups = clcd_grps,
512 .ngroups = ARRAY_SIZE(clcd_grps),
513};
514
515/* Pad multiplexing for EMI (Parallel NOR flash) device */
516static const unsigned emi_pins[] = { 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56,
517 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
518 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92,
519 93, 94, 95, 96, 97 };
520static struct spear_muxreg emi_muxreg[] = {
521 {
522 .reg = PMX_CONFIG_REG,
523 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
524 .val = 0,
525 },
526};
527
528static struct spear_muxreg emi_ext_muxreg[] = {
529 {
530 .reg = IP_SEL_PAD_40_49_REG,
531 .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
532 .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
533 }, {
534 .reg = IP_SEL_PAD_50_59_REG,
535 .mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK |
536 PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK,
537 .val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL |
538 PMX_FSMC_EMI_PL_54_55_56_VAL |
539 PMX_FSMC_EMI_PL_58_59_VAL,
540 }, {
541 .reg = IP_SEL_PAD_60_69_REG,
542 .mask = PMX_PL_69_MASK,
543 .val = PMX_EMI_PL_69_VAL,
544 }, {
545 .reg = IP_SEL_PAD_70_79_REG,
546 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
547 PMX_PL_74_MASK | PMX_PL_75_76_MASK |
548 PMX_PL_77_78_79_MASK,
549 .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
550 PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL |
551 PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL,
552 }, {
553 .reg = IP_SEL_PAD_80_89_REG,
554 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
555 PMX_PL_88_89_MASK,
556 .val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL |
557 PMX_EMI_PL_88_89_VAL,
558 }, {
559 .reg = IP_SEL_PAD_90_99_REG,
560 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
561 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
562 .val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL |
563 PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL,
564 }, {
565 .reg = EXT_CTRL_REG,
566 .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
567 .val = EMI_FSMC_DYNAMIC_MUX_MASK,
568 },
569};
570
571static struct spear_modemux emi_modemux[] = {
572 {
573 .modes = AUTO_EXP_MODE | EXTENDED_MODE,
574 .muxregs = emi_muxreg,
575 .nmuxregs = ARRAY_SIZE(emi_muxreg),
576 }, {
577 .modes = EXTENDED_MODE,
578 .muxregs = emi_ext_muxreg,
579 .nmuxregs = ARRAY_SIZE(emi_ext_muxreg),
580 },
581};
582
583static struct spear_pingroup emi_pingroup = {
584 .name = "emi_grp",
585 .pins = emi_pins,
586 .npins = ARRAY_SIZE(emi_pins),
587 .modemuxs = emi_modemux,
588 .nmodemuxs = ARRAY_SIZE(emi_modemux),
589};
590
591static const char *const emi_grps[] = { "emi_grp" };
592static struct spear_function emi_function = {
593 .name = "emi",
594 .groups = emi_grps,
595 .ngroups = ARRAY_SIZE(emi_grps),
596};
597
598/* Pad multiplexing for FSMC (NAND flash) device */
599static const unsigned fsmc_8bit_pins[] = { 52, 53, 54, 55, 56, 57, 58, 59, 60,
600 61, 62, 63, 64, 65, 66, 67, 68 };
601static struct spear_muxreg fsmc_8bit_muxreg[] = {
602 {
603 .reg = IP_SEL_PAD_50_59_REG,
604 .mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK |
605 PMX_PL_57_MASK | PMX_PL_58_59_MASK,
606 .val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL |
607 PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL,
608 }, {
609 .reg = IP_SEL_PAD_60_69_REG,
610 .mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK |
611 PMX_PL_65_TO_68_MASK,
612 .val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL |
613 PMX_FSMC_PL_65_TO_68_VAL,
614 }, {
615 .reg = EXT_CTRL_REG,
616 .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
617 .val = EMI_FSMC_DYNAMIC_MUX_MASK,
618 },
619};
620
621static struct spear_modemux fsmc_8bit_modemux[] = {
622 {
623 .modes = EXTENDED_MODE,
624 .muxregs = fsmc_8bit_muxreg,
625 .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
626 },
627};
628
629static struct spear_pingroup fsmc_8bit_pingroup = {
630 .name = "fsmc_8bit_grp",
631 .pins = fsmc_8bit_pins,
632 .npins = ARRAY_SIZE(fsmc_8bit_pins),
633 .modemuxs = fsmc_8bit_modemux,
634 .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux),
635};
636
637static const unsigned fsmc_16bit_pins[] = { 46, 47, 48, 49, 52, 53, 54, 55, 56,
638 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73 };
639static struct spear_muxreg fsmc_16bit_autoexp_muxreg[] = {
640 {
641 .reg = PMX_CONFIG_REG,
642 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
643 .val = 0,
644 },
645};
646
647static struct spear_muxreg fsmc_16bit_muxreg[] = {
648 {
649 .reg = IP_SEL_PAD_40_49_REG,
650 .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
651 .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL,
652 }, {
653 .reg = IP_SEL_PAD_70_79_REG,
654 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK,
655 .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL |
656 PMX_FSMC_EMI_PL_73_VAL,
657 }
658};
659
660static struct spear_modemux fsmc_16bit_modemux[] = {
661 {
662 .modes = EXTENDED_MODE,
663 .muxregs = fsmc_8bit_muxreg,
664 .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg),
665 }, {
666 .modes = AUTO_EXP_MODE | EXTENDED_MODE,
667 .muxregs = fsmc_16bit_autoexp_muxreg,
668 .nmuxregs = ARRAY_SIZE(fsmc_16bit_autoexp_muxreg),
669 }, {
670 .modes = EXTENDED_MODE,
671 .muxregs = fsmc_16bit_muxreg,
672 .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg),
673 },
674};
675
676static struct spear_pingroup fsmc_16bit_pingroup = {
677 .name = "fsmc_16bit_grp",
678 .pins = fsmc_16bit_pins,
679 .npins = ARRAY_SIZE(fsmc_16bit_pins),
680 .modemuxs = fsmc_16bit_modemux,
681 .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux),
682};
683
684static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp" };
685static struct spear_function fsmc_function = {
686 .name = "fsmc",
687 .groups = fsmc_grps,
688 .ngroups = ARRAY_SIZE(fsmc_grps),
689};
690
691/* Pad multiplexing for SPP device */
692static const unsigned spp_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
693 80, 81, 82, 83, 84, 85 };
694static struct spear_muxreg spp_muxreg[] = {
695 {
696 .reg = IP_SEL_PAD_60_69_REG,
697 .mask = PMX_PL_69_MASK,
698 .val = PMX_SPP_PL_69_VAL,
699 }, {
700 .reg = IP_SEL_PAD_70_79_REG,
701 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
702 PMX_PL_74_MASK | PMX_PL_75_76_MASK |
703 PMX_PL_77_78_79_MASK,
704 .val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL |
705 PMX_SPP_PL_73_VAL | PMX_SPP_PL_74_VAL |
706 PMX_SPP_PL_75_76_VAL | PMX_SPP_PL_77_78_79_VAL,
707 }, {
708 .reg = IP_SEL_PAD_80_89_REG,
709 .mask = PMX_PL_80_TO_85_MASK,
710 .val = PMX_SPP_PL_80_TO_85_VAL,
711 },
712};
713
714static struct spear_modemux spp_modemux[] = {
715 {
716 .modes = EXTENDED_MODE,
717 .muxregs = spp_muxreg,
718 .nmuxregs = ARRAY_SIZE(spp_muxreg),
719 },
720};
721
722static struct spear_pingroup spp_pingroup = {
723 .name = "spp_grp",
724 .pins = spp_pins,
725 .npins = ARRAY_SIZE(spp_pins),
726 .modemuxs = spp_modemux,
727 .nmodemuxs = ARRAY_SIZE(spp_modemux),
728};
729
730static const char *const spp_grps[] = { "spp_grp" };
731static struct spear_function spp_function = {
732 .name = "spp",
733 .groups = spp_grps,
734 .ngroups = ARRAY_SIZE(spp_grps),
735};
736
737/* Pad multiplexing for SDHCI device */
738static const unsigned sdhci_led_pins[] = { 34 };
739static struct spear_muxreg sdhci_led_muxreg[] = {
740 {
741 .reg = PMX_CONFIG_REG,
742 .mask = PMX_SSP_CS_MASK,
743 .val = 0,
744 },
745};
746
747static struct spear_muxreg sdhci_led_ext_muxreg[] = {
748 {
749 .reg = IP_SEL_PAD_30_39_REG,
750 .mask = PMX_PL_34_MASK,
751 .val = PMX_PWM2_PL_34_VAL,
752 },
753};
754
755static struct spear_modemux sdhci_led_modemux[] = {
756 {
757 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
758 .muxregs = sdhci_led_muxreg,
759 .nmuxregs = ARRAY_SIZE(sdhci_led_muxreg),
760 }, {
761 .modes = EXTENDED_MODE,
762 .muxregs = sdhci_led_ext_muxreg,
763 .nmuxregs = ARRAY_SIZE(sdhci_led_ext_muxreg),
764 },
765};
766
767static struct spear_pingroup sdhci_led_pingroup = {
768 .name = "sdhci_led_grp",
769 .pins = sdhci_led_pins,
770 .npins = ARRAY_SIZE(sdhci_led_pins),
771 .modemuxs = sdhci_led_modemux,
772 .nmodemuxs = ARRAY_SIZE(sdhci_led_modemux),
773};
774
775static const unsigned sdhci_cd_12_pins[] = { 12, 43, 44, 45, 46, 47, 48, 49,
776 50};
777static const unsigned sdhci_cd_51_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51
778};
779static struct spear_muxreg sdhci_muxreg[] = {
780 {
781 .reg = PMX_CONFIG_REG,
782 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
783 .val = 0,
784 },
785};
786
787static struct spear_muxreg sdhci_ext_muxreg[] = {
788 {
789 .reg = IP_SEL_PAD_40_49_REG,
790 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK |
791 PMX_PL_48_49_MASK,
792 .val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL |
793 PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL,
794 }, {
795 .reg = IP_SEL_PAD_50_59_REG,
796 .mask = PMX_PL_50_MASK,
797 .val = PMX_SDHCI_PL_50_VAL,
798 }, {
799 .reg = IP_SEL_PAD_90_99_REG,
800 .mask = PMX_PL_99_MASK,
801 .val = PMX_SDHCI_PL_99_VAL,
802 }, {
803 .reg = IP_SEL_MIX_PAD_REG,
804 .mask = PMX_PL_100_101_MASK,
805 .val = PMX_SDHCI_PL_100_101_VAL,
806 },
807};
808
809static struct spear_muxreg sdhci_cd_12_muxreg[] = {
810 {
811 .reg = PMX_CONFIG_REG,
812 .mask = PMX_MII_MASK,
813 .val = 0,
814 }, {
815 .reg = IP_SEL_PAD_10_19_REG,
816 .mask = PMX_PL_12_MASK,
817 .val = PMX_SDHCI_CD_PL_12_VAL,
818 }, {
819 .reg = IP_SEL_MIX_PAD_REG,
820 .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
821 .val = PMX_SDHCI_CD_PORT_12_VAL,
822 },
823};
824
825static struct spear_muxreg sdhci_cd_51_muxreg[] = {
826 {
827 .reg = IP_SEL_PAD_50_59_REG,
828 .mask = PMX_PL_51_MASK,
829 .val = PMX_SDHCI_CD_PL_51_VAL,
830 }, {
831 .reg = IP_SEL_MIX_PAD_REG,
832 .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
833 .val = PMX_SDHCI_CD_PORT_51_VAL,
834 },
835};
836
837#define pmx_sdhci_common_modemux \
838 { \
839 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | \
840 SMALL_PRINTERS_MODE | EXTENDED_MODE, \
841 .muxregs = sdhci_muxreg, \
842 .nmuxregs = ARRAY_SIZE(sdhci_muxreg), \
843 }, { \
844 .modes = EXTENDED_MODE, \
845 .muxregs = sdhci_ext_muxreg, \
846 .nmuxregs = ARRAY_SIZE(sdhci_ext_muxreg), \
847 }
848
849static struct spear_modemux sdhci_modemux[][3] = {
850 {
851 /* select pin 12 for cd */
852 pmx_sdhci_common_modemux,
853 {
854 .modes = EXTENDED_MODE,
855 .muxregs = sdhci_cd_12_muxreg,
856 .nmuxregs = ARRAY_SIZE(sdhci_cd_12_muxreg),
857 },
858 }, {
859 /* select pin 51 for cd */
860 pmx_sdhci_common_modemux,
861 {
862 .modes = EXTENDED_MODE,
863 .muxregs = sdhci_cd_51_muxreg,
864 .nmuxregs = ARRAY_SIZE(sdhci_cd_51_muxreg),
865 },
866 }
867};
868
869static struct spear_pingroup sdhci_pingroup[] = {
870 {
871 .name = "sdhci_cd_12_grp",
872 .pins = sdhci_cd_12_pins,
873 .npins = ARRAY_SIZE(sdhci_cd_12_pins),
874 .modemuxs = sdhci_modemux[0],
875 .nmodemuxs = ARRAY_SIZE(sdhci_modemux[0]),
876 }, {
877 .name = "sdhci_cd_51_grp",
878 .pins = sdhci_cd_51_pins,
879 .npins = ARRAY_SIZE(sdhci_cd_51_pins),
880 .modemuxs = sdhci_modemux[1],
881 .nmodemuxs = ARRAY_SIZE(sdhci_modemux[1]),
882 },
883};
884
885static const char *const sdhci_grps[] = { "sdhci_cd_12_grp", "sdhci_cd_51_grp",
886 "sdhci_led_grp" };
887
888static struct spear_function sdhci_function = {
889 .name = "sdhci",
890 .groups = sdhci_grps,
891 .ngroups = ARRAY_SIZE(sdhci_grps),
892};
893
894/* Pad multiplexing for I2S device */
895static const unsigned i2s_pins[] = { 35, 39, 40, 41, 42 };
896static struct spear_muxreg i2s_muxreg[] = {
897 {
898 .reg = PMX_CONFIG_REG,
899 .mask = PMX_SSP_CS_MASK,
900 .val = 0,
901 }, {
902 .reg = PMX_CONFIG_REG,
903 .mask = PMX_UART0_MODEM_MASK,
904 .val = 0,
905 },
906};
907
908static struct spear_muxreg i2s_ext_muxreg[] = {
909 {
910 .reg = IP_SEL_PAD_30_39_REG,
911 .mask = PMX_PL_35_MASK | PMX_PL_39_MASK,
912 .val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL,
913 }, {
914 .reg = IP_SEL_PAD_40_49_REG,
915 .mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK,
916 .val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL,
917 },
918};
919
920static struct spear_modemux i2s_modemux[] = {
921 {
922 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
923 .muxregs = i2s_muxreg,
924 .nmuxregs = ARRAY_SIZE(i2s_muxreg),
925 }, {
926 .modes = EXTENDED_MODE,
927 .muxregs = i2s_ext_muxreg,
928 .nmuxregs = ARRAY_SIZE(i2s_ext_muxreg),
929 },
930};
931
932static struct spear_pingroup i2s_pingroup = {
933 .name = "i2s_grp",
934 .pins = i2s_pins,
935 .npins = ARRAY_SIZE(i2s_pins),
936 .modemuxs = i2s_modemux,
937 .nmodemuxs = ARRAY_SIZE(i2s_modemux),
938};
939
940static const char *const i2s_grps[] = { "i2s_grp" };
941static struct spear_function i2s_function = {
942 .name = "i2s",
943 .groups = i2s_grps,
944 .ngroups = ARRAY_SIZE(i2s_grps),
945};
946
947/* Pad multiplexing for UART1 device */
948static const unsigned uart1_pins[] = { 28, 29 };
949static struct spear_muxreg uart1_muxreg[] = {
950 {
951 .reg = PMX_CONFIG_REG,
952 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
953 .val = 0,
954 },
955};
956
957static struct spear_muxreg uart1_ext_muxreg[] = {
958 {
959 .reg = IP_SEL_PAD_20_29_REG,
960 .mask = PMX_PL_28_29_MASK,
961 .val = PMX_UART1_PL_28_29_VAL,
962 },
963};
964
965static struct spear_modemux uart1_modemux[] = {
966 {
967 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
968 | SMALL_PRINTERS_MODE | EXTENDED_MODE,
969 .muxregs = uart1_muxreg,
970 .nmuxregs = ARRAY_SIZE(uart1_muxreg),
971 }, {
972 .modes = EXTENDED_MODE,
973 .muxregs = uart1_ext_muxreg,
974 .nmuxregs = ARRAY_SIZE(uart1_ext_muxreg),
975 },
976};
977
978static struct spear_pingroup uart1_pingroup = {
979 .name = "uart1_grp",
980 .pins = uart1_pins,
981 .npins = ARRAY_SIZE(uart1_pins),
982 .modemuxs = uart1_modemux,
983 .nmodemuxs = ARRAY_SIZE(uart1_modemux),
984};
985
986static const char *const uart1_grps[] = { "uart1_grp" };
987static struct spear_function uart1_function = {
988 .name = "uart1",
989 .groups = uart1_grps,
990 .ngroups = ARRAY_SIZE(uart1_grps),
991};
992
993/* Pad multiplexing for UART1 Modem device */
994static const unsigned uart1_modem_2_to_7_pins[] = { 2, 3, 4, 5, 6, 7 };
995static const unsigned uart1_modem_31_to_36_pins[] = { 31, 32, 33, 34, 35, 36 };
996static const unsigned uart1_modem_34_to_45_pins[] = { 34, 35, 36, 43, 44, 45 };
997static const unsigned uart1_modem_80_to_85_pins[] = { 80, 81, 82, 83, 84, 85 };
998
999static struct spear_muxreg uart1_modem_ext_2_to_7_muxreg[] = {
1000 {
1001 .reg = PMX_CONFIG_REG,
1002 .mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK,
1003 .val = 0,
1004 }, {
1005 .reg = IP_SEL_PAD_0_9_REG,
1006 .mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK,
1007 .val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL |
1008 PMX_UART1_ENH_PL_6_7_VAL,
1009 }, {
1010 .reg = IP_SEL_MIX_PAD_REG,
1011 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1012 .val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL,
1013 },
1014};
1015
1016static struct spear_muxreg uart1_modem_31_to_36_muxreg[] = {
1017 {
1018 .reg = PMX_CONFIG_REG,
1019 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
1020 PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
1021 .val = 0,
1022 },
1023};
1024
1025static struct spear_muxreg uart1_modem_ext_31_to_36_muxreg[] = {
1026 {
1027 .reg = IP_SEL_PAD_30_39_REG,
1028 .mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK |
1029 PMX_PL_35_MASK | PMX_PL_36_MASK,
1030 .val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL |
1031 PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
1032 PMX_UART1_ENH_PL_36_VAL,
1033 }, {
1034 .reg = IP_SEL_MIX_PAD_REG,
1035 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1036 .val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL,
1037 },
1038};
1039
1040static struct spear_muxreg uart1_modem_34_to_45_muxreg[] = {
1041 {
1042 .reg = PMX_CONFIG_REG,
1043 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK |
1044 PMX_SSP_CS_MASK,
1045 .val = 0,
1046 },
1047};
1048
1049static struct spear_muxreg uart1_modem_ext_34_to_45_muxreg[] = {
1050 {
1051 .reg = IP_SEL_PAD_30_39_REG,
1052 .mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK,
1053 .val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL |
1054 PMX_UART1_ENH_PL_36_VAL,
1055 }, {
1056 .reg = IP_SEL_PAD_40_49_REG,
1057 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
1058 .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
1059 }, {
1060 .reg = IP_SEL_MIX_PAD_REG,
1061 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1062 .val = PMX_UART1_ENH_PORT_44_45_34_36_VAL,
1063 },
1064};
1065
1066static struct spear_muxreg uart1_modem_ext_80_to_85_muxreg[] = {
1067 {
1068 .reg = IP_SEL_PAD_80_89_REG,
1069 .mask = PMX_PL_80_TO_85_MASK,
1070 .val = PMX_UART1_ENH_PL_80_TO_85_VAL,
1071 }, {
1072 .reg = IP_SEL_PAD_40_49_REG,
1073 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
1074 .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL,
1075 }, {
1076 .reg = IP_SEL_MIX_PAD_REG,
1077 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1078 .val = PMX_UART1_ENH_PORT_81_TO_85_VAL,
1079 },
1080};
1081
1082static struct spear_modemux uart1_modem_2_to_7_modemux[] = {
1083 {
1084 .modes = EXTENDED_MODE,
1085 .muxregs = uart1_modem_ext_2_to_7_muxreg,
1086 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_2_to_7_muxreg),
1087 },
1088};
1089
1090static struct spear_modemux uart1_modem_31_to_36_modemux[] = {
1091 {
1092 .modes = SMALL_PRINTERS_MODE | EXTENDED_MODE,
1093 .muxregs = uart1_modem_31_to_36_muxreg,
1094 .nmuxregs = ARRAY_SIZE(uart1_modem_31_to_36_muxreg),
1095 }, {
1096 .modes = EXTENDED_MODE,
1097 .muxregs = uart1_modem_ext_31_to_36_muxreg,
1098 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_31_to_36_muxreg),
1099 },
1100};
1101
1102static struct spear_modemux uart1_modem_34_to_45_modemux[] = {
1103 {
1104 .modes = AUTO_EXP_MODE | EXTENDED_MODE,
1105 .muxregs = uart1_modem_34_to_45_muxreg,
1106 .nmuxregs = ARRAY_SIZE(uart1_modem_34_to_45_muxreg),
1107 }, {
1108 .modes = EXTENDED_MODE,
1109 .muxregs = uart1_modem_ext_34_to_45_muxreg,
1110 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_34_to_45_muxreg),
1111 },
1112};
1113
1114static struct spear_modemux uart1_modem_80_to_85_modemux[] = {
1115 {
1116 .modes = EXTENDED_MODE,
1117 .muxregs = uart1_modem_ext_80_to_85_muxreg,
1118 .nmuxregs = ARRAY_SIZE(uart1_modem_ext_80_to_85_muxreg),
1119 },
1120};
1121
1122static struct spear_pingroup uart1_modem_pingroup[] = {
1123 {
1124 .name = "uart1_modem_2_to_7_grp",
1125 .pins = uart1_modem_2_to_7_pins,
1126 .npins = ARRAY_SIZE(uart1_modem_2_to_7_pins),
1127 .modemuxs = uart1_modem_2_to_7_modemux,
1128 .nmodemuxs = ARRAY_SIZE(uart1_modem_2_to_7_modemux),
1129 }, {
1130 .name = "uart1_modem_31_to_36_grp",
1131 .pins = uart1_modem_31_to_36_pins,
1132 .npins = ARRAY_SIZE(uart1_modem_31_to_36_pins),
1133 .modemuxs = uart1_modem_31_to_36_modemux,
1134 .nmodemuxs = ARRAY_SIZE(uart1_modem_31_to_36_modemux),
1135 }, {
1136 .name = "uart1_modem_34_to_45_grp",
1137 .pins = uart1_modem_34_to_45_pins,
1138 .npins = ARRAY_SIZE(uart1_modem_34_to_45_pins),
1139 .modemuxs = uart1_modem_34_to_45_modemux,
1140 .nmodemuxs = ARRAY_SIZE(uart1_modem_34_to_45_modemux),
1141 }, {
1142 .name = "uart1_modem_80_to_85_grp",
1143 .pins = uart1_modem_80_to_85_pins,
1144 .npins = ARRAY_SIZE(uart1_modem_80_to_85_pins),
1145 .modemuxs = uart1_modem_80_to_85_modemux,
1146 .nmodemuxs = ARRAY_SIZE(uart1_modem_80_to_85_modemux),
1147 },
1148};
1149
1150static const char *const uart1_modem_grps[] = { "uart1_modem_2_to_7_grp",
1151 "uart1_modem_31_to_36_grp", "uart1_modem_34_to_45_grp",
1152 "uart1_modem_80_to_85_grp" };
1153static struct spear_function uart1_modem_function = {
1154 .name = "uart1_modem",
1155 .groups = uart1_modem_grps,
1156 .ngroups = ARRAY_SIZE(uart1_modem_grps),
1157};
1158
1159/* Pad multiplexing for UART2 device */
1160static const unsigned uart2_pins[] = { 0, 1 };
1161static struct spear_muxreg uart2_muxreg[] = {
1162 {
1163 .reg = PMX_CONFIG_REG,
1164 .mask = PMX_FIRDA_MASK,
1165 .val = 0,
1166 },
1167};
1168
1169static struct spear_muxreg uart2_ext_muxreg[] = {
1170 {
1171 .reg = IP_SEL_PAD_0_9_REG,
1172 .mask = PMX_PL_0_1_MASK,
1173 .val = PMX_UART2_PL_0_1_VAL,
1174 },
1175};
1176
1177static struct spear_modemux uart2_modemux[] = {
1178 {
1179 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1180 | SMALL_PRINTERS_MODE | EXTENDED_MODE,
1181 .muxregs = uart2_muxreg,
1182 .nmuxregs = ARRAY_SIZE(uart2_muxreg),
1183 }, {
1184 .modes = EXTENDED_MODE,
1185 .muxregs = uart2_ext_muxreg,
1186 .nmuxregs = ARRAY_SIZE(uart2_ext_muxreg),
1187 },
1188};
1189
1190static struct spear_pingroup uart2_pingroup = {
1191 .name = "uart2_grp",
1192 .pins = uart2_pins,
1193 .npins = ARRAY_SIZE(uart2_pins),
1194 .modemuxs = uart2_modemux,
1195 .nmodemuxs = ARRAY_SIZE(uart2_modemux),
1196};
1197
1198static const char *const uart2_grps[] = { "uart2_grp" };
1199static struct spear_function uart2_function = {
1200 .name = "uart2",
1201 .groups = uart2_grps,
1202 .ngroups = ARRAY_SIZE(uart2_grps),
1203};
1204
1205/* Pad multiplexing for uart3 device */
1206static const unsigned uart3_pins[][2] = { { 8, 9 }, { 15, 16 }, { 41, 42 },
1207 { 52, 53 }, { 73, 74 }, { 94, 95 }, { 98, 99 } };
1208
1209static struct spear_muxreg uart3_ext_8_9_muxreg[] = {
1210 {
1211 .reg = PMX_CONFIG_REG,
1212 .mask = PMX_SSP_MASK,
1213 .val = 0,
1214 }, {
1215 .reg = IP_SEL_PAD_0_9_REG,
1216 .mask = PMX_PL_8_9_MASK,
1217 .val = PMX_UART3_PL_8_9_VAL,
1218 }, {
1219 .reg = IP_SEL_MIX_PAD_REG,
1220 .mask = PMX_UART3_PORT_SEL_MASK,
1221 .val = PMX_UART3_PORT_8_VAL,
1222 },
1223};
1224
1225static struct spear_muxreg uart3_ext_15_16_muxreg[] = {
1226 {
1227 .reg = PMX_CONFIG_REG,
1228 .mask = PMX_MII_MASK,
1229 .val = 0,
1230 }, {
1231 .reg = IP_SEL_PAD_10_19_REG,
1232 .mask = PMX_PL_15_16_MASK,
1233 .val = PMX_UART3_PL_15_16_VAL,
1234 }, {
1235 .reg = IP_SEL_MIX_PAD_REG,
1236 .mask = PMX_UART3_PORT_SEL_MASK,
1237 .val = PMX_UART3_PORT_15_VAL,
1238 },
1239};
1240
1241static struct spear_muxreg uart3_ext_41_42_muxreg[] = {
1242 {
1243 .reg = PMX_CONFIG_REG,
1244 .mask = PMX_UART0_MODEM_MASK,
1245 .val = 0,
1246 }, {
1247 .reg = IP_SEL_PAD_40_49_REG,
1248 .mask = PMX_PL_41_42_MASK,
1249 .val = PMX_UART3_PL_41_42_VAL,
1250 }, {
1251 .reg = IP_SEL_MIX_PAD_REG,
1252 .mask = PMX_UART3_PORT_SEL_MASK,
1253 .val = PMX_UART3_PORT_41_VAL,
1254 },
1255};
1256
1257static struct spear_muxreg uart3_ext_52_53_muxreg[] = {
1258 {
1259 .reg = IP_SEL_PAD_50_59_REG,
1260 .mask = PMX_PL_52_53_MASK,
1261 .val = PMX_UART3_PL_52_53_VAL,
1262 }, {
1263 .reg = IP_SEL_MIX_PAD_REG,
1264 .mask = PMX_UART3_PORT_SEL_MASK,
1265 .val = PMX_UART3_PORT_52_VAL,
1266 },
1267};
1268
1269static struct spear_muxreg uart3_ext_73_74_muxreg[] = {
1270 {
1271 .reg = IP_SEL_PAD_70_79_REG,
1272 .mask = PMX_PL_73_MASK | PMX_PL_74_MASK,
1273 .val = PMX_UART3_PL_73_VAL | PMX_UART3_PL_74_VAL,
1274 }, {
1275 .reg = IP_SEL_MIX_PAD_REG,
1276 .mask = PMX_UART3_PORT_SEL_MASK,
1277 .val = PMX_UART3_PORT_73_VAL,
1278 },
1279};
1280
1281static struct spear_muxreg uart3_ext_94_95_muxreg[] = {
1282 {
1283 .reg = IP_SEL_PAD_90_99_REG,
1284 .mask = PMX_PL_94_95_MASK,
1285 .val = PMX_UART3_PL_94_95_VAL,
1286 }, {
1287 .reg = IP_SEL_MIX_PAD_REG,
1288 .mask = PMX_UART3_PORT_SEL_MASK,
1289 .val = PMX_UART3_PORT_94_VAL,
1290 },
1291};
1292
1293static struct spear_muxreg uart3_ext_98_99_muxreg[] = {
1294 {
1295 .reg = IP_SEL_PAD_90_99_REG,
1296 .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
1297 .val = PMX_UART3_PL_98_VAL | PMX_UART3_PL_99_VAL,
1298 }, {
1299 .reg = IP_SEL_MIX_PAD_REG,
1300 .mask = PMX_UART3_PORT_SEL_MASK,
1301 .val = PMX_UART3_PORT_99_VAL,
1302 },
1303};
1304
1305static struct spear_modemux uart3_modemux[][1] = {
1306 {
1307 /* Select signals on pins 8_9 */
1308 {
1309 .modes = EXTENDED_MODE,
1310 .muxregs = uart3_ext_8_9_muxreg,
1311 .nmuxregs = ARRAY_SIZE(uart3_ext_8_9_muxreg),
1312 },
1313 }, {
1314 /* Select signals on pins 15_16 */
1315 {
1316 .modes = EXTENDED_MODE,
1317 .muxregs = uart3_ext_15_16_muxreg,
1318 .nmuxregs = ARRAY_SIZE(uart3_ext_15_16_muxreg),
1319 },
1320 }, {
1321 /* Select signals on pins 41_42 */
1322 {
1323 .modes = EXTENDED_MODE,
1324 .muxregs = uart3_ext_41_42_muxreg,
1325 .nmuxregs = ARRAY_SIZE(uart3_ext_41_42_muxreg),
1326 },
1327 }, {
1328 /* Select signals on pins 52_53 */
1329 {
1330 .modes = EXTENDED_MODE,
1331 .muxregs = uart3_ext_52_53_muxreg,
1332 .nmuxregs = ARRAY_SIZE(uart3_ext_52_53_muxreg),
1333 },
1334 }, {
1335 /* Select signals on pins 73_74 */
1336 {
1337 .modes = EXTENDED_MODE,
1338 .muxregs = uart3_ext_73_74_muxreg,
1339 .nmuxregs = ARRAY_SIZE(uart3_ext_73_74_muxreg),
1340 },
1341 }, {
1342 /* Select signals on pins 94_95 */
1343 {
1344 .modes = EXTENDED_MODE,
1345 .muxregs = uart3_ext_94_95_muxreg,
1346 .nmuxregs = ARRAY_SIZE(uart3_ext_94_95_muxreg),
1347 },
1348 }, {
1349 /* Select signals on pins 98_99 */
1350 {
1351 .modes = EXTENDED_MODE,
1352 .muxregs = uart3_ext_98_99_muxreg,
1353 .nmuxregs = ARRAY_SIZE(uart3_ext_98_99_muxreg),
1354 },
1355 },
1356};
1357
1358static struct spear_pingroup uart3_pingroup[] = {
1359 {
1360 .name = "uart3_8_9_grp",
1361 .pins = uart3_pins[0],
1362 .npins = ARRAY_SIZE(uart3_pins[0]),
1363 .modemuxs = uart3_modemux[0],
1364 .nmodemuxs = ARRAY_SIZE(uart3_modemux[0]),
1365 }, {
1366 .name = "uart3_15_16_grp",
1367 .pins = uart3_pins[1],
1368 .npins = ARRAY_SIZE(uart3_pins[1]),
1369 .modemuxs = uart3_modemux[1],
1370 .nmodemuxs = ARRAY_SIZE(uart3_modemux[1]),
1371 }, {
1372 .name = "uart3_41_42_grp",
1373 .pins = uart3_pins[2],
1374 .npins = ARRAY_SIZE(uart3_pins[2]),
1375 .modemuxs = uart3_modemux[2],
1376 .nmodemuxs = ARRAY_SIZE(uart3_modemux[2]),
1377 }, {
1378 .name = "uart3_52_53_grp",
1379 .pins = uart3_pins[3],
1380 .npins = ARRAY_SIZE(uart3_pins[3]),
1381 .modemuxs = uart3_modemux[3],
1382 .nmodemuxs = ARRAY_SIZE(uart3_modemux[3]),
1383 }, {
1384 .name = "uart3_73_74_grp",
1385 .pins = uart3_pins[4],
1386 .npins = ARRAY_SIZE(uart3_pins[4]),
1387 .modemuxs = uart3_modemux[4],
1388 .nmodemuxs = ARRAY_SIZE(uart3_modemux[4]),
1389 }, {
1390 .name = "uart3_94_95_grp",
1391 .pins = uart3_pins[5],
1392 .npins = ARRAY_SIZE(uart3_pins[5]),
1393 .modemuxs = uart3_modemux[5],
1394 .nmodemuxs = ARRAY_SIZE(uart3_modemux[5]),
1395 }, {
1396 .name = "uart3_98_99_grp",
1397 .pins = uart3_pins[6],
1398 .npins = ARRAY_SIZE(uart3_pins[6]),
1399 .modemuxs = uart3_modemux[6],
1400 .nmodemuxs = ARRAY_SIZE(uart3_modemux[6]),
1401 },
1402};
1403
1404static const char *const uart3_grps[] = { "uart3_8_9_grp", "uart3_15_16_grp",
1405 "uart3_41_42_grp", "uart3_52_53_grp", "uart3_73_74_grp",
1406 "uart3_94_95_grp", "uart3_98_99_grp" };
1407
1408static struct spear_function uart3_function = {
1409 .name = "uart3",
1410 .groups = uart3_grps,
1411 .ngroups = ARRAY_SIZE(uart3_grps),
1412};
1413
1414/* Pad multiplexing for uart4 device */
1415static const unsigned uart4_pins[][2] = { { 6, 7 }, { 13, 14 }, { 39, 40 },
1416 { 71, 72 }, { 92, 93 }, { 100, 101 } };
1417
1418static struct spear_muxreg uart4_ext_6_7_muxreg[] = {
1419 {
1420 .reg = PMX_CONFIG_REG,
1421 .mask = PMX_SSP_MASK,
1422 .val = 0,
1423 }, {
1424 .reg = IP_SEL_PAD_0_9_REG,
1425 .mask = PMX_PL_6_7_MASK,
1426 .val = PMX_UART4_PL_6_7_VAL,
1427 }, {
1428 .reg = IP_SEL_MIX_PAD_REG,
1429 .mask = PMX_UART4_PORT_SEL_MASK,
1430 .val = PMX_UART4_PORT_6_VAL,
1431 },
1432};
1433
1434static struct spear_muxreg uart4_ext_13_14_muxreg[] = {
1435 {
1436 .reg = PMX_CONFIG_REG,
1437 .mask = PMX_MII_MASK,
1438 .val = 0,
1439 }, {
1440 .reg = IP_SEL_PAD_10_19_REG,
1441 .mask = PMX_PL_13_14_MASK,
1442 .val = PMX_UART4_PL_13_14_VAL,
1443 }, {
1444 .reg = IP_SEL_MIX_PAD_REG,
1445 .mask = PMX_UART4_PORT_SEL_MASK,
1446 .val = PMX_UART4_PORT_13_VAL,
1447 },
1448};
1449
1450static struct spear_muxreg uart4_ext_39_40_muxreg[] = {
1451 {
1452 .reg = PMX_CONFIG_REG,
1453 .mask = PMX_UART0_MODEM_MASK,
1454 .val = 0,
1455 }, {
1456 .reg = IP_SEL_PAD_30_39_REG,
1457 .mask = PMX_PL_39_MASK,
1458 .val = PMX_UART4_PL_39_VAL,
1459 }, {
1460 .reg = IP_SEL_PAD_40_49_REG,
1461 .mask = PMX_PL_40_MASK,
1462 .val = PMX_UART4_PL_40_VAL,
1463 }, {
1464 .reg = IP_SEL_MIX_PAD_REG,
1465 .mask = PMX_UART4_PORT_SEL_MASK,
1466 .val = PMX_UART4_PORT_39_VAL,
1467 },
1468};
1469
1470static struct spear_muxreg uart4_ext_71_72_muxreg[] = {
1471 {
1472 .reg = IP_SEL_PAD_70_79_REG,
1473 .mask = PMX_PL_71_72_MASK,
1474 .val = PMX_UART4_PL_71_72_VAL,
1475 }, {
1476 .reg = IP_SEL_MIX_PAD_REG,
1477 .mask = PMX_UART4_PORT_SEL_MASK,
1478 .val = PMX_UART4_PORT_71_VAL,
1479 },
1480};
1481
1482static struct spear_muxreg uart4_ext_92_93_muxreg[] = {
1483 {
1484 .reg = IP_SEL_PAD_90_99_REG,
1485 .mask = PMX_PL_92_93_MASK,
1486 .val = PMX_UART4_PL_92_93_VAL,
1487 }, {
1488 .reg = IP_SEL_MIX_PAD_REG,
1489 .mask = PMX_UART4_PORT_SEL_MASK,
1490 .val = PMX_UART4_PORT_92_VAL,
1491 },
1492};
1493
1494static struct spear_muxreg uart4_ext_100_101_muxreg[] = {
1495 {
1496 .reg = IP_SEL_MIX_PAD_REG,
1497 .mask = PMX_PL_100_101_MASK |
1498 PMX_UART4_PORT_SEL_MASK,
1499 .val = PMX_UART4_PL_100_101_VAL |
1500 PMX_UART4_PORT_101_VAL,
1501 },
1502};
1503
1504static struct spear_modemux uart4_modemux[][1] = {
1505 {
1506 /* Select signals on pins 6_7 */
1507 {
1508 .modes = EXTENDED_MODE,
1509 .muxregs = uart4_ext_6_7_muxreg,
1510 .nmuxregs = ARRAY_SIZE(uart4_ext_6_7_muxreg),
1511 },
1512 }, {
1513 /* Select signals on pins 13_14 */
1514 {
1515 .modes = EXTENDED_MODE,
1516 .muxregs = uart4_ext_13_14_muxreg,
1517 .nmuxregs = ARRAY_SIZE(uart4_ext_13_14_muxreg),
1518 },
1519 }, {
1520 /* Select signals on pins 39_40 */
1521 {
1522 .modes = EXTENDED_MODE,
1523 .muxregs = uart4_ext_39_40_muxreg,
1524 .nmuxregs = ARRAY_SIZE(uart4_ext_39_40_muxreg),
1525 },
1526 }, {
1527 /* Select signals on pins 71_72 */
1528 {
1529 .modes = EXTENDED_MODE,
1530 .muxregs = uart4_ext_71_72_muxreg,
1531 .nmuxregs = ARRAY_SIZE(uart4_ext_71_72_muxreg),
1532 },
1533 }, {
1534 /* Select signals on pins 92_93 */
1535 {
1536 .modes = EXTENDED_MODE,
1537 .muxregs = uart4_ext_92_93_muxreg,
1538 .nmuxregs = ARRAY_SIZE(uart4_ext_92_93_muxreg),
1539 },
1540 }, {
1541 /* Select signals on pins 100_101_ */
1542 {
1543 .modes = EXTENDED_MODE,
1544 .muxregs = uart4_ext_100_101_muxreg,
1545 .nmuxregs = ARRAY_SIZE(uart4_ext_100_101_muxreg),
1546 },
1547 },
1548};
1549
1550static struct spear_pingroup uart4_pingroup[] = {
1551 {
1552 .name = "uart4_6_7_grp",
1553 .pins = uart4_pins[0],
1554 .npins = ARRAY_SIZE(uart4_pins[0]),
1555 .modemuxs = uart4_modemux[0],
1556 .nmodemuxs = ARRAY_SIZE(uart4_modemux[0]),
1557 }, {
1558 .name = "uart4_13_14_grp",
1559 .pins = uart4_pins[1],
1560 .npins = ARRAY_SIZE(uart4_pins[1]),
1561 .modemuxs = uart4_modemux[1],
1562 .nmodemuxs = ARRAY_SIZE(uart4_modemux[1]),
1563 }, {
1564 .name = "uart4_39_40_grp",
1565 .pins = uart4_pins[2],
1566 .npins = ARRAY_SIZE(uart4_pins[2]),
1567 .modemuxs = uart4_modemux[2],
1568 .nmodemuxs = ARRAY_SIZE(uart4_modemux[2]),
1569 }, {
1570 .name = "uart4_71_72_grp",
1571 .pins = uart4_pins[3],
1572 .npins = ARRAY_SIZE(uart4_pins[3]),
1573 .modemuxs = uart4_modemux[3],
1574 .nmodemuxs = ARRAY_SIZE(uart4_modemux[3]),
1575 }, {
1576 .name = "uart4_92_93_grp",
1577 .pins = uart4_pins[4],
1578 .npins = ARRAY_SIZE(uart4_pins[4]),
1579 .modemuxs = uart4_modemux[4],
1580 .nmodemuxs = ARRAY_SIZE(uart4_modemux[4]),
1581 }, {
1582 .name = "uart4_100_101_grp",
1583 .pins = uart4_pins[5],
1584 .npins = ARRAY_SIZE(uart4_pins[5]),
1585 .modemuxs = uart4_modemux[5],
1586 .nmodemuxs = ARRAY_SIZE(uart4_modemux[5]),
1587 },
1588};
1589
1590static const char *const uart4_grps[] = { "uart4_6_7_grp", "uart4_13_14_grp",
1591 "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp",
1592 "uart4_100_101_grp" };
1593
1594static struct spear_function uart4_function = {
1595 .name = "uart4",
1596 .groups = uart4_grps,
1597 .ngroups = ARRAY_SIZE(uart4_grps),
1598};
1599
1600/* Pad multiplexing for uart5 device */
1601static const unsigned uart5_pins[][2] = { { 4, 5 }, { 37, 38 }, { 69, 70 },
1602 { 90, 91 } };
1603
1604static struct spear_muxreg uart5_ext_4_5_muxreg[] = {
1605 {
1606 .reg = PMX_CONFIG_REG,
1607 .mask = PMX_I2C_MASK,
1608 .val = 0,
1609 }, {
1610 .reg = IP_SEL_PAD_0_9_REG,
1611 .mask = PMX_PL_4_5_MASK,
1612 .val = PMX_UART5_PL_4_5_VAL,
1613 }, {
1614 .reg = IP_SEL_MIX_PAD_REG,
1615 .mask = PMX_UART5_PORT_SEL_MASK,
1616 .val = PMX_UART5_PORT_4_VAL,
1617 },
1618};
1619
1620static struct spear_muxreg uart5_ext_37_38_muxreg[] = {
1621 {
1622 .reg = PMX_CONFIG_REG,
1623 .mask = PMX_UART0_MODEM_MASK,
1624 .val = 0,
1625 }, {
1626 .reg = IP_SEL_PAD_30_39_REG,
1627 .mask = PMX_PL_37_38_MASK,
1628 .val = PMX_UART5_PL_37_38_VAL,
1629 }, {
1630 .reg = IP_SEL_MIX_PAD_REG,
1631 .mask = PMX_UART5_PORT_SEL_MASK,
1632 .val = PMX_UART5_PORT_37_VAL,
1633 },
1634};
1635
1636static struct spear_muxreg uart5_ext_69_70_muxreg[] = {
1637 {
1638 .reg = IP_SEL_PAD_60_69_REG,
1639 .mask = PMX_PL_69_MASK,
1640 .val = PMX_UART5_PL_69_VAL,
1641 }, {
1642 .reg = IP_SEL_PAD_70_79_REG,
1643 .mask = PMX_PL_70_MASK,
1644 .val = PMX_UART5_PL_70_VAL,
1645 }, {
1646 .reg = IP_SEL_MIX_PAD_REG,
1647 .mask = PMX_UART5_PORT_SEL_MASK,
1648 .val = PMX_UART5_PORT_69_VAL,
1649 },
1650};
1651
1652static struct spear_muxreg uart5_ext_90_91_muxreg[] = {
1653 {
1654 .reg = IP_SEL_PAD_90_99_REG,
1655 .mask = PMX_PL_90_91_MASK,
1656 .val = PMX_UART5_PL_90_91_VAL,
1657 }, {
1658 .reg = IP_SEL_MIX_PAD_REG,
1659 .mask = PMX_UART5_PORT_SEL_MASK,
1660 .val = PMX_UART5_PORT_90_VAL,
1661 },
1662};
1663
1664static struct spear_modemux uart5_modemux[][1] = {
1665 {
1666 /* Select signals on pins 4_5 */
1667 {
1668 .modes = EXTENDED_MODE,
1669 .muxregs = uart5_ext_4_5_muxreg,
1670 .nmuxregs = ARRAY_SIZE(uart5_ext_4_5_muxreg),
1671 },
1672 }, {
1673 /* Select signals on pins 37_38 */
1674 {
1675 .modes = EXTENDED_MODE,
1676 .muxregs = uart5_ext_37_38_muxreg,
1677 .nmuxregs = ARRAY_SIZE(uart5_ext_37_38_muxreg),
1678 },
1679 }, {
1680 /* Select signals on pins 69_70 */
1681 {
1682 .modes = EXTENDED_MODE,
1683 .muxregs = uart5_ext_69_70_muxreg,
1684 .nmuxregs = ARRAY_SIZE(uart5_ext_69_70_muxreg),
1685 },
1686 }, {
1687 /* Select signals on pins 90_91 */
1688 {
1689 .modes = EXTENDED_MODE,
1690 .muxregs = uart5_ext_90_91_muxreg,
1691 .nmuxregs = ARRAY_SIZE(uart5_ext_90_91_muxreg),
1692 },
1693 },
1694};
1695
1696static struct spear_pingroup uart5_pingroup[] = {
1697 {
1698 .name = "uart5_4_5_grp",
1699 .pins = uart5_pins[0],
1700 .npins = ARRAY_SIZE(uart5_pins[0]),
1701 .modemuxs = uart5_modemux[0],
1702 .nmodemuxs = ARRAY_SIZE(uart5_modemux[0]),
1703 }, {
1704 .name = "uart5_37_38_grp",
1705 .pins = uart5_pins[1],
1706 .npins = ARRAY_SIZE(uart5_pins[1]),
1707 .modemuxs = uart5_modemux[1],
1708 .nmodemuxs = ARRAY_SIZE(uart5_modemux[1]),
1709 }, {
1710 .name = "uart5_69_70_grp",
1711 .pins = uart5_pins[2],
1712 .npins = ARRAY_SIZE(uart5_pins[2]),
1713 .modemuxs = uart5_modemux[2],
1714 .nmodemuxs = ARRAY_SIZE(uart5_modemux[2]),
1715 }, {
1716 .name = "uart5_90_91_grp",
1717 .pins = uart5_pins[3],
1718 .npins = ARRAY_SIZE(uart5_pins[3]),
1719 .modemuxs = uart5_modemux[3],
1720 .nmodemuxs = ARRAY_SIZE(uart5_modemux[3]),
1721 },
1722};
1723
1724static const char *const uart5_grps[] = { "uart5_4_5_grp", "uart5_37_38_grp",
1725 "uart5_69_70_grp", "uart5_90_91_grp" };
1726static struct spear_function uart5_function = {
1727 .name = "uart5",
1728 .groups = uart5_grps,
1729 .ngroups = ARRAY_SIZE(uart5_grps),
1730};
1731
1732/* Pad multiplexing for uart6 device */
1733static const unsigned uart6_pins[][2] = { { 2, 3 }, { 88, 89 } };
1734static struct spear_muxreg uart6_ext_2_3_muxreg[] = {
1735 {
1736 .reg = PMX_CONFIG_REG,
1737 .mask = PMX_UART0_MASK,
1738 .val = 0,
1739 }, {
1740 .reg = IP_SEL_PAD_0_9_REG,
1741 .mask = PMX_PL_2_3_MASK,
1742 .val = PMX_UART6_PL_2_3_VAL,
1743 }, {
1744 .reg = IP_SEL_MIX_PAD_REG,
1745 .mask = PMX_UART6_PORT_SEL_MASK,
1746 .val = PMX_UART6_PORT_2_VAL,
1747 },
1748};
1749
1750static struct spear_muxreg uart6_ext_88_89_muxreg[] = {
1751 {
1752 .reg = IP_SEL_PAD_80_89_REG,
1753 .mask = PMX_PL_88_89_MASK,
1754 .val = PMX_UART6_PL_88_89_VAL,
1755 }, {
1756 .reg = IP_SEL_MIX_PAD_REG,
1757 .mask = PMX_UART6_PORT_SEL_MASK,
1758 .val = PMX_UART6_PORT_88_VAL,
1759 },
1760};
1761
1762static struct spear_modemux uart6_modemux[][1] = {
1763 {
1764 /* Select signals on pins 2_3 */
1765 {
1766 .modes = EXTENDED_MODE,
1767 .muxregs = uart6_ext_2_3_muxreg,
1768 .nmuxregs = ARRAY_SIZE(uart6_ext_2_3_muxreg),
1769 },
1770 }, {
1771 /* Select signals on pins 88_89 */
1772 {
1773 .modes = EXTENDED_MODE,
1774 .muxregs = uart6_ext_88_89_muxreg,
1775 .nmuxregs = ARRAY_SIZE(uart6_ext_88_89_muxreg),
1776 },
1777 },
1778};
1779
1780static struct spear_pingroup uart6_pingroup[] = {
1781 {
1782 .name = "uart6_2_3_grp",
1783 .pins = uart6_pins[0],
1784 .npins = ARRAY_SIZE(uart6_pins[0]),
1785 .modemuxs = uart6_modemux[0],
1786 .nmodemuxs = ARRAY_SIZE(uart6_modemux[0]),
1787 }, {
1788 .name = "uart6_88_89_grp",
1789 .pins = uart6_pins[1],
1790 .npins = ARRAY_SIZE(uart6_pins[1]),
1791 .modemuxs = uart6_modemux[1],
1792 .nmodemuxs = ARRAY_SIZE(uart6_modemux[1]),
1793 },
1794};
1795
1796static const char *const uart6_grps[] = { "uart6_2_3_grp", "uart6_88_89_grp" };
1797static struct spear_function uart6_function = {
1798 .name = "uart6",
1799 .groups = uart6_grps,
1800 .ngroups = ARRAY_SIZE(uart6_grps),
1801};
1802
1803/* UART - RS485 pmx */
1804static const unsigned rs485_pins[] = { 77, 78, 79 };
1805static struct spear_muxreg rs485_muxreg[] = {
1806 {
1807 .reg = IP_SEL_PAD_70_79_REG,
1808 .mask = PMX_PL_77_78_79_MASK,
1809 .val = PMX_RS485_PL_77_78_79_VAL,
1810 },
1811};
1812
1813static struct spear_modemux rs485_modemux[] = {
1814 {
1815 .modes = EXTENDED_MODE,
1816 .muxregs = rs485_muxreg,
1817 .nmuxregs = ARRAY_SIZE(rs485_muxreg),
1818 },
1819};
1820
1821static struct spear_pingroup rs485_pingroup = {
1822 .name = "rs485_grp",
1823 .pins = rs485_pins,
1824 .npins = ARRAY_SIZE(rs485_pins),
1825 .modemuxs = rs485_modemux,
1826 .nmodemuxs = ARRAY_SIZE(rs485_modemux),
1827};
1828
1829static const char *const rs485_grps[] = { "rs485_grp" };
1830static struct spear_function rs485_function = {
1831 .name = "rs485",
1832 .groups = rs485_grps,
1833 .ngroups = ARRAY_SIZE(rs485_grps),
1834};
1835
1836/* Pad multiplexing for Touchscreen device */
1837static const unsigned touchscreen_pins[] = { 5, 36 };
1838static struct spear_muxreg touchscreen_muxreg[] = {
1839 {
1840 .reg = PMX_CONFIG_REG,
1841 .mask = PMX_I2C_MASK | PMX_SSP_CS_MASK,
1842 .val = 0,
1843 },
1844};
1845
1846static struct spear_muxreg touchscreen_ext_muxreg[] = {
1847 {
1848 .reg = IP_SEL_PAD_0_9_REG,
1849 .mask = PMX_PL_5_MASK,
1850 .val = PMX_TOUCH_Y_PL_5_VAL,
1851 }, {
1852 .reg = IP_SEL_PAD_30_39_REG,
1853 .mask = PMX_PL_36_MASK,
1854 .val = PMX_TOUCH_X_PL_36_VAL,
1855 },
1856};
1857
1858static struct spear_modemux touchscreen_modemux[] = {
1859 {
1860 .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
1861 .muxregs = touchscreen_muxreg,
1862 .nmuxregs = ARRAY_SIZE(touchscreen_muxreg),
1863 }, {
1864 .modes = EXTENDED_MODE,
1865 .muxregs = touchscreen_ext_muxreg,
1866 .nmuxregs = ARRAY_SIZE(touchscreen_ext_muxreg),
1867 },
1868};
1869
1870static struct spear_pingroup touchscreen_pingroup = {
1871 .name = "touchscreen_grp",
1872 .pins = touchscreen_pins,
1873 .npins = ARRAY_SIZE(touchscreen_pins),
1874 .modemuxs = touchscreen_modemux,
1875 .nmodemuxs = ARRAY_SIZE(touchscreen_modemux),
1876};
1877
1878static const char *const touchscreen_grps[] = { "touchscreen_grp" };
1879static struct spear_function touchscreen_function = {
1880 .name = "touchscreen",
1881 .groups = touchscreen_grps,
1882 .ngroups = ARRAY_SIZE(touchscreen_grps),
1883};
1884
1885/* Pad multiplexing for CAN device */
1886static const unsigned can0_pins[] = { 32, 33 };
1887static struct spear_muxreg can0_muxreg[] = {
1888 {
1889 .reg = PMX_CONFIG_REG,
1890 .mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
1891 .val = 0,
1892 },
1893};
1894
1895static struct spear_muxreg can0_ext_muxreg[] = {
1896 {
1897 .reg = IP_SEL_PAD_30_39_REG,
1898 .mask = PMX_PL_32_33_MASK,
1899 .val = PMX_CAN0_PL_32_33_VAL,
1900 },
1901};
1902
1903static struct spear_modemux can0_modemux[] = {
1904 {
1905 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1906 | EXTENDED_MODE,
1907 .muxregs = can0_muxreg,
1908 .nmuxregs = ARRAY_SIZE(can0_muxreg),
1909 }, {
1910 .modes = EXTENDED_MODE,
1911 .muxregs = can0_ext_muxreg,
1912 .nmuxregs = ARRAY_SIZE(can0_ext_muxreg),
1913 },
1914};
1915
1916static struct spear_pingroup can0_pingroup = {
1917 .name = "can0_grp",
1918 .pins = can0_pins,
1919 .npins = ARRAY_SIZE(can0_pins),
1920 .modemuxs = can0_modemux,
1921 .nmodemuxs = ARRAY_SIZE(can0_modemux),
1922};
1923
1924static const char *const can0_grps[] = { "can0_grp" };
1925static struct spear_function can0_function = {
1926 .name = "can0",
1927 .groups = can0_grps,
1928 .ngroups = ARRAY_SIZE(can0_grps),
1929};
1930
1931static const unsigned can1_pins[] = { 30, 31 };
1932static struct spear_muxreg can1_muxreg[] = {
1933 {
1934 .reg = PMX_CONFIG_REG,
1935 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
1936 .val = 0,
1937 },
1938};
1939
1940static struct spear_muxreg can1_ext_muxreg[] = {
1941 {
1942 .reg = IP_SEL_PAD_30_39_REG,
1943 .mask = PMX_PL_30_31_MASK,
1944 .val = PMX_CAN1_PL_30_31_VAL,
1945 },
1946};
1947
1948static struct spear_modemux can1_modemux[] = {
1949 {
1950 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE
1951 | EXTENDED_MODE,
1952 .muxregs = can1_muxreg,
1953 .nmuxregs = ARRAY_SIZE(can1_muxreg),
1954 }, {
1955 .modes = EXTENDED_MODE,
1956 .muxregs = can1_ext_muxreg,
1957 .nmuxregs = ARRAY_SIZE(can1_ext_muxreg),
1958 },
1959};
1960
1961static struct spear_pingroup can1_pingroup = {
1962 .name = "can1_grp",
1963 .pins = can1_pins,
1964 .npins = ARRAY_SIZE(can1_pins),
1965 .modemuxs = can1_modemux,
1966 .nmodemuxs = ARRAY_SIZE(can1_modemux),
1967};
1968
1969static const char *const can1_grps[] = { "can1_grp" };
1970static struct spear_function can1_function = {
1971 .name = "can1",
1972 .groups = can1_grps,
1973 .ngroups = ARRAY_SIZE(can1_grps),
1974};
1975
1976/* Pad multiplexing for PWM0_1 device */
1977static const unsigned pwm0_1_pins[][2] = { { 37, 38 }, { 14, 15 }, { 8, 9 },
1978 { 30, 31 }, { 42, 43 }, { 59, 60 }, { 88, 89 } };
1979
1980static struct spear_muxreg pwm0_1_pin_8_9_muxreg[] = {
1981 {
1982 .reg = PMX_CONFIG_REG,
1983 .mask = PMX_SSP_MASK,
1984 .val = 0,
1985 }, {
1986 .reg = IP_SEL_PAD_0_9_REG,
1987 .mask = PMX_PL_8_9_MASK,
1988 .val = PMX_PWM_0_1_PL_8_9_VAL,
1989 },
1990};
1991
1992static struct spear_muxreg pwm0_1_autoexpsmallpri_muxreg[] = {
1993 {
1994 .reg = PMX_CONFIG_REG,
1995 .mask = PMX_MII_MASK,
1996 .val = 0,
1997 },
1998};
1999
2000static struct spear_muxreg pwm0_1_pin_14_15_muxreg[] = {
2001 {
2002 .reg = IP_SEL_PAD_10_19_REG,
2003 .mask = PMX_PL_14_MASK | PMX_PL_15_MASK,
2004 .val = PMX_PWM1_PL_14_VAL | PMX_PWM0_PL_15_VAL,
2005 },
2006};
2007
2008static struct spear_muxreg pwm0_1_pin_30_31_muxreg[] = {
2009 {
2010 .reg = PMX_CONFIG_REG,
2011 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
2012 .val = 0,
2013 }, {
2014 .reg = IP_SEL_PAD_30_39_REG,
2015 .mask = PMX_PL_30_MASK | PMX_PL_31_MASK,
2016 .val = PMX_PWM1_EXT_PL_30_VAL | PMX_PWM0_EXT_PL_31_VAL,
2017 },
2018};
2019
2020static struct spear_muxreg pwm0_1_net_muxreg[] = {
2021 {
2022 .reg = PMX_CONFIG_REG,
2023 .mask = PMX_UART0_MODEM_MASK,
2024 .val = 0,
2025 },
2026};
2027
2028static struct spear_muxreg pwm0_1_pin_37_38_muxreg[] = {
2029 {
2030 .reg = IP_SEL_PAD_30_39_REG,
2031 .mask = PMX_PL_37_38_MASK,
2032 .val = PMX_PWM0_1_PL_37_38_VAL,
2033 },
2034};
2035
2036static struct spear_muxreg pwm0_1_pin_42_43_muxreg[] = {
2037 {
2038 .reg = PMX_CONFIG_REG,
2039 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK ,
2040 .val = 0,
2041 }, {
2042 .reg = IP_SEL_PAD_40_49_REG,
2043 .mask = PMX_PL_42_MASK | PMX_PL_43_MASK,
2044 .val = PMX_PWM1_PL_42_VAL |
2045 PMX_PWM0_PL_43_VAL,
2046 },
2047};
2048
2049static struct spear_muxreg pwm0_1_pin_59_60_muxreg[] = {
2050 {
2051 .reg = IP_SEL_PAD_50_59_REG,
2052 .mask = PMX_PL_59_MASK,
2053 .val = PMX_PWM1_PL_59_VAL,
2054 }, {
2055 .reg = IP_SEL_PAD_60_69_REG,
2056 .mask = PMX_PL_60_MASK,
2057 .val = PMX_PWM0_PL_60_VAL,
2058 },
2059};
2060
2061static struct spear_muxreg pwm0_1_pin_88_89_muxreg[] = {
2062 {
2063 .reg = IP_SEL_PAD_80_89_REG,
2064 .mask = PMX_PL_88_89_MASK,
2065 .val = PMX_PWM0_1_PL_88_89_VAL,
2066 },
2067};
2068
2069static struct spear_modemux pwm0_1_pin_8_9_modemux[] = {
2070 {
2071 .modes = EXTENDED_MODE,
2072 .muxregs = pwm0_1_pin_8_9_muxreg,
2073 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_8_9_muxreg),
2074 },
2075};
2076
2077static struct spear_modemux pwm0_1_pin_14_15_modemux[] = {
2078 {
2079 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
2080 .muxregs = pwm0_1_autoexpsmallpri_muxreg,
2081 .nmuxregs = ARRAY_SIZE(pwm0_1_autoexpsmallpri_muxreg),
2082 }, {
2083 .modes = EXTENDED_MODE,
2084 .muxregs = pwm0_1_pin_14_15_muxreg,
2085 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_14_15_muxreg),
2086 },
2087};
2088
2089static struct spear_modemux pwm0_1_pin_30_31_modemux[] = {
2090 {
2091 .modes = EXTENDED_MODE,
2092 .muxregs = pwm0_1_pin_30_31_muxreg,
2093 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_30_31_muxreg),
2094 },
2095};
2096
2097static struct spear_modemux pwm0_1_pin_37_38_modemux[] = {
2098 {
2099 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
2100 .muxregs = pwm0_1_net_muxreg,
2101 .nmuxregs = ARRAY_SIZE(pwm0_1_net_muxreg),
2102 }, {
2103 .modes = EXTENDED_MODE,
2104 .muxregs = pwm0_1_pin_37_38_muxreg,
2105 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_37_38_muxreg),
2106 },
2107};
2108
2109static struct spear_modemux pwm0_1_pin_42_43_modemux[] = {
2110 {
2111 .modes = EXTENDED_MODE,
2112 .muxregs = pwm0_1_pin_42_43_muxreg,
2113 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_42_43_muxreg),
2114 },
2115};
2116
2117static struct spear_modemux pwm0_1_pin_59_60_modemux[] = {
2118 {
2119 .modes = EXTENDED_MODE,
2120 .muxregs = pwm0_1_pin_59_60_muxreg,
2121 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_59_60_muxreg),
2122 },
2123};
2124
2125static struct spear_modemux pwm0_1_pin_88_89_modemux[] = {
2126 {
2127 .modes = EXTENDED_MODE,
2128 .muxregs = pwm0_1_pin_88_89_muxreg,
2129 .nmuxregs = ARRAY_SIZE(pwm0_1_pin_88_89_muxreg),
2130 },
2131};
2132
2133static struct spear_pingroup pwm0_1_pingroup[] = {
2134 {
2135 .name = "pwm0_1_pin_8_9_grp",
2136 .pins = pwm0_1_pins[0],
2137 .npins = ARRAY_SIZE(pwm0_1_pins[0]),
2138 .modemuxs = pwm0_1_pin_8_9_modemux,
2139 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_8_9_modemux),
2140 }, {
2141 .name = "pwm0_1_pin_14_15_grp",
2142 .pins = pwm0_1_pins[1],
2143 .npins = ARRAY_SIZE(pwm0_1_pins[1]),
2144 .modemuxs = pwm0_1_pin_14_15_modemux,
2145 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_14_15_modemux),
2146 }, {
2147 .name = "pwm0_1_pin_30_31_grp",
2148 .pins = pwm0_1_pins[2],
2149 .npins = ARRAY_SIZE(pwm0_1_pins[2]),
2150 .modemuxs = pwm0_1_pin_30_31_modemux,
2151 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_30_31_modemux),
2152 }, {
2153 .name = "pwm0_1_pin_37_38_grp",
2154 .pins = pwm0_1_pins[3],
2155 .npins = ARRAY_SIZE(pwm0_1_pins[3]),
2156 .modemuxs = pwm0_1_pin_37_38_modemux,
2157 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_37_38_modemux),
2158 }, {
2159 .name = "pwm0_1_pin_42_43_grp",
2160 .pins = pwm0_1_pins[4],
2161 .npins = ARRAY_SIZE(pwm0_1_pins[4]),
2162 .modemuxs = pwm0_1_pin_42_43_modemux,
2163 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_42_43_modemux),
2164 }, {
2165 .name = "pwm0_1_pin_59_60_grp",
2166 .pins = pwm0_1_pins[5],
2167 .npins = ARRAY_SIZE(pwm0_1_pins[5]),
2168 .modemuxs = pwm0_1_pin_59_60_modemux,
2169 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_59_60_modemux),
2170 }, {
2171 .name = "pwm0_1_pin_88_89_grp",
2172 .pins = pwm0_1_pins[6],
2173 .npins = ARRAY_SIZE(pwm0_1_pins[6]),
2174 .modemuxs = pwm0_1_pin_88_89_modemux,
2175 .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_88_89_modemux),
2176 },
2177};
2178
2179static const char *const pwm0_1_grps[] = { "pwm0_1_pin_8_9_grp",
2180 "pwm0_1_pin_14_15_grp", "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp",
2181 "pwm0_1_pin_42_43_grp", "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp"
2182};
2183
2184static struct spear_function pwm0_1_function = {
2185 .name = "pwm0_1",
2186 .groups = pwm0_1_grps,
2187 .ngroups = ARRAY_SIZE(pwm0_1_grps),
2188};
2189
2190/* Pad multiplexing for PWM2 device */
2191static const unsigned pwm2_pins[][1] = { { 7 }, { 13 }, { 29 }, { 34 }, { 41 },
2192 { 58 }, { 87 } };
2193static struct spear_muxreg pwm2_net_muxreg[] = {
2194 {
2195 .reg = PMX_CONFIG_REG,
2196 .mask = PMX_SSP_CS_MASK,
2197 .val = 0,
2198 },
2199};
2200
2201static struct spear_muxreg pwm2_pin_7_muxreg[] = {
2202 {
2203 .reg = IP_SEL_PAD_0_9_REG,
2204 .mask = PMX_PL_7_MASK,
2205 .val = PMX_PWM_2_PL_7_VAL,
2206 },
2207};
2208
2209static struct spear_muxreg pwm2_autoexpsmallpri_muxreg[] = {
2210 {
2211 .reg = PMX_CONFIG_REG,
2212 .mask = PMX_MII_MASK,
2213 .val = 0,
2214 },
2215};
2216
2217static struct spear_muxreg pwm2_pin_13_muxreg[] = {
2218 {
2219 .reg = IP_SEL_PAD_10_19_REG,
2220 .mask = PMX_PL_13_MASK,
2221 .val = PMX_PWM2_PL_13_VAL,
2222 },
2223};
2224
2225static struct spear_muxreg pwm2_pin_29_muxreg[] = {
2226 {
2227 .reg = PMX_CONFIG_REG,
2228 .mask = PMX_GPIO_PIN1_MASK,
2229 .val = 0,
2230 }, {
2231 .reg = IP_SEL_PAD_20_29_REG,
2232 .mask = PMX_PL_29_MASK,
2233 .val = PMX_PWM_2_PL_29_VAL,
2234 },
2235};
2236
2237static struct spear_muxreg pwm2_pin_34_muxreg[] = {
2238 {
2239 .reg = PMX_CONFIG_REG,
2240 .mask = PMX_SSP_CS_MASK,
2241 .val = 0,
2242 }, {
2243 .reg = IP_SEL_PAD_30_39_REG,
2244 .mask = PMX_PL_34_MASK,
2245 .val = PMX_PWM2_PL_34_VAL,
2246 },
2247};
2248
2249static struct spear_muxreg pwm2_pin_41_muxreg[] = {
2250 {
2251 .reg = PMX_CONFIG_REG,
2252 .mask = PMX_UART0_MODEM_MASK,
2253 .val = 0,
2254 }, {
2255 .reg = IP_SEL_PAD_40_49_REG,
2256 .mask = PMX_PL_41_MASK,
2257 .val = PMX_PWM2_PL_41_VAL,
2258 },
2259};
2260
2261static struct spear_muxreg pwm2_pin_58_muxreg[] = {
2262 {
2263 .reg = IP_SEL_PAD_50_59_REG,
2264 .mask = PMX_PL_58_MASK,
2265 .val = PMX_PWM2_PL_58_VAL,
2266 },
2267};
2268
2269static struct spear_muxreg pwm2_pin_87_muxreg[] = {
2270 {
2271 .reg = IP_SEL_PAD_80_89_REG,
2272 .mask = PMX_PL_87_MASK,
2273 .val = PMX_PWM2_PL_87_VAL,
2274 },
2275};
2276
2277static struct spear_modemux pwm2_pin_7_modemux[] = {
2278 {
2279 .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE,
2280 .muxregs = pwm2_net_muxreg,
2281 .nmuxregs = ARRAY_SIZE(pwm2_net_muxreg),
2282 }, {
2283 .modes = EXTENDED_MODE,
2284 .muxregs = pwm2_pin_7_muxreg,
2285 .nmuxregs = ARRAY_SIZE(pwm2_pin_7_muxreg),
2286 },
2287};
2288static struct spear_modemux pwm2_pin_13_modemux[] = {
2289 {
2290 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE,
2291 .muxregs = pwm2_autoexpsmallpri_muxreg,
2292 .nmuxregs = ARRAY_SIZE(pwm2_autoexpsmallpri_muxreg),
2293 }, {
2294 .modes = EXTENDED_MODE,
2295 .muxregs = pwm2_pin_13_muxreg,
2296 .nmuxregs = ARRAY_SIZE(pwm2_pin_13_muxreg),
2297 },
2298};
2299static struct spear_modemux pwm2_pin_29_modemux[] = {
2300 {
2301 .modes = EXTENDED_MODE,
2302 .muxregs = pwm2_pin_29_muxreg,
2303 .nmuxregs = ARRAY_SIZE(pwm2_pin_29_muxreg),
2304 },
2305};
2306static struct spear_modemux pwm2_pin_34_modemux[] = {
2307 {
2308 .modes = EXTENDED_MODE,
2309 .muxregs = pwm2_pin_34_muxreg,
2310 .nmuxregs = ARRAY_SIZE(pwm2_pin_34_muxreg),
2311 },
2312};
2313
2314static struct spear_modemux pwm2_pin_41_modemux[] = {
2315 {
2316 .modes = EXTENDED_MODE,
2317 .muxregs = pwm2_pin_41_muxreg,
2318 .nmuxregs = ARRAY_SIZE(pwm2_pin_41_muxreg),
2319 },
2320};
2321
2322static struct spear_modemux pwm2_pin_58_modemux[] = {
2323 {
2324 .modes = EXTENDED_MODE,
2325 .muxregs = pwm2_pin_58_muxreg,
2326 .nmuxregs = ARRAY_SIZE(pwm2_pin_58_muxreg),
2327 },
2328};
2329
2330static struct spear_modemux pwm2_pin_87_modemux[] = {
2331 {
2332 .modes = EXTENDED_MODE,
2333 .muxregs = pwm2_pin_87_muxreg,
2334 .nmuxregs = ARRAY_SIZE(pwm2_pin_87_muxreg),
2335 },
2336};
2337
2338static struct spear_pingroup pwm2_pingroup[] = {
2339 {
2340 .name = "pwm2_pin_7_grp",
2341 .pins = pwm2_pins[0],
2342 .npins = ARRAY_SIZE(pwm2_pins[0]),
2343 .modemuxs = pwm2_pin_7_modemux,
2344 .nmodemuxs = ARRAY_SIZE(pwm2_pin_7_modemux),
2345 }, {
2346 .name = "pwm2_pin_13_grp",
2347 .pins = pwm2_pins[1],
2348 .npins = ARRAY_SIZE(pwm2_pins[1]),
2349 .modemuxs = pwm2_pin_13_modemux,
2350 .nmodemuxs = ARRAY_SIZE(pwm2_pin_13_modemux),
2351 }, {
2352 .name = "pwm2_pin_29_grp",
2353 .pins = pwm2_pins[2],
2354 .npins = ARRAY_SIZE(pwm2_pins[2]),
2355 .modemuxs = pwm2_pin_29_modemux,
2356 .nmodemuxs = ARRAY_SIZE(pwm2_pin_29_modemux),
2357 }, {
2358 .name = "pwm2_pin_34_grp",
2359 .pins = pwm2_pins[3],
2360 .npins = ARRAY_SIZE(pwm2_pins[3]),
2361 .modemuxs = pwm2_pin_34_modemux,
2362 .nmodemuxs = ARRAY_SIZE(pwm2_pin_34_modemux),
2363 }, {
2364 .name = "pwm2_pin_41_grp",
2365 .pins = pwm2_pins[4],
2366 .npins = ARRAY_SIZE(pwm2_pins[4]),
2367 .modemuxs = pwm2_pin_41_modemux,
2368 .nmodemuxs = ARRAY_SIZE(pwm2_pin_41_modemux),
2369 }, {
2370 .name = "pwm2_pin_58_grp",
2371 .pins = pwm2_pins[5],
2372 .npins = ARRAY_SIZE(pwm2_pins[5]),
2373 .modemuxs = pwm2_pin_58_modemux,
2374 .nmodemuxs = ARRAY_SIZE(pwm2_pin_58_modemux),
2375 }, {
2376 .name = "pwm2_pin_87_grp",
2377 .pins = pwm2_pins[6],
2378 .npins = ARRAY_SIZE(pwm2_pins[6]),
2379 .modemuxs = pwm2_pin_87_modemux,
2380 .nmodemuxs = ARRAY_SIZE(pwm2_pin_87_modemux),
2381 },
2382};
2383
2384static const char *const pwm2_grps[] = { "pwm2_pin_7_grp", "pwm2_pin_13_grp",
2385 "pwm2_pin_29_grp", "pwm2_pin_34_grp", "pwm2_pin_41_grp",
2386 "pwm2_pin_58_grp", "pwm2_pin_87_grp" };
2387static struct spear_function pwm2_function = {
2388 .name = "pwm2",
2389 .groups = pwm2_grps,
2390 .ngroups = ARRAY_SIZE(pwm2_grps),
2391};
2392
2393/* Pad multiplexing for PWM3 device */
2394static const unsigned pwm3_pins[][1] = { { 6 }, { 12 }, { 28 }, { 40 }, { 57 },
2395 { 86 } };
2396static struct spear_muxreg pwm3_pin_6_muxreg[] = {
2397 {
2398 .reg = PMX_CONFIG_REG,
2399 .mask = PMX_SSP_MASK,
2400 .val = 0,
2401 }, {
2402 .reg = IP_SEL_PAD_0_9_REG,
2403 .mask = PMX_PL_6_MASK,
2404 .val = PMX_PWM_3_PL_6_VAL,
2405 },
2406};
2407
2408static struct spear_muxreg pwm3_muxreg[] = {
2409 {
2410 .reg = PMX_CONFIG_REG,
2411 .mask = PMX_MII_MASK,
2412 .val = 0,
2413 },
2414};
2415
2416static struct spear_muxreg pwm3_pin_12_muxreg[] = {
2417 {
2418 .reg = IP_SEL_PAD_10_19_REG,
2419 .mask = PMX_PL_12_MASK,
2420 .val = PMX_PWM3_PL_12_VAL,
2421 },
2422};
2423
2424static struct spear_muxreg pwm3_pin_28_muxreg[] = {
2425 {
2426 .reg = PMX_CONFIG_REG,
2427 .mask = PMX_GPIO_PIN0_MASK,
2428 .val = 0,
2429 }, {
2430 .reg = IP_SEL_PAD_20_29_REG,
2431 .mask = PMX_PL_28_MASK,
2432 .val = PMX_PWM_3_PL_28_VAL,
2433 },
2434};
2435
2436static struct spear_muxreg pwm3_pin_40_muxreg[] = {
2437 {
2438 .reg = PMX_CONFIG_REG,
2439 .mask = PMX_UART0_MODEM_MASK,
2440 .val = 0,
2441 }, {
2442 .reg = IP_SEL_PAD_40_49_REG,
2443 .mask = PMX_PL_40_MASK,
2444 .val = PMX_PWM3_PL_40_VAL,
2445 },
2446};
2447
2448static struct spear_muxreg pwm3_pin_57_muxreg[] = {
2449 {
2450 .reg = IP_SEL_PAD_50_59_REG,
2451 .mask = PMX_PL_57_MASK,
2452 .val = PMX_PWM3_PL_57_VAL,
2453 },
2454};
2455
2456static struct spear_muxreg pwm3_pin_86_muxreg[] = {
2457 {
2458 .reg = IP_SEL_PAD_80_89_REG,
2459 .mask = PMX_PL_86_MASK,
2460 .val = PMX_PWM3_PL_86_VAL,
2461 },
2462};
2463
2464static struct spear_modemux pwm3_pin_6_modemux[] = {
2465 {
2466 .modes = EXTENDED_MODE,
2467 .muxregs = pwm3_pin_6_muxreg,
2468 .nmuxregs = ARRAY_SIZE(pwm3_pin_6_muxreg),
2469 },
2470};
2471
2472static struct spear_modemux pwm3_pin_12_modemux[] = {
2473 {
2474 .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE |
2475 AUTO_NET_SMII_MODE | EXTENDED_MODE,
2476 .muxregs = pwm3_muxreg,
2477 .nmuxregs = ARRAY_SIZE(pwm3_muxreg),
2478 }, {
2479 .modes = EXTENDED_MODE,
2480 .muxregs = pwm3_pin_12_muxreg,
2481 .nmuxregs = ARRAY_SIZE(pwm3_pin_12_muxreg),
2482 },
2483};
2484
2485static struct spear_modemux pwm3_pin_28_modemux[] = {
2486 {
2487 .modes = EXTENDED_MODE,
2488 .muxregs = pwm3_pin_28_muxreg,
2489 .nmuxregs = ARRAY_SIZE(pwm3_pin_28_muxreg),
2490 },
2491};
2492
2493static struct spear_modemux pwm3_pin_40_modemux[] = {
2494 {
2495 .modes = EXTENDED_MODE,
2496 .muxregs = pwm3_pin_40_muxreg,
2497 .nmuxregs = ARRAY_SIZE(pwm3_pin_40_muxreg),
2498 },
2499};
2500
2501static struct spear_modemux pwm3_pin_57_modemux[] = {
2502 {
2503 .modes = EXTENDED_MODE,
2504 .muxregs = pwm3_pin_57_muxreg,
2505 .nmuxregs = ARRAY_SIZE(pwm3_pin_57_muxreg),
2506 },
2507};
2508
2509static struct spear_modemux pwm3_pin_86_modemux[] = {
2510 {
2511 .modes = EXTENDED_MODE,
2512 .muxregs = pwm3_pin_86_muxreg,
2513 .nmuxregs = ARRAY_SIZE(pwm3_pin_86_muxreg),
2514 },
2515};
2516
2517static struct spear_pingroup pwm3_pingroup[] = {
2518 {
2519 .name = "pwm3_pin_6_grp",
2520 .pins = pwm3_pins[0],
2521 .npins = ARRAY_SIZE(pwm3_pins[0]),
2522 .modemuxs = pwm3_pin_6_modemux,
2523 .nmodemuxs = ARRAY_SIZE(pwm3_pin_6_modemux),
2524 }, {
2525 .name = "pwm3_pin_12_grp",
2526 .pins = pwm3_pins[1],
2527 .npins = ARRAY_SIZE(pwm3_pins[1]),
2528 .modemuxs = pwm3_pin_12_modemux,
2529 .nmodemuxs = ARRAY_SIZE(pwm3_pin_12_modemux),
2530 }, {
2531 .name = "pwm3_pin_28_grp",
2532 .pins = pwm3_pins[2],
2533 .npins = ARRAY_SIZE(pwm3_pins[2]),
2534 .modemuxs = pwm3_pin_28_modemux,
2535 .nmodemuxs = ARRAY_SIZE(pwm3_pin_28_modemux),
2536 }, {
2537 .name = "pwm3_pin_40_grp",
2538 .pins = pwm3_pins[3],
2539 .npins = ARRAY_SIZE(pwm3_pins[3]),
2540 .modemuxs = pwm3_pin_40_modemux,
2541 .nmodemuxs = ARRAY_SIZE(pwm3_pin_40_modemux),
2542 }, {
2543 .name = "pwm3_pin_57_grp",
2544 .pins = pwm3_pins[4],
2545 .npins = ARRAY_SIZE(pwm3_pins[4]),
2546 .modemuxs = pwm3_pin_57_modemux,
2547 .nmodemuxs = ARRAY_SIZE(pwm3_pin_57_modemux),
2548 }, {
2549 .name = "pwm3_pin_86_grp",
2550 .pins = pwm3_pins[5],
2551 .npins = ARRAY_SIZE(pwm3_pins[5]),
2552 .modemuxs = pwm3_pin_86_modemux,
2553 .nmodemuxs = ARRAY_SIZE(pwm3_pin_86_modemux),
2554 },
2555};
2556
2557static const char *const pwm3_grps[] = { "pwm3_pin_6_grp", "pwm3_pin_12_grp",
2558 "pwm3_pin_28_grp", "pwm3_pin_40_grp", "pwm3_pin_57_grp",
2559 "pwm3_pin_86_grp" };
2560static struct spear_function pwm3_function = {
2561 .name = "pwm3",
2562 .groups = pwm3_grps,
2563 .ngroups = ARRAY_SIZE(pwm3_grps),
2564};
2565
2566/* Pad multiplexing for SSP1 device */
2567static const unsigned ssp1_pins[][2] = { { 17, 20 }, { 36, 39 }, { 48, 51 },
2568 { 65, 68 }, { 94, 97 } };
2569static struct spear_muxreg ssp1_muxreg[] = {
2570 {
2571 .reg = PMX_CONFIG_REG,
2572 .mask = PMX_MII_MASK,
2573 .val = 0,
2574 },
2575};
2576
2577static struct spear_muxreg ssp1_ext_17_20_muxreg[] = {
2578 {
2579 .reg = IP_SEL_PAD_10_19_REG,
2580 .mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK,
2581 .val = PMX_SSP1_PL_17_18_19_20_VAL,
2582 }, {
2583 .reg = IP_SEL_PAD_20_29_REG,
2584 .mask = PMX_PL_20_MASK,
2585 .val = PMX_SSP1_PL_17_18_19_20_VAL,
2586 }, {
2587 .reg = IP_SEL_MIX_PAD_REG,
2588 .mask = PMX_SSP1_PORT_SEL_MASK,
2589 .val = PMX_SSP1_PORT_17_TO_20_VAL,
2590 },
2591};
2592
2593static struct spear_muxreg ssp1_ext_36_39_muxreg[] = {
2594 {
2595 .reg = PMX_CONFIG_REG,
2596 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
2597 .val = 0,
2598 }, {
2599 .reg = IP_SEL_PAD_30_39_REG,
2600 .mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK,
2601 .val = PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL |
2602 PMX_SSP1_PL_39_VAL,
2603 }, {
2604 .reg = IP_SEL_MIX_PAD_REG,
2605 .mask = PMX_SSP1_PORT_SEL_MASK,
2606 .val = PMX_SSP1_PORT_36_TO_39_VAL,
2607 },
2608};
2609
2610static struct spear_muxreg ssp1_ext_48_51_muxreg[] = {
2611 {
2612 .reg = PMX_CONFIG_REG,
2613 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
2614 .val = 0,
2615 }, {
2616 .reg = IP_SEL_PAD_40_49_REG,
2617 .mask = PMX_PL_48_49_MASK,
2618 .val = PMX_SSP1_PL_48_49_VAL,
2619 }, {
2620 .reg = IP_SEL_PAD_50_59_REG,
2621 .mask = PMX_PL_50_51_MASK,
2622 .val = PMX_SSP1_PL_50_51_VAL,
2623 }, {
2624 .reg = IP_SEL_MIX_PAD_REG,
2625 .mask = PMX_SSP1_PORT_SEL_MASK,
2626 .val = PMX_SSP1_PORT_48_TO_51_VAL,
2627 },
2628};
2629
2630static struct spear_muxreg ssp1_ext_65_68_muxreg[] = {
2631 {
2632 .reg = IP_SEL_PAD_60_69_REG,
2633 .mask = PMX_PL_65_TO_68_MASK,
2634 .val = PMX_SSP1_PL_65_TO_68_VAL,
2635 }, {
2636 .reg = IP_SEL_MIX_PAD_REG,
2637 .mask = PMX_SSP1_PORT_SEL_MASK,
2638 .val = PMX_SSP1_PORT_65_TO_68_VAL,
2639 },
2640};
2641
2642static struct spear_muxreg ssp1_ext_94_97_muxreg[] = {
2643 {
2644 .reg = IP_SEL_PAD_90_99_REG,
2645 .mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
2646 .val = PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL,
2647 }, {
2648 .reg = IP_SEL_MIX_PAD_REG,
2649 .mask = PMX_SSP1_PORT_SEL_MASK,
2650 .val = PMX_SSP1_PORT_94_TO_97_VAL,
2651 },
2652};
2653
2654static struct spear_modemux ssp1_17_20_modemux[] = {
2655 {
2656 .modes = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE |
2657 EXTENDED_MODE,
2658 .muxregs = ssp1_muxreg,
2659 .nmuxregs = ARRAY_SIZE(ssp1_muxreg),
2660 }, {
2661 .modes = EXTENDED_MODE,
2662 .muxregs = ssp1_ext_17_20_muxreg,
2663 .nmuxregs = ARRAY_SIZE(ssp1_ext_17_20_muxreg),
2664 },
2665};
2666
2667static struct spear_modemux ssp1_36_39_modemux[] = {
2668 {
2669 .modes = EXTENDED_MODE,
2670 .muxregs = ssp1_ext_36_39_muxreg,
2671 .nmuxregs = ARRAY_SIZE(ssp1_ext_36_39_muxreg),
2672 },
2673};
2674
2675static struct spear_modemux ssp1_48_51_modemux[] = {
2676 {
2677 .modes = EXTENDED_MODE,
2678 .muxregs = ssp1_ext_48_51_muxreg,
2679 .nmuxregs = ARRAY_SIZE(ssp1_ext_48_51_muxreg),
2680 },
2681};
2682static struct spear_modemux ssp1_65_68_modemux[] = {
2683 {
2684 .modes = EXTENDED_MODE,
2685 .muxregs = ssp1_ext_65_68_muxreg,
2686 .nmuxregs = ARRAY_SIZE(ssp1_ext_65_68_muxreg),
2687 },
2688};
2689
2690static struct spear_modemux ssp1_94_97_modemux[] = {
2691 {
2692 .modes = EXTENDED_MODE,
2693 .muxregs = ssp1_ext_94_97_muxreg,
2694 .nmuxregs = ARRAY_SIZE(ssp1_ext_94_97_muxreg),
2695 },
2696};
2697
2698static struct spear_pingroup ssp1_pingroup[] = {
2699 {
2700 .name = "ssp1_17_20_grp",
2701 .pins = ssp1_pins[0],
2702 .npins = ARRAY_SIZE(ssp1_pins[0]),
2703 .modemuxs = ssp1_17_20_modemux,
2704 .nmodemuxs = ARRAY_SIZE(ssp1_17_20_modemux),
2705 }, {
2706 .name = "ssp1_36_39_grp",
2707 .pins = ssp1_pins[1],
2708 .npins = ARRAY_SIZE(ssp1_pins[1]),
2709 .modemuxs = ssp1_36_39_modemux,
2710 .nmodemuxs = ARRAY_SIZE(ssp1_36_39_modemux),
2711 }, {
2712 .name = "ssp1_48_51_grp",
2713 .pins = ssp1_pins[2],
2714 .npins = ARRAY_SIZE(ssp1_pins[2]),
2715 .modemuxs = ssp1_48_51_modemux,
2716 .nmodemuxs = ARRAY_SIZE(ssp1_48_51_modemux),
2717 }, {
2718 .name = "ssp1_65_68_grp",
2719 .pins = ssp1_pins[3],
2720 .npins = ARRAY_SIZE(ssp1_pins[3]),
2721 .modemuxs = ssp1_65_68_modemux,
2722 .nmodemuxs = ARRAY_SIZE(ssp1_65_68_modemux),
2723 }, {
2724 .name = "ssp1_94_97_grp",
2725 .pins = ssp1_pins[4],
2726 .npins = ARRAY_SIZE(ssp1_pins[4]),
2727 .modemuxs = ssp1_94_97_modemux,
2728 .nmodemuxs = ARRAY_SIZE(ssp1_94_97_modemux),
2729 },
2730};
2731
2732static const char *const ssp1_grps[] = { "ssp1_17_20_grp", "ssp1_36_39_grp",
2733 "ssp1_48_51_grp", "ssp1_65_68_grp", "ssp1_94_97_grp"
2734};
2735static struct spear_function ssp1_function = {
2736 .name = "ssp1",
2737 .groups = ssp1_grps,
2738 .ngroups = ARRAY_SIZE(ssp1_grps),
2739};
2740
2741/* Pad multiplexing for SSP2 device */
2742static const unsigned ssp2_pins[][2] = { { 13, 16 }, { 32, 35 }, { 44, 47 },
2743 { 61, 64 }, { 90, 93 } };
2744static struct spear_muxreg ssp2_muxreg[] = {
2745 {
2746 .reg = PMX_CONFIG_REG,
2747 .mask = PMX_MII_MASK,
2748 .val = 0,
2749 },
2750};
2751
2752static struct spear_muxreg ssp2_ext_13_16_muxreg[] = {
2753 {
2754 .reg = IP_SEL_PAD_10_19_REG,
2755 .mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK,
2756 .val = PMX_SSP2_PL_13_14_15_16_VAL,
2757 }, {
2758 .reg = IP_SEL_MIX_PAD_REG,
2759 .mask = PMX_SSP2_PORT_SEL_MASK,
2760 .val = PMX_SSP2_PORT_13_TO_16_VAL,
2761 },
2762};
2763
2764static struct spear_muxreg ssp2_ext_32_35_muxreg[] = {
2765 {
2766 .reg = PMX_CONFIG_REG,
2767 .mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK |
2768 PMX_GPIO_PIN5_MASK,
2769 .val = 0,
2770 }, {
2771 .reg = IP_SEL_PAD_30_39_REG,
2772 .mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK,
2773 .val = PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL |
2774 PMX_SSP2_PL_35_VAL,
2775 }, {
2776 .reg = IP_SEL_MIX_PAD_REG,
2777 .mask = PMX_SSP2_PORT_SEL_MASK,
2778 .val = PMX_SSP2_PORT_32_TO_35_VAL,
2779 },
2780};
2781
2782static struct spear_muxreg ssp2_ext_44_47_muxreg[] = {
2783 {
2784 .reg = PMX_CONFIG_REG,
2785 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
2786 .val = 0,
2787 }, {
2788 .reg = IP_SEL_PAD_40_49_REG,
2789 .mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK,
2790 .val = PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL,
2791 }, {
2792 .reg = IP_SEL_MIX_PAD_REG,
2793 .mask = PMX_SSP2_PORT_SEL_MASK,
2794 .val = PMX_SSP2_PORT_44_TO_47_VAL,
2795 },
2796};
2797
2798static struct spear_muxreg ssp2_ext_61_64_muxreg[] = {
2799 {
2800 .reg = IP_SEL_PAD_60_69_REG,
2801 .mask = PMX_PL_61_TO_64_MASK,
2802 .val = PMX_SSP2_PL_61_TO_64_VAL,
2803 }, {
2804 .reg = IP_SEL_MIX_PAD_REG,
2805 .mask = PMX_SSP2_PORT_SEL_MASK,
2806 .val = PMX_SSP2_PORT_61_TO_64_VAL,
2807 },
2808};
2809
2810static struct spear_muxreg ssp2_ext_90_93_muxreg[] = {
2811 {
2812 .reg = IP_SEL_PAD_90_99_REG,
2813 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK,
2814 .val = PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL,
2815 }, {
2816 .reg = IP_SEL_MIX_PAD_REG,
2817 .mask = PMX_SSP2_PORT_SEL_MASK,
2818 .val = PMX_SSP2_PORT_90_TO_93_VAL,
2819 },
2820};
2821
2822static struct spear_modemux ssp2_13_16_modemux[] = {
2823 {
2824 .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE,
2825 .muxregs = ssp2_muxreg,
2826 .nmuxregs = ARRAY_SIZE(ssp2_muxreg),
2827 }, {
2828 .modes = EXTENDED_MODE,
2829 .muxregs = ssp2_ext_13_16_muxreg,
2830 .nmuxregs = ARRAY_SIZE(ssp2_ext_13_16_muxreg),
2831 },
2832};
2833
2834static struct spear_modemux ssp2_32_35_modemux[] = {
2835 {
2836 .modes = EXTENDED_MODE,
2837 .muxregs = ssp2_ext_32_35_muxreg,
2838 .nmuxregs = ARRAY_SIZE(ssp2_ext_32_35_muxreg),
2839 },
2840};
2841
2842static struct spear_modemux ssp2_44_47_modemux[] = {
2843 {
2844 .modes = EXTENDED_MODE,
2845 .muxregs = ssp2_ext_44_47_muxreg,
2846 .nmuxregs = ARRAY_SIZE(ssp2_ext_44_47_muxreg),
2847 },
2848};
2849
2850static struct spear_modemux ssp2_61_64_modemux[] = {
2851 {
2852 .modes = EXTENDED_MODE,
2853 .muxregs = ssp2_ext_61_64_muxreg,
2854 .nmuxregs = ARRAY_SIZE(ssp2_ext_61_64_muxreg),
2855 },
2856};
2857
2858static struct spear_modemux ssp2_90_93_modemux[] = {
2859 {
2860 .modes = EXTENDED_MODE,
2861 .muxregs = ssp2_ext_90_93_muxreg,
2862 .nmuxregs = ARRAY_SIZE(ssp2_ext_90_93_muxreg),
2863 },
2864};
2865
2866static struct spear_pingroup ssp2_pingroup[] = {
2867 {
2868 .name = "ssp2_13_16_grp",
2869 .pins = ssp2_pins[0],
2870 .npins = ARRAY_SIZE(ssp2_pins[0]),
2871 .modemuxs = ssp2_13_16_modemux,
2872 .nmodemuxs = ARRAY_SIZE(ssp2_13_16_modemux),
2873 }, {
2874 .name = "ssp2_32_35_grp",
2875 .pins = ssp2_pins[1],
2876 .npins = ARRAY_SIZE(ssp2_pins[1]),
2877 .modemuxs = ssp2_32_35_modemux,
2878 .nmodemuxs = ARRAY_SIZE(ssp2_32_35_modemux),
2879 }, {
2880 .name = "ssp2_44_47_grp",
2881 .pins = ssp2_pins[2],
2882 .npins = ARRAY_SIZE(ssp2_pins[2]),
2883 .modemuxs = ssp2_44_47_modemux,
2884 .nmodemuxs = ARRAY_SIZE(ssp2_44_47_modemux),
2885 }, {
2886 .name = "ssp2_61_64_grp",
2887 .pins = ssp2_pins[3],
2888 .npins = ARRAY_SIZE(ssp2_pins[3]),
2889 .modemuxs = ssp2_61_64_modemux,
2890 .nmodemuxs = ARRAY_SIZE(ssp2_61_64_modemux),
2891 }, {
2892 .name = "ssp2_90_93_grp",
2893 .pins = ssp2_pins[4],
2894 .npins = ARRAY_SIZE(ssp2_pins[4]),
2895 .modemuxs = ssp2_90_93_modemux,
2896 .nmodemuxs = ARRAY_SIZE(ssp2_90_93_modemux),
2897 },
2898};
2899
2900static const char *const ssp2_grps[] = { "ssp2_13_16_grp", "ssp2_32_35_grp",
2901 "ssp2_44_47_grp", "ssp2_61_64_grp", "ssp2_90_93_grp" };
2902static struct spear_function ssp2_function = {
2903 .name = "ssp2",
2904 .groups = ssp2_grps,
2905 .ngroups = ARRAY_SIZE(ssp2_grps),
2906};
2907
2908/* Pad multiplexing for cadence mii2 as mii device */
2909static const unsigned mii2_pins[] = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
2910 90, 91, 92, 93, 94, 95, 96, 97 };
2911static struct spear_muxreg mii2_muxreg[] = {
2912 {
2913 .reg = IP_SEL_PAD_80_89_REG,
2914 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
2915 PMX_PL_88_89_MASK,
2916 .val = PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL |
2917 PMX_MII2_PL_88_89_VAL,
2918 }, {
2919 .reg = IP_SEL_PAD_90_99_REG,
2920 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
2921 PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
2922 .val = PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL |
2923 PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL,
2924 }, {
2925 .reg = EXT_CTRL_REG,
2926 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
2927 (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
2928 MII_MDIO_MASK,
2929 .val = (MAC_MODE_MII << MAC2_MODE_SHIFT) |
2930 (MAC_MODE_MII << MAC1_MODE_SHIFT) |
2931 MII_MDIO_81_VAL,
2932 },
2933};
2934
2935static struct spear_modemux mii2_modemux[] = {
2936 {
2937 .modes = EXTENDED_MODE,
2938 .muxregs = mii2_muxreg,
2939 .nmuxregs = ARRAY_SIZE(mii2_muxreg),
2940 },
2941};
2942
2943static struct spear_pingroup mii2_pingroup = {
2944 .name = "mii2_grp",
2945 .pins = mii2_pins,
2946 .npins = ARRAY_SIZE(mii2_pins),
2947 .modemuxs = mii2_modemux,
2948 .nmodemuxs = ARRAY_SIZE(mii2_modemux),
2949};
2950
2951static const char *const mii2_grps[] = { "mii2_grp" };
2952static struct spear_function mii2_function = {
2953 .name = "mii2",
2954 .groups = mii2_grps,
2955 .ngroups = ARRAY_SIZE(mii2_grps),
2956};
2957
2958/* Pad multiplexing for cadence mii 1_2 as smii or rmii device */
2959static const unsigned smii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20,
2960 21, 22, 23, 24, 25, 26, 27 };
2961static const unsigned rmii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 };
2962static struct spear_muxreg mii0_1_muxreg[] = {
2963 {
2964 .reg = PMX_CONFIG_REG,
2965 .mask = PMX_MII_MASK,
2966 .val = 0,
2967 },
2968};
2969
2970static struct spear_muxreg smii0_1_ext_muxreg[] = {
2971 {
2972 .reg = IP_SEL_PAD_10_19_REG,
2973 .mask = PMX_PL_10_11_MASK,
2974 .val = PMX_SMII_PL_10_11_VAL,
2975 }, {
2976 .reg = IP_SEL_PAD_20_29_REG,
2977 .mask = PMX_PL_21_TO_27_MASK,
2978 .val = PMX_SMII_PL_21_TO_27_VAL,
2979 }, {
2980 .reg = EXT_CTRL_REG,
2981 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
2982 (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
2983 MII_MDIO_MASK,
2984 .val = (MAC_MODE_SMII << MAC2_MODE_SHIFT)
2985 | (MAC_MODE_SMII << MAC1_MODE_SHIFT)
2986 | MII_MDIO_10_11_VAL,
2987 },
2988};
2989
2990static struct spear_muxreg rmii0_1_ext_muxreg[] = {
2991 {
2992 .reg = IP_SEL_PAD_10_19_REG,
2993 .mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK |
2994 PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK,
2995 .val = PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL |
2996 PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL |
2997 PMX_RMII_PL_19_VAL,
2998 }, {
2999 .reg = IP_SEL_PAD_20_29_REG,
3000 .mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK,
3001 .val = PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL,
3002 }, {
3003 .reg = EXT_CTRL_REG,
3004 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
3005 (MAC_MODE_MASK << MAC1_MODE_SHIFT) |
3006 MII_MDIO_MASK,
3007 .val = (MAC_MODE_RMII << MAC2_MODE_SHIFT)
3008 | (MAC_MODE_RMII << MAC1_MODE_SHIFT)
3009 | MII_MDIO_10_11_VAL,
3010 },
3011};
3012
3013static struct spear_modemux mii0_1_modemux[][2] = {
3014 {
3015 /* configure as smii */
3016 {
3017 .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
3018 SMALL_PRINTERS_MODE | EXTENDED_MODE,
3019 .muxregs = mii0_1_muxreg,
3020 .nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
3021 }, {
3022 .modes = EXTENDED_MODE,
3023 .muxregs = smii0_1_ext_muxreg,
3024 .nmuxregs = ARRAY_SIZE(smii0_1_ext_muxreg),
3025 },
3026 }, {
3027 /* configure as rmii */
3028 {
3029 .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE |
3030 SMALL_PRINTERS_MODE | EXTENDED_MODE,
3031 .muxregs = mii0_1_muxreg,
3032 .nmuxregs = ARRAY_SIZE(mii0_1_muxreg),
3033 }, {
3034 .modes = EXTENDED_MODE,
3035 .muxregs = rmii0_1_ext_muxreg,
3036 .nmuxregs = ARRAY_SIZE(rmii0_1_ext_muxreg),
3037 },
3038 },
3039};
3040
3041static struct spear_pingroup mii0_1_pingroup[] = {
3042 {
3043 .name = "smii0_1_grp",
3044 .pins = smii0_1_pins,
3045 .npins = ARRAY_SIZE(smii0_1_pins),
3046 .modemuxs = mii0_1_modemux[0],
3047 .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[0]),
3048 }, {
3049 .name = "rmii0_1_grp",
3050 .pins = rmii0_1_pins,
3051 .npins = ARRAY_SIZE(rmii0_1_pins),
3052 .modemuxs = mii0_1_modemux[1],
3053 .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[1]),
3054 },
3055};
3056
3057static const char *const mii0_1_grps[] = { "smii0_1_grp", "rmii0_1_grp" };
3058static struct spear_function mii0_1_function = {
3059 .name = "mii0_1",
3060 .groups = mii0_1_grps,
3061 .ngroups = ARRAY_SIZE(mii0_1_grps),
3062};
3063
3064/* Pad multiplexing for i2c1 device */
3065static const unsigned i2c1_pins[][2] = { { 8, 9 }, { 98, 99 } };
3066static struct spear_muxreg i2c1_ext_8_9_muxreg[] = {
3067 {
3068 .reg = PMX_CONFIG_REG,
3069 .mask = PMX_SSP_CS_MASK,
3070 .val = 0,
3071 }, {
3072 .reg = IP_SEL_PAD_0_9_REG,
3073 .mask = PMX_PL_8_9_MASK,
3074 .val = PMX_I2C1_PL_8_9_VAL,
3075 }, {
3076 .reg = IP_SEL_MIX_PAD_REG,
3077 .mask = PMX_I2C1_PORT_SEL_MASK,
3078 .val = PMX_I2C1_PORT_8_9_VAL,
3079 },
3080};
3081
3082static struct spear_muxreg i2c1_ext_98_99_muxreg[] = {
3083 {
3084 .reg = IP_SEL_PAD_90_99_REG,
3085 .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
3086 .val = PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL,
3087 }, {
3088 .reg = IP_SEL_MIX_PAD_REG,
3089 .mask = PMX_I2C1_PORT_SEL_MASK,
3090 .val = PMX_I2C1_PORT_98_99_VAL,
3091 },
3092};
3093
3094static struct spear_modemux i2c1_modemux[][1] = {
3095 {
3096 /* Select signals on pins 8-9 */
3097 {
3098 .modes = EXTENDED_MODE,
3099 .muxregs = i2c1_ext_8_9_muxreg,
3100 .nmuxregs = ARRAY_SIZE(i2c1_ext_8_9_muxreg),
3101 },
3102 }, {
3103 /* Select signals on pins 98-99 */
3104 {
3105 .modes = EXTENDED_MODE,
3106 .muxregs = i2c1_ext_98_99_muxreg,
3107 .nmuxregs = ARRAY_SIZE(i2c1_ext_98_99_muxreg),
3108 },
3109 },
3110};
3111
3112static struct spear_pingroup i2c1_pingroup[] = {
3113 {
3114 .name = "i2c1_8_9_grp",
3115 .pins = i2c1_pins[0],
3116 .npins = ARRAY_SIZE(i2c1_pins[0]),
3117 .modemuxs = i2c1_modemux[0],
3118 .nmodemuxs = ARRAY_SIZE(i2c1_modemux[0]),
3119 }, {
3120 .name = "i2c1_98_99_grp",
3121 .pins = i2c1_pins[1],
3122 .npins = ARRAY_SIZE(i2c1_pins[1]),
3123 .modemuxs = i2c1_modemux[1],
3124 .nmodemuxs = ARRAY_SIZE(i2c1_modemux[1]),
3125 },
3126};
3127
3128static const char *const i2c1_grps[] = { "i2c1_8_9_grp", "i2c1_98_99_grp" };
3129static struct spear_function i2c1_function = {
3130 .name = "i2c1",
3131 .groups = i2c1_grps,
3132 .ngroups = ARRAY_SIZE(i2c1_grps),
3133};
3134
3135/* Pad multiplexing for i2c2 device */
3136static const unsigned i2c2_pins[][2] = { { 0, 1 }, { 2, 3 }, { 19, 20 },
3137 { 75, 76 }, { 96, 97 } };
3138static struct spear_muxreg i2c2_ext_0_1_muxreg[] = {
3139 {
3140 .reg = PMX_CONFIG_REG,
3141 .mask = PMX_FIRDA_MASK,
3142 .val = 0,
3143 }, {
3144 .reg = IP_SEL_PAD_0_9_REG,
3145 .mask = PMX_PL_0_1_MASK,
3146 .val = PMX_I2C2_PL_0_1_VAL,
3147 }, {
3148 .reg = IP_SEL_MIX_PAD_REG,
3149 .mask = PMX_I2C2_PORT_SEL_MASK,
3150 .val = PMX_I2C2_PORT_0_1_VAL,
3151 },
3152};
3153
3154static struct spear_muxreg i2c2_ext_2_3_muxreg[] = {
3155 {
3156 .reg = PMX_CONFIG_REG,
3157 .mask = PMX_UART0_MASK,
3158 .val = 0,
3159 }, {
3160 .reg = IP_SEL_PAD_0_9_REG,
3161 .mask = PMX_PL_2_3_MASK,
3162 .val = PMX_I2C2_PL_2_3_VAL,
3163 }, {
3164 .reg = IP_SEL_MIX_PAD_REG,
3165 .mask = PMX_I2C2_PORT_SEL_MASK,
3166 .val = PMX_I2C2_PORT_2_3_VAL,
3167 },
3168};
3169
3170static struct spear_muxreg i2c2_ext_19_20_muxreg[] = {
3171 {
3172 .reg = PMX_CONFIG_REG,
3173 .mask = PMX_MII_MASK,
3174 .val = 0,
3175 }, {
3176 .reg = IP_SEL_PAD_10_19_REG,
3177 .mask = PMX_PL_19_MASK,
3178 .val = PMX_I2C2_PL_19_VAL,
3179 }, {
3180 .reg = IP_SEL_PAD_20_29_REG,
3181 .mask = PMX_PL_20_MASK,
3182 .val = PMX_I2C2_PL_20_VAL,
3183 }, {
3184 .reg = IP_SEL_MIX_PAD_REG,
3185 .mask = PMX_I2C2_PORT_SEL_MASK,
3186 .val = PMX_I2C2_PORT_19_20_VAL,
3187 },
3188};
3189
3190static struct spear_muxreg i2c2_ext_75_76_muxreg[] = {
3191 {
3192 .reg = IP_SEL_PAD_70_79_REG,
3193 .mask = PMX_PL_75_76_MASK,
3194 .val = PMX_I2C2_PL_75_76_VAL,
3195 }, {
3196 .reg = IP_SEL_MIX_PAD_REG,
3197 .mask = PMX_I2C2_PORT_SEL_MASK,
3198 .val = PMX_I2C2_PORT_75_76_VAL,
3199 },
3200};
3201
3202static struct spear_muxreg i2c2_ext_96_97_muxreg[] = {
3203 {
3204 .reg = IP_SEL_PAD_90_99_REG,
3205 .mask = PMX_PL_96_97_MASK,
3206 .val = PMX_I2C2_PL_96_97_VAL,
3207 }, {
3208 .reg = IP_SEL_MIX_PAD_REG,
3209 .mask = PMX_I2C2_PORT_SEL_MASK,
3210 .val = PMX_I2C2_PORT_96_97_VAL,
3211 },
3212};
3213
3214static struct spear_modemux i2c2_modemux[][1] = {
3215 {
3216 /* Select signals on pins 0_1 */
3217 {
3218 .modes = EXTENDED_MODE,
3219 .muxregs = i2c2_ext_0_1_muxreg,
3220 .nmuxregs = ARRAY_SIZE(i2c2_ext_0_1_muxreg),
3221 },
3222 }, {
3223 /* Select signals on pins 2_3 */
3224 {
3225 .modes = EXTENDED_MODE,
3226 .muxregs = i2c2_ext_2_3_muxreg,
3227 .nmuxregs = ARRAY_SIZE(i2c2_ext_2_3_muxreg),
3228 },
3229 }, {
3230 /* Select signals on pins 19_20 */
3231 {
3232 .modes = EXTENDED_MODE,
3233 .muxregs = i2c2_ext_19_20_muxreg,
3234 .nmuxregs = ARRAY_SIZE(i2c2_ext_19_20_muxreg),
3235 },
3236 }, {
3237 /* Select signals on pins 75_76 */
3238 {
3239 .modes = EXTENDED_MODE,
3240 .muxregs = i2c2_ext_75_76_muxreg,
3241 .nmuxregs = ARRAY_SIZE(i2c2_ext_75_76_muxreg),
3242 },
3243 }, {
3244 /* Select signals on pins 96_97 */
3245 {
3246 .modes = EXTENDED_MODE,
3247 .muxregs = i2c2_ext_96_97_muxreg,
3248 .nmuxregs = ARRAY_SIZE(i2c2_ext_96_97_muxreg),
3249 },
3250 },
3251};
3252
3253static struct spear_pingroup i2c2_pingroup[] = {
3254 {
3255 .name = "i2c2_0_1_grp",
3256 .pins = i2c2_pins[0],
3257 .npins = ARRAY_SIZE(i2c2_pins[0]),
3258 .modemuxs = i2c2_modemux[0],
3259 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[0]),
3260 }, {
3261 .name = "i2c2_2_3_grp",
3262 .pins = i2c2_pins[1],
3263 .npins = ARRAY_SIZE(i2c2_pins[1]),
3264 .modemuxs = i2c2_modemux[1],
3265 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[1]),
3266 }, {
3267 .name = "i2c2_19_20_grp",
3268 .pins = i2c2_pins[2],
3269 .npins = ARRAY_SIZE(i2c2_pins[2]),
3270 .modemuxs = i2c2_modemux[2],
3271 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[2]),
3272 }, {
3273 .name = "i2c2_75_76_grp",
3274 .pins = i2c2_pins[3],
3275 .npins = ARRAY_SIZE(i2c2_pins[3]),
3276 .modemuxs = i2c2_modemux[3],
3277 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[3]),
3278 }, {
3279 .name = "i2c2_96_97_grp",
3280 .pins = i2c2_pins[4],
3281 .npins = ARRAY_SIZE(i2c2_pins[4]),
3282 .modemuxs = i2c2_modemux[4],
3283 .nmodemuxs = ARRAY_SIZE(i2c2_modemux[4]),
3284 },
3285};
3286
3287static const char *const i2c2_grps[] = { "i2c2_0_1_grp", "i2c2_2_3_grp",
3288 "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" };
3289static struct spear_function i2c2_function = {
3290 .name = "i2c2",
3291 .groups = i2c2_grps,
3292 .ngroups = ARRAY_SIZE(i2c2_grps),
3293};
3294
3295/* pingroups */
3296static struct spear_pingroup *spear320_pingroups[] = {
3297 SPEAR3XX_COMMON_PINGROUPS,
3298 &clcd_pingroup,
3299 &emi_pingroup,
3300 &fsmc_8bit_pingroup,
3301 &fsmc_16bit_pingroup,
3302 &spp_pingroup,
3303 &sdhci_led_pingroup,
3304 &sdhci_pingroup[0],
3305 &sdhci_pingroup[1],
3306 &i2s_pingroup,
3307 &uart1_pingroup,
3308 &uart1_modem_pingroup[0],
3309 &uart1_modem_pingroup[1],
3310 &uart1_modem_pingroup[2],
3311 &uart1_modem_pingroup[3],
3312 &uart2_pingroup,
3313 &uart3_pingroup[0],
3314 &uart3_pingroup[1],
3315 &uart3_pingroup[2],
3316 &uart3_pingroup[3],
3317 &uart3_pingroup[4],
3318 &uart3_pingroup[5],
3319 &uart3_pingroup[6],
3320 &uart4_pingroup[0],
3321 &uart4_pingroup[1],
3322 &uart4_pingroup[2],
3323 &uart4_pingroup[3],
3324 &uart4_pingroup[4],
3325 &uart4_pingroup[5],
3326 &uart5_pingroup[0],
3327 &uart5_pingroup[1],
3328 &uart5_pingroup[2],
3329 &uart5_pingroup[3],
3330 &uart6_pingroup[0],
3331 &uart6_pingroup[1],
3332 &rs485_pingroup,
3333 &touchscreen_pingroup,
3334 &can0_pingroup,
3335 &can1_pingroup,
3336 &pwm0_1_pingroup[0],
3337 &pwm0_1_pingroup[1],
3338 &pwm0_1_pingroup[2],
3339 &pwm0_1_pingroup[3],
3340 &pwm0_1_pingroup[4],
3341 &pwm0_1_pingroup[5],
3342 &pwm0_1_pingroup[6],
3343 &pwm2_pingroup[0],
3344 &pwm2_pingroup[1],
3345 &pwm2_pingroup[2],
3346 &pwm2_pingroup[3],
3347 &pwm2_pingroup[4],
3348 &pwm2_pingroup[5],
3349 &pwm2_pingroup[6],
3350 &pwm3_pingroup[0],
3351 &pwm3_pingroup[1],
3352 &pwm3_pingroup[2],
3353 &pwm3_pingroup[3],
3354 &pwm3_pingroup[4],
3355 &pwm3_pingroup[5],
3356 &ssp1_pingroup[0],
3357 &ssp1_pingroup[1],
3358 &ssp1_pingroup[2],
3359 &ssp1_pingroup[3],
3360 &ssp1_pingroup[4],
3361 &ssp2_pingroup[0],
3362 &ssp2_pingroup[1],
3363 &ssp2_pingroup[2],
3364 &ssp2_pingroup[3],
3365 &ssp2_pingroup[4],
3366 &mii2_pingroup,
3367 &mii0_1_pingroup[0],
3368 &mii0_1_pingroup[1],
3369 &i2c1_pingroup[0],
3370 &i2c1_pingroup[1],
3371 &i2c2_pingroup[0],
3372 &i2c2_pingroup[1],
3373 &i2c2_pingroup[2],
3374 &i2c2_pingroup[3],
3375 &i2c2_pingroup[4],
3376};
3377
3378/* functions */
3379static struct spear_function *spear320_functions[] = {
3380 SPEAR3XX_COMMON_FUNCTIONS,
3381 &clcd_function,
3382 &emi_function,
3383 &fsmc_function,
3384 &spp_function,
3385 &sdhci_function,
3386 &i2s_function,
3387 &uart1_function,
3388 &uart1_modem_function,
3389 &uart2_function,
3390 &uart3_function,
3391 &uart4_function,
3392 &uart5_function,
3393 &uart6_function,
3394 &rs485_function,
3395 &touchscreen_function,
3396 &can0_function,
3397 &can1_function,
3398 &pwm0_1_function,
3399 &pwm2_function,
3400 &pwm3_function,
3401 &ssp1_function,
3402 &ssp2_function,
3403 &mii2_function,
3404 &mii0_1_function,
3405 &i2c1_function,
3406 &i2c2_function,
3407};
3408
3409static struct of_device_id spear320_pinctrl_of_match[] __devinitdata = {
3410 {
3411 .compatible = "st,spear320-pinmux",
3412 },
3413 {},
3414};
3415
3416static int __devinit spear320_pinctrl_probe(struct platform_device *pdev)
3417{
3418 int ret;
3419
3420 spear3xx_machdata.groups = spear320_pingroups;
3421 spear3xx_machdata.ngroups = ARRAY_SIZE(spear320_pingroups);
3422 spear3xx_machdata.functions = spear320_functions;
3423 spear3xx_machdata.nfunctions = ARRAY_SIZE(spear320_functions);
3424
3425 spear3xx_machdata.modes_supported = true;
3426 spear3xx_machdata.pmx_modes = spear320_pmx_modes;
3427 spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes);
3428
3429 pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
3430
3431 ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
3432 if (ret)
3433 return ret;
3434
3435 return 0;
3436}
3437
3438static int __devexit spear320_pinctrl_remove(struct platform_device *pdev)
3439{
3440 return spear_pinctrl_remove(pdev);
3441}
3442
3443static struct platform_driver spear320_pinctrl_driver = {
3444 .driver = {
3445 .name = DRIVER_NAME,
3446 .owner = THIS_MODULE,
3447 .of_match_table = spear320_pinctrl_of_match,
3448 },
3449 .probe = spear320_pinctrl_probe,
3450 .remove = __devexit_p(spear320_pinctrl_remove),
3451};
3452
3453static int __init spear320_pinctrl_init(void)
3454{
3455 return platform_driver_register(&spear320_pinctrl_driver);
3456}
3457arch_initcall(spear320_pinctrl_init);
3458
3459static void __exit spear320_pinctrl_exit(void)
3460{
3461 platform_driver_unregister(&spear320_pinctrl_driver);
3462}
3463module_exit(spear320_pinctrl_exit);
3464
3465MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");
3466MODULE_DESCRIPTION("ST Microelectronics SPEAr320 pinctrl driver");
3467MODULE_LICENSE("GPL v2");
3468MODULE_DEVICE_TABLE(of, spear320_pinctrl_of_match);
diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.c b/drivers/pinctrl/spear/pinctrl-spear3xx.c
new file mode 100644
index 00000000000..832049a8b1c
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear3xx.c
@@ -0,0 +1,588 @@
1/*
2 * Driver for the ST Microelectronics SPEAr3xx pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/pinctrl/pinctrl.h>
13
14#include "pinctrl-spear3xx.h"
15
16/* pins */
17static const struct pinctrl_pin_desc spear3xx_pins[] = {
18 PINCTRL_PIN(0, "PLGPIO0"),
19 PINCTRL_PIN(1, "PLGPIO1"),
20 PINCTRL_PIN(2, "PLGPIO2"),
21 PINCTRL_PIN(3, "PLGPIO3"),
22 PINCTRL_PIN(4, "PLGPIO4"),
23 PINCTRL_PIN(5, "PLGPIO5"),
24 PINCTRL_PIN(6, "PLGPIO6"),
25 PINCTRL_PIN(7, "PLGPIO7"),
26 PINCTRL_PIN(8, "PLGPIO8"),
27 PINCTRL_PIN(9, "PLGPIO9"),
28 PINCTRL_PIN(10, "PLGPIO10"),
29 PINCTRL_PIN(11, "PLGPIO11"),
30 PINCTRL_PIN(12, "PLGPIO12"),
31 PINCTRL_PIN(13, "PLGPIO13"),
32 PINCTRL_PIN(14, "PLGPIO14"),
33 PINCTRL_PIN(15, "PLGPIO15"),
34 PINCTRL_PIN(16, "PLGPIO16"),
35 PINCTRL_PIN(17, "PLGPIO17"),
36 PINCTRL_PIN(18, "PLGPIO18"),
37 PINCTRL_PIN(19, "PLGPIO19"),
38 PINCTRL_PIN(20, "PLGPIO20"),
39 PINCTRL_PIN(21, "PLGPIO21"),
40 PINCTRL_PIN(22, "PLGPIO22"),
41 PINCTRL_PIN(23, "PLGPIO23"),
42 PINCTRL_PIN(24, "PLGPIO24"),
43 PINCTRL_PIN(25, "PLGPIO25"),
44 PINCTRL_PIN(26, "PLGPIO26"),
45 PINCTRL_PIN(27, "PLGPIO27"),
46 PINCTRL_PIN(28, "PLGPIO28"),
47 PINCTRL_PIN(29, "PLGPIO29"),
48 PINCTRL_PIN(30, "PLGPIO30"),
49 PINCTRL_PIN(31, "PLGPIO31"),
50 PINCTRL_PIN(32, "PLGPIO32"),
51 PINCTRL_PIN(33, "PLGPIO33"),
52 PINCTRL_PIN(34, "PLGPIO34"),
53 PINCTRL_PIN(35, "PLGPIO35"),
54 PINCTRL_PIN(36, "PLGPIO36"),
55 PINCTRL_PIN(37, "PLGPIO37"),
56 PINCTRL_PIN(38, "PLGPIO38"),
57 PINCTRL_PIN(39, "PLGPIO39"),
58 PINCTRL_PIN(40, "PLGPIO40"),
59 PINCTRL_PIN(41, "PLGPIO41"),
60 PINCTRL_PIN(42, "PLGPIO42"),
61 PINCTRL_PIN(43, "PLGPIO43"),
62 PINCTRL_PIN(44, "PLGPIO44"),
63 PINCTRL_PIN(45, "PLGPIO45"),
64 PINCTRL_PIN(46, "PLGPIO46"),
65 PINCTRL_PIN(47, "PLGPIO47"),
66 PINCTRL_PIN(48, "PLGPIO48"),
67 PINCTRL_PIN(49, "PLGPIO49"),
68 PINCTRL_PIN(50, "PLGPIO50"),
69 PINCTRL_PIN(51, "PLGPIO51"),
70 PINCTRL_PIN(52, "PLGPIO52"),
71 PINCTRL_PIN(53, "PLGPIO53"),
72 PINCTRL_PIN(54, "PLGPIO54"),
73 PINCTRL_PIN(55, "PLGPIO55"),
74 PINCTRL_PIN(56, "PLGPIO56"),
75 PINCTRL_PIN(57, "PLGPIO57"),
76 PINCTRL_PIN(58, "PLGPIO58"),
77 PINCTRL_PIN(59, "PLGPIO59"),
78 PINCTRL_PIN(60, "PLGPIO60"),
79 PINCTRL_PIN(61, "PLGPIO61"),
80 PINCTRL_PIN(62, "PLGPIO62"),
81 PINCTRL_PIN(63, "PLGPIO63"),
82 PINCTRL_PIN(64, "PLGPIO64"),
83 PINCTRL_PIN(65, "PLGPIO65"),
84 PINCTRL_PIN(66, "PLGPIO66"),
85 PINCTRL_PIN(67, "PLGPIO67"),
86 PINCTRL_PIN(68, "PLGPIO68"),
87 PINCTRL_PIN(69, "PLGPIO69"),
88 PINCTRL_PIN(70, "PLGPIO70"),
89 PINCTRL_PIN(71, "PLGPIO71"),
90 PINCTRL_PIN(72, "PLGPIO72"),
91 PINCTRL_PIN(73, "PLGPIO73"),
92 PINCTRL_PIN(74, "PLGPIO74"),
93 PINCTRL_PIN(75, "PLGPIO75"),
94 PINCTRL_PIN(76, "PLGPIO76"),
95 PINCTRL_PIN(77, "PLGPIO77"),
96 PINCTRL_PIN(78, "PLGPIO78"),
97 PINCTRL_PIN(79, "PLGPIO79"),
98 PINCTRL_PIN(80, "PLGPIO80"),
99 PINCTRL_PIN(81, "PLGPIO81"),
100 PINCTRL_PIN(82, "PLGPIO82"),
101 PINCTRL_PIN(83, "PLGPIO83"),
102 PINCTRL_PIN(84, "PLGPIO84"),
103 PINCTRL_PIN(85, "PLGPIO85"),
104 PINCTRL_PIN(86, "PLGPIO86"),
105 PINCTRL_PIN(87, "PLGPIO87"),
106 PINCTRL_PIN(88, "PLGPIO88"),
107 PINCTRL_PIN(89, "PLGPIO89"),
108 PINCTRL_PIN(90, "PLGPIO90"),
109 PINCTRL_PIN(91, "PLGPIO91"),
110 PINCTRL_PIN(92, "PLGPIO92"),
111 PINCTRL_PIN(93, "PLGPIO93"),
112 PINCTRL_PIN(94, "PLGPIO94"),
113 PINCTRL_PIN(95, "PLGPIO95"),
114 PINCTRL_PIN(96, "PLGPIO96"),
115 PINCTRL_PIN(97, "PLGPIO97"),
116 PINCTRL_PIN(98, "PLGPIO98"),
117 PINCTRL_PIN(99, "PLGPIO99"),
118 PINCTRL_PIN(100, "PLGPIO100"),
119 PINCTRL_PIN(101, "PLGPIO101"),
120};
121
122/* firda_pins */
123static const unsigned firda_pins[] = { 0, 1 };
124static struct spear_muxreg firda_muxreg[] = {
125 {
126 .reg = -1,
127 .mask = PMX_FIRDA_MASK,
128 .val = PMX_FIRDA_MASK,
129 },
130};
131
132static struct spear_modemux firda_modemux[] = {
133 {
134 .modes = ~0,
135 .muxregs = firda_muxreg,
136 .nmuxregs = ARRAY_SIZE(firda_muxreg),
137 },
138};
139
140struct spear_pingroup spear3xx_firda_pingroup = {
141 .name = "firda_grp",
142 .pins = firda_pins,
143 .npins = ARRAY_SIZE(firda_pins),
144 .modemuxs = firda_modemux,
145 .nmodemuxs = ARRAY_SIZE(firda_modemux),
146};
147
148static const char *const firda_grps[] = { "firda_grp" };
149struct spear_function spear3xx_firda_function = {
150 .name = "firda",
151 .groups = firda_grps,
152 .ngroups = ARRAY_SIZE(firda_grps),
153};
154
155/* i2c_pins */
156static const unsigned i2c_pins[] = { 4, 5 };
157static struct spear_muxreg i2c_muxreg[] = {
158 {
159 .reg = -1,
160 .mask = PMX_I2C_MASK,
161 .val = PMX_I2C_MASK,
162 },
163};
164
165static struct spear_modemux i2c_modemux[] = {
166 {
167 .modes = ~0,
168 .muxregs = i2c_muxreg,
169 .nmuxregs = ARRAY_SIZE(i2c_muxreg),
170 },
171};
172
173struct spear_pingroup spear3xx_i2c_pingroup = {
174 .name = "i2c0_grp",
175 .pins = i2c_pins,
176 .npins = ARRAY_SIZE(i2c_pins),
177 .modemuxs = i2c_modemux,
178 .nmodemuxs = ARRAY_SIZE(i2c_modemux),
179};
180
181static const char *const i2c_grps[] = { "i2c0_grp" };
182struct spear_function spear3xx_i2c_function = {
183 .name = "i2c0",
184 .groups = i2c_grps,
185 .ngroups = ARRAY_SIZE(i2c_grps),
186};
187
188/* ssp_cs_pins */
189static const unsigned ssp_cs_pins[] = { 34, 35, 36 };
190static struct spear_muxreg ssp_cs_muxreg[] = {
191 {
192 .reg = -1,
193 .mask = PMX_SSP_CS_MASK,
194 .val = PMX_SSP_CS_MASK,
195 },
196};
197
198static struct spear_modemux ssp_cs_modemux[] = {
199 {
200 .modes = ~0,
201 .muxregs = ssp_cs_muxreg,
202 .nmuxregs = ARRAY_SIZE(ssp_cs_muxreg),
203 },
204};
205
206struct spear_pingroup spear3xx_ssp_cs_pingroup = {
207 .name = "ssp_cs_grp",
208 .pins = ssp_cs_pins,
209 .npins = ARRAY_SIZE(ssp_cs_pins),
210 .modemuxs = ssp_cs_modemux,
211 .nmodemuxs = ARRAY_SIZE(ssp_cs_modemux),
212};
213
214static const char *const ssp_cs_grps[] = { "ssp_cs_grp" };
215struct spear_function spear3xx_ssp_cs_function = {
216 .name = "ssp_cs",
217 .groups = ssp_cs_grps,
218 .ngroups = ARRAY_SIZE(ssp_cs_grps),
219};
220
221/* ssp_pins */
222static const unsigned ssp_pins[] = { 6, 7, 8, 9 };
223static struct spear_muxreg ssp_muxreg[] = {
224 {
225 .reg = -1,
226 .mask = PMX_SSP_MASK,
227 .val = PMX_SSP_MASK,
228 },
229};
230
231static struct spear_modemux ssp_modemux[] = {
232 {
233 .modes = ~0,
234 .muxregs = ssp_muxreg,
235 .nmuxregs = ARRAY_SIZE(ssp_muxreg),
236 },
237};
238
239struct spear_pingroup spear3xx_ssp_pingroup = {
240 .name = "ssp0_grp",
241 .pins = ssp_pins,
242 .npins = ARRAY_SIZE(ssp_pins),
243 .modemuxs = ssp_modemux,
244 .nmodemuxs = ARRAY_SIZE(ssp_modemux),
245};
246
247static const char *const ssp_grps[] = { "ssp0_grp" };
248struct spear_function spear3xx_ssp_function = {
249 .name = "ssp0",
250 .groups = ssp_grps,
251 .ngroups = ARRAY_SIZE(ssp_grps),
252};
253
254/* mii_pins */
255static const unsigned mii_pins[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
256 21, 22, 23, 24, 25, 26, 27 };
257static struct spear_muxreg mii_muxreg[] = {
258 {
259 .reg = -1,
260 .mask = PMX_MII_MASK,
261 .val = PMX_MII_MASK,
262 },
263};
264
265static struct spear_modemux mii_modemux[] = {
266 {
267 .modes = ~0,
268 .muxregs = mii_muxreg,
269 .nmuxregs = ARRAY_SIZE(mii_muxreg),
270 },
271};
272
273struct spear_pingroup spear3xx_mii_pingroup = {
274 .name = "mii0_grp",
275 .pins = mii_pins,
276 .npins = ARRAY_SIZE(mii_pins),
277 .modemuxs = mii_modemux,
278 .nmodemuxs = ARRAY_SIZE(mii_modemux),
279};
280
281static const char *const mii_grps[] = { "mii0_grp" };
282struct spear_function spear3xx_mii_function = {
283 .name = "mii0",
284 .groups = mii_grps,
285 .ngroups = ARRAY_SIZE(mii_grps),
286};
287
288/* gpio0_pin0_pins */
289static const unsigned gpio0_pin0_pins[] = { 28 };
290static struct spear_muxreg gpio0_pin0_muxreg[] = {
291 {
292 .reg = -1,
293 .mask = PMX_GPIO_PIN0_MASK,
294 .val = PMX_GPIO_PIN0_MASK,
295 },
296};
297
298static struct spear_modemux gpio0_pin0_modemux[] = {
299 {
300 .modes = ~0,
301 .muxregs = gpio0_pin0_muxreg,
302 .nmuxregs = ARRAY_SIZE(gpio0_pin0_muxreg),
303 },
304};
305
306struct spear_pingroup spear3xx_gpio0_pin0_pingroup = {
307 .name = "gpio0_pin0_grp",
308 .pins = gpio0_pin0_pins,
309 .npins = ARRAY_SIZE(gpio0_pin0_pins),
310 .modemuxs = gpio0_pin0_modemux,
311 .nmodemuxs = ARRAY_SIZE(gpio0_pin0_modemux),
312};
313
314/* gpio0_pin1_pins */
315static const unsigned gpio0_pin1_pins[] = { 29 };
316static struct spear_muxreg gpio0_pin1_muxreg[] = {
317 {
318 .reg = -1,
319 .mask = PMX_GPIO_PIN1_MASK,
320 .val = PMX_GPIO_PIN1_MASK,
321 },
322};
323
324static struct spear_modemux gpio0_pin1_modemux[] = {
325 {
326 .modes = ~0,
327 .muxregs = gpio0_pin1_muxreg,
328 .nmuxregs = ARRAY_SIZE(gpio0_pin1_muxreg),
329 },
330};
331
332struct spear_pingroup spear3xx_gpio0_pin1_pingroup = {
333 .name = "gpio0_pin1_grp",
334 .pins = gpio0_pin1_pins,
335 .npins = ARRAY_SIZE(gpio0_pin1_pins),
336 .modemuxs = gpio0_pin1_modemux,
337 .nmodemuxs = ARRAY_SIZE(gpio0_pin1_modemux),
338};
339
340/* gpio0_pin2_pins */
341static const unsigned gpio0_pin2_pins[] = { 30 };
342static struct spear_muxreg gpio0_pin2_muxreg[] = {
343 {
344 .reg = -1,
345 .mask = PMX_GPIO_PIN2_MASK,
346 .val = PMX_GPIO_PIN2_MASK,
347 },
348};
349
350static struct spear_modemux gpio0_pin2_modemux[] = {
351 {
352 .modes = ~0,
353 .muxregs = gpio0_pin2_muxreg,
354 .nmuxregs = ARRAY_SIZE(gpio0_pin2_muxreg),
355 },
356};
357
358struct spear_pingroup spear3xx_gpio0_pin2_pingroup = {
359 .name = "gpio0_pin2_grp",
360 .pins = gpio0_pin2_pins,
361 .npins = ARRAY_SIZE(gpio0_pin2_pins),
362 .modemuxs = gpio0_pin2_modemux,
363 .nmodemuxs = ARRAY_SIZE(gpio0_pin2_modemux),
364};
365
366/* gpio0_pin3_pins */
367static const unsigned gpio0_pin3_pins[] = { 31 };
368static struct spear_muxreg gpio0_pin3_muxreg[] = {
369 {
370 .reg = -1,
371 .mask = PMX_GPIO_PIN3_MASK,
372 .val = PMX_GPIO_PIN3_MASK,
373 },
374};
375
376static struct spear_modemux gpio0_pin3_modemux[] = {
377 {
378 .modes = ~0,
379 .muxregs = gpio0_pin3_muxreg,
380 .nmuxregs = ARRAY_SIZE(gpio0_pin3_muxreg),
381 },
382};
383
384struct spear_pingroup spear3xx_gpio0_pin3_pingroup = {
385 .name = "gpio0_pin3_grp",
386 .pins = gpio0_pin3_pins,
387 .npins = ARRAY_SIZE(gpio0_pin3_pins),
388 .modemuxs = gpio0_pin3_modemux,
389 .nmodemuxs = ARRAY_SIZE(gpio0_pin3_modemux),
390};
391
392/* gpio0_pin4_pins */
393static const unsigned gpio0_pin4_pins[] = { 32 };
394static struct spear_muxreg gpio0_pin4_muxreg[] = {
395 {
396 .reg = -1,
397 .mask = PMX_GPIO_PIN4_MASK,
398 .val = PMX_GPIO_PIN4_MASK,
399 },
400};
401
402static struct spear_modemux gpio0_pin4_modemux[] = {
403 {
404 .modes = ~0,
405 .muxregs = gpio0_pin4_muxreg,
406 .nmuxregs = ARRAY_SIZE(gpio0_pin4_muxreg),
407 },
408};
409
410struct spear_pingroup spear3xx_gpio0_pin4_pingroup = {
411 .name = "gpio0_pin4_grp",
412 .pins = gpio0_pin4_pins,
413 .npins = ARRAY_SIZE(gpio0_pin4_pins),
414 .modemuxs = gpio0_pin4_modemux,
415 .nmodemuxs = ARRAY_SIZE(gpio0_pin4_modemux),
416};
417
418/* gpio0_pin5_pins */
419static const unsigned gpio0_pin5_pins[] = { 33 };
420static struct spear_muxreg gpio0_pin5_muxreg[] = {
421 {
422 .reg = -1,
423 .mask = PMX_GPIO_PIN5_MASK,
424 .val = PMX_GPIO_PIN5_MASK,
425 },
426};
427
428static struct spear_modemux gpio0_pin5_modemux[] = {
429 {
430 .modes = ~0,
431 .muxregs = gpio0_pin5_muxreg,
432 .nmuxregs = ARRAY_SIZE(gpio0_pin5_muxreg),
433 },
434};
435
436struct spear_pingroup spear3xx_gpio0_pin5_pingroup = {
437 .name = "gpio0_pin5_grp",
438 .pins = gpio0_pin5_pins,
439 .npins = ARRAY_SIZE(gpio0_pin5_pins),
440 .modemuxs = gpio0_pin5_modemux,
441 .nmodemuxs = ARRAY_SIZE(gpio0_pin5_modemux),
442};
443
444static const char *const gpio0_grps[] = { "gpio0_pin0_grp", "gpio0_pin1_grp",
445 "gpio0_pin2_grp", "gpio0_pin3_grp", "gpio0_pin4_grp", "gpio0_pin5_grp",
446};
447struct spear_function spear3xx_gpio0_function = {
448 .name = "gpio0",
449 .groups = gpio0_grps,
450 .ngroups = ARRAY_SIZE(gpio0_grps),
451};
452
453/* uart0_ext_pins */
454static const unsigned uart0_ext_pins[] = { 37, 38, 39, 40, 41, 42 };
455static struct spear_muxreg uart0_ext_muxreg[] = {
456 {
457 .reg = -1,
458 .mask = PMX_UART0_MODEM_MASK,
459 .val = PMX_UART0_MODEM_MASK,
460 },
461};
462
463static struct spear_modemux uart0_ext_modemux[] = {
464 {
465 .modes = ~0,
466 .muxregs = uart0_ext_muxreg,
467 .nmuxregs = ARRAY_SIZE(uart0_ext_muxreg),
468 },
469};
470
471struct spear_pingroup spear3xx_uart0_ext_pingroup = {
472 .name = "uart0_ext_grp",
473 .pins = uart0_ext_pins,
474 .npins = ARRAY_SIZE(uart0_ext_pins),
475 .modemuxs = uart0_ext_modemux,
476 .nmodemuxs = ARRAY_SIZE(uart0_ext_modemux),
477};
478
479static const char *const uart0_ext_grps[] = { "uart0_ext_grp" };
480struct spear_function spear3xx_uart0_ext_function = {
481 .name = "uart0_ext",
482 .groups = uart0_ext_grps,
483 .ngroups = ARRAY_SIZE(uart0_ext_grps),
484};
485
486/* uart0_pins */
487static const unsigned uart0_pins[] = { 2, 3 };
488static struct spear_muxreg uart0_muxreg[] = {
489 {
490 .reg = -1,
491 .mask = PMX_UART0_MASK,
492 .val = PMX_UART0_MASK,
493 },
494};
495
496static struct spear_modemux uart0_modemux[] = {
497 {
498 .modes = ~0,
499 .muxregs = uart0_muxreg,
500 .nmuxregs = ARRAY_SIZE(uart0_muxreg),
501 },
502};
503
504struct spear_pingroup spear3xx_uart0_pingroup = {
505 .name = "uart0_grp",
506 .pins = uart0_pins,
507 .npins = ARRAY_SIZE(uart0_pins),
508 .modemuxs = uart0_modemux,
509 .nmodemuxs = ARRAY_SIZE(uart0_modemux),
510};
511
512static const char *const uart0_grps[] = { "uart0_grp" };
513struct spear_function spear3xx_uart0_function = {
514 .name = "uart0",
515 .groups = uart0_grps,
516 .ngroups = ARRAY_SIZE(uart0_grps),
517};
518
519/* timer_0_1_pins */
520static const unsigned timer_0_1_pins[] = { 43, 44, 47, 48 };
521static struct spear_muxreg timer_0_1_muxreg[] = {
522 {
523 .reg = -1,
524 .mask = PMX_TIMER_0_1_MASK,
525 .val = PMX_TIMER_0_1_MASK,
526 },
527};
528
529static struct spear_modemux timer_0_1_modemux[] = {
530 {
531 .modes = ~0,
532 .muxregs = timer_0_1_muxreg,
533 .nmuxregs = ARRAY_SIZE(timer_0_1_muxreg),
534 },
535};
536
537struct spear_pingroup spear3xx_timer_0_1_pingroup = {
538 .name = "timer_0_1_grp",
539 .pins = timer_0_1_pins,
540 .npins = ARRAY_SIZE(timer_0_1_pins),
541 .modemuxs = timer_0_1_modemux,
542 .nmodemuxs = ARRAY_SIZE(timer_0_1_modemux),
543};
544
545static const char *const timer_0_1_grps[] = { "timer_0_1_grp" };
546struct spear_function spear3xx_timer_0_1_function = {
547 .name = "timer_0_1",
548 .groups = timer_0_1_grps,
549 .ngroups = ARRAY_SIZE(timer_0_1_grps),
550};
551
552/* timer_2_3_pins */
553static const unsigned timer_2_3_pins[] = { 45, 46, 49, 50 };
554static struct spear_muxreg timer_2_3_muxreg[] = {
555 {
556 .reg = -1,
557 .mask = PMX_TIMER_2_3_MASK,
558 .val = PMX_TIMER_2_3_MASK,
559 },
560};
561
562static struct spear_modemux timer_2_3_modemux[] = {
563 {
564 .modes = ~0,
565 .muxregs = timer_2_3_muxreg,
566 .nmuxregs = ARRAY_SIZE(timer_2_3_muxreg),
567 },
568};
569
570struct spear_pingroup spear3xx_timer_2_3_pingroup = {
571 .name = "timer_2_3_grp",
572 .pins = timer_2_3_pins,
573 .npins = ARRAY_SIZE(timer_2_3_pins),
574 .modemuxs = timer_2_3_modemux,
575 .nmodemuxs = ARRAY_SIZE(timer_2_3_modemux),
576};
577
578static const char *const timer_2_3_grps[] = { "timer_2_3_grp" };
579struct spear_function spear3xx_timer_2_3_function = {
580 .name = "timer_2_3",
581 .groups = timer_2_3_grps,
582 .ngroups = ARRAY_SIZE(timer_2_3_grps),
583};
584
585struct spear_pinctrl_machdata spear3xx_machdata = {
586 .pins = spear3xx_pins,
587 .npins = ARRAY_SIZE(spear3xx_pins),
588};
diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.h b/drivers/pinctrl/spear/pinctrl-spear3xx.h
new file mode 100644
index 00000000000..5d5fdd8df7b
--- /dev/null
+++ b/drivers/pinctrl/spear/pinctrl-spear3xx.h
@@ -0,0 +1,92 @@
1/*
2 * Header file for the ST Microelectronics SPEAr3xx pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.kumar@st.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#ifndef __PINMUX_SPEAR3XX_H__
13#define __PINMUX_SPEAR3XX_H__
14
15#include "pinctrl-spear.h"
16
17/* pad mux declarations */
18#define PMX_FIRDA_MASK (1 << 14)
19#define PMX_I2C_MASK (1 << 13)
20#define PMX_SSP_CS_MASK (1 << 12)
21#define PMX_SSP_MASK (1 << 11)
22#define PMX_MII_MASK (1 << 10)
23#define PMX_GPIO_PIN0_MASK (1 << 9)
24#define PMX_GPIO_PIN1_MASK (1 << 8)
25#define PMX_GPIO_PIN2_MASK (1 << 7)
26#define PMX_GPIO_PIN3_MASK (1 << 6)
27#define PMX_GPIO_PIN4_MASK (1 << 5)
28#define PMX_GPIO_PIN5_MASK (1 << 4)
29#define PMX_UART0_MODEM_MASK (1 << 3)
30#define PMX_UART0_MASK (1 << 2)
31#define PMX_TIMER_2_3_MASK (1 << 1)
32#define PMX_TIMER_0_1_MASK (1 << 0)
33
34extern struct spear_pingroup spear3xx_firda_pingroup;
35extern struct spear_pingroup spear3xx_gpio0_pin0_pingroup;
36extern struct spear_pingroup spear3xx_gpio0_pin1_pingroup;
37extern struct spear_pingroup spear3xx_gpio0_pin2_pingroup;
38extern struct spear_pingroup spear3xx_gpio0_pin3_pingroup;
39extern struct spear_pingroup spear3xx_gpio0_pin4_pingroup;
40extern struct spear_pingroup spear3xx_gpio0_pin5_pingroup;
41extern struct spear_pingroup spear3xx_i2c_pingroup;
42extern struct spear_pingroup spear3xx_mii_pingroup;
43extern struct spear_pingroup spear3xx_ssp_cs_pingroup;
44extern struct spear_pingroup spear3xx_ssp_pingroup;
45extern struct spear_pingroup spear3xx_timer_0_1_pingroup;
46extern struct spear_pingroup spear3xx_timer_2_3_pingroup;
47extern struct spear_pingroup spear3xx_uart0_ext_pingroup;
48extern struct spear_pingroup spear3xx_uart0_pingroup;
49
50#define SPEAR3XX_COMMON_PINGROUPS \
51 &spear3xx_firda_pingroup, \
52 &spear3xx_gpio0_pin0_pingroup, \
53 &spear3xx_gpio0_pin1_pingroup, \
54 &spear3xx_gpio0_pin2_pingroup, \
55 &spear3xx_gpio0_pin3_pingroup, \
56 &spear3xx_gpio0_pin4_pingroup, \
57 &spear3xx_gpio0_pin5_pingroup, \
58 &spear3xx_i2c_pingroup, \
59 &spear3xx_mii_pingroup, \
60 &spear3xx_ssp_cs_pingroup, \
61 &spear3xx_ssp_pingroup, \
62 &spear3xx_timer_0_1_pingroup, \
63 &spear3xx_timer_2_3_pingroup, \
64 &spear3xx_uart0_ext_pingroup, \
65 &spear3xx_uart0_pingroup
66
67extern struct spear_function spear3xx_firda_function;
68extern struct spear_function spear3xx_gpio0_function;
69extern struct spear_function spear3xx_i2c_function;
70extern struct spear_function spear3xx_mii_function;
71extern struct spear_function spear3xx_ssp_cs_function;
72extern struct spear_function spear3xx_ssp_function;
73extern struct spear_function spear3xx_timer_0_1_function;
74extern struct spear_function spear3xx_timer_2_3_function;
75extern struct spear_function spear3xx_uart0_ext_function;
76extern struct spear_function spear3xx_uart0_function;
77
78#define SPEAR3XX_COMMON_FUNCTIONS \
79 &spear3xx_firda_function, \
80 &spear3xx_gpio0_function, \
81 &spear3xx_i2c_function, \
82 &spear3xx_mii_function, \
83 &spear3xx_ssp_cs_function, \
84 &spear3xx_ssp_function, \
85 &spear3xx_timer_0_1_function, \
86 &spear3xx_timer_2_3_function, \
87 &spear3xx_uart0_ext_function, \
88 &spear3xx_uart0_function
89
90extern struct spear_pinctrl_machdata spear3xx_machdata;
91
92#endif /* __PINMUX_SPEAR3XX_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 07:33:52 -0400